LLVM  6.0.0svn
Namespaces | Macros | Functions | Variables
HexagonGenInsert.cpp File Reference
#include "BitTracker.h"
#include "HexagonBitTracker.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include <vector>
Include dependency graph for HexagonGenInsert.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "hexinsert"
 

Functions

static bool isDebug ()
 
void llvm::initializeHexagonGenInsertPass (PassRegistry &)
 
FunctionPassllvm::createHexagonGenInsert ()
 
 INITIALIZE_PASS_BEGIN (HexagonGenInsert, "hexinsert", "Hexagon generate \nsert\instructions", false, false) INITIALIZE_PASS_END(HexagonGenInsert
 

Variables

static cl::opt< unsignedVRegIndexCutoff ("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation."))
 
static cl::opt< unsignedVRegDistCutoff ("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert " "generation."))
 
static cl::opt< boolOptTiming ("insert-timing", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable timing of insert generation"))
 
static cl::opt< boolOptTimingDetail ("insert-timing-detail", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert " "generation"))
 
static cl::opt< boolOptSelectAll0 ("insert-all0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
static cl::opt< boolOptSelectHas0 ("insert-has0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
static cl::opt< boolOptConst ("insert-const", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
 hexinsert
 
Hexagon generate insert instructions
 
Hexagon generate insert false
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "hexinsert"

Definition at line 46 of file HexagonGenInsert.cpp.

Referenced by isDebug().

Function Documentation

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( HexagonGenInsert  ,
"hexinsert"  ,
"Hexagon generate \nsert\instructions ,
false  ,
false   
)

◆ isDebug()

static bool isDebug ( )
inlinestatic

Definition at line 75 of file HexagonGenInsert.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::AnalysisUsage::addPreserved(), llvm::MachineInstrBuilder::addReg(), llvm::AnalysisUsage::addRequired(), llvm::BitVector::any(), llvm::BitVector::anyCommon(), assert(), B, llvm::sys::path::const_iterator::begin, llvm::sys::path::begin(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), C, llvm::BitVector::clear(), llvm::HexagonISD::CP, llvm::createHexagonGenInsert(), D, llvm::dbgs(), DEBUG_TYPE, llvm::DebugFlag, E, llvm::sys::path::const_iterator::end, llvm::sys::path::end(), llvm::WebAssembly::End, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), F(), llvm::find(), llvm::BitVector::find_first(), llvm::BitVector::find_next(), first, llvm::MachineFunctionPass::getAnalysisUsage(), llvm::DomTreeNodeBase< NodeT >::getBlock(), llvm::MachineInstr::getDebugLoc(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineFunction::getFunction(), llvm::MachineBasicBlock::getNumber(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PassRegistry::getPassRegistry(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::Hi_32(), I, llvm::AMDGPUISD::IF, llvm::TargetRegisterInfo::index2VirtReg(), llvm::initializeHexagonGenInsertPass(), IR, llvm::BitTracker::BitValue::is(), isConstant(), llvm::MachineInstr::isCopy(), llvm::isCurrentDebugType(), llvm::MachineOperand::isDef(), llvm::MachineInstr::isInlineAsm(), llvm::isInt< 16 >(), llvm::isInt< 8 >(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegSequence(), llvm::MachineInstr::isSafeToMove(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ARM_MB::LD, llvm::ISD::LIFETIME_END, llvm::ISD::LIFETIME_START, llvm::Lo_32(), llvm::BitTracker::lookup(), lookup(), llvm::lower_bound(), llvm::max(), MI, MRI, N, llvm::RISCVFenceField::O, llvm::MachineInstr::operands(), llvm::operator<<(), llvm::BitVector::operator[](), llvm::BitVector::operator|=(), OptConst, OptSelectAll0, OptSelectHas0, OptTiming, OptTimingDetail, P, llvm::BitTracker::BitRef::Pos, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_end(), llvm::PrintReg(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::MachineBasicBlock::rbegin(), llvm::BitTracker::BitValue::Ref, llvm::BitTracker::BitValue::RefI, llvm::BitTracker::BitRef::Reg, Regs, llvm::sys::fs::remove(), llvm::remove_if(), llvm::MachineBasicBlock::rend(), llvm::BitVector::reset(), RPO, llvm::BitTracker::run(), second, llvm::BitVector::set(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, llvm::MachineBasicBlock::size(), llvm::parallel::sort(), llvm::ARM_MB::ST, stats, llvm::SPII::Store, llvm::X86II::TB, llvm::BitVector::test(), llvm::BitTracker::trace(), llvm::BitTracker::BitValue::Type, llvm::NVPTX::PTXLdStInstCode::V2, llvm::TargetRegisterInfo::virtReg2Index(), VRegDistCutoff, VRegIndexCutoff, llvm::RISCVFenceField::W, llvm::BitTracker::RegisterCell::width(), and llvm::Z.

Variable Documentation

◆ false

Hexagon generate insert false

Definition at line 1615 of file HexagonGenInsert.cpp.

◆ hexinsert

hexinsert

Definition at line 1615 of file HexagonGenInsert.cpp.

◆ instructions

Hexagon generate insert instructions

Definition at line 1615 of file HexagonGenInsert.cpp.

◆ OptConst

cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

Referenced by isDebug().

◆ OptSelectAll0

cl::opt<bool> OptSelectAll0("insert-all0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

Referenced by isDebug().

◆ OptSelectHas0

cl::opt<bool> OptSelectHas0("insert-has0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

Referenced by isDebug().

◆ OptTiming

cl::opt<bool> OptTiming("insert-timing", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable timing of insert generation"))
static

Referenced by isDebug().

◆ OptTimingDetail

cl::opt<bool> OptTimingDetail("insert-timing-detail", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert " "generation"))
static

Referenced by isDebug().

◆ VRegDistCutoff

cl::opt<unsigned> VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert " "generation."))
static

Referenced by isDebug().

◆ VRegIndexCutoff

cl::opt<unsigned> VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation."))
static

Referenced by isDebug().