14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H 15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H 31 namespace HexagonISD {
97 int VarArgsFrameOffset;
101 bool CanReturnSmallStruct(
const Function* CalleeFn,
unsigned& RetSize)
108 bool isHVXVectorType(
MVT Ty)
const;
121 unsigned Intrinsic)
const override;
123 bool isTruncateFree(
Type *Ty1,
Type *Ty2)
const override;
124 bool isTruncateFree(
EVT VT1,
EVT VT2)
const override;
130 bool allowTruncateForTailCall(
Type *Ty1,
Type *Ty2)
const override;
136 bool isFMAFasterThanFMulAndFAdd(
EVT)
const override;
139 bool shouldExpandBuildVectorWithShuffles(
EVT VT,
140 unsigned DefinedValues)
const override;
152 const char *getTargetNodeName(
unsigned Opcode)
const override;
223 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
225 unsigned getRegisterByName(
const char* RegName,
EVT VT,
247 EVT VT)
const override {
261 std::pair<unsigned, const TargetRegisterClass *>
267 if (ConstraintCode ==
"o")
281 Type *Ty,
unsigned AS,
287 bool isFPImmLegal(
const APFloat &Imm,
EVT VT)
const override;
293 bool isLegalICmpImmediate(int64_t Imm)
const override;
295 EVT getOptimalMemOpType(uint64_t
Size,
unsigned DstAlign,
296 unsigned SrcAlign,
bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
299 bool allowsMisalignedMemoryAccesses(
EVT VT,
unsigned AddrSpace,
300 unsigned Align,
bool *
Fast)
const override;
307 EVT NewVT)
const override;
315 bool shouldExpandAtomicStoreInIR(
StoreInst *
SI)
const override;
321 return AtomicExpansionKind::LLSC;
325 void initializeHVXLowering();
326 void validateConstPtrAlignment(
SDValue Ptr,
const SDLoc &dl,
327 unsigned NeedAlign)
const;
329 std::pair<SDValue,int> getBaseAndOffset(
SDValue Addr)
const;
360 using VectorPair = std::pair<SDValue, SDValue>;
361 using TypePair = std::pair<MVT, MVT>;
369 TypePair ty(
const VectorPair &Ops)
const {
370 return { Ops.first.getValueType().getSimpleVT(),
371 Ops.second.getValueType().getSimpleVT() };
373 MVT tyScalar(
MVT Ty)
const {
383 assert((TyWidth % ElemWidth) == 0);
387 MVT typeJoin(
const TypePair &Tys)
const;
388 TypePair typeSplit(
MVT Ty)
const;
389 MVT typeExtElem(
MVT VecTy,
unsigned Factor)
const;
390 MVT typeTruncElem(
MVT VecTy,
unsigned Factor)
const;
397 bool isHvxSingleTy(
MVT Ty)
const;
398 bool isHvxPairTy(
MVT Ty)
const;
410 unsigned BitBytes,
bool ZeroFill,
451 std::pair<const TargetRegisterClass*, uint8_t>
455 bool isHvxOperation(
SDValue Op)
const;
461 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
static MVT getIntegerVT(unsigned BitWidth)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This class represents lattice values for constants.
static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static MVT getVectorVT(MVT VT, unsigned NumElements)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
bool isVector() const
Return true if this is a vector value type.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This class represents a function call, abstracting a target machine's calling convention.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Function Alias Analysis Results
static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG)
unsigned const TargetRegisterInfo * TRI
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
An instruction for reading from memory.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static unsigned getInt(StringRef R)
Get an unsigned integer, including error checks.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM's memory model.
unsigned getSizeInBits() const
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
An instruction for storing to memory.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
MVT getVectorElementType() const
Analysis containing CSE Info
UNDEF - An undefined node.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
bool isMachineOpcode() const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
This is an important base class in LLVM.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
unsigned getMachineOpcode() const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
static bool isUndef(ArrayRef< int > Mask)
static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
static Value * insertVector(IRBuilderTy &IRB, Value *Old, Value *V, unsigned BeginIndex, const Twine &Name)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isVector() const
Return true if this is a vector value type.
static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
unsigned getOpcode() const
static Value * extractVector(IRBuilderTy &IRB, Value *V, unsigned BeginIndex, unsigned EndIndex, const Twine &Name)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.