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HexagonISelLowering.h
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1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
17 
18 #include "Hexagon.h"
19 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include <cstdint>
28 #include <utility>
29 
30 namespace llvm {
31 
32 namespace HexagonISD {
33 
34  enum NodeType : unsigned {
36 
38  CONST32_GP, // For marking data present in GP.
40 
41  AT_GOT, // Index in GOT.
42  AT_PCREL, // Offset relative to PC.
43 
44  CALL, // Function call.
45  CALLnr, // Function call that does not return.
47 
48  RET_FLAG, // Return with a flag operand.
49  BARRIER, // Memory barrier.
50  JT, // Jump table.
51  CP, // Constant pool.
52 
59 
71 
73  };
74 
75 } // end namespace HexagonISD
76 
77  class HexagonSubtarget;
78 
80  int VarArgsFrameOffset; // Frame offset to start of varargs area.
81  const HexagonTargetMachine &HTM;
82  const HexagonSubtarget &Subtarget;
83 
84  bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
85  const;
86  void promoteLdStType(MVT VT, MVT PromotedLdStVT);
87 
88  public:
89  explicit HexagonTargetLowering(const TargetMachine &TM,
90  const HexagonSubtarget &ST);
91 
92  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
93  /// for tail call optimization. Targets which want to do tail call
94  /// optimization should implement this function.
95  bool IsEligibleForTailCallOptimization(SDValue Callee,
96  CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
97  bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
98  const SmallVectorImpl<SDValue> &OutVals,
100 
101  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
102  bool isTruncateFree(EVT VT1, EVT VT2) const override;
103 
104  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
105 
106  /// Return true if an FMA operation is faster than a pair of mul and add
107  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
108  /// method returns true (and FMAs are legal), otherwise fmuladd is
109  /// expanded to mul + add.
110  bool isFMAFasterThanFMulAndFAdd(EVT) const override;
111 
112  // Should we expand the build vector with shuffles?
113  bool shouldExpandBuildVectorWithShuffles(EVT VT,
114  unsigned DefinedValues) const override;
115 
116  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
117 
118  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
119  const char *getTargetNodeName(unsigned Opcode) const override;
121  SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
122  SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const;
123  SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
125  SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
126  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
128  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
129  SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
131  SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
132  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
133  SDValue
134  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
136  const SDLoc &dl, SelectionDAG &DAG,
137  SmallVectorImpl<SDValue> &InVals) const override;
138  SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
139  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
140  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
141  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
142  SelectionDAG &DAG) const;
143  SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
144  SelectionDAG &DAG) const;
145  SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
146  SelectionDAG &DAG) const;
147  SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
148  GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
149  unsigned ReturnReg, unsigned char OperandFlags) const;
150  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
151 
153  SmallVectorImpl<SDValue> &InVals) const override;
154  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
155  CallingConv::ID CallConv, bool isVarArg,
157  const SDLoc &dl, SelectionDAG &DAG,
158  SmallVectorImpl<SDValue> &InVals,
159  const SmallVectorImpl<SDValue> &OutVals,
160  SDValue Callee) const;
161 
162  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
163  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
164  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
167 
168  bool CanLowerReturn(CallingConv::ID CallConv,
169  MachineFunction &MF, bool isVarArg,
171  LLVMContext &Context) const override;
172 
173  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
175  const SmallVectorImpl<SDValue> &OutVals,
176  const SDLoc &dl, SelectionDAG &DAG) const override;
177 
178  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
179 
180  /// If a physical register, this returns the register that receives the
181  /// exception address on entry to an EH pad.
182  unsigned
183  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
184  return Hexagon::R0;
185  }
186 
187  /// If a physical register, this returns the register that receives the
188  /// exception typeid on entry to a landing pad.
189  unsigned
190  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
191  return Hexagon::R1;
192  }
193 
194  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
195  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
196  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
197 
199  EVT VT) const override {
200  if (!VT.isVector())
201  return MVT::i1;
202  else
204  }
205 
206  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
209  SelectionDAG &DAG) const override;
210 
211  ConstraintType getConstraintType(StringRef Constraint) const override;
212 
213  std::pair<unsigned, const TargetRegisterClass *>
214  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
215  StringRef Constraint, MVT VT) const override;
216 
217  unsigned
218  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
219  if (ConstraintCode == "o")
221  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
222  }
223 
224  // Intrinsics
225  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
226  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
227  /// isLegalAddressingMode - Return true if the addressing mode represented
228  /// by AM is legal for this target, for a load/store of the specified type.
229  /// The type may be VoidTy, in which case only return true if the addressing
230  /// mode is legal for a load/store of any legal type.
231  /// TODO: Handle pre/postinc as well.
232  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
233  Type *Ty, unsigned AS,
234  Instruction *I = nullptr) const override;
235  /// Return true if folding a constant offset with the given GlobalAddress
236  /// is legal. It is frequently not legal in PIC relocation models.
237  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
238 
239  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
240 
241  /// isLegalICmpImmediate - Return true if the specified immediate is legal
242  /// icmp immediate, that is the target has icmp instructions which can
243  /// compare a register against the immediate without having to materialize
244  /// the immediate into a register.
245  bool isLegalICmpImmediate(int64_t Imm) const override;
246 
247  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
248  unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
249  MachineFunction &MF) const override;
250 
251  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
252  unsigned Align, bool *Fast) const override;
253 
254  /// Returns relocation base for the given PIC jumptable.
255  SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
256  const override;
257 
258  // Handling of atomic RMW instructions.
259  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
260  AtomicOrdering Ord) const override;
261  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
262  Value *Addr, AtomicOrdering Ord) const override;
263  AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
264  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
265  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
266 
269  return AtomicExpansionKind::LLSC;
270  }
271 
272  protected:
273  std::pair<const TargetRegisterClass*, uint8_t>
274  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
275  const override;
276  };
277 
278 } // end namespace llvm
279 
280 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
uint64_t CallInst * C
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
This class represents a function call, abstracting a target machine&#39;s calling convention.
static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG)
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
An instruction for storing to memory.
Definition: Instructions.h:306
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
This is an important base class in LLVM.
Definition: Constant.h:42
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871