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HexagonISelLowering.h
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1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
17 
18 #include "Hexagon.h"
19 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include <cstdint>
28 #include <utility>
29 
30 namespace llvm {
31 
32 namespace HexagonISD {
33 
34  enum NodeType : unsigned {
36 
38  CONST32_GP, // For marking data present in GP.
40 
41  AT_GOT, // Index in GOT.
42  AT_PCREL, // Offset relative to PC.
43 
44  CALL, // Function call.
45  CALLnr, // Function call that does not return.
47 
48  RET_FLAG, // Return with a flag operand.
49  BARRIER, // Memory barrier.
50  JT, // Jump table.
51  CP, // Constant pool.
52 
58 
69  D2P, // Convert 8-byte value to 8-bit predicate register. [*]
70  P2D, // Convert 8-bit predicate register to 8-byte value. [*]
71  V2Q, // Convert HVX vector to a vector predicate reg. [*]
72  Q2V, // Convert vector predicate to an HVX vector. [*]
73  // [*] The equivalence is defined as "Q <=> (V != 0)",
74  // where the != operation compares bytes.
75  // Note: V != 0 is implemented as V >u 0.
80  TYPECAST, // No-op that's used to convert between different legal
81  // types in a register.
82  VALIGNADDR, // Align vector address: Op & -HwLen, except when it is
83  // an address in a vector load, then it's a no-op.
85  };
86 
87 } // end namespace HexagonISD
88 
89  class HexagonSubtarget;
90 
92  int VarArgsFrameOffset; // Frame offset to start of varargs area.
93  const HexagonTargetMachine &HTM;
94  const HexagonSubtarget &Subtarget;
95 
96  bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
97  const;
98  void promoteLdStType(MVT VT, MVT PromotedLdStVT);
99 
100  public:
101  explicit HexagonTargetLowering(const TargetMachine &TM,
102  const HexagonSubtarget &ST);
103 
104  bool isHVXVectorType(MVT Ty) const;
105 
106  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
107  /// for tail call optimization. Targets which want to do tail call
108  /// optimization should implement this function.
109  bool IsEligibleForTailCallOptimization(SDValue Callee,
110  CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
111  bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
112  const SmallVectorImpl<SDValue> &OutVals,
113  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
114 
115  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
116  MachineFunction &MF,
117  unsigned Intrinsic) const override;
118 
119  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
120  bool isTruncateFree(EVT VT1, EVT VT2) const override;
121 
122  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
123 
124  /// Return true if an FMA operation is faster than a pair of mul and add
125  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
126  /// method returns true (and FMAs are legal), otherwise fmuladd is
127  /// expanded to mul + add.
128  bool isFMAFasterThanFMulAndFAdd(EVT) const override;
129 
130  // Should we expand the build vector with shuffles?
131  bool shouldExpandBuildVectorWithShuffles(EVT VT,
132  unsigned DefinedValues) const override;
133 
134  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
135  TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
136  const override;
137 
138  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
139  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
140  SelectionDAG &DAG) const override;
141 
142  const char *getTargetNodeName(unsigned Opcode) const override;
143 
144  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
151  SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
152  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
156 
158  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
159  SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
161  SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
162  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
163  SDValue
164  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
166  const SDLoc &dl, SelectionDAG &DAG,
167  SmallVectorImpl<SDValue> &InVals) const override;
168  SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
169  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
170  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
172  SelectionDAG &DAG) const;
173  SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
174  SelectionDAG &DAG) const;
175  SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
176  SelectionDAG &DAG) const;
177  SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
178  GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
179  unsigned ReturnReg, unsigned char OperandFlags) const;
180  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
181 
183  SmallVectorImpl<SDValue> &InVals) const override;
184  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
185  CallingConv::ID CallConv, bool isVarArg,
187  const SDLoc &dl, SelectionDAG &DAG,
188  SmallVectorImpl<SDValue> &InVals,
189  const SmallVectorImpl<SDValue> &OutVals,
190  SDValue Callee) const;
191 
192  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
193  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
194  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
197 
198  bool CanLowerReturn(CallingConv::ID CallConv,
199  MachineFunction &MF, bool isVarArg,
201  LLVMContext &Context) const override;
202 
203  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
205  const SmallVectorImpl<SDValue> &OutVals,
206  const SDLoc &dl, SelectionDAG &DAG) const override;
207 
208  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
209 
210  /// If a physical register, this returns the register that receives the
211  /// exception address on entry to an EH pad.
212  unsigned
213  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
214  return Hexagon::R0;
215  }
216 
217  /// If a physical register, this returns the register that receives the
218  /// exception typeid on entry to a landing pad.
219  unsigned
220  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
221  return Hexagon::R1;
222  }
223 
224  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
225  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
226  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
227 
229  EVT VT) const override {
230  if (!VT.isVector())
231  return MVT::i1;
232  else
234  }
235 
236  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
239  SelectionDAG &DAG) const override;
240 
241  ConstraintType getConstraintType(StringRef Constraint) const override;
242 
243  std::pair<unsigned, const TargetRegisterClass *>
244  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
245  StringRef Constraint, MVT VT) const override;
246 
247  unsigned
248  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
249  if (ConstraintCode == "o")
251  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
252  }
253 
254  // Intrinsics
255  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
256  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
257  /// isLegalAddressingMode - Return true if the addressing mode represented
258  /// by AM is legal for this target, for a load/store of the specified type.
259  /// The type may be VoidTy, in which case only return true if the addressing
260  /// mode is legal for a load/store of any legal type.
261  /// TODO: Handle pre/postinc as well.
262  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
263  Type *Ty, unsigned AS,
264  Instruction *I = nullptr) const override;
265  /// Return true if folding a constant offset with the given GlobalAddress
266  /// is legal. It is frequently not legal in PIC relocation models.
267  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
268 
269  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
270 
271  /// isLegalICmpImmediate - Return true if the specified immediate is legal
272  /// icmp immediate, that is the target has icmp instructions which can
273  /// compare a register against the immediate without having to materialize
274  /// the immediate into a register.
275  bool isLegalICmpImmediate(int64_t Imm) const override;
276 
277  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
278  unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
279  MachineFunction &MF) const override;
280 
281  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
282  unsigned Align, bool *Fast) const override;
283 
284  /// Returns relocation base for the given PIC jumptable.
285  SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
286  const override;
287 
288  // Handling of atomic RMW instructions.
289  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
290  AtomicOrdering Ord) const override;
291  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
292  Value *Addr, AtomicOrdering Ord) const override;
293  AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
294  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
295  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
296 
299  return AtomicExpansionKind::LLSC;
300  }
301 
302  private:
303  void initializeHVXLowering();
304  std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
305 
306  bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
307  SelectionDAG &DAG,
308  MutableArrayRef<ConstantInt*> Consts) const;
309  SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
310  SelectionDAG &DAG) const;
311  SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
312  SelectionDAG &DAG) const;
313  SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
314  MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
315  SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
316  const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
317  SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
318  SelectionDAG &DAG) const;
319  SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
320  SelectionDAG &DAG) const;
321  SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
322 
323  bool isUndef(SDValue Op) const {
324  if (Op.isMachineOpcode())
325  return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
326  return Op.getOpcode() == ISD::UNDEF;
327  }
328  SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
329  ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
330  SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
331  return SDValue(N, 0);
332  }
333  SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
334 
335  using VectorPair = std::pair<SDValue, SDValue>;
336  using TypePair = std::pair<MVT, MVT>;
337 
338  SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
339  const SDLoc &dl, SelectionDAG &DAG) const;
340 
341  MVT ty(SDValue Op) const {
342  return Op.getValueType().getSimpleVT();
343  }
344  TypePair ty(const VectorPair &Ops) const {
345  return { Ops.first.getValueType().getSimpleVT(),
346  Ops.second.getValueType().getSimpleVT() };
347  }
348  MVT tyScalar(MVT Ty) const {
349  if (!Ty.isVector())
350  return Ty;
351  return MVT::getIntegerVT(Ty.getSizeInBits());
352  }
353  MVT tyVector(MVT Ty, MVT ElemTy) const {
354  if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
355  return Ty;
356  unsigned TyWidth = Ty.getSizeInBits();
357  unsigned ElemWidth = ElemTy.getSizeInBits();
358  assert((TyWidth % ElemWidth) == 0);
359  return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
360  }
361 
362  MVT typeJoin(const TypePair &Tys) const;
363  TypePair typeSplit(MVT Ty) const;
364  MVT typeExtElem(MVT VecTy, unsigned Factor) const;
365  MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
366 
367  SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
368  SelectionDAG &DAG) const;
369  VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
370  SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
371 
372  bool isHvxSingleTy(MVT Ty) const;
373  bool isHvxPairTy(MVT Ty) const;
374  SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
375  SelectionDAG &DAG) const;
376  SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
377  SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
378  ArrayRef<int> Mask, SelectionDAG &DAG) const;
379 
380  SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
381  MVT VecTy, SelectionDAG &DAG) const;
382  SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
383  MVT VecTy, SelectionDAG &DAG) const;
384  SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
385  unsigned BitBytes, bool ZeroFill,
386  SelectionDAG &DAG) const;
387  SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
388  MVT ResTy, SelectionDAG &DAG) const;
389  SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
390  MVT ResTy, SelectionDAG &DAG) const;
391  SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
392  const SDLoc &dl, SelectionDAG &DAG) const;
393  SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
394  const SDLoc &dl, SelectionDAG &DAG) const;
395  SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
396  MVT ResTy, SelectionDAG &DAG) const;
397  SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
398  MVT ResTy, SelectionDAG &DAG) const;
399  SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
400  const SDLoc &dl, SelectionDAG &DAG) const;
401  SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
402  const SDLoc &dl, SelectionDAG &DAG) const;
403  SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
404  bool ZeroExt, SelectionDAG &DAG) const;
405 
406  SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
407  SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
408  SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
409  SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
410  SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
411  SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
412 
413  SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
414  SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
415  SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
416  SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
417  SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
418  SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
419  SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
420  SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
421  SDValue LowerHvxUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
422 
423  SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
424  SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
425 
426  std::pair<const TargetRegisterClass*, uint8_t>
427  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
428  const override;
429 
430  bool isHvxOperation(SDValue Op) const;
431  SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
432  };
433 
434 } // end namespace llvm
435 
436 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
uint64_t CallInst * C
static MVT getIntegerVT(unsigned BitWidth)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static MVT getVectorVT(MVT VT, unsigned NumElements)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
bool isVector() const
Return true if this is a vector value type.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This class represents a function call, abstracting a target machine&#39;s calling convention.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Function Alias Analysis Results
static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG)
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
static unsigned getInt(StringRef R)
Get an unsigned integer, including error checks.
Definition: DataLayout.cpp:213
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:707
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
unsigned getSizeInBits() const
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
An instruction for storing to memory.
Definition: Instructions.h:306
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
MVT getVectorElementType() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:178
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:291
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
bool isMachineOpcode() const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
This is an important base class in LLVM.
Definition: Constant.h:42
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
unsigned getMachineOpcode() const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
static bool isUndef(ArrayRef< int > Mask)
static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
static Value * insertVector(IRBuilderTy &IRB, Value *Old, Value *V, unsigned BeginIndex, const Twine &Name)
Definition: SROA.cpp:2147
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
unsigned getOpcode() const
static Value * extractVector(IRBuilderTy &IRB, Value *V, unsigned BeginIndex, unsigned EndIndex, const Twine &Name)
Definition: SROA.cpp:2121
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:873