LLVM  6.0.0svn
Macros | Functions | Variables
HexagonInstrInfo.cpp File Reference
#include "HexagonInstrInfo.h"
#include "Hexagon.h"
#include "HexagonFrameLowering.h"
#include "HexagonHazardRecognizer.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <cctype>
#include <cstdint>
#include <cstring>
#include <iterator>
#include <string>
#include <utility>
#include "HexagonDepTimingClasses.h"
#include "HexagonGenDFAPacketizer.inc"
#include "HexagonGenInstrInfo.inc"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "hexagon-instrinfo"
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_INSTRMAP_INFO
 

Functions

static bool isIntRegForSubInst (unsigned Reg)
 
static bool isDblRegForSubInst (unsigned Reg, const HexagonRegisterInfo &HRI)
 
static unsigned nonDbgMICount (MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
 Calculate number of instructions excluding the debug instructions. More...
 
static MachineInstrfindLoopInstr (MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
 Find the hardware loop instruction used to set-up the specified loop. More...
 
static void parseOperands (const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
 Gather register def/uses from MI. More...
 
static bool isDuplexPairMatch (unsigned Ga, unsigned Gb)
 
static void getLiveRegsAt (LivePhysRegs &Regs, const MachineInstr &MI)
 

Variables

cl::opt< boolScheduleInlineAsm ("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))
 
static cl::opt< boolEnableBranchPrediction ("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
 
static cl::opt< boolDisableNVSchedule ("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
 
static cl::opt< boolEnableTimingClassLatency ("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
 
static cl::opt< boolEnableALUForwarding ("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
 
static cl::opt< boolEnableACCForwarding ("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
 
static cl::opt< boolBranchRelaxAsmLarge ("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
 
static cl::opt< boolUseDFAHazardRec ("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
 
const int Hexagon_MEMW_OFFSET_MAX = 4095
 Constants for Hexagon instructions. More...
 
const int Hexagon_MEMW_OFFSET_MIN = -4096
 
const int Hexagon_MEMD_OFFSET_MAX = 8191
 
const int Hexagon_MEMD_OFFSET_MIN = -8192
 
const int Hexagon_MEMH_OFFSET_MAX = 2047
 
const int Hexagon_MEMH_OFFSET_MIN = -2048
 
const int Hexagon_MEMB_OFFSET_MAX = 1023
 
const int Hexagon_MEMB_OFFSET_MIN = -1024
 
const int Hexagon_ADDI_OFFSET_MAX = 32767
 
const int Hexagon_ADDI_OFFSET_MIN = -32768
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "hexagon-instrinfo"

Definition at line 65 of file HexagonInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 67 of file HexagonInstrInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 68 of file HexagonInstrInfo.cpp.

Function Documentation

◆ findLoopInstr()

static MachineInstr* findLoopInstr ( MachineBasicBlock BB,
unsigned  EndLoopOp,
MachineBasicBlock TargetBB,
SmallPtrSet< MachineBasicBlock *, 8 > &  Visited 
)
static

Find the hardware loop instruction used to set-up the specified loop.

On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.

Definition at line 147 of file HexagonInstrInfo.cpp.

References E, I, llvm::SmallPtrSetImpl< PtrType >::insert(), and llvm::MachineBasicBlock::predecessors().

Referenced by llvm::HexagonInstrInfo::insertBranch(), and llvm::HexagonInstrInfo::reduceLoopCount().

◆ getLiveRegsAt()

static void getLiveRegsAt ( LivePhysRegs Regs,
const MachineInstr MI 
)
static

◆ isDblRegForSubInst()

static bool isDblRegForSubInst ( unsigned  Reg,
const HexagonRegisterInfo HRI 
)
static

◆ isDuplexPairMatch()

static bool isDuplexPairMatch ( unsigned  Ga,
unsigned  Gb 
)
static

◆ isIntRegForSubInst()

static bool isIntRegForSubInst ( unsigned  Reg)
static

◆ nonDbgMICount()

Calculate number of instructions excluding the debug instructions.

Definition at line 133 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::nonDbgBBSize(), and llvm::HexagonInstrInfo::nonDbgBundleSize().

◆ parseOperands()

static void parseOperands ( const MachineInstr MI,
SmallVector< unsigned, 4 > &  Defs,
SmallVector< unsigned, 8 > &  Uses 
)
inlinestatic

Variable Documentation

◆ BranchRelaxAsmLarge

cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
static

◆ DisableNVSchedule

cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
static

◆ EnableACCForwarding

cl::opt<bool> EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
static

◆ EnableALUForwarding

cl::opt<bool> EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
static

◆ EnableBranchPrediction

cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
static

◆ EnableTimingClassLatency

cl::opt<bool> EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
static

◆ Hexagon_ADDI_OFFSET_MAX

const int Hexagon_ADDI_OFFSET_MAX = 32767

Definition at line 112 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_ADDI_OFFSET_MIN

const int Hexagon_ADDI_OFFSET_MIN = -32768

Definition at line 113 of file HexagonInstrInfo.cpp.

◆ Hexagon_MEMB_OFFSET_MAX

const int Hexagon_MEMB_OFFSET_MAX = 1023

Definition at line 110 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMB_OFFSET_MIN

const int Hexagon_MEMB_OFFSET_MIN = -1024

Definition at line 111 of file HexagonInstrInfo.cpp.

◆ Hexagon_MEMD_OFFSET_MAX

const int Hexagon_MEMD_OFFSET_MAX = 8191

Definition at line 106 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMD_OFFSET_MIN

const int Hexagon_MEMD_OFFSET_MIN = -8192

Definition at line 107 of file HexagonInstrInfo.cpp.

◆ Hexagon_MEMH_OFFSET_MAX

const int Hexagon_MEMH_OFFSET_MAX = 2047

Definition at line 108 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMH_OFFSET_MIN

const int Hexagon_MEMH_OFFSET_MIN = -2048

Definition at line 109 of file HexagonInstrInfo.cpp.

◆ Hexagon_MEMW_OFFSET_MAX

const int Hexagon_MEMW_OFFSET_MAX = 4095

Constants for Hexagon instructions.

Definition at line 104 of file HexagonInstrInfo.cpp.

Referenced by llvm::HexagonInstrInfo::isValidOffset().

◆ Hexagon_MEMW_OFFSET_MIN

const int Hexagon_MEMW_OFFSET_MIN = -4096

Definition at line 105 of file HexagonInstrInfo.cpp.

◆ ScheduleInlineAsm

cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))

◆ UseDFAHazardRec

cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
static