LLVM  8.0.0svn
HexagonMCDuplexInfo.cpp
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1 //===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements duplexing of instructions to reduce code size
11 //
12 //===----------------------------------------------------------------------===//
13 
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/Debug.h"
25 #include <cassert>
26 #include <cstdint>
27 #include <iterator>
28 #include <map>
29 #include <utility>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-mcduplex-info"
35 
36 // pair table of subInstructions with opcodes
37 static const std::pair<unsigned, unsigned> opcodeData[] = {
38  std::make_pair((unsigned)SA1_addi, 0),
39  std::make_pair((unsigned)SA1_addrx, 6144),
40  std::make_pair((unsigned)SA1_addsp, 3072),
41  std::make_pair((unsigned)SA1_and1, 4608),
42  std::make_pair((unsigned)SA1_clrf, 6768),
43  std::make_pair((unsigned)SA1_clrfnew, 6736),
44  std::make_pair((unsigned)SA1_clrt, 6752),
45  std::make_pair((unsigned)SA1_clrtnew, 6720),
46  std::make_pair((unsigned)SA1_cmpeqi, 6400),
47  std::make_pair((unsigned)SA1_combine0i, 7168),
48  std::make_pair((unsigned)SA1_combine1i, 7176),
49  std::make_pair((unsigned)SA1_combine2i, 7184),
50  std::make_pair((unsigned)SA1_combine3i, 7192),
51  std::make_pair((unsigned)SA1_combinerz, 7432),
52  std::make_pair((unsigned)SA1_combinezr, 7424),
53  std::make_pair((unsigned)SA1_dec, 4864),
54  std::make_pair((unsigned)SA1_inc, 4352),
55  std::make_pair((unsigned)SA1_seti, 2048),
56  std::make_pair((unsigned)SA1_setin1, 6656),
57  std::make_pair((unsigned)SA1_sxtb, 5376),
58  std::make_pair((unsigned)SA1_sxth, 5120),
59  std::make_pair((unsigned)SA1_tfr, 4096),
60  std::make_pair((unsigned)SA1_zxtb, 5888),
61  std::make_pair((unsigned)SA1_zxth, 5632),
62  std::make_pair((unsigned)SL1_loadri_io, 0),
63  std::make_pair((unsigned)SL1_loadrub_io, 4096),
64  std::make_pair((unsigned)SL2_deallocframe, 7936),
65  std::make_pair((unsigned)SL2_jumpr31, 8128),
66  std::make_pair((unsigned)SL2_jumpr31_f, 8133),
67  std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),
68  std::make_pair((unsigned)SL2_jumpr31_t, 8132),
69  std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),
70  std::make_pair((unsigned)SL2_loadrb_io, 4096),
71  std::make_pair((unsigned)SL2_loadrd_sp, 7680),
72  std::make_pair((unsigned)SL2_loadrh_io, 0),
73  std::make_pair((unsigned)SL2_loadri_sp, 7168),
74  std::make_pair((unsigned)SL2_loadruh_io, 2048),
75  std::make_pair((unsigned)SL2_return, 8000),
76  std::make_pair((unsigned)SL2_return_f, 8005),
77  std::make_pair((unsigned)SL2_return_fnew, 8007),
78  std::make_pair((unsigned)SL2_return_t, 8004),
79  std::make_pair((unsigned)SL2_return_tnew, 8006),
80  std::make_pair((unsigned)SS1_storeb_io, 4096),
81  std::make_pair((unsigned)SS1_storew_io, 0),
82  std::make_pair((unsigned)SS2_allocframe, 7168),
83  std::make_pair((unsigned)SS2_storebi0, 4608),
84  std::make_pair((unsigned)SS2_storebi1, 4864),
85  std::make_pair((unsigned)SS2_stored_sp, 2560),
86  std::make_pair((unsigned)SS2_storeh_io, 0),
87  std::make_pair((unsigned)SS2_storew_sp, 2048),
88  std::make_pair((unsigned)SS2_storewi0, 4096),
89  std::make_pair((unsigned)SS2_storewi1, 4352)};
90 
91 bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) {
92  switch (Ga) {
94  default:
95  return false;
96  case HexagonII::HSIG_L1:
97  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
98  case HexagonII::HSIG_L2:
99  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
100  Gb == HexagonII::HSIG_A);
101  case HexagonII::HSIG_S1:
102  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
103  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
104  case HexagonII::HSIG_S2:
105  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
106  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
107  Gb == HexagonII::HSIG_A);
108  case HexagonII::HSIG_A:
109  return (Gb == HexagonII::HSIG_A);
111  return (Gb == HexagonII::HSIG_Compound);
112  }
113  return false;
114 }
115 
116 unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
117  switch (Ga) {
119  default:
120  break;
121  case HexagonII::HSIG_L1:
122  switch (Gb) {
123  default:
124  break;
125  case HexagonII::HSIG_L1:
126  return 0;
127  case HexagonII::HSIG_A:
128  return 0x4;
129  }
130  break;
131  case HexagonII::HSIG_L2:
132  switch (Gb) {
133  default:
134  break;
135  case HexagonII::HSIG_L1:
136  return 0x1;
137  case HexagonII::HSIG_L2:
138  return 0x2;
139  case HexagonII::HSIG_A:
140  return 0x5;
141  }
142  break;
143  case HexagonII::HSIG_S1:
144  switch (Gb) {
145  default:
146  break;
147  case HexagonII::HSIG_L1:
148  return 0x8;
149  case HexagonII::HSIG_L2:
150  return 0x9;
151  case HexagonII::HSIG_S1:
152  return 0xA;
153  case HexagonII::HSIG_A:
154  return 0x6;
155  }
156  break;
157  case HexagonII::HSIG_S2:
158  switch (Gb) {
159  default:
160  break;
161  case HexagonII::HSIG_L1:
162  return 0xC;
163  case HexagonII::HSIG_L2:
164  return 0xD;
165  case HexagonII::HSIG_S1:
166  return 0xB;
167  case HexagonII::HSIG_S2:
168  return 0xE;
169  case HexagonII::HSIG_A:
170  return 0x7;
171  }
172  break;
173  case HexagonII::HSIG_A:
174  switch (Gb) {
175  default:
176  break;
177  case HexagonII::HSIG_A:
178  return 0x3;
179  }
180  break;
182  switch (Gb) {
184  return 0xFFFFFFFF;
185  }
186  break;
187  }
188  return 0xFFFFFFFF;
189 }
190 
192  unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
193 
194  switch (MCI.getOpcode()) {
195  default:
196  return HexagonII::HSIG_None;
197  //
198  // Group L1:
199  //
200  // Rd = memw(Rs+#u4:2)
201  // Rd = memub(Rs+#u4:0)
202  case Hexagon::L2_loadri_io:
203  DstReg = MCI.getOperand(0).getReg();
204  SrcReg = MCI.getOperand(1).getReg();
205  // Special case this one from Group L2.
206  // Rd = memw(r29+#u5:2)
208  if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
209  Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
210  return HexagonII::HSIG_L2;
211  }
212  // Rd = memw(Rs+#u4:2)
214  inRange<4, 2>(MCI, 2)) {
215  return HexagonII::HSIG_L1;
216  }
217  }
218  break;
219  case Hexagon::L2_loadrub_io:
220  // Rd = memub(Rs+#u4:0)
221  DstReg = MCI.getOperand(0).getReg();
222  SrcReg = MCI.getOperand(1).getReg();
225  inRange<4>(MCI, 2)) {
226  return HexagonII::HSIG_L1;
227  }
228  break;
229  //
230  // Group L2:
231  //
232  // Rd = memh/memuh(Rs+#u3:1)
233  // Rd = memb(Rs+#u3:0)
234  // Rd = memw(r29+#u5:2) - Handled above.
235  // Rdd = memd(r29+#u5:3)
236  // deallocframe
237  // [if ([!]p0[.new])] dealloc_return
238  // [if ([!]p0[.new])] jumpr r31
239  case Hexagon::L2_loadrh_io:
240  case Hexagon::L2_loadruh_io:
241  // Rd = memh/memuh(Rs+#u3:1)
242  DstReg = MCI.getOperand(0).getReg();
243  SrcReg = MCI.getOperand(1).getReg();
246  inRange<3, 1>(MCI, 2)) {
247  return HexagonII::HSIG_L2;
248  }
249  break;
250  case Hexagon::L2_loadrb_io:
251  // Rd = memb(Rs+#u3:0)
252  DstReg = MCI.getOperand(0).getReg();
253  SrcReg = MCI.getOperand(1).getReg();
256  inRange<3>(MCI, 2)) {
257  return HexagonII::HSIG_L2;
258  }
259  break;
260  case Hexagon::L2_loadrd_io:
261  // Rdd = memd(r29+#u5:3)
262  DstReg = MCI.getOperand(0).getReg();
263  SrcReg = MCI.getOperand(1).getReg();
265  HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
266  inRange<5, 3>(MCI, 2)) {
267  return HexagonII::HSIG_L2;
268  }
269  break;
270 
271  case Hexagon::L4_return:
272  case Hexagon::L2_deallocframe:
273  return HexagonII::HSIG_L2;
274 
275  case Hexagon::EH_RETURN_JMPR:
276  case Hexagon::J2_jumpr:
277  case Hexagon::PS_jmpret:
278  // jumpr r31
279  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
280  DstReg = MCI.getOperand(0).getReg();
281  if (Hexagon::R31 == DstReg)
282  return HexagonII::HSIG_L2;
283  break;
284 
285  case Hexagon::J2_jumprt:
286  case Hexagon::J2_jumprf:
287  case Hexagon::J2_jumprtnew:
288  case Hexagon::J2_jumprfnew:
289  case Hexagon::J2_jumprtnewpt:
290  case Hexagon::J2_jumprfnewpt:
291  case Hexagon::PS_jmprett:
292  case Hexagon::PS_jmpretf:
293  case Hexagon::PS_jmprettnew:
294  case Hexagon::PS_jmpretfnew:
295  case Hexagon::PS_jmprettnewpt:
296  case Hexagon::PS_jmpretfnewpt:
297  DstReg = MCI.getOperand(1).getReg();
298  SrcReg = MCI.getOperand(0).getReg();
299  // [if ([!]p0[.new])] jumpr r31
300  if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) &&
301  (Hexagon::R31 == DstReg)) {
302  return HexagonII::HSIG_L2;
303  }
304  break;
305  case Hexagon::L4_return_t:
306  case Hexagon::L4_return_f:
307  case Hexagon::L4_return_tnew_pnt:
308  case Hexagon::L4_return_fnew_pnt:
309  case Hexagon::L4_return_tnew_pt:
310  case Hexagon::L4_return_fnew_pt:
311  // [if ([!]p0[.new])] dealloc_return
312  SrcReg = MCI.getOperand(1).getReg();
313  if (Hexagon::P0 == SrcReg) {
314  return HexagonII::HSIG_L2;
315  }
316  break;
317  //
318  // Group S1:
319  //
320  // memw(Rs+#u4:2) = Rt
321  // memb(Rs+#u4:0) = Rt
322  case Hexagon::S2_storeri_io:
323  // Special case this one from Group S2.
324  // memw(r29+#u5:2) = Rt
325  Src1Reg = MCI.getOperand(0).getReg();
326  Src2Reg = MCI.getOperand(2).getReg();
327  if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
329  Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
330  return HexagonII::HSIG_S2;
331  }
332  // memw(Rs+#u4:2) = Rt
335  inRange<4, 2>(MCI, 1)) {
336  return HexagonII::HSIG_S1;
337  }
338  break;
339  case Hexagon::S2_storerb_io:
340  // memb(Rs+#u4:0) = Rt
341  Src1Reg = MCI.getOperand(0).getReg();
342  Src2Reg = MCI.getOperand(2).getReg();
345  inRange<4>(MCI, 1)) {
346  return HexagonII::HSIG_S1;
347  }
348  break;
349  //
350  // Group S2:
351  //
352  // memh(Rs+#u3:1) = Rt
353  // memw(r29+#u5:2) = Rt
354  // memd(r29+#s6:3) = Rtt
355  // memw(Rs+#u4:2) = #U1
356  // memb(Rs+#u4) = #U1
357  // allocframe(#u5:3)
358  case Hexagon::S2_storerh_io:
359  // memh(Rs+#u3:1) = Rt
360  Src1Reg = MCI.getOperand(0).getReg();
361  Src2Reg = MCI.getOperand(2).getReg();
364  inRange<3, 1>(MCI, 1)) {
365  return HexagonII::HSIG_S2;
366  }
367  break;
368  case Hexagon::S2_storerd_io:
369  // memd(r29+#s6:3) = Rtt
370  Src1Reg = MCI.getOperand(0).getReg();
371  Src2Reg = MCI.getOperand(2).getReg();
373  HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg &&
374  inSRange<6, 3>(MCI, 1)) {
375  return HexagonII::HSIG_S2;
376  }
377  break;
378  case Hexagon::S4_storeiri_io:
379  // memw(Rs+#u4:2) = #U1
380  Src1Reg = MCI.getOperand(0).getReg();
382  inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {
383  return HexagonII::HSIG_S2;
384  }
385  break;
386  case Hexagon::S4_storeirb_io:
387  // memb(Rs+#u4) = #U1
388  Src1Reg = MCI.getOperand(0).getReg();
390  inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {
391  return HexagonII::HSIG_S2;
392  }
393  break;
394  case Hexagon::S2_allocframe:
395  if (inRange<5, 3>(MCI, 2))
396  return HexagonII::HSIG_S2;
397  break;
398  //
399  // Group A:
400  //
401  // Rx = add(Rx,#s7)
402  // Rd = Rs
403  // Rd = #u6
404  // Rd = #-1
405  // if ([!]P0[.new]) Rd = #0
406  // Rd = add(r29,#u6:2)
407  // Rx = add(Rx,Rs)
408  // P0 = cmp.eq(Rs,#u2)
409  // Rdd = combine(#0,Rs)
410  // Rdd = combine(Rs,#0)
411  // Rdd = combine(#u2,#U2)
412  // Rd = add(Rs,#1)
413  // Rd = add(Rs,#-1)
414  // Rd = sxth/sxtb/zxtb/zxth(Rs)
415  // Rd = and(Rs,#1)
416  case Hexagon::A2_addi:
417  DstReg = MCI.getOperand(0).getReg();
418  SrcReg = MCI.getOperand(1).getReg();
420  // Rd = add(r29,#u6:2)
421  if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
422  inRange<6, 2>(MCI, 2)) {
423  return HexagonII::HSIG_A;
424  }
425  // Rx = add(Rx,#s7)
426  if (DstReg == SrcReg) {
427  return HexagonII::HSIG_A;
428  }
429  // Rd = add(Rs,#1)
430  // Rd = add(Rs,#-1)
432  (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == -1)) {
433  return HexagonII::HSIG_A;
434  }
435  }
436  break;
437  case Hexagon::A2_add:
438  // Rx = add(Rx,Rs)
439  DstReg = MCI.getOperand(0).getReg();
440  Src1Reg = MCI.getOperand(1).getReg();
441  Src2Reg = MCI.getOperand(2).getReg();
442  if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
444  return HexagonII::HSIG_A;
445  }
446  break;
447  case Hexagon::A2_andir:
448  DstReg = MCI.getOperand(0).getReg();
449  SrcReg = MCI.getOperand(1).getReg();
452  (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == 255)) {
453  return HexagonII::HSIG_A;
454  }
455  break;
456  case Hexagon::A2_tfr:
457  // Rd = Rs
458  DstReg = MCI.getOperand(0).getReg();
459  SrcReg = MCI.getOperand(1).getReg();
462  return HexagonII::HSIG_A;
463  }
464  break;
465  case Hexagon::A2_tfrsi:
466  DstReg = MCI.getOperand(0).getReg();
467 
469  return HexagonII::HSIG_A;
470  }
471  break;
472  case Hexagon::C2_cmoveit:
473  case Hexagon::C2_cmovenewit:
474  case Hexagon::C2_cmoveif:
475  case Hexagon::C2_cmovenewif:
476  // if ([!]P0[.new]) Rd = #0
477  // Actual form:
478  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
479  DstReg = MCI.getOperand(0).getReg(); // Rd
480  PredReg = MCI.getOperand(1).getReg(); // P0
482  Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
483  return HexagonII::HSIG_A;
484  }
485  break;
486  case Hexagon::C2_cmpeqi:
487  // P0 = cmp.eq(Rs,#u2)
488  DstReg = MCI.getOperand(0).getReg();
489  SrcReg = MCI.getOperand(1).getReg();
490  if (Hexagon::P0 == DstReg &&
492  inRange<2>(MCI, 2)) {
493  return HexagonII::HSIG_A;
494  }
495  break;
496  case Hexagon::A2_combineii:
497  case Hexagon::A4_combineii:
498  // Rdd = combine(#u2,#U2)
499  DstReg = MCI.getOperand(0).getReg();
501  inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {
502  return HexagonII::HSIG_A;
503  }
504  break;
505  case Hexagon::A4_combineri:
506  // Rdd = combine(Rs,#0)
507  DstReg = MCI.getOperand(0).getReg();
508  SrcReg = MCI.getOperand(1).getReg();
511  minConstant(MCI, 2) == 0) {
512  return HexagonII::HSIG_A;
513  }
514  break;
515  case Hexagon::A4_combineir:
516  // Rdd = combine(#0,Rs)
517  DstReg = MCI.getOperand(0).getReg();
518  SrcReg = MCI.getOperand(2).getReg();
521  minConstant(MCI, 1) == 0) {
522  return HexagonII::HSIG_A;
523  }
524  break;
525  case Hexagon::A2_sxtb:
526  case Hexagon::A2_sxth:
527  case Hexagon::A2_zxtb:
528  case Hexagon::A2_zxth:
529  // Rd = sxth/sxtb/zxtb/zxth(Rs)
530  DstReg = MCI.getOperand(0).getReg();
531  SrcReg = MCI.getOperand(1).getReg();
534  return HexagonII::HSIG_A;
535  }
536  break;
537  }
538 
539  return HexagonII::HSIG_None;
540 }
541 
543  unsigned DstReg, SrcReg;
544  switch (potentialDuplex.getOpcode()) {
545  case Hexagon::A2_addi:
546  // testing for case of: Rx = add(Rx,#s7)
547  DstReg = potentialDuplex.getOperand(0).getReg();
548  SrcReg = potentialDuplex.getOperand(1).getReg();
549  if (DstReg == SrcReg && HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
550  int64_t Value;
551  if (!potentialDuplex.getOperand(2).getExpr()->evaluateAsAbsolute(Value))
552  return true;
553  if (!isShiftedInt<7, 0>(Value))
554  return true;
555  }
556  break;
557  case Hexagon::A2_tfrsi:
558  DstReg = potentialDuplex.getOperand(0).getReg();
559 
561  int64_t Value;
562  if (!potentialDuplex.getOperand(1).getExpr()->evaluateAsAbsolute(Value))
563  return true;
564  // Check for case of Rd = #-1.
565  if (Value == -1)
566  return false;
567  // Check for case of Rd = #u6.
568  if (!isShiftedUInt<6, 0>(Value))
569  return true;
570  }
571  break;
572  default:
573  break;
574  }
575  return false;
576 }
577 
578 /// non-Symmetrical. See if these two instructions are fit for duplex pair.
580  MCInst const &MIa, bool ExtendedA,
581  MCInst const &MIb, bool ExtendedB,
582  bool bisReversable,
583  MCSubtargetInfo const &STI) {
584  // Slot 1 cannot be extended in duplexes PRM 10.5
585  if (ExtendedA)
586  return false;
587  // Only A2_addi and A2_tfrsi can be extended in duplex form PRM 10.5
588  if (ExtendedB) {
589  unsigned Opcode = MIb.getOpcode();
590  if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
591  return false;
592  }
593  unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa),
595 
596  static std::map<unsigned, unsigned> subinstOpcodeMap(std::begin(opcodeData),
598 
599  // If a duplex contains 2 insns in the same group, the insns must be
600  // ordered such that the numerically smaller opcode is in slot 1.
601  if ((MIaG != HexagonII::HSIG_None) && (MIaG == MIbG) && bisReversable) {
604 
605  unsigned zeroedSubInstS0 =
606  subinstOpcodeMap.find(SubInst0.getOpcode())->second;
607  unsigned zeroedSubInstS1 =
608  subinstOpcodeMap.find(SubInst1.getOpcode())->second;
609 
610  if (zeroedSubInstS0 < zeroedSubInstS1)
611  // subinstS0 (maps to slot 0) must be greater than
612  // subinstS1 (maps to slot 1)
613  return false;
614  }
615 
616  // allocframe must always be in slot 0
617  if (MIb.getOpcode() == Hexagon::S2_allocframe)
618  return false;
619 
620  if ((MIaG != HexagonII::HSIG_None) && (MIbG != HexagonII::HSIG_None)) {
621  // Prevent 2 instructions with extenders from duplexing
622  // Note that MIb (slot1) can be extended and MIa (slot0)
623  // can never be extended
624  if (subInstWouldBeExtended(MIa))
625  return false;
626 
627  // If duplexing produces an extender, but the original did not
628  // have an extender, do not duplex.
629  if (subInstWouldBeExtended(MIb) && !ExtendedB)
630  return false;
631  }
632 
633  // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
634  if (MIbG == HexagonII::HSIG_L2) {
635  if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() &&
636  (MIb.getOperand(1).getReg() == Hexagon::R31))
637  return false;
638  if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() &&
639  (MIb.getOperand(0).getReg() == Hexagon::R31))
640  return false;
641  }
642 
643  if (STI.getCPU().equals_lower("hexagonv5") ||
644  STI.getCPU().equals_lower("hexagonv55") ||
645  STI.getCPU().equals_lower("hexagonv60")) {
646  // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb);
647  // therefore, not duplexable if slot 1 is a store, and slot 0 is not.
648  if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) {
649  if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2))
650  return false;
651  }
652  }
653 
654  return (isDuplexPairMatch(MIaG, MIbG));
655 }
656 
657 /// Symmetrical. See if these two instructions are fit for duplex pair.
658 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
659  unsigned MIaG = getDuplexCandidateGroup(MIa),
660  MIbG = getDuplexCandidateGroup(MIb);
661  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
662 }
663 
664 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
665  unsigned opNum) {
666  if (Inst.getOperand(opNum).isReg()) {
667  switch (Inst.getOperand(opNum).getReg()) {
668  default:
669  llvm_unreachable("Not Duplexable Register");
670  break;
671  case Hexagon::R0:
672  case Hexagon::R1:
673  case Hexagon::R2:
674  case Hexagon::R3:
675  case Hexagon::R4:
676  case Hexagon::R5:
677  case Hexagon::R6:
678  case Hexagon::R7:
679  case Hexagon::D0:
680  case Hexagon::D1:
681  case Hexagon::D2:
682  case Hexagon::D3:
683  case Hexagon::R16:
684  case Hexagon::R17:
685  case Hexagon::R18:
686  case Hexagon::R19:
687  case Hexagon::R20:
688  case Hexagon::R21:
689  case Hexagon::R22:
690  case Hexagon::R23:
691  case Hexagon::D8:
692  case Hexagon::D9:
693  case Hexagon::D10:
694  case Hexagon::D11:
695  case Hexagon::P0:
696  subInstPtr.addOperand(Inst.getOperand(opNum));
697  break;
698  }
699  } else
700  subInstPtr.addOperand(Inst.getOperand(opNum));
701 }
702 
704  MCInst Result;
705  bool Absolute;
706  int64_t Value;
707  switch (Inst.getOpcode()) {
708  default:
709  // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
710  llvm_unreachable("Unimplemented subinstruction \n");
711  break;
712  case Hexagon::A2_addi:
713  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
714  if (Absolute) {
715  if (Value == 1) {
716  Result.setOpcode(Hexagon::SA1_inc);
717  addOps(Result, Inst, 0);
718  addOps(Result, Inst, 1);
719  break;
720  } // 1,2 SUBInst $Rd = add($Rs, #1)
721  if (Value == -1) {
722  Result.setOpcode(Hexagon::SA1_dec);
723  addOps(Result, Inst, 0);
724  addOps(Result, Inst, 1);
725  addOps(Result, Inst, 2);
726  break;
727  } // 1,2 SUBInst $Rd = add($Rs,#-1)
728  if (Inst.getOperand(1).getReg() == Hexagon::R29) {
729  Result.setOpcode(Hexagon::SA1_addsp);
730  addOps(Result, Inst, 0);
731  addOps(Result, Inst, 2);
732  break;
733  } // 1,3 SUBInst $Rd = add(r29, #$u6_2)
734  }
735  Result.setOpcode(Hexagon::SA1_addi);
736  addOps(Result, Inst, 0);
737  addOps(Result, Inst, 1);
738  addOps(Result, Inst, 2);
739  break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
740  case Hexagon::A2_add:
741  Result.setOpcode(Hexagon::SA1_addrx);
742  addOps(Result, Inst, 0);
743  addOps(Result, Inst, 1);
744  addOps(Result, Inst, 2);
745  break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
746  case Hexagon::S2_allocframe:
747  Result.setOpcode(Hexagon::SS2_allocframe);
748  addOps(Result, Inst, 2);
749  break; // 1 SUBInst allocframe(#$u5_3)
750  case Hexagon::A2_andir:
751  if (minConstant(Inst, 2) == 255) {
752  Result.setOpcode(Hexagon::SA1_zxtb);
753  addOps(Result, Inst, 0);
754  addOps(Result, Inst, 1);
755  break; // 1,2 $Rd = and($Rs, #255)
756  } else {
757  Result.setOpcode(Hexagon::SA1_and1);
758  addOps(Result, Inst, 0);
759  addOps(Result, Inst, 1);
760  break; // 1,2 SUBInst $Rd = and($Rs, #1)
761  }
762  case Hexagon::C2_cmpeqi:
763  Result.setOpcode(Hexagon::SA1_cmpeqi);
764  addOps(Result, Inst, 1);
765  addOps(Result, Inst, 2);
766  break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
767  case Hexagon::A4_combineii:
768  case Hexagon::A2_combineii:
769  Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
770  assert(Absolute);(void)Absolute;
771  if (Value == 1) {
772  Result.setOpcode(Hexagon::SA1_combine1i);
773  addOps(Result, Inst, 0);
774  addOps(Result, Inst, 2);
775  break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
776  }
777  if (Value == 3) {
778  Result.setOpcode(Hexagon::SA1_combine3i);
779  addOps(Result, Inst, 0);
780  addOps(Result, Inst, 2);
781  break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
782  }
783  if (Value == 0) {
784  Result.setOpcode(Hexagon::SA1_combine0i);
785  addOps(Result, Inst, 0);
786  addOps(Result, Inst, 2);
787  break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
788  }
789  if (Value == 2) {
790  Result.setOpcode(Hexagon::SA1_combine2i);
791  addOps(Result, Inst, 0);
792  addOps(Result, Inst, 2);
793  break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
794  }
795  break;
796  case Hexagon::A4_combineir:
797  Result.setOpcode(Hexagon::SA1_combinezr);
798  addOps(Result, Inst, 0);
799  addOps(Result, Inst, 2);
800  break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
801  case Hexagon::A4_combineri:
802  Result.setOpcode(Hexagon::SA1_combinerz);
803  addOps(Result, Inst, 0);
804  addOps(Result, Inst, 1);
805  break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
806  case Hexagon::L4_return_tnew_pnt:
807  case Hexagon::L4_return_tnew_pt:
808  Result.setOpcode(Hexagon::SL2_return_tnew);
809  break; // none SUBInst if (p0.new) dealloc_return:nt
810  case Hexagon::L4_return_fnew_pnt:
811  case Hexagon::L4_return_fnew_pt:
812  Result.setOpcode(Hexagon::SL2_return_fnew);
813  break; // none SUBInst if (!p0.new) dealloc_return:nt
814  case Hexagon::L4_return_f:
815  Result.setOpcode(Hexagon::SL2_return_f);
816  break; // none SUBInst if (!p0) dealloc_return
817  case Hexagon::L4_return_t:
818  Result.setOpcode(Hexagon::SL2_return_t);
819  break; // none SUBInst if (p0) dealloc_return
820  case Hexagon::L4_return:
821  Result.setOpcode(Hexagon::SL2_return);
822  break; // none SUBInst dealloc_return
823  case Hexagon::L2_deallocframe:
824  Result.setOpcode(Hexagon::SL2_deallocframe);
825  break; // none SUBInst deallocframe
826  case Hexagon::EH_RETURN_JMPR:
827  case Hexagon::J2_jumpr:
828  case Hexagon::PS_jmpret:
829  Result.setOpcode(Hexagon::SL2_jumpr31);
830  break; // none SUBInst jumpr r31
831  case Hexagon::J2_jumprf:
832  case Hexagon::PS_jmpretf:
833  Result.setOpcode(Hexagon::SL2_jumpr31_f);
834  break; // none SUBInst if (!p0) jumpr r31
835  case Hexagon::J2_jumprfnew:
836  case Hexagon::J2_jumprfnewpt:
837  case Hexagon::PS_jmpretfnewpt:
838  case Hexagon::PS_jmpretfnew:
839  Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
840  break; // none SUBInst if (!p0.new) jumpr:nt r31
841  case Hexagon::J2_jumprt:
842  case Hexagon::PS_jmprett:
843  Result.setOpcode(Hexagon::SL2_jumpr31_t);
844  break; // none SUBInst if (p0) jumpr r31
845  case Hexagon::J2_jumprtnew:
846  case Hexagon::J2_jumprtnewpt:
847  case Hexagon::PS_jmprettnewpt:
848  case Hexagon::PS_jmprettnew:
849  Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
850  break; // none SUBInst if (p0.new) jumpr:nt r31
851  case Hexagon::L2_loadrb_io:
852  Result.setOpcode(Hexagon::SL2_loadrb_io);
853  addOps(Result, Inst, 0);
854  addOps(Result, Inst, 1);
855  addOps(Result, Inst, 2);
856  break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
857  case Hexagon::L2_loadrd_io:
858  Result.setOpcode(Hexagon::SL2_loadrd_sp);
859  addOps(Result, Inst, 0);
860  addOps(Result, Inst, 2);
861  break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
862  case Hexagon::L2_loadrh_io:
863  Result.setOpcode(Hexagon::SL2_loadrh_io);
864  addOps(Result, Inst, 0);
865  addOps(Result, Inst, 1);
866  addOps(Result, Inst, 2);
867  break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
868  case Hexagon::L2_loadrub_io:
869  Result.setOpcode(Hexagon::SL1_loadrub_io);
870  addOps(Result, Inst, 0);
871  addOps(Result, Inst, 1);
872  addOps(Result, Inst, 2);
873  break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
874  case Hexagon::L2_loadruh_io:
875  Result.setOpcode(Hexagon::SL2_loadruh_io);
876  addOps(Result, Inst, 0);
877  addOps(Result, Inst, 1);
878  addOps(Result, Inst, 2);
879  break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
880  case Hexagon::L2_loadri_io:
881  if (Inst.getOperand(1).getReg() == Hexagon::R29) {
882  Result.setOpcode(Hexagon::SL2_loadri_sp);
883  addOps(Result, Inst, 0);
884  addOps(Result, Inst, 2);
885  break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
886  } else {
887  Result.setOpcode(Hexagon::SL1_loadri_io);
888  addOps(Result, Inst, 0);
889  addOps(Result, Inst, 1);
890  addOps(Result, Inst, 2);
891  break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
892  }
893  case Hexagon::S4_storeirb_io:
894  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
895  assert(Absolute);(void)Absolute;
896  if (Value == 0) {
897  Result.setOpcode(Hexagon::SS2_storebi0);
898  addOps(Result, Inst, 0);
899  addOps(Result, Inst, 1);
900  break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
901  } else if (Value == 1) {
902  Result.setOpcode(Hexagon::SS2_storebi1);
903  addOps(Result, Inst, 0);
904  addOps(Result, Inst, 1);
905  break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
906  }
907  break;
908  case Hexagon::S2_storerb_io:
909  Result.setOpcode(Hexagon::SS1_storeb_io);
910  addOps(Result, Inst, 0);
911  addOps(Result, Inst, 1);
912  addOps(Result, Inst, 2);
913  break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
914  case Hexagon::S2_storerd_io:
915  Result.setOpcode(Hexagon::SS2_stored_sp);
916  addOps(Result, Inst, 1);
917  addOps(Result, Inst, 2);
918  break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
919  case Hexagon::S2_storerh_io:
920  Result.setOpcode(Hexagon::SS2_storeh_io);
921  addOps(Result, Inst, 0);
922  addOps(Result, Inst, 1);
923  addOps(Result, Inst, 2);
924  break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
925  case Hexagon::S4_storeiri_io:
926  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
927  assert(Absolute);(void)Absolute;
928  if (Value == 0) {
929  Result.setOpcode(Hexagon::SS2_storewi0);
930  addOps(Result, Inst, 0);
931  addOps(Result, Inst, 1);
932  break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
933  } else if (Value == 1) {
934  Result.setOpcode(Hexagon::SS2_storewi1);
935  addOps(Result, Inst, 0);
936  addOps(Result, Inst, 1);
937  break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
938  } else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
939  Result.setOpcode(Hexagon::SS2_storew_sp);
940  addOps(Result, Inst, 1);
941  addOps(Result, Inst, 2);
942  break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
943  }
944  break;
945  case Hexagon::S2_storeri_io:
946  if (Inst.getOperand(0).getReg() == Hexagon::R29) {
947  Result.setOpcode(Hexagon::SS2_storew_sp);
948  addOps(Result, Inst, 1);
949  addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
950  } else {
951  Result.setOpcode(Hexagon::SS1_storew_io);
952  addOps(Result, Inst, 0);
953  addOps(Result, Inst, 1);
954  addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
955  }
956  break;
957  case Hexagon::A2_sxtb:
958  Result.setOpcode(Hexagon::SA1_sxtb);
959  addOps(Result, Inst, 0);
960  addOps(Result, Inst, 1);
961  break; // 1,2 SUBInst $Rd = sxtb($Rs)
962  case Hexagon::A2_sxth:
963  Result.setOpcode(Hexagon::SA1_sxth);
964  addOps(Result, Inst, 0);
965  addOps(Result, Inst, 1);
966  break; // 1,2 SUBInst $Rd = sxth($Rs)
967  case Hexagon::A2_tfr:
968  Result.setOpcode(Hexagon::SA1_tfr);
969  addOps(Result, Inst, 0);
970  addOps(Result, Inst, 1);
971  break; // 1,2 SUBInst $Rd = $Rs
972  case Hexagon::C2_cmovenewif:
973  Result.setOpcode(Hexagon::SA1_clrfnew);
974  addOps(Result, Inst, 0);
975  addOps(Result, Inst, 1);
976  break; // 2 SUBInst if (!p0.new) $Rd = #0
977  case Hexagon::C2_cmovenewit:
978  Result.setOpcode(Hexagon::SA1_clrtnew);
979  addOps(Result, Inst, 0);
980  addOps(Result, Inst, 1);
981  break; // 2 SUBInst if (p0.new) $Rd = #0
982  case Hexagon::C2_cmoveif:
983  Result.setOpcode(Hexagon::SA1_clrf);
984  addOps(Result, Inst, 0);
985  addOps(Result, Inst, 1);
986  break; // 2 SUBInst if (!p0) $Rd = #0
987  case Hexagon::C2_cmoveit:
988  Result.setOpcode(Hexagon::SA1_clrt);
989  addOps(Result, Inst, 0);
990  addOps(Result, Inst, 1);
991  break; // 2 SUBInst if (p0) $Rd = #0
992  case Hexagon::A2_tfrsi:
993  Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
994  if (Absolute && Value == -1) {
995  Result.setOpcode(Hexagon::SA1_setin1);
996  addOps(Result, Inst, 0);
997  addOps(Result, Inst, 1);
998  break; // 2 1 SUBInst $Rd = #-1
999  } else {
1000  Result.setOpcode(Hexagon::SA1_seti);
1001  addOps(Result, Inst, 0);
1002  addOps(Result, Inst, 1);
1003  break; // 1,2 SUBInst $Rd = #$u6
1004  }
1005  case Hexagon::A2_zxtb:
1006  Result.setOpcode(Hexagon::SA1_zxtb);
1007  addOps(Result, Inst, 0);
1008  addOps(Result, Inst, 1);
1009  break; // 1,2 $Rd = and($Rs, #255)
1010 
1011  case Hexagon::A2_zxth:
1012  Result.setOpcode(Hexagon::SA1_zxth);
1013  addOps(Result, Inst, 0);
1014  addOps(Result, Inst, 1);
1015  break; // 1,2 SUBInst $Rd = zxth($Rs)
1016  }
1017  return Result;
1018 }
1019 
1020 static bool isStoreInst(unsigned opCode) {
1021  switch (opCode) {
1022  case Hexagon::S2_storeri_io:
1023  case Hexagon::S2_storerb_io:
1024  case Hexagon::S2_storerh_io:
1025  case Hexagon::S2_storerd_io:
1026  case Hexagon::S4_storeiri_io:
1027  case Hexagon::S4_storeirb_io:
1028  case Hexagon::S2_allocframe:
1029  return true;
1030  default:
1031  return false;
1032  }
1033 }
1034 
1037  MCSubtargetInfo const &STI,
1038  MCInst const &MCB) {
1039  assert(isBundle(MCB));
1040  SmallVector<DuplexCandidate, 8> duplexToTry;
1041  // Use an "order matters" version of isDuplexPair.
1042  unsigned numInstrInPacket = MCB.getNumOperands();
1043 
1044  for (unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1046  k = j + distance;
1047  (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1048 
1049  // Check if reversible.
1050  bool bisReversable = true;
1051  if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1052  isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {
1053  LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j
1054  << "\n");
1055  bisReversable = false;
1056  }
1057  if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf
1058  bisReversable = false;
1059 
1060  // Try in order.
1061  if (isOrderedDuplexPair(
1062  MCII, *MCB.getOperand(k).getInst(),
1064  *MCB.getOperand(j).getInst(),
1066  bisReversable, STI)) {
1067  // Get iClass.
1068  unsigned iClass = iClassOfDuplexPair(
1071 
1072  // Save off pairs for duplex checking.
1073  duplexToTry.push_back(DuplexCandidate(j, k, iClass));
1074  LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":"
1075  << MCB.getOperand(j).getInst()->getOpcode() << ","
1076  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1077  continue;
1078  } else {
1079  LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":"
1080  << MCB.getOperand(j).getInst()->getOpcode() << ","
1081  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1082  }
1083 
1084  // Try reverse.
1085  if (bisReversable) {
1086  if (isOrderedDuplexPair(
1087  MCII, *MCB.getOperand(j).getInst(),
1089  *MCB.getOperand(k).getInst(),
1091  bisReversable, STI)) {
1092  // Get iClass.
1093  unsigned iClass = iClassOfDuplexPair(
1096 
1097  // Save off pairs for duplex checking.
1098  duplexToTry.push_back(DuplexCandidate(k, j, iClass));
1099  LLVM_DEBUG(dbgs()
1100  << "adding pair:" << k << "," << j << ":"
1101  << MCB.getOperand(j).getInst()->getOpcode() << ","
1102  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1103  } else {
1104  LLVM_DEBUG(dbgs()
1105  << "skipping pair: " << k << "," << j << ":"
1106  << MCB.getOperand(j).getInst()->getOpcode() << ","
1107  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1108  }
1109  }
1110  }
1111  }
1112  return duplexToTry;
1113 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
#define R4(n)
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
This class represents lattice values for constants.
Definition: AllocatorList.h:24
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:176
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
static const std::pair< unsigned, unsigned > opcodeData[]
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:58
unsigned second
bool isDblRegForSubInst(unsigned Reg)
#define R2(n)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
const MCInst * getInst() const
Definition: MCInst.h:106
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
unsigned getDuplexCandidateGroup(MCInst const &MI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getNumOperands() const
Definition: MCInst.h:184
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addOps(MCInst &subInstPtr, MCInst const &Inst, unsigned opNum)
void setOpcode(unsigned Op)
Definition: MCInst.h:173
size_t const bundleInstructionsOffset
#define R6(n)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
int64_t minConstant(MCInst const &MCI, size_t Index)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
StringRef getCPU() const
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool isMemReorderDisabled(MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Generic base class for all target subtargets.
static bool isStoreInst(unsigned opCode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
unsigned getOpcode() const
Definition: MCInst.h:174
#define LLVM_DEBUG(X)
Definition: Debug.h:123
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
non-Symmetrical. See if these two instructions are fit for duplex pair.