LLVM  6.0.0svn
HexagonMCDuplexInfo.cpp
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1 //===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements duplexing of instructions to reduce code size
11 //
12 //===----------------------------------------------------------------------===//
13 
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/Debug.h"
25 #include <cassert>
26 #include <cstdint>
27 #include <iterator>
28 #include <map>
29 #include <utility>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-mcduplex-info"
35 
36 // pair table of subInstructions with opcodes
37 static const std::pair<unsigned, unsigned> opcodeData[] = {
38  std::make_pair((unsigned)SA1_addi, 0),
39  std::make_pair((unsigned)SA1_addrx, 6144),
40  std::make_pair((unsigned)SA1_addsp, 3072),
41  std::make_pair((unsigned)SA1_and1, 4608),
42  std::make_pair((unsigned)SA1_clrf, 6768),
43  std::make_pair((unsigned)SA1_clrfnew, 6736),
44  std::make_pair((unsigned)SA1_clrt, 6752),
45  std::make_pair((unsigned)SA1_clrtnew, 6720),
46  std::make_pair((unsigned)SA1_cmpeqi, 6400),
47  std::make_pair((unsigned)SA1_combine0i, 7168),
48  std::make_pair((unsigned)SA1_combine1i, 7176),
49  std::make_pair((unsigned)SA1_combine2i, 7184),
50  std::make_pair((unsigned)SA1_combine3i, 7192),
51  std::make_pair((unsigned)SA1_combinerz, 7432),
52  std::make_pair((unsigned)SA1_combinezr, 7424),
53  std::make_pair((unsigned)SA1_dec, 4864),
54  std::make_pair((unsigned)SA1_inc, 4352),
55  std::make_pair((unsigned)SA1_seti, 2048),
56  std::make_pair((unsigned)SA1_setin1, 6656),
57  std::make_pair((unsigned)SA1_sxtb, 5376),
58  std::make_pair((unsigned)SA1_sxth, 5120),
59  std::make_pair((unsigned)SA1_tfr, 4096),
60  std::make_pair((unsigned)SA1_zxtb, 5888),
61  std::make_pair((unsigned)SA1_zxth, 5632),
62  std::make_pair((unsigned)SL1_loadri_io, 0),
63  std::make_pair((unsigned)SL1_loadrub_io, 4096),
64  std::make_pair((unsigned)SL2_deallocframe, 7936),
65  std::make_pair((unsigned)SL2_jumpr31, 8128),
66  std::make_pair((unsigned)SL2_jumpr31_f, 8133),
67  std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),
68  std::make_pair((unsigned)SL2_jumpr31_t, 8132),
69  std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),
70  std::make_pair((unsigned)SL2_loadrb_io, 4096),
71  std::make_pair((unsigned)SL2_loadrd_sp, 7680),
72  std::make_pair((unsigned)SL2_loadrh_io, 0),
73  std::make_pair((unsigned)SL2_loadri_sp, 7168),
74  std::make_pair((unsigned)SL2_loadruh_io, 2048),
75  std::make_pair((unsigned)SL2_return, 8000),
76  std::make_pair((unsigned)SL2_return_f, 8005),
77  std::make_pair((unsigned)SL2_return_fnew, 8007),
78  std::make_pair((unsigned)SL2_return_t, 8004),
79  std::make_pair((unsigned)SL2_return_tnew, 8006),
80  std::make_pair((unsigned)SS1_storeb_io, 4096),
81  std::make_pair((unsigned)SS1_storew_io, 0),
82  std::make_pair((unsigned)SS2_allocframe, 7168),
83  std::make_pair((unsigned)SS2_storebi0, 4608),
84  std::make_pair((unsigned)SS2_storebi1, 4864),
85  std::make_pair((unsigned)SS2_stored_sp, 2560),
86  std::make_pair((unsigned)SS2_storeh_io, 0),
87  std::make_pair((unsigned)SS2_storew_sp, 2048),
88  std::make_pair((unsigned)SS2_storewi0, 4096),
89  std::make_pair((unsigned)SS2_storewi1, 4352)};
90 
91 bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) {
92  switch (Ga) {
94  default:
95  return false;
96  case HexagonII::HSIG_L1:
97  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
98  case HexagonII::HSIG_L2:
99  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
100  Gb == HexagonII::HSIG_A);
101  case HexagonII::HSIG_S1:
102  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
103  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
104  case HexagonII::HSIG_S2:
105  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
106  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
107  Gb == HexagonII::HSIG_A);
108  case HexagonII::HSIG_A:
109  return (Gb == HexagonII::HSIG_A);
111  return (Gb == HexagonII::HSIG_Compound);
112  }
113  return false;
114 }
115 
116 unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
117  switch (Ga) {
119  default:
120  break;
121  case HexagonII::HSIG_L1:
122  switch (Gb) {
123  default:
124  break;
125  case HexagonII::HSIG_L1:
126  return 0;
127  case HexagonII::HSIG_A:
128  return 0x4;
129  }
130  case HexagonII::HSIG_L2:
131  switch (Gb) {
132  default:
133  break;
134  case HexagonII::HSIG_L1:
135  return 0x1;
136  case HexagonII::HSIG_L2:
137  return 0x2;
138  case HexagonII::HSIG_A:
139  return 0x5;
140  }
141  case HexagonII::HSIG_S1:
142  switch (Gb) {
143  default:
144  break;
145  case HexagonII::HSIG_L1:
146  return 0x8;
147  case HexagonII::HSIG_L2:
148  return 0x9;
149  case HexagonII::HSIG_S1:
150  return 0xA;
151  case HexagonII::HSIG_A:
152  return 0x6;
153  }
154  case HexagonII::HSIG_S2:
155  switch (Gb) {
156  default:
157  break;
158  case HexagonII::HSIG_L1:
159  return 0xC;
160  case HexagonII::HSIG_L2:
161  return 0xD;
162  case HexagonII::HSIG_S1:
163  return 0xB;
164  case HexagonII::HSIG_S2:
165  return 0xE;
166  case HexagonII::HSIG_A:
167  return 0x7;
168  }
169  case HexagonII::HSIG_A:
170  switch (Gb) {
171  default:
172  break;
173  case HexagonII::HSIG_A:
174  return 0x3;
175  }
177  switch (Gb) {
179  return 0xFFFFFFFF;
180  }
181  }
182  return 0xFFFFFFFF;
183 }
184 
186  unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
187 
188  switch (MCI.getOpcode()) {
189  default:
190  return HexagonII::HSIG_None;
191  //
192  // Group L1:
193  //
194  // Rd = memw(Rs+#u4:2)
195  // Rd = memub(Rs+#u4:0)
196  case Hexagon::L2_loadri_io:
197  DstReg = MCI.getOperand(0).getReg();
198  SrcReg = MCI.getOperand(1).getReg();
199  // Special case this one from Group L2.
200  // Rd = memw(r29+#u5:2)
202  if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
203  Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
204  return HexagonII::HSIG_L2;
205  }
206  // Rd = memw(Rs+#u4:2)
208  inRange<4, 2>(MCI, 2)) {
209  return HexagonII::HSIG_L1;
210  }
211  }
212  break;
213  case Hexagon::L2_loadrub_io:
214  // Rd = memub(Rs+#u4:0)
215  DstReg = MCI.getOperand(0).getReg();
216  SrcReg = MCI.getOperand(1).getReg();
219  inRange<4>(MCI, 2)) {
220  return HexagonII::HSIG_L1;
221  }
222  break;
223  //
224  // Group L2:
225  //
226  // Rd = memh/memuh(Rs+#u3:1)
227  // Rd = memb(Rs+#u3:0)
228  // Rd = memw(r29+#u5:2) - Handled above.
229  // Rdd = memd(r29+#u5:3)
230  // deallocframe
231  // [if ([!]p0[.new])] dealloc_return
232  // [if ([!]p0[.new])] jumpr r31
233  case Hexagon::L2_loadrh_io:
234  case Hexagon::L2_loadruh_io:
235  // Rd = memh/memuh(Rs+#u3:1)
236  DstReg = MCI.getOperand(0).getReg();
237  SrcReg = MCI.getOperand(1).getReg();
240  inRange<3, 1>(MCI, 2)) {
241  return HexagonII::HSIG_L2;
242  }
243  break;
244  case Hexagon::L2_loadrb_io:
245  // Rd = memb(Rs+#u3:0)
246  DstReg = MCI.getOperand(0).getReg();
247  SrcReg = MCI.getOperand(1).getReg();
250  inRange<3>(MCI, 2)) {
251  return HexagonII::HSIG_L2;
252  }
253  break;
254  case Hexagon::L2_loadrd_io:
255  // Rdd = memd(r29+#u5:3)
256  DstReg = MCI.getOperand(0).getReg();
257  SrcReg = MCI.getOperand(1).getReg();
259  HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
260  inRange<5, 3>(MCI, 2)) {
261  return HexagonII::HSIG_L2;
262  }
263  break;
264 
265  case Hexagon::L4_return:
266 
267  case Hexagon::L2_deallocframe:
268 
269  return HexagonII::HSIG_L2;
270  case Hexagon::EH_RETURN_JMPR:
271 
272  case Hexagon::J2_jumpr:
273  case Hexagon::PS_jmpret:
274  // jumpr r31
275  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
276  DstReg = MCI.getOperand(0).getReg();
277  if (Hexagon::R31 == DstReg)
278  return HexagonII::HSIG_L2;
279  break;
280 
281  case Hexagon::J2_jumprt:
282  case Hexagon::J2_jumprf:
283  case Hexagon::J2_jumprtnew:
284  case Hexagon::J2_jumprfnew:
285  case Hexagon::J2_jumprtnewpt:
286  case Hexagon::J2_jumprfnewpt:
287  case Hexagon::PS_jmprett:
288  case Hexagon::PS_jmpretf:
289  case Hexagon::PS_jmprettnew:
290  case Hexagon::PS_jmpretfnew:
291  case Hexagon::PS_jmprettnewpt:
292  case Hexagon::PS_jmpretfnewpt:
293  DstReg = MCI.getOperand(1).getReg();
294  SrcReg = MCI.getOperand(0).getReg();
295  // [if ([!]p0[.new])] jumpr r31
296  if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) &&
297  (Hexagon::R31 == DstReg)) {
298  return HexagonII::HSIG_L2;
299  }
300  break;
301  case Hexagon::L4_return_t:
302  case Hexagon::L4_return_f:
303  case Hexagon::L4_return_tnew_pnt:
304  case Hexagon::L4_return_fnew_pnt:
305  case Hexagon::L4_return_tnew_pt:
306  case Hexagon::L4_return_fnew_pt:
307  // [if ([!]p0[.new])] dealloc_return
308  SrcReg = MCI.getOperand(1).getReg();
309  if (Hexagon::P0 == SrcReg) {
310  return HexagonII::HSIG_L2;
311  }
312  break;
313  //
314  // Group S1:
315  //
316  // memw(Rs+#u4:2) = Rt
317  // memb(Rs+#u4:0) = Rt
318  case Hexagon::S2_storeri_io:
319  // Special case this one from Group S2.
320  // memw(r29+#u5:2) = Rt
321  Src1Reg = MCI.getOperand(0).getReg();
322  Src2Reg = MCI.getOperand(2).getReg();
323  if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
325  Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
326  return HexagonII::HSIG_S2;
327  }
328  // memw(Rs+#u4:2) = Rt
331  inRange<4, 2>(MCI, 1)) {
332  return HexagonII::HSIG_S1;
333  }
334  break;
335  case Hexagon::S2_storerb_io:
336  // memb(Rs+#u4:0) = Rt
337  Src1Reg = MCI.getOperand(0).getReg();
338  Src2Reg = MCI.getOperand(2).getReg();
341  inRange<4>(MCI, 1)) {
342  return HexagonII::HSIG_S1;
343  }
344  break;
345  //
346  // Group S2:
347  //
348  // memh(Rs+#u3:1) = Rt
349  // memw(r29+#u5:2) = Rt
350  // memd(r29+#s6:3) = Rtt
351  // memw(Rs+#u4:2) = #U1
352  // memb(Rs+#u4) = #U1
353  // allocframe(#u5:3)
354  case Hexagon::S2_storerh_io:
355  // memh(Rs+#u3:1) = Rt
356  Src1Reg = MCI.getOperand(0).getReg();
357  Src2Reg = MCI.getOperand(2).getReg();
360  inRange<3, 1>(MCI, 1)) {
361  return HexagonII::HSIG_S2;
362  }
363  break;
364  case Hexagon::S2_storerd_io:
365  // memd(r29+#s6:3) = Rtt
366  Src1Reg = MCI.getOperand(0).getReg();
367  Src2Reg = MCI.getOperand(2).getReg();
369  HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg &&
370  inSRange<6, 3>(MCI, 1)) {
371  return HexagonII::HSIG_S2;
372  }
373  break;
374  case Hexagon::S4_storeiri_io:
375  // memw(Rs+#u4:2) = #U1
376  Src1Reg = MCI.getOperand(0).getReg();
378  inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {
379  return HexagonII::HSIG_S2;
380  }
381  break;
382  case Hexagon::S4_storeirb_io:
383  // memb(Rs+#u4) = #U1
384  Src1Reg = MCI.getOperand(0).getReg();
386  inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {
387  return HexagonII::HSIG_S2;
388  }
389  break;
390  case Hexagon::S2_allocframe:
391  if (inRange<5, 3>(MCI, 2))
392  return HexagonII::HSIG_S2;
393  break;
394  //
395  // Group A:
396  //
397  // Rx = add(Rx,#s7)
398  // Rd = Rs
399  // Rd = #u6
400  // Rd = #-1
401  // if ([!]P0[.new]) Rd = #0
402  // Rd = add(r29,#u6:2)
403  // Rx = add(Rx,Rs)
404  // P0 = cmp.eq(Rs,#u2)
405  // Rdd = combine(#0,Rs)
406  // Rdd = combine(Rs,#0)
407  // Rdd = combine(#u2,#U2)
408  // Rd = add(Rs,#1)
409  // Rd = add(Rs,#-1)
410  // Rd = sxth/sxtb/zxtb/zxth(Rs)
411  // Rd = and(Rs,#1)
412  case Hexagon::A2_addi:
413  DstReg = MCI.getOperand(0).getReg();
414  SrcReg = MCI.getOperand(1).getReg();
416  // Rd = add(r29,#u6:2)
417  if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
418  inRange<6, 2>(MCI, 2)) {
419  return HexagonII::HSIG_A;
420  }
421  // Rx = add(Rx,#s7)
422  if (DstReg == SrcReg) {
423  return HexagonII::HSIG_A;
424  }
425  // Rd = add(Rs,#1)
426  // Rd = add(Rs,#-1)
428  (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == -1)) {
429  return HexagonII::HSIG_A;
430  }
431  }
432  break;
433  case Hexagon::A2_add:
434  // Rx = add(Rx,Rs)
435  DstReg = MCI.getOperand(0).getReg();
436  Src1Reg = MCI.getOperand(1).getReg();
437  Src2Reg = MCI.getOperand(2).getReg();
438  if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
440  return HexagonII::HSIG_A;
441  }
442  break;
443  case Hexagon::A2_andir:
444  DstReg = MCI.getOperand(0).getReg();
445  SrcReg = MCI.getOperand(1).getReg();
448  (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == 255)) {
449  return HexagonII::HSIG_A;
450  }
451  break;
452  case Hexagon::A2_tfr:
453  // Rd = Rs
454  DstReg = MCI.getOperand(0).getReg();
455  SrcReg = MCI.getOperand(1).getReg();
458  return HexagonII::HSIG_A;
459  }
460  break;
461  case Hexagon::A2_tfrsi:
462  DstReg = MCI.getOperand(0).getReg();
463 
465  return HexagonII::HSIG_A;
466  }
467  break;
468  case Hexagon::C2_cmoveit:
469  case Hexagon::C2_cmovenewit:
470  case Hexagon::C2_cmoveif:
471  case Hexagon::C2_cmovenewif:
472  // if ([!]P0[.new]) Rd = #0
473  // Actual form:
474  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
475  DstReg = MCI.getOperand(0).getReg(); // Rd
476  PredReg = MCI.getOperand(1).getReg(); // P0
478  Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
479  return HexagonII::HSIG_A;
480  }
481  break;
482  case Hexagon::C2_cmpeqi:
483  // P0 = cmp.eq(Rs,#u2)
484  DstReg = MCI.getOperand(0).getReg();
485  SrcReg = MCI.getOperand(1).getReg();
486  if (Hexagon::P0 == DstReg &&
488  inRange<2>(MCI, 2)) {
489  return HexagonII::HSIG_A;
490  }
491  break;
492  case Hexagon::A2_combineii:
493  case Hexagon::A4_combineii:
494  // Rdd = combine(#u2,#U2)
495  DstReg = MCI.getOperand(0).getReg();
497  inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {
498  return HexagonII::HSIG_A;
499  }
500  break;
501  case Hexagon::A4_combineri:
502  // Rdd = combine(Rs,#0)
503  DstReg = MCI.getOperand(0).getReg();
504  SrcReg = MCI.getOperand(1).getReg();
507  minConstant(MCI, 2) == 0) {
508  return HexagonII::HSIG_A;
509  }
510  break;
511  case Hexagon::A4_combineir:
512  // Rdd = combine(#0,Rs)
513  DstReg = MCI.getOperand(0).getReg();
514  SrcReg = MCI.getOperand(2).getReg();
517  minConstant(MCI, 1) == 0) {
518  return HexagonII::HSIG_A;
519  }
520  break;
521  case Hexagon::A2_sxtb:
522  case Hexagon::A2_sxth:
523  case Hexagon::A2_zxtb:
524  case Hexagon::A2_zxth:
525  // Rd = sxth/sxtb/zxtb/zxth(Rs)
526  DstReg = MCI.getOperand(0).getReg();
527  SrcReg = MCI.getOperand(1).getReg();
530  return HexagonII::HSIG_A;
531  }
532  break;
533  }
534 
535  return HexagonII::HSIG_None;
536 }
537 
539  unsigned DstReg, SrcReg;
540  switch (potentialDuplex.getOpcode()) {
541  case Hexagon::A2_addi:
542  // testing for case of: Rx = add(Rx,#s7)
543  DstReg = potentialDuplex.getOperand(0).getReg();
544  SrcReg = potentialDuplex.getOperand(1).getReg();
545  if (DstReg == SrcReg && HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
546  int64_t Value;
547  if (!potentialDuplex.getOperand(2).getExpr()->evaluateAsAbsolute(Value))
548  return true;
549  if (!isShiftedInt<7, 0>(Value))
550  return true;
551  }
552  break;
553  case Hexagon::A2_tfrsi:
554  DstReg = potentialDuplex.getOperand(0).getReg();
555 
557  int64_t Value;
558  if (!potentialDuplex.getOperand(1).getExpr()->evaluateAsAbsolute(Value))
559  return true;
560  // Check for case of Rd = #-1.
561  if (Value == -1)
562  return false;
563  // Check for case of Rd = #u6.
564  if (!isShiftedUInt<6, 0>(Value))
565  return true;
566  }
567  break;
568  default:
569  break;
570  }
571  return false;
572 }
573 
574 /// non-Symmetrical. See if these two instructions are fit for duplex pair.
576  MCInst const &MIa, bool ExtendedA,
577  MCInst const &MIb, bool ExtendedB,
578  bool bisReversable,
579  MCSubtargetInfo const &STI) {
580  // Slot 1 cannot be extended in duplexes PRM 10.5
581  if (ExtendedA)
582  return false;
583  // Only A2_addi and A2_tfrsi can be extended in duplex form PRM 10.5
584  if (ExtendedB) {
585  unsigned Opcode = MIb.getOpcode();
586  if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
587  return false;
588  }
589  unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa),
591 
592  static std::map<unsigned, unsigned> subinstOpcodeMap(std::begin(opcodeData),
594 
595  // If a duplex contains 2 insns in the same group, the insns must be
596  // ordered such that the numerically smaller opcode is in slot 1.
597  if ((MIaG != HexagonII::HSIG_None) && (MIaG == MIbG) && bisReversable) {
600 
601  unsigned zeroedSubInstS0 =
602  subinstOpcodeMap.find(SubInst0.getOpcode())->second;
603  unsigned zeroedSubInstS1 =
604  subinstOpcodeMap.find(SubInst1.getOpcode())->second;
605 
606  if (zeroedSubInstS0 < zeroedSubInstS1)
607  // subinstS0 (maps to slot 0) must be greater than
608  // subinstS1 (maps to slot 1)
609  return false;
610  }
611 
612  // allocframe must always be in slot 0
613  if (MIb.getOpcode() == Hexagon::S2_allocframe)
614  return false;
615 
616  if ((MIaG != HexagonII::HSIG_None) && (MIbG != HexagonII::HSIG_None)) {
617  // Prevent 2 instructions with extenders from duplexing
618  // Note that MIb (slot1) can be extended and MIa (slot0)
619  // can never be extended
620  if (subInstWouldBeExtended(MIa))
621  return false;
622 
623  // If duplexing produces an extender, but the original did not
624  // have an extender, do not duplex.
625  if (subInstWouldBeExtended(MIb) && !ExtendedB)
626  return false;
627  }
628 
629  // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
630  if (MIbG == HexagonII::HSIG_L2) {
631  if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() &&
632  (MIb.getOperand(1).getReg() == Hexagon::R31))
633  return false;
634  if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() &&
635  (MIb.getOperand(0).getReg() == Hexagon::R31))
636  return false;
637  }
638 
639  if (STI.getCPU().equals_lower("hexagonv4") ||
640  STI.getCPU().equals_lower("hexagonv5") ||
641  STI.getCPU().equals_lower("hexagonv55") ||
642  STI.getCPU().equals_lower("hexagonv60")) {
643  // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb);
644  // therefore, not duplexable if slot 1 is a store, and slot 0 is not.
645  if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) {
646  if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2))
647  return false;
648  }
649  }
650 
651  return (isDuplexPairMatch(MIaG, MIbG));
652 }
653 
654 /// Symmetrical. See if these two instructions are fit for duplex pair.
655 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
656  unsigned MIaG = getDuplexCandidateGroup(MIa),
657  MIbG = getDuplexCandidateGroup(MIb);
658  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
659 }
660 
661 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
662  unsigned opNum) {
663  if (Inst.getOperand(opNum).isReg()) {
664  switch (Inst.getOperand(opNum).getReg()) {
665  default:
666  llvm_unreachable("Not Duplexable Register");
667  break;
668  case Hexagon::R0:
669  case Hexagon::R1:
670  case Hexagon::R2:
671  case Hexagon::R3:
672  case Hexagon::R4:
673  case Hexagon::R5:
674  case Hexagon::R6:
675  case Hexagon::R7:
676  case Hexagon::D0:
677  case Hexagon::D1:
678  case Hexagon::D2:
679  case Hexagon::D3:
680  case Hexagon::R16:
681  case Hexagon::R17:
682  case Hexagon::R18:
683  case Hexagon::R19:
684  case Hexagon::R20:
685  case Hexagon::R21:
686  case Hexagon::R22:
687  case Hexagon::R23:
688  case Hexagon::D8:
689  case Hexagon::D9:
690  case Hexagon::D10:
691  case Hexagon::D11:
692  case Hexagon::P0:
693  subInstPtr.addOperand(Inst.getOperand(opNum));
694  break;
695  }
696  } else
697  subInstPtr.addOperand(Inst.getOperand(opNum));
698 }
699 
701  MCInst Result;
702  bool Absolute;
703  int64_t Value;
704  switch (Inst.getOpcode()) {
705  default:
706  // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
707  llvm_unreachable("Unimplemented subinstruction \n");
708  break;
709  case Hexagon::A2_addi:
710  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
711  if (Absolute) {
712  if (Value == 1) {
713  Result.setOpcode(Hexagon::SA1_inc);
714  addOps(Result, Inst, 0);
715  addOps(Result, Inst, 1);
716  break;
717  } // 1,2 SUBInst $Rd = add($Rs, #1)
718  if (Value == -1) {
719  Result.setOpcode(Hexagon::SA1_dec);
720  addOps(Result, Inst, 0);
721  addOps(Result, Inst, 1);
722  addOps(Result, Inst, 2);
723  break;
724  } // 1,2 SUBInst $Rd = add($Rs,#-1)
725  if (Inst.getOperand(1).getReg() == Hexagon::R29) {
726  Result.setOpcode(Hexagon::SA1_addsp);
727  addOps(Result, Inst, 0);
728  addOps(Result, Inst, 2);
729  break;
730  } // 1,3 SUBInst $Rd = add(r29, #$u6_2)
731  }
732  Result.setOpcode(Hexagon::SA1_addi);
733  addOps(Result, Inst, 0);
734  addOps(Result, Inst, 1);
735  addOps(Result, Inst, 2);
736  break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
737  case Hexagon::A2_add:
738  Result.setOpcode(Hexagon::SA1_addrx);
739  addOps(Result, Inst, 0);
740  addOps(Result, Inst, 1);
741  addOps(Result, Inst, 2);
742  break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
743  case Hexagon::S2_allocframe:
744  Result.setOpcode(Hexagon::SS2_allocframe);
745  addOps(Result, Inst, 2);
746  break; // 1 SUBInst allocframe(#$u5_3)
747  case Hexagon::A2_andir:
748  if (minConstant(Inst, 2) == 255) {
749  Result.setOpcode(Hexagon::SA1_zxtb);
750  addOps(Result, Inst, 0);
751  addOps(Result, Inst, 1);
752  break; // 1,2 $Rd = and($Rs, #255)
753  } else {
754  Result.setOpcode(Hexagon::SA1_and1);
755  addOps(Result, Inst, 0);
756  addOps(Result, Inst, 1);
757  break; // 1,2 SUBInst $Rd = and($Rs, #1)
758  }
759  case Hexagon::C2_cmpeqi:
760  Result.setOpcode(Hexagon::SA1_cmpeqi);
761  addOps(Result, Inst, 1);
762  addOps(Result, Inst, 2);
763  break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
764  case Hexagon::A4_combineii:
765  case Hexagon::A2_combineii:
766  Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
767  assert(Absolute);(void)Absolute;
768  if (Value == 1) {
769  Result.setOpcode(Hexagon::SA1_combine1i);
770  addOps(Result, Inst, 0);
771  addOps(Result, Inst, 2);
772  break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
773  }
774  if (Value == 3) {
775  Result.setOpcode(Hexagon::SA1_combine3i);
776  addOps(Result, Inst, 0);
777  addOps(Result, Inst, 2);
778  break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
779  }
780  if (Value == 0) {
781  Result.setOpcode(Hexagon::SA1_combine0i);
782  addOps(Result, Inst, 0);
783  addOps(Result, Inst, 2);
784  break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
785  }
786  if (Value == 2) {
787  Result.setOpcode(Hexagon::SA1_combine2i);
788  addOps(Result, Inst, 0);
789  addOps(Result, Inst, 2);
790  break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
791  }
792  case Hexagon::A4_combineir:
793  Result.setOpcode(Hexagon::SA1_combinezr);
794  addOps(Result, Inst, 0);
795  addOps(Result, Inst, 2);
796  break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
797 
798  case Hexagon::A4_combineri:
799  Result.setOpcode(Hexagon::SA1_combinerz);
800  addOps(Result, Inst, 0);
801  addOps(Result, Inst, 1);
802  break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
803  case Hexagon::L4_return_tnew_pnt:
804  case Hexagon::L4_return_tnew_pt:
805  Result.setOpcode(Hexagon::SL2_return_tnew);
806  break; // none SUBInst if (p0.new) dealloc_return:nt
807  case Hexagon::L4_return_fnew_pnt:
808  case Hexagon::L4_return_fnew_pt:
809  Result.setOpcode(Hexagon::SL2_return_fnew);
810  break; // none SUBInst if (!p0.new) dealloc_return:nt
811  case Hexagon::L4_return_f:
812  Result.setOpcode(Hexagon::SL2_return_f);
813  break; // none SUBInst if (!p0) dealloc_return
814  case Hexagon::L4_return_t:
815  Result.setOpcode(Hexagon::SL2_return_t);
816  break; // none SUBInst if (p0) dealloc_return
817  case Hexagon::L4_return:
818  Result.setOpcode(Hexagon::SL2_return);
819  break; // none SUBInst dealloc_return
820  case Hexagon::L2_deallocframe:
821  Result.setOpcode(Hexagon::SL2_deallocframe);
822  break; // none SUBInst deallocframe
823  case Hexagon::EH_RETURN_JMPR:
824  case Hexagon::J2_jumpr:
825  case Hexagon::PS_jmpret:
826  Result.setOpcode(Hexagon::SL2_jumpr31);
827  break; // none SUBInst jumpr r31
828  case Hexagon::J2_jumprf:
829  case Hexagon::PS_jmpretf:
830  Result.setOpcode(Hexagon::SL2_jumpr31_f);
831  break; // none SUBInst if (!p0) jumpr r31
832  case Hexagon::J2_jumprfnew:
833  case Hexagon::J2_jumprfnewpt:
834  case Hexagon::PS_jmpretfnewpt:
835  case Hexagon::PS_jmpretfnew:
836  Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
837  break; // none SUBInst if (!p0.new) jumpr:nt r31
838  case Hexagon::J2_jumprt:
839  case Hexagon::PS_jmprett:
840  Result.setOpcode(Hexagon::SL2_jumpr31_t);
841  break; // none SUBInst if (p0) jumpr r31
842  case Hexagon::J2_jumprtnew:
843  case Hexagon::J2_jumprtnewpt:
844  case Hexagon::PS_jmprettnewpt:
845  case Hexagon::PS_jmprettnew:
846  Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
847  break; // none SUBInst if (p0.new) jumpr:nt r31
848  case Hexagon::L2_loadrb_io:
849  Result.setOpcode(Hexagon::SL2_loadrb_io);
850  addOps(Result, Inst, 0);
851  addOps(Result, Inst, 1);
852  addOps(Result, Inst, 2);
853  break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
854  case Hexagon::L2_loadrd_io:
855  Result.setOpcode(Hexagon::SL2_loadrd_sp);
856  addOps(Result, Inst, 0);
857  addOps(Result, Inst, 2);
858  break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
859  case Hexagon::L2_loadrh_io:
860  Result.setOpcode(Hexagon::SL2_loadrh_io);
861  addOps(Result, Inst, 0);
862  addOps(Result, Inst, 1);
863  addOps(Result, Inst, 2);
864  break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
865  case Hexagon::L2_loadrub_io:
866  Result.setOpcode(Hexagon::SL1_loadrub_io);
867  addOps(Result, Inst, 0);
868  addOps(Result, Inst, 1);
869  addOps(Result, Inst, 2);
870  break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
871  case Hexagon::L2_loadruh_io:
872  Result.setOpcode(Hexagon::SL2_loadruh_io);
873  addOps(Result, Inst, 0);
874  addOps(Result, Inst, 1);
875  addOps(Result, Inst, 2);
876  break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
877  case Hexagon::L2_loadri_io:
878  if (Inst.getOperand(1).getReg() == Hexagon::R29) {
879  Result.setOpcode(Hexagon::SL2_loadri_sp);
880  addOps(Result, Inst, 0);
881  addOps(Result, Inst, 2);
882  break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
883  } else {
884  Result.setOpcode(Hexagon::SL1_loadri_io);
885  addOps(Result, Inst, 0);
886  addOps(Result, Inst, 1);
887  addOps(Result, Inst, 2);
888  break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
889  }
890  case Hexagon::S4_storeirb_io:
891  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
892  assert(Absolute);(void)Absolute;
893  if (Value == 0) {
894  Result.setOpcode(Hexagon::SS2_storebi0);
895  addOps(Result, Inst, 0);
896  addOps(Result, Inst, 1);
897  break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
898  } else if (Value == 1) {
899  Result.setOpcode(Hexagon::SS2_storebi1);
900  addOps(Result, Inst, 0);
901  addOps(Result, Inst, 1);
902  break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
903  }
904  case Hexagon::S2_storerb_io:
905  Result.setOpcode(Hexagon::SS1_storeb_io);
906  addOps(Result, Inst, 0);
907  addOps(Result, Inst, 1);
908  addOps(Result, Inst, 2);
909  break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
910  case Hexagon::S2_storerd_io:
911  Result.setOpcode(Hexagon::SS2_stored_sp);
912  addOps(Result, Inst, 1);
913  addOps(Result, Inst, 2);
914  break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
915  case Hexagon::S2_storerh_io:
916  Result.setOpcode(Hexagon::SS2_storeh_io);
917  addOps(Result, Inst, 0);
918  addOps(Result, Inst, 1);
919  addOps(Result, Inst, 2);
920  break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
921  case Hexagon::S4_storeiri_io:
922  Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
923  assert(Absolute);(void)Absolute;
924  if (Value == 0) {
925  Result.setOpcode(Hexagon::SS2_storewi0);
926  addOps(Result, Inst, 0);
927  addOps(Result, Inst, 1);
928  break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
929  } else if (Value == 1) {
930  Result.setOpcode(Hexagon::SS2_storewi1);
931  addOps(Result, Inst, 0);
932  addOps(Result, Inst, 1);
933  break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
934  } else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
935  Result.setOpcode(Hexagon::SS2_storew_sp);
936  addOps(Result, Inst, 1);
937  addOps(Result, Inst, 2);
938  break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
939  }
940  case Hexagon::S2_storeri_io:
941  if (Inst.getOperand(0).getReg() == Hexagon::R29) {
942  Result.setOpcode(Hexagon::SS2_storew_sp);
943  addOps(Result, Inst, 1);
944  addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
945  } else {
946  Result.setOpcode(Hexagon::SS1_storew_io);
947  addOps(Result, Inst, 0);
948  addOps(Result, Inst, 1);
949  addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
950  }
951  break;
952  case Hexagon::A2_sxtb:
953  Result.setOpcode(Hexagon::SA1_sxtb);
954  addOps(Result, Inst, 0);
955  addOps(Result, Inst, 1);
956  break; // 1,2 SUBInst $Rd = sxtb($Rs)
957  case Hexagon::A2_sxth:
958  Result.setOpcode(Hexagon::SA1_sxth);
959  addOps(Result, Inst, 0);
960  addOps(Result, Inst, 1);
961  break; // 1,2 SUBInst $Rd = sxth($Rs)
962  case Hexagon::A2_tfr:
963  Result.setOpcode(Hexagon::SA1_tfr);
964  addOps(Result, Inst, 0);
965  addOps(Result, Inst, 1);
966  break; // 1,2 SUBInst $Rd = $Rs
967  case Hexagon::C2_cmovenewif:
968  Result.setOpcode(Hexagon::SA1_clrfnew);
969  addOps(Result, Inst, 0);
970  addOps(Result, Inst, 1);
971  break; // 2 SUBInst if (!p0.new) $Rd = #0
972  case Hexagon::C2_cmovenewit:
973  Result.setOpcode(Hexagon::SA1_clrtnew);
974  addOps(Result, Inst, 0);
975  addOps(Result, Inst, 1);
976  break; // 2 SUBInst if (p0.new) $Rd = #0
977  case Hexagon::C2_cmoveif:
978  Result.setOpcode(Hexagon::SA1_clrf);
979  addOps(Result, Inst, 0);
980  addOps(Result, Inst, 1);
981  break; // 2 SUBInst if (!p0) $Rd = #0
982  case Hexagon::C2_cmoveit:
983  Result.setOpcode(Hexagon::SA1_clrt);
984  addOps(Result, Inst, 0);
985  addOps(Result, Inst, 1);
986  break; // 2 SUBInst if (p0) $Rd = #0
987  case Hexagon::A2_tfrsi:
988  Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
989  if (Absolute && Value == -1) {
990  Result.setOpcode(Hexagon::SA1_setin1);
991  addOps(Result, Inst, 0);
992  addOps(Result, Inst, 1);
993  break; // 2 1 SUBInst $Rd = #-1
994  } else {
995  Result.setOpcode(Hexagon::SA1_seti);
996  addOps(Result, Inst, 0);
997  addOps(Result, Inst, 1);
998  break; // 1,2 SUBInst $Rd = #$u6
999  }
1000  case Hexagon::A2_zxtb:
1001  Result.setOpcode(Hexagon::SA1_zxtb);
1002  addOps(Result, Inst, 0);
1003  addOps(Result, Inst, 1);
1004  break; // 1,2 $Rd = and($Rs, #255)
1005 
1006  case Hexagon::A2_zxth:
1007  Result.setOpcode(Hexagon::SA1_zxth);
1008  addOps(Result, Inst, 0);
1009  addOps(Result, Inst, 1);
1010  break; // 1,2 SUBInst $Rd = zxth($Rs)
1011  }
1012  return Result;
1013 }
1014 
1015 static bool isStoreInst(unsigned opCode) {
1016  switch (opCode) {
1017  case Hexagon::S2_storeri_io:
1018  case Hexagon::S2_storerb_io:
1019  case Hexagon::S2_storerh_io:
1020  case Hexagon::S2_storerd_io:
1021  case Hexagon::S4_storeiri_io:
1022  case Hexagon::S4_storeirb_io:
1023  case Hexagon::S2_allocframe:
1024  return true;
1025  default:
1026  return false;
1027  }
1028 }
1029 
1032  MCSubtargetInfo const &STI,
1033  MCInst const &MCB) {
1034  assert(isBundle(MCB));
1035  SmallVector<DuplexCandidate, 8> duplexToTry;
1036  // Use an "order matters" version of isDuplexPair.
1037  unsigned numInstrInPacket = MCB.getNumOperands();
1038 
1039  for (unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1041  k = j + distance;
1042  (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1043 
1044  // Check if reversible.
1045  bool bisReversable = true;
1046  if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1047  isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {
1048  DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j
1049  << "\n");
1050  bisReversable = false;
1051  }
1052  if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf
1053  bisReversable = false;
1054 
1055  // Try in order.
1056  if (isOrderedDuplexPair(
1057  MCII, *MCB.getOperand(k).getInst(),
1059  *MCB.getOperand(j).getInst(),
1061  bisReversable, STI)) {
1062  // Get iClass.
1063  unsigned iClass = iClassOfDuplexPair(
1066 
1067  // Save off pairs for duplex checking.
1068  duplexToTry.push_back(DuplexCandidate(j, k, iClass));
1069  DEBUG(dbgs() << "adding pair: " << j << "," << k << ":"
1070  << MCB.getOperand(j).getInst()->getOpcode() << ","
1071  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1072  continue;
1073  } else {
1074  DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":"
1075  << MCB.getOperand(j).getInst()->getOpcode() << ","
1076  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1077  }
1078 
1079  // Try reverse.
1080  if (bisReversable) {
1081  if (isOrderedDuplexPair(
1082  MCII, *MCB.getOperand(j).getInst(),
1084  *MCB.getOperand(k).getInst(),
1086  bisReversable, STI)) {
1087  // Get iClass.
1088  unsigned iClass = iClassOfDuplexPair(
1091 
1092  // Save off pairs for duplex checking.
1093  duplexToTry.push_back(DuplexCandidate(k, j, iClass));
1094  DEBUG(dbgs() << "adding pair:" << k << "," << j << ":"
1095  << MCB.getOperand(j).getInst()->getOpcode() << ","
1096  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1097  } else {
1098  DEBUG(dbgs() << "skipping pair: " << k << "," << j << ":"
1099  << MCB.getOperand(j).getInst()->getOpcode() << ","
1100  << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1101  }
1102  }
1103  }
1104  }
1105  return duplexToTry;
1106 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
#define R4(n)
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:236
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:176
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
static const std::pair< unsigned, unsigned > opcodeData[]
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:58
unsigned second
bool isDblRegForSubInst(unsigned Reg)
#define R2(n)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
const MCInst * getInst() const
Definition: MCInst.h:106
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
unsigned getDuplexCandidateGroup(MCInst const &MI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getNumOperands() const
Definition: MCInst.h:182
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addOps(MCInst &subInstPtr, MCInst const &Inst, unsigned opNum)
void setOpcode(unsigned Op)
Definition: MCInst.h:171
size_t const bundleInstructionsOffset
#define R6(n)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
int64_t minConstant(MCInst const &MCI, size_t Index)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
StringRef getCPU() const
getCPU - Return the CPU string.
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool isMemReorderDisabled(MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
MCSubtargetInfo - Generic base class for all target subtargets.
static bool isStoreInst(unsigned opCode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
#define DEBUG(X)
Definition: Debug.h:118
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:172
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
non-Symmetrical. See if these two instructions are fit for duplex pair.