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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Hexagon.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/Support/Casting.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <limits>
33 
34 using namespace llvm;
35 
37  return Register != Hexagon::NoRegister;
38 }
39 
41  MCInst const &Inst)
42  : MCII(MCII), BundleCurrent(Inst.begin() +
43  HexagonMCInstrInfo::bundleInstructionsOffset),
44  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
45 
47  MCInst const &Inst, std::nullptr_t)
48  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
49  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
50 
52  if (DuplexCurrent != DuplexEnd) {
53  ++DuplexCurrent;
54  if (DuplexCurrent == DuplexEnd) {
55  DuplexCurrent = BundleEnd;
56  DuplexEnd = BundleEnd;
57  ++BundleCurrent;
58  }
59  return *this;
60  }
61  ++BundleCurrent;
62  if (BundleCurrent != BundleEnd) {
63  MCInst const &Inst = *BundleCurrent->getInst();
64  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
65  DuplexCurrent = Inst.begin();
66  DuplexEnd = Inst.end();
67  }
68  }
69  return *this;
70 }
71 
73  if (DuplexCurrent != DuplexEnd)
74  return *DuplexCurrent->getInst();
75  return *BundleCurrent->getInst();
76 }
77 
79  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
80  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
81 }
82 
84  MCContext &Context) {
86 }
87 
89  MCInstrInfo const &MCII, MCInst &MCB,
90  MCInst const &MCI) {
92  MCOperand const &exOp =
94 
95  // Create the extender.
96  MCInst *XMCI =
97  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
98  XMCI->setLoc(MCI.getLoc());
99 
101 }
102 
105  MCInst const &MCI) {
106  assert(isBundle(MCI));
107  return make_range(Hexagon::PacketIterator(MCII, MCI),
108  Hexagon::PacketIterator(MCII, MCI, nullptr));
109 }
110 
113  assert(isBundle(MCI));
114  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
115 }
116 
119  return (MCI.size() - bundleInstructionsOffset);
120  else
121  return (1);
122 }
123 
125  MCSubtargetInfo const &STI,
126  MCContext &Context, MCInst &MCB,
128  // Check the bundle for errors.
129  bool CheckOk = Check ? Check->check(false) : true;
130  if (!CheckOk)
131  return false;
132  // Examine the packet and convert pairs of instructions to compound
133  // instructions when possible.
135  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
136  HexagonMCShuffle(Context, false, MCII, STI, MCB);
137  // Examine the packet and convert pairs of instructions to duplex
138  // instructions when possible.
139  MCInst InstBundlePreDuplex = MCInst(MCB);
140  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
141  SmallVector<DuplexCandidate, 8> possibleDuplexes;
142  possibleDuplexes =
144  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
145  }
146  // Examines packet and pad the packet, if needed, when an
147  // end-loop is in the bundle.
148  HexagonMCInstrInfo::padEndloop(MCB, Context);
149  // If compounding and duplexing didn't reduce the size below
150  // 4 or less we have a packet that is too big.
152  return false;
153  // Check the bundle for errors.
154  CheckOk = Check ? Check->check(true) : true;
155  if (!CheckOk)
156  return false;
157  HexagonMCShuffle(Context, true, MCII, STI, MCB);
158  return true;
159 }
160 
162  MCInst const &Inst,
163  MCOperand const &MO) {
165  HexagonMCInstrInfo::isExtended(MCII, Inst));
166 
167  MCInst XMI;
168  XMI.setOpcode(Hexagon::A4_ext);
169  if (MO.isImm())
170  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
171  else if (MO.isExpr())
173  else
174  llvm_unreachable("invalid extendable operand");
175  return XMI;
176 }
177 
179  MCInst const &inst0,
180  MCInst const &inst1) {
181  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
182  MCInst *duplexInst = new (Context) MCInst;
183  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
184 
185  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
186  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
187  duplexInst->addOperand(MCOperand::createInst(SubInst0));
188  duplexInst->addOperand(MCOperand::createInst(SubInst1));
189  return duplexInst;
190 }
191 
193  size_t Index) {
194  assert(Index <= bundleSize(MCB));
195  if (Index == 0)
196  return nullptr;
197  MCInst const *Inst =
198  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
199  if (isImmext(*Inst))
200  return Inst;
201  return nullptr;
202 }
203 
205  MCInstrInfo const &MCII, MCInst &MCB,
206  MCInst const &MCI) {
207  if (isConstExtended(MCII, MCI))
208  addConstExtender(Context, MCII, MCB, MCI);
209 }
210 
212  MCInst const &MCI) {
213  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
216 }
217 
219  MCInst const &MCI) {
220  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
221  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
223 }
224 
226  MCInst const &MCI) {
227  return MCII.get(MCI.getOpcode());
228 }
229 
231  using namespace Hexagon;
232 
233  switch (Reg) {
234  default:
235  llvm_unreachable("unknown duplex register");
236  // Rs Rss
237  case R0:
238  case D0:
239  return 0;
240  case R1:
241  case D1:
242  return 1;
243  case R2:
244  case D2:
245  return 2;
246  case R3:
247  case D3:
248  return 3;
249  case R4:
250  case D8:
251  return 4;
252  case R5:
253  case D9:
254  return 5;
255  case R6:
256  case D10:
257  return 6;
258  case R7:
259  case D11:
260  return 7;
261  case R16:
262  return 8;
263  case R17:
264  return 9;
265  case R18:
266  return 10;
267  case R19:
268  return 11;
269  case R20:
270  return 12;
271  case R21:
272  return 13;
273  case R22:
274  return 14;
275  case R23:
276  return 15;
277  }
278 }
279 
281  const auto &HExpr = cast<HexagonMCExpr>(Expr);
282  assert(HExpr.getExpr());
283  return *HExpr.getExpr();
284 }
285 
287  MCInst const &MCI) {
288  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
290 }
291 
292 MCOperand const &
294  MCInst const &MCI) {
295  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
296  MCOperand const &MO = MCI.getOperand(O);
297 
299  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
300  (MO.isImm() || MO.isExpr()));
301  return (MO);
302 }
303 
305  MCInst const &MCI) {
306  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
308 }
309 
311  MCInst const &MCI) {
312  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
314 }
315 
317  MCInst const &MCI) {
318  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
320 }
321 
322 /// Return the maximum value of an extendable operand.
324  MCInst const &MCI) {
326  HexagonMCInstrInfo::isExtended(MCII, MCI));
327 
328  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
329  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
330  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
331 }
332 
333 /// Return the minimum value of an extendable operand.
335  MCInst const &MCI) {
337  HexagonMCInstrInfo::isExtended(MCII, MCI));
338 
339  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
340  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
341  return 0;
342 }
343 
345  MCInst const &MCI) {
346  return MCII.getName(MCI.getOpcode());
347 }
348 
350  MCInst const &MCI) {
351  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
353 }
354 
356  MCInst const &MCI) {
357  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
358  // VTMP doesn't actually exist in the encodings for these 184
359  // 3 instructions so go ahead and create it here.
360  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
361  return (MCO);
362  } else {
363  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
364  MCOperand const &MCO = MCI.getOperand(O);
365 
367  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
368  MCO.isReg());
369  return (MCO);
370  }
371 }
372 
373 /// Return the new value or the newly produced value.
375  MCInst const &MCI) {
376  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
378 }
379 
380 MCOperand const &
382  MCInst const &MCI) {
383  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
384  MCOperand const &MCO = MCI.getOperand(O);
385 
387  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
388  MCO.isReg());
389  return (MCO);
390 }
391 
392 /// Return the Hexagon ISA class for the insn.
394  MCInst const &MCI) {
395  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
396  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
397 }
398 
399 /// Return the slots this instruction can execute out of
401  MCSubtargetInfo const &STI,
402  MCInst const &MCI) {
404  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
405  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
406 }
407 
408 /// Return the slots this instruction consumes in addition to
409 /// the slot(s) it can execute out of
410 
412  MCSubtargetInfo const &STI,
413  MCInst const &MCI) {
415  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
416  unsigned Slots = 0;
417 
418  // FirstStage are slots that this instruction can execute in.
419  // FirstStage+1 are slots that are also consumed by this instruction.
420  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
421  for (unsigned Stage = II[SchedClass].FirstStage + 1;
422  Stage < II[SchedClass].LastStage; ++Stage) {
423  unsigned Units = (Stage + HexagonStages)->getUnits();
424  if (Units > HexagonGetLastSlot())
425  break;
426  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
427  Slots |= Units;
428  }
429 
430  // if 0 is returned, then no additional slots are consumed by this inst.
431  return Slots;
432 }
433 
434 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
436  return false;
437 
438  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
439  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
440  return true;
441  }
442 
443  return false;
444 }
445 
447  return extenderForIndex(MCB, Index) != nullptr;
448 }
449 
452  return false;
453 
454  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
455  if (isImmext(*I.getInst()))
456  return true;
457  }
458 
459  return false;
460 }
461 
462 /// Return whether the insn produces a value.
464  MCInst const &MCI) {
465  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
467 }
468 
469 /// Return whether the insn produces a second value.
471  MCInst const &MCI) {
472  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
474 }
475 
477  assert(isBundle(MCB));
478  assert(Index < HEXAGON_PACKET_SIZE);
479  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
480 }
481 
482 /// Return where the instruction is an accumulator.
484  MCInst const &MCI) {
485  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
487 }
488 
490  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
491  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
492  return Result;
493 }
494 
496  MCInst const &MCI) {
497  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
498  return true;
499  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
500  return false;
502  if (isa<HexagonMCExpr>(MO.getExpr()) &&
504  return true;
505  // Branch insns are handled as necessary by relaxation.
506  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
508  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
511  return false;
512  // Otherwise loop instructions and other CR insts are handled by relaxation
513  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
514  (MCI.getOpcode() != Hexagon::C4_addipc))
515  return false;
516 
517  assert(!MO.isImm());
518  if (isa<HexagonMCExpr>(MO.getExpr()) &&
520  return false;
521  int64_t Value;
522  if (!MO.getExpr()->evaluateAsAbsolute(Value))
523  return true;
524  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
525  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
526  return (MinValue > Value || Value > MaxValue);
527 }
528 
529 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
530  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
531  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
532 }
533 
534 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
535  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
537 }
538 
540  MCInst const &MCI) {
541  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
543 }
544 
546  MCInst const &MCI) {
547  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
549 }
550 
552  MCInst const &MCI) {
553  return (getType(MCII, MCI) == HexagonII::TypeCJ);
554 }
555 
556 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
557  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
559 }
560 
562  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
563  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
564 }
565 
566 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
568 }
569 
571  MCInst const &MCI) {
572  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
574 }
575 
577  MCInst const &MCI) {
578  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
580 }
581 
582 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
583  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
584  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
585 }
586 
587 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
588  const uint64_t V = getType(MCII, MCI);
590 }
591 
593  return MCI.getOpcode() == Hexagon::A4_ext;
594 }
595 
597  assert(isBundle(MCI));
598  int64_t Flags = MCI.getOperand(0).getImm();
599  return (Flags & innerLoopMask) != 0;
600 }
601 
603  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
604 }
605 
607  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
608  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
609 }
610 
611 /// Return whether the insn expects newly produced value.
613  MCInst const &MCI) {
614  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
616 }
617 
618 /// Return whether the operand is extendable.
620  MCInst const &MCI, unsigned short O) {
621  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
622 }
623 
625  assert(isBundle(MCI));
626  int64_t Flags = MCI.getOperand(0).getImm();
627  return (Flags & outerLoopMask) != 0;
628 }
629 
631  MCInst const &MCI) {
632  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
634 }
635 
636 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
638 }
639 
641  MCInst const &MCI) {
642  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
644 }
645 
646 /// Return whether the insn is newly predicated.
648  MCInst const &MCI) {
649  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
651 }
652 
654  MCInst const &MCI) {
655  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
656  return (
658 }
659 
661  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
662 }
663 
664 /// Return whether the insn can be packaged only with A and X-type insns.
665 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
666  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
668 }
669 
670 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
672  MCInst const &MCI) {
673  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
674  return ((F >> HexagonII::RestrictSlot1AOKPos) &
676 }
677 
679  MCInst const &MCI) {
680  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
681  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
683 }
684 
685 /// Return whether the insn is solo, i.e., cannot be in a packet.
686 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
687  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
688  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
689 }
690 
692  assert(isBundle(MCI));
693  auto Flags = MCI.getOperand(0).getImm();
694  return (Flags & memReorderDisabledMask) != 0;
695 }
696 
698  switch (MCI.getOpcode()) {
699  default:
700  return false;
701  case Hexagon::SA1_addi:
702  case Hexagon::SA1_addrx:
703  case Hexagon::SA1_addsp:
704  case Hexagon::SA1_and1:
705  case Hexagon::SA1_clrf:
706  case Hexagon::SA1_clrfnew:
707  case Hexagon::SA1_clrt:
708  case Hexagon::SA1_clrtnew:
709  case Hexagon::SA1_cmpeqi:
710  case Hexagon::SA1_combine0i:
711  case Hexagon::SA1_combine1i:
712  case Hexagon::SA1_combine2i:
713  case Hexagon::SA1_combine3i:
714  case Hexagon::SA1_combinerz:
715  case Hexagon::SA1_combinezr:
716  case Hexagon::SA1_dec:
717  case Hexagon::SA1_inc:
718  case Hexagon::SA1_seti:
719  case Hexagon::SA1_setin1:
720  case Hexagon::SA1_sxtb:
721  case Hexagon::SA1_sxth:
722  case Hexagon::SA1_tfr:
723  case Hexagon::SA1_zxtb:
724  case Hexagon::SA1_zxth:
725  case Hexagon::SL1_loadri_io:
726  case Hexagon::SL1_loadrub_io:
727  case Hexagon::SL2_deallocframe:
728  case Hexagon::SL2_jumpr31:
729  case Hexagon::SL2_jumpr31_f:
730  case Hexagon::SL2_jumpr31_fnew:
731  case Hexagon::SL2_jumpr31_t:
732  case Hexagon::SL2_jumpr31_tnew:
733  case Hexagon::SL2_loadrb_io:
734  case Hexagon::SL2_loadrd_sp:
735  case Hexagon::SL2_loadrh_io:
736  case Hexagon::SL2_loadri_sp:
737  case Hexagon::SL2_loadruh_io:
738  case Hexagon::SL2_return:
739  case Hexagon::SL2_return_f:
740  case Hexagon::SL2_return_fnew:
741  case Hexagon::SL2_return_t:
742  case Hexagon::SL2_return_tnew:
743  case Hexagon::SS1_storeb_io:
744  case Hexagon::SS1_storew_io:
745  case Hexagon::SS2_allocframe:
746  case Hexagon::SS2_storebi0:
747  case Hexagon::SS2_storebi1:
748  case Hexagon::SS2_stored_sp:
749  case Hexagon::SS2_storeh_io:
750  case Hexagon::SS2_storew_sp:
751  case Hexagon::SS2_storewi0:
752  case Hexagon::SS2_storewi1:
753  return true;
754  }
755 }
756 
757 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
758  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
759  (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
760  return true;
761  return false;
762 }
763 
764 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
765  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
766  << 8;
767  if (MCI.size() <= Index)
768  return Sentinal;
769  MCOperand const &MCO = MCI.getOperand(Index);
770  if (!MCO.isExpr())
771  return Sentinal;
772  int64_t Value;
773  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
774  return Sentinal;
775  return Value;
776 }
777 
778 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
779  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
780  HExpr.setMustExtend(Val);
781 }
782 
784  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
785  return HExpr.mustExtend();
786 }
787 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
788  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
789  HExpr.setMustNotExtend(Val);
790 }
792  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
793  return HExpr.mustNotExtend();
794 }
795 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
796  HexagonMCExpr &HExpr =
797  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
798  HExpr.setS27_2_reloc(Val);
799 }
801  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
802  if (!HExpr)
803  return false;
804  return HExpr->s27_2_reloc();
805 }
806 
808  MCInst Nop;
809  Nop.setOpcode(Hexagon::A2_nop);
810  assert(isBundle(MCB));
811  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
815  MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
816 }
817 
820  if (!isPredicated(MCII, MCI))
821  return {0, 0, false};
822  MCInstrDesc const &Desc = getDesc(MCII, MCI);
823  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
824  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
825  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
826  return {0, 0, false};
827 }
828 
830  MCInst const &MCI) {
831  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
833 }
834 
835 /// return true if instruction has hasTmpDst attribute.
836 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
837  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
839 }
840 
842  DuplexCandidate Candidate) {
843  assert(Candidate.packetIndexI < MCB.size());
844  assert(Candidate.packetIndexJ < MCB.size());
845  assert(isBundle(MCB));
846  MCInst *Duplex =
847  deriveDuplex(Context, Candidate.iClass,
848  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
849  *MCB.getOperand(Candidate.packetIndexI).getInst());
850  assert(Duplex != nullptr);
851  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
852  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
853 }
854 
856  assert(isBundle(MCI));
857  MCOperand &Operand = MCI.getOperand(0);
858  Operand.setImm(Operand.getImm() | innerLoopMask);
859 }
860 
862  assert(isBundle(MCI));
863  MCOperand &Operand = MCI.getOperand(0);
864  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
866 }
867 
869  assert(isBundle(MCI));
870  MCOperand &Operand = MCI.getOperand(0);
871  Operand.setImm(Operand.getImm() | outerLoopMask);
872 }
873 
874 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
875  unsigned Producer,
876  unsigned Producer2) {
877  // If we're a single vector consumer of a double producer, set subreg bit
878  // based on if we're accessing the lower or upper register component
879  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
880  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
881  return (Consumer - Hexagon::V0) & 0x1;
882  if (Producer2 != Hexagon::NoRegister)
883  return Consumer == Producer;
884  return 0;
885 }
#define HEXAGON_PACKET_INNER_SIZE
Definition: Hexagon.h:36
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const & operator*() const
iterator end()
Definition: MCInst.h:196
iterator begin()
Definition: MCInst.h:194
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:250
bool isImm() const
Definition: MCInst.h:59
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:241
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool s27_2_reloc() const
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void setInst(const MCInst *Val)
Definition: MCInst.h:111
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
bool isIntRegForSubInst(unsigned Reg)
unsigned Reg
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
bool isReg() const
Definition: MCInst.h:58
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:241
#define R2(n)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:275
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:209
const FeatureBitset & getFeatureBits() const
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
void erase(iterator I)
Definition: MCInst.h:192
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool s27_2_reloc(MCExpr const &Expr)
void padEndloop(MCInst &MCI, MCContext &Context)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:63
MCInst const & instruction(MCInst const &MCB, size_t Index)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
const MCInst * getInst() const
Definition: MCInst.h:106
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const MCExpr * getExpr() const
Definition: MCInst.h:96
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:314
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
void setS27_2_reloc(bool Val=true)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:76
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:570
void setImm(int64_t Val)
Definition: MCInst.h:81
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool mustExtend(MCExpr const &Expr)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
int64_t const memReorderDisabledMask
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
cl::opt< bool > HexagonDisableCompound
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isExpr() const
Definition: MCInst.h:61
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
bool mustNotExtend() const
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
void setLoc(SMLoc loc)
Definition: MCInst.h:179
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:173
size_t const bundleInstructionsOffset
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:224
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
SMLoc getLoc() const
Definition: MCInst.h:180
unsigned const TypeCVI_FIRST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const TypeCVI_LAST
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
Definition: Hexagon.h:37
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
MCExpr const & getExpr(MCExpr const &Expr)
size_t size() const
Definition: MCInst.h:193
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:73
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
const InstrStage HexagonStages[]
bool mustExtend() const
uint16_t LastStage
Index of last + 1 stage in itinerary.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool check(bool FullCheck=true)
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
LLVM Value Representation.
Definition: Value.h:73
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:173
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:174
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)