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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Hexagon.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/Support/Casting.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <limits>
33 
34 using namespace llvm;
35 
37  MCInst const &Inst)
38  : MCII(MCII), BundleCurrent(Inst.begin() +
39  HexagonMCInstrInfo::bundleInstructionsOffset),
40  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
41 
43  MCInst const &Inst, std::nullptr_t)
44  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
45  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
46 
48  if (DuplexCurrent != DuplexEnd) {
49  ++DuplexCurrent;
50  if (DuplexCurrent == DuplexEnd) {
51  DuplexCurrent = BundleEnd;
52  DuplexEnd = BundleEnd;
53  }
54  return *this;
55  }
56  ++BundleCurrent;
57  if (BundleCurrent != BundleEnd) {
58  MCInst const &Inst = *BundleCurrent->getInst();
59  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
60  DuplexCurrent = Inst.begin();
61  DuplexEnd = Inst.end();
62  }
63  }
64  return *this;
65 }
66 
68  if (DuplexCurrent != DuplexEnd)
69  return *DuplexCurrent->getInst();
70  return *BundleCurrent->getInst();
71 }
72 
74  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
75  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
76 }
77 
79  MCContext &Context) {
81 }
82 
84  MCInstrInfo const &MCII, MCInst &MCB,
85  MCInst const &MCI) {
87  MCOperand const &exOp =
89 
90  // Create the extender.
91  MCInst *XMCI =
92  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
93 
95 }
96 
99  MCInst const &MCI) {
100  assert(isBundle(MCI));
101  return make_range(Hexagon::PacketIterator(MCII, MCI),
102  Hexagon::PacketIterator(MCII, MCI, nullptr));
103 }
104 
107  assert(isBundle(MCI));
108  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
109 }
110 
113  return (MCI.size() - bundleInstructionsOffset);
114  else
115  return (1);
116 }
117 
119  MCSubtargetInfo const &STI,
120  MCContext &Context, MCInst &MCB,
122  // Check the bundle for errors.
123  bool CheckOk = Check ? Check->check(false) : true;
124  if (!CheckOk)
125  return false;
126  // Examine the packet and convert pairs of instructions to compound
127  // instructions when possible.
129  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
130  HexagonMCShuffle(Context, false, MCII, STI, MCB);
131  // Examine the packet and convert pairs of instructions to duplex
132  // instructions when possible.
133  MCInst InstBundlePreDuplex = MCInst(MCB);
134  if (!HexagonDisableDuplex) {
135  SmallVector<DuplexCandidate, 8> possibleDuplexes;
136  possibleDuplexes =
138  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
139  }
140  // Examines packet and pad the packet, if needed, when an
141  // end-loop is in the bundle.
142  HexagonMCInstrInfo::padEndloop(MCB, Context);
143  // If compounding and duplexing didn't reduce the size below
144  // 4 or less we have a packet that is too big.
146  return false;
147  // Check the bundle for errors.
148  CheckOk = Check ? Check->check(true) : true;
149  if (!CheckOk)
150  return false;
151  HexagonMCShuffle(Context, true, MCII, STI, MCB);
152  return true;
153 }
154 
156  MCContext &Context, MCInst &MCI) {
158  HexagonMCInstrInfo::isExtended(MCII, MCI));
159  MCOperand &exOp =
161  // If the extended value is a constant, then use it for the extended and
162  // for the extender instructions, masking off the lower 6 bits and
163  // including the assumed bits.
164  int64_t Value;
165  if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
166  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
168  MCConstantExpr::create((Value & 0x3f) << Shift, Context), Context));
169  }
170 }
171 
173  MCInst Result;
174  Result.setOpcode(Hexagon::BUNDLE);
175  Result.addOperand(MCOperand::createImm(0));
176  return Result;
177 }
178 
180  MCInst const &Inst,
181  MCOperand const &MO) {
183  HexagonMCInstrInfo::isExtended(MCII, Inst));
184 
185  MCInst XMI;
186  XMI.setOpcode(Hexagon::A4_ext);
187  if (MO.isImm())
188  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
189  else if (MO.isExpr())
191  else
192  llvm_unreachable("invalid extendable operand");
193  return XMI;
194 }
195 
197  MCInst const &inst0,
198  MCInst const &inst1) {
199  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
200  MCInst *duplexInst = new (Context) MCInst;
201  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
202 
203  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
204  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
205  duplexInst->addOperand(MCOperand::createInst(SubInst0));
206  duplexInst->addOperand(MCOperand::createInst(SubInst1));
207  return duplexInst;
208 }
209 
211  size_t Index) {
212  assert(Index <= bundleSize(MCB));
213  if (Index == 0)
214  return nullptr;
215  MCInst const *Inst =
216  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
217  if (isImmext(*Inst))
218  return Inst;
219  return nullptr;
220 }
221 
223  MCInstrInfo const &MCII, MCInst &MCB,
224  MCInst const &MCI) {
225  if (isConstExtended(MCII, MCI))
226  addConstExtender(Context, MCII, MCB, MCI);
227 }
228 
230  MCInst const &MCI) {
231  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
234 }
235 
237  MCInst const &MCI) {
238  return MCII.get(MCI.getOpcode());
239 }
240 
242  using namespace Hexagon;
243 
244  switch (Reg) {
245  default:
246  llvm_unreachable("unknown duplex register");
247  // Rs Rss
248  case R0:
249  case D0:
250  return 0;
251  case R1:
252  case D1:
253  return 1;
254  case R2:
255  case D2:
256  return 2;
257  case R3:
258  case D3:
259  return 3;
260  case R4:
261  case D8:
262  return 4;
263  case R5:
264  case D9:
265  return 5;
266  case R6:
267  case D10:
268  return 6;
269  case R7:
270  case D11:
271  return 7;
272  case R16:
273  return 8;
274  case R17:
275  return 9;
276  case R18:
277  return 10;
278  case R19:
279  return 11;
280  case R20:
281  return 12;
282  case R21:
283  return 13;
284  case R22:
285  return 14;
286  case R23:
287  return 15;
288  }
289 }
290 
292  const auto &HExpr = cast<HexagonMCExpr>(Expr);
293  assert(HExpr.getExpr());
294  return *HExpr.getExpr();
295 }
296 
298  MCInst const &MCI) {
299  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
301 }
302 
303 MCOperand const &
305  MCInst const &MCI) {
306  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
307  MCOperand const &MO = MCI.getOperand(O);
308 
310  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
311  (MO.isImm() || MO.isExpr()));
312  return (MO);
313 }
314 
316  MCInst const &MCI) {
317  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
319 }
320 
322  MCInst const &MCI) {
323  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
325 }
326 
327 /// Return the maximum value of an extendable operand.
329  MCInst const &MCI) {
330  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
332 
334  HexagonMCInstrInfo::isExtended(MCII, MCI));
335 
336  if (S) // if value is signed
337  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
338  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
339 }
340 
341 /// Return the minimum value of an extendable operand.
343  MCInst const &MCI) {
344  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
346 
348  HexagonMCInstrInfo::isExtended(MCII, MCI));
349 
350  if (S) // if value is signed
351  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
352  return 0;
353 }
354 
356  MCInst const &MCI) {
357  return MCII.getName(MCI.getOpcode());
358 }
359 
361  MCInst const &MCI) {
362  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
364 }
365 
367  MCInst const &MCI) {
368  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
369  MCOperand const &MCO = MCI.getOperand(O);
370 
372  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
373  MCO.isReg());
374  return (MCO);
375 }
376 
377 /// Return the new value or the newly produced value.
379  MCInst const &MCI) {
380  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
382 }
383 
384 MCOperand const &
386  MCInst const &MCI) {
387  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
388  MCOperand const &MCO = MCI.getOperand(O);
389 
391  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
392  MCO.isReg());
393  return (MCO);
394 }
395 
396 /// Return the Hexagon ISA class for the insn.
398  MCInst const &MCI) {
399  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
400  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
401 }
402 
403 /// Return the slots this instruction can execute out of
405  MCSubtargetInfo const &STI,
406  MCInst const &MCI) {
408  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
409  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
410 }
411 
412 /// Return the slots this instruction consumes in addition to
413 /// the slot(s) it can execute out of
414 
416  MCSubtargetInfo const &STI,
417  MCInst const &MCI) {
419  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
420  unsigned Slots = 0;
421 
422  // FirstStage are slots that this instruction can execute in.
423  // FirstStage+1 are slots that are also consumed by this instruction.
424  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
425  for (unsigned Stage = II[SchedClass].FirstStage + 1;
426  Stage < II[SchedClass].LastStage; ++Stage) {
427  unsigned Units = (Stage + HexagonStages)->getUnits();
428  if (Units > HexagonGetLastSlot())
429  break;
430  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
431  Slots |= Units;
432  }
433 
434  // if 0 is returned, then no additional slots are consumed by this inst.
435  return Slots;
436 }
437 
438 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
440  return false;
441 
442  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCI)) {
443  if (HexagonMCInstrInfo::isDuplex(MCII, I))
444  return true;
445  }
446 
447  return false;
448 }
449 
450 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
451  return extenderForIndex(MCB, Index) != nullptr;
452 }
453 
456  return false;
457 
458  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
459  if (isImmext(*I.getInst()))
460  return true;
461  }
462 
463  return false;
464 }
465 
466 /// Return whether the insn produces a value.
468  MCInst const &MCI) {
469  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
471 }
472 
473 /// Return whether the insn produces a second value.
475  MCInst const &MCI) {
476  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
478 }
479 
480 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
481  assert(isBundle(MCB));
482  assert(Index < HEXAGON_PACKET_SIZE);
483  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
484 }
485 
486 /// Return where the instruction is an accumulator.
488  MCInst const &MCI) {
489  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
491 }
492 
494  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
495  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
496  return Result;
497 }
498 
500  MCInst const &MCI) {
501  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
502  return true;
503  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
504  return false;
506  if (isa<HexagonMCExpr>(MO.getExpr()) &&
508  return true;
509  // Branch insns are handled as necessary by relaxation.
510  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
512  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
515  return false;
516  // Otherwise loop instructions and other CR insts are handled by relaxation
517  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
518  (MCI.getOpcode() != Hexagon::C4_addipc))
519  return false;
520 
521  assert(!MO.isImm());
522  if (isa<HexagonMCExpr>(MO.getExpr()) &&
524  return false;
525  int64_t Value;
526  if (!MO.getExpr()->evaluateAsAbsolute(Value))
527  return true;
528  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
529  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
530  return (MinValue > Value || Value > MaxValue);
531 }
532 
533 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
534  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
535  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
536 }
537 
538 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
539  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
541 }
542 
544  MCInst const &MCI) {
545  return (getType(MCII, MCI) == HexagonII::TypeCJ);
546 }
547 
548 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
549  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
551 }
552 
554  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
555  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
556 }
557 
558 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
560 }
561 
563  MCInst const &MCI) {
564  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
566 }
567 
569  MCInst const &MCI) {
570  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
572 }
573 
574 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
575  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
576  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
577 }
578 
580  return MCI.getOpcode() == Hexagon::A4_ext;
581 }
582 
584  assert(isBundle(MCI));
585  int64_t Flags = MCI.getOperand(0).getImm();
586  return (Flags & innerLoopMask) != 0;
587 }
588 
590  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
591 }
592 
594  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
595  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
596 }
597 
598 /// Return whether the insn expects newly produced value.
600  MCInst const &MCI) {
601  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
603 }
604 
605 /// Return whether the operand is extendable.
607  MCInst const &MCI, unsigned short O) {
608  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
609 }
610 
612  assert(isBundle(MCI));
613  int64_t Flags = MCI.getOperand(0).getImm();
614  return (Flags & outerLoopMask) != 0;
615 }
616 
618  MCInst const &MCI) {
619  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
621 }
622 
623 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
625 }
626 
628  MCInst const &MCI) {
629  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
631 }
632 
633 /// Return whether the insn is newly predicated.
635  MCInst const &MCI) {
636  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
638 }
639 
641  MCInst const &MCI) {
642  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
643  return (
645 }
646 
648  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
649 }
650 
651 /// Return whether the insn can be packaged only with A and X-type insns.
652 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
653  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
655 }
656 
657 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
659  MCInst const &MCI) {
660  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
662 }
663 
664 /// Return whether the insn is solo, i.e., cannot be in a packet.
665 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
666  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
667  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
668 }
669 
671  assert(isBundle(MCI));
672  auto Flags = MCI.getOperand(0).getImm();
673  return (Flags & memReorderDisabledMask) != 0;
674 }
675 
677  assert(isBundle(MCI));
678  auto Flags = MCI.getOperand(0).getImm();
679  return (Flags & memStoreReorderEnabledMask) != 0;
680 }
681 
683  switch (MCI.getOpcode()) {
684  default:
685  return false;
686  case Hexagon::SA1_addi:
687  case Hexagon::SA1_addrx:
688  case Hexagon::SA1_addsp:
689  case Hexagon::SA1_and1:
690  case Hexagon::SA1_clrf:
691  case Hexagon::SA1_clrfnew:
692  case Hexagon::SA1_clrt:
693  case Hexagon::SA1_clrtnew:
694  case Hexagon::SA1_cmpeqi:
695  case Hexagon::SA1_combine0i:
696  case Hexagon::SA1_combine1i:
697  case Hexagon::SA1_combine2i:
698  case Hexagon::SA1_combine3i:
699  case Hexagon::SA1_combinerz:
700  case Hexagon::SA1_combinezr:
701  case Hexagon::SA1_dec:
702  case Hexagon::SA1_inc:
703  case Hexagon::SA1_seti:
704  case Hexagon::SA1_setin1:
705  case Hexagon::SA1_sxtb:
706  case Hexagon::SA1_sxth:
707  case Hexagon::SA1_tfr:
708  case Hexagon::SA1_zxtb:
709  case Hexagon::SA1_zxth:
710  case Hexagon::SL1_loadri_io:
711  case Hexagon::SL1_loadrub_io:
712  case Hexagon::SL2_deallocframe:
713  case Hexagon::SL2_jumpr31:
714  case Hexagon::SL2_jumpr31_f:
715  case Hexagon::SL2_jumpr31_fnew:
716  case Hexagon::SL2_jumpr31_t:
717  case Hexagon::SL2_jumpr31_tnew:
718  case Hexagon::SL2_loadrb_io:
719  case Hexagon::SL2_loadrd_sp:
720  case Hexagon::SL2_loadrh_io:
721  case Hexagon::SL2_loadri_sp:
722  case Hexagon::SL2_loadruh_io:
723  case Hexagon::SL2_return:
724  case Hexagon::SL2_return_f:
725  case Hexagon::SL2_return_fnew:
726  case Hexagon::SL2_return_t:
727  case Hexagon::SL2_return_tnew:
728  case Hexagon::SS1_storeb_io:
729  case Hexagon::SS1_storew_io:
730  case Hexagon::SS2_allocframe:
731  case Hexagon::SS2_storebi0:
732  case Hexagon::SS2_storebi1:
733  case Hexagon::SS2_stored_sp:
734  case Hexagon::SS2_storeh_io:
735  case Hexagon::SS2_storew_sp:
736  case Hexagon::SS2_storewi0:
737  case Hexagon::SS2_storewi1:
738  return true;
739  }
740 }
741 
742 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
743  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
744  (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
745  return true;
746  return false;
747 }
748 
749 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
750  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
751  << 8;
752  if (MCI.size() <= Index)
753  return Sentinal;
754  MCOperand const &MCO = MCI.getOperand(Index);
755  if (!MCO.isExpr())
756  return Sentinal;
757  int64_t Value;
758  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
759  return Sentinal;
760  return Value;
761 }
762 
763 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
764  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
765  HExpr.setMustExtend(Val);
766 }
767 
769  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
770  return HExpr.mustExtend();
771 }
772 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
773  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
774  HExpr.setMustNotExtend(Val);
775 }
777  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
778  return HExpr.mustNotExtend();
779 }
780 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
781  HexagonMCExpr &HExpr =
782  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
783  HExpr.setS27_2_reloc(Val);
784 }
786  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
787  if (!HExpr)
788  return false;
789  return HExpr->s27_2_reloc();
790 }
791 
793  MCInst Nop;
794  Nop.setOpcode(Hexagon::A2_nop);
795  assert(isBundle(MCB));
796  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
800  MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
801 }
802 
804  MCInst const &MCI) {
805  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
807 }
808 
810  DuplexCandidate Candidate) {
811  assert(Candidate.packetIndexI < MCB.size());
812  assert(Candidate.packetIndexJ < MCB.size());
813  assert(isBundle(MCB));
814  MCInst *Duplex =
815  deriveDuplex(Context, Candidate.iClass,
816  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
817  *MCB.getOperand(Candidate.packetIndexI).getInst());
818  assert(Duplex != nullptr);
819  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
820  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
821 }
822 
824  assert(isBundle(MCI));
825  MCOperand &Operand = MCI.getOperand(0);
826  Operand.setImm(Operand.getImm() | innerLoopMask);
827 }
828 
830  assert(isBundle(MCI));
831  MCOperand &Operand = MCI.getOperand(0);
832  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
834 }
835 
837  assert(isBundle(MCI));
838  MCOperand &Operand = MCI.getOperand(0);
839  Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
841 }
842 
844  assert(isBundle(MCI));
845  MCOperand &Operand = MCI.getOperand(0);
846  Operand.setImm(Operand.getImm() | outerLoopMask);
847 }
848 
849 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
850  unsigned Producer,
851  unsigned Producer2) {
852  // If we're a single vector consumer of a double producer, set subreg bit
853  // based on if we're accessing the lower or upper register component
854  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
855  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
856  return (Consumer - Hexagon::V0) & 0x1;
857  if (Consumer == Producer2)
858  return 0x1;
859  return 0;
860 }
bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
#define HEXAGON_PACKET_INNER_SIZE
Definition: Hexagon.h:36
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const & operator*() const
iterator end()
Definition: MCInst.h:194
iterator begin()
Definition: MCInst.h:192
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
bool isImm() const
Definition: MCInst.h:59
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:235
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool s27_2_reloc() const
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void setInst(const MCInst *Val)
Definition: MCInst.h:111
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isIntRegForSubInst(unsigned Reg)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
bool isReg() const
Definition: MCInst.h:58
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
#define R2(n)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:270
bool isMemStoreReorderEnabled(MCInst const &MCI)
bool isImmext(MCInst const &MCI)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
void erase(iterator I)
Definition: MCInst.h:190
Reg
All possible values of the reg field in the ModR/M byte.
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool s27_2_reloc(MCExpr const &Expr)
void padEndloop(MCInst &MCI, MCContext &Context)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:59
MCInst const & instruction(MCInst const &MCB, size_t Index)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
const MCInst * getInst() const
Definition: MCInst.h:106
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const MCExpr * getExpr() const
Definition: MCInst.h:96
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:194
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
void setS27_2_reloc(bool Val=true)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:76
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
void setMemStoreReorderEnabled(MCInst &MCI)
void setImm(int64_t Val)
Definition: MCInst.h:81
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
bool mustExtend(MCExpr const &Expr)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
int64_t const memReorderDisabledMask
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
cl::opt< bool > HexagonDisableCompound
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isExpr() const
Definition: MCInst.h:61
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
bool mustNotExtend() const
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t const memStoreReorderEnabledMask
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:171
size_t const bundleInstructionsOffset
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
unsigned LastStage
Index of last + 1 stage in itinerary.
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
unsigned const TypeCVI_FIRST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const TypeCVI_LAST
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
Definition: Hexagon.h:37
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
MCExpr const & getExpr(MCExpr const &Expr)
size_t size() const
Definition: MCInst.h:191
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
MCSubtargetInfo - Generic base class for all target subtargets.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
const InstrStage HexagonStages[]
bool mustExtend() const
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool check(bool FullCheck=true)
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
LLVM Value Representation.
Definition: Value.h:73
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:172
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
cl::opt< bool > HexagonDisableDuplex
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
void setExpr(const MCExpr *Val)
Definition: MCInst.h:101
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)