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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "Hexagon.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/Support/Casting.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <limits>
32 
33 using namespace llvm;
34 
36  return Register != Hexagon::NoRegister;
37 }
38 
40  MCInst const &Inst)
41  : MCII(MCII), BundleCurrent(Inst.begin() +
42  HexagonMCInstrInfo::bundleInstructionsOffset),
43  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44 
46  MCInst const &Inst, std::nullptr_t)
47  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49 
51  if (DuplexCurrent != DuplexEnd) {
52  ++DuplexCurrent;
53  if (DuplexCurrent == DuplexEnd) {
54  DuplexCurrent = BundleEnd;
55  DuplexEnd = BundleEnd;
56  ++BundleCurrent;
57  }
58  return *this;
59  }
60  ++BundleCurrent;
61  if (BundleCurrent != BundleEnd) {
62  MCInst const &Inst = *BundleCurrent->getInst();
63  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64  DuplexCurrent = Inst.begin();
65  DuplexEnd = Inst.end();
66  }
67  }
68  return *this;
69 }
70 
72  if (DuplexCurrent != DuplexEnd)
73  return *DuplexCurrent->getInst();
74  return *BundleCurrent->getInst();
75 }
76 
78  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80 }
81 
83  MCContext &Context) {
85 }
86 
88  MCInstrInfo const &MCII, MCInst &MCB,
89  MCInst const &MCI) {
91  MCOperand const &exOp =
93 
94  // Create the extender.
95  MCInst *XMCI =
96  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97  XMCI->setLoc(MCI.getLoc());
98 
100 }
101 
104  MCInst const &MCI) {
105  assert(isBundle(MCI));
106  return make_range(Hexagon::PacketIterator(MCII, MCI),
107  Hexagon::PacketIterator(MCII, MCI, nullptr));
108 }
109 
112  assert(isBundle(MCI));
113  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
114 }
115 
118  return (MCI.size() - bundleInstructionsOffset);
119  else
120  return (1);
121 }
122 
124  MCSubtargetInfo const &STI,
125  MCContext &Context, MCInst &MCB,
127  // Check the bundle for errors.
128  bool CheckOk = Check ? Check->check(false) : true;
129  if (!CheckOk)
130  return false;
131  // Examine the packet and convert pairs of instructions to compound
132  // instructions when possible.
134  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
135  HexagonMCShuffle(Context, false, MCII, STI, MCB);
136  // Examine the packet and convert pairs of instructions to duplex
137  // instructions when possible.
138  MCInst InstBundlePreDuplex = MCInst(MCB);
139  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
140  SmallVector<DuplexCandidate, 8> possibleDuplexes;
141  possibleDuplexes =
143  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
144  }
145  // Examines packet and pad the packet, if needed, when an
146  // end-loop is in the bundle.
147  HexagonMCInstrInfo::padEndloop(MCB, Context);
148  // If compounding and duplexing didn't reduce the size below
149  // 4 or less we have a packet that is too big.
151  return false;
152  // Check the bundle for errors.
153  CheckOk = Check ? Check->check(true) : true;
154  if (!CheckOk)
155  return false;
156  HexagonMCShuffle(Context, true, MCII, STI, MCB);
157  return true;
158 }
159 
161  MCInst const &Inst,
162  MCOperand const &MO) {
164  HexagonMCInstrInfo::isExtended(MCII, Inst));
165 
166  MCInst XMI;
167  XMI.setOpcode(Hexagon::A4_ext);
168  if (MO.isImm())
169  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
170  else if (MO.isExpr())
172  else
173  llvm_unreachable("invalid extendable operand");
174  return XMI;
175 }
176 
178  MCInst const &inst0,
179  MCInst const &inst1) {
180  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
181  MCInst *duplexInst = new (Context) MCInst;
182  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
183 
184  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
185  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
186  duplexInst->addOperand(MCOperand::createInst(SubInst0));
187  duplexInst->addOperand(MCOperand::createInst(SubInst1));
188  return duplexInst;
189 }
190 
192  size_t Index) {
193  assert(Index <= bundleSize(MCB));
194  if (Index == 0)
195  return nullptr;
196  MCInst const *Inst =
197  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
198  if (isImmext(*Inst))
199  return Inst;
200  return nullptr;
201 }
202 
204  MCInstrInfo const &MCII, MCInst &MCB,
205  MCInst const &MCI) {
206  if (isConstExtended(MCII, MCI))
207  addConstExtender(Context, MCII, MCB, MCI);
208 }
209 
211  MCInst const &MCI) {
212  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
215 }
216 
218  MCInst const &MCI) {
219  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
220  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
222 }
223 
225  MCInst const &MCI) {
226  return MCII.get(MCI.getOpcode());
227 }
228 
230  using namespace Hexagon;
231 
232  switch (Reg) {
233  default:
234  llvm_unreachable("unknown duplex register");
235  // Rs Rss
236  case R0:
237  case D0:
238  return 0;
239  case R1:
240  case D1:
241  return 1;
242  case R2:
243  case D2:
244  return 2;
245  case R3:
246  case D3:
247  return 3;
248  case R4:
249  case D8:
250  return 4;
251  case R5:
252  case D9:
253  return 5;
254  case R6:
255  case D10:
256  return 6;
257  case R7:
258  case D11:
259  return 7;
260  case R16:
261  return 8;
262  case R17:
263  return 9;
264  case R18:
265  return 10;
266  case R19:
267  return 11;
268  case R20:
269  return 12;
270  case R21:
271  return 13;
272  case R22:
273  return 14;
274  case R23:
275  return 15;
276  }
277 }
278 
280  const auto &HExpr = cast<HexagonMCExpr>(Expr);
281  assert(HExpr.getExpr());
282  return *HExpr.getExpr();
283 }
284 
286  MCInst const &MCI) {
287  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
289 }
290 
291 MCOperand const &
293  MCInst const &MCI) {
294  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
295  MCOperand const &MO = MCI.getOperand(O);
296 
298  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
299  (MO.isImm() || MO.isExpr()));
300  return (MO);
301 }
302 
304  MCInst const &MCI) {
305  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
307 }
308 
310  MCInst const &MCI) {
311  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
313 }
314 
316  MCInst const &MCI) {
317  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
319 }
320 
321 /// Return the maximum value of an extendable operand.
323  MCInst const &MCI) {
325  HexagonMCInstrInfo::isExtended(MCII, MCI));
326 
327  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
328  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
329  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
330 }
331 
332 /// Return the minimum value of an extendable operand.
334  MCInst const &MCI) {
336  HexagonMCInstrInfo::isExtended(MCII, MCI));
337 
338  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
339  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
340  return 0;
341 }
342 
344  MCInst const &MCI) {
345  return MCII.getName(MCI.getOpcode());
346 }
347 
349  MCInst const &MCI) {
350  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
352 }
353 
355  MCInst const &MCI) {
356  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
357  // VTMP doesn't actually exist in the encodings for these 184
358  // 3 instructions so go ahead and create it here.
359  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
360  return (MCO);
361  } else {
362  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
363  MCOperand const &MCO = MCI.getOperand(O);
364 
366  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
367  MCO.isReg());
368  return (MCO);
369  }
370 }
371 
372 /// Return the new value or the newly produced value.
374  MCInst const &MCI) {
375  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
377 }
378 
379 MCOperand const &
381  MCInst const &MCI) {
382  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
383  MCOperand const &MCO = MCI.getOperand(O);
384 
386  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
387  MCO.isReg());
388  return (MCO);
389 }
390 
391 /// Return the Hexagon ISA class for the insn.
393  MCInst const &MCI) {
394  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
395  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
396 }
397 
398 /// Return the slots this instruction can execute out of
400  MCSubtargetInfo const &STI,
401  MCInst const &MCI) {
403  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
404  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
405 }
406 
407 /// Return the slots this instruction consumes in addition to
408 /// the slot(s) it can execute out of
409 
411  MCSubtargetInfo const &STI,
412  MCInst const &MCI) {
414  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
415  unsigned Slots = 0;
416 
417  // FirstStage are slots that this instruction can execute in.
418  // FirstStage+1 are slots that are also consumed by this instruction.
419  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
420  for (unsigned Stage = II[SchedClass].FirstStage + 1;
421  Stage < II[SchedClass].LastStage; ++Stage) {
422  unsigned Units = (Stage + HexagonStages)->getUnits();
423  if (Units > HexagonGetLastSlot())
424  break;
425  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
426  Slots |= Units;
427  }
428 
429  // if 0 is returned, then no additional slots are consumed by this inst.
430  return Slots;
431 }
432 
433 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
435  return false;
436 
437  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
438  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
439  return true;
440  }
441 
442  return false;
443 }
444 
446  return extenderForIndex(MCB, Index) != nullptr;
447 }
448 
451  return false;
452 
453  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
454  if (isImmext(*I.getInst()))
455  return true;
456  }
457 
458  return false;
459 }
460 
461 /// Return whether the insn produces a value.
463  MCInst const &MCI) {
464  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
466 }
467 
468 /// Return whether the insn produces a second value.
470  MCInst const &MCI) {
471  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
473 }
474 
476  assert(isBundle(MCB));
477  assert(Index < HEXAGON_PACKET_SIZE);
478  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
479 }
480 
481 /// Return where the instruction is an accumulator.
483  MCInst const &MCI) {
484  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
486 }
487 
489  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
490  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
491  return Result;
492 }
493 
495  MCInst const &MCI) {
496  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
497  return true;
498  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
499  return false;
501  if (isa<HexagonMCExpr>(MO.getExpr()) &&
503  return true;
504  // Branch insns are handled as necessary by relaxation.
505  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
507  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
510  return false;
511  // Otherwise loop instructions and other CR insts are handled by relaxation
512  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
513  (MCI.getOpcode() != Hexagon::C4_addipc))
514  return false;
515 
516  assert(!MO.isImm());
517  if (isa<HexagonMCExpr>(MO.getExpr()) &&
519  return false;
520  int64_t Value;
521  if (!MO.getExpr()->evaluateAsAbsolute(Value))
522  return true;
523  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
524  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
525  return (MinValue > Value || Value > MaxValue);
526 }
527 
528 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
529  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
530  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
531 }
532 
533 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
534  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
536 }
537 
539  MCInst const &MCI) {
540  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
542 }
543 
545  MCInst const &MCI) {
546  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
548 }
549 
551  MCInst const &MCI) {
552  return (getType(MCII, MCI) == HexagonII::TypeCJ);
553 }
554 
555 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
556  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
558 }
559 
561  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
562  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
563 }
564 
565 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
567 }
568 
570  MCInst const &MCI) {
571  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
573 }
574 
576  MCInst const &MCI) {
577  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
579 }
580 
581 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
582  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
583  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
584 }
585 
586 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
587  const uint64_t V = getType(MCII, MCI);
589 }
590 
592  return MCI.getOpcode() == Hexagon::A4_ext;
593 }
594 
596  assert(isBundle(MCI));
597  int64_t Flags = MCI.getOperand(0).getImm();
598  return (Flags & innerLoopMask) != 0;
599 }
600 
602  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
603 }
604 
606  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
607  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
608 }
609 
610 /// Return whether the insn expects newly produced value.
612  MCInst const &MCI) {
613  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
615 }
616 
617 /// Return whether the operand is extendable.
619  MCInst const &MCI, unsigned short O) {
620  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
621 }
622 
624  assert(isBundle(MCI));
625  int64_t Flags = MCI.getOperand(0).getImm();
626  return (Flags & outerLoopMask) != 0;
627 }
628 
630  MCInst const &MCI) {
631  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
633 }
634 
635 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
637 }
638 
640  MCInst const &MCI) {
641  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
643 }
644 
645 /// Return whether the insn is newly predicated.
647  MCInst const &MCI) {
648  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
650 }
651 
653  MCInst const &MCI) {
654  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
655  return (
657 }
658 
660  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
661 }
662 
663 /// Return whether the insn can be packaged only with A and X-type insns.
664 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
665  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
667 }
668 
669 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
671  MCInst const &MCI) {
672  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
673  return ((F >> HexagonII::RestrictSlot1AOKPos) &
675 }
676 
678  MCInst const &MCI) {
679  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
680  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
682 }
683 
684 /// Return whether the insn is solo, i.e., cannot be in a packet.
685 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
686  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
687  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
688 }
689 
691  assert(isBundle(MCI));
692  auto Flags = MCI.getOperand(0).getImm();
693  return (Flags & memReorderDisabledMask) != 0;
694 }
695 
697  switch (MCI.getOpcode()) {
698  default:
699  return false;
700  case Hexagon::SA1_addi:
701  case Hexagon::SA1_addrx:
702  case Hexagon::SA1_addsp:
703  case Hexagon::SA1_and1:
704  case Hexagon::SA1_clrf:
705  case Hexagon::SA1_clrfnew:
706  case Hexagon::SA1_clrt:
707  case Hexagon::SA1_clrtnew:
708  case Hexagon::SA1_cmpeqi:
709  case Hexagon::SA1_combine0i:
710  case Hexagon::SA1_combine1i:
711  case Hexagon::SA1_combine2i:
712  case Hexagon::SA1_combine3i:
713  case Hexagon::SA1_combinerz:
714  case Hexagon::SA1_combinezr:
715  case Hexagon::SA1_dec:
716  case Hexagon::SA1_inc:
717  case Hexagon::SA1_seti:
718  case Hexagon::SA1_setin1:
719  case Hexagon::SA1_sxtb:
720  case Hexagon::SA1_sxth:
721  case Hexagon::SA1_tfr:
722  case Hexagon::SA1_zxtb:
723  case Hexagon::SA1_zxth:
724  case Hexagon::SL1_loadri_io:
725  case Hexagon::SL1_loadrub_io:
726  case Hexagon::SL2_deallocframe:
727  case Hexagon::SL2_jumpr31:
728  case Hexagon::SL2_jumpr31_f:
729  case Hexagon::SL2_jumpr31_fnew:
730  case Hexagon::SL2_jumpr31_t:
731  case Hexagon::SL2_jumpr31_tnew:
732  case Hexagon::SL2_loadrb_io:
733  case Hexagon::SL2_loadrd_sp:
734  case Hexagon::SL2_loadrh_io:
735  case Hexagon::SL2_loadri_sp:
736  case Hexagon::SL2_loadruh_io:
737  case Hexagon::SL2_return:
738  case Hexagon::SL2_return_f:
739  case Hexagon::SL2_return_fnew:
740  case Hexagon::SL2_return_t:
741  case Hexagon::SL2_return_tnew:
742  case Hexagon::SS1_storeb_io:
743  case Hexagon::SS1_storew_io:
744  case Hexagon::SS2_allocframe:
745  case Hexagon::SS2_storebi0:
746  case Hexagon::SS2_storebi1:
747  case Hexagon::SS2_stored_sp:
748  case Hexagon::SS2_storeh_io:
749  case Hexagon::SS2_storew_sp:
750  case Hexagon::SS2_storewi0:
751  case Hexagon::SS2_storewi1:
752  return true;
753  }
754 }
755 
756 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
757  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
758  (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
759  return true;
760  return false;
761 }
762 
763 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
764  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
765  << 8;
766  if (MCI.size() <= Index)
767  return Sentinal;
768  MCOperand const &MCO = MCI.getOperand(Index);
769  if (!MCO.isExpr())
770  return Sentinal;
771  int64_t Value;
772  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
773  return Sentinal;
774  return Value;
775 }
776 
777 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
778  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
779  HExpr.setMustExtend(Val);
780 }
781 
783  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
784  return HExpr.mustExtend();
785 }
786 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
787  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
788  HExpr.setMustNotExtend(Val);
789 }
791  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
792  return HExpr.mustNotExtend();
793 }
794 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
795  HexagonMCExpr &HExpr =
796  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
797  HExpr.setS27_2_reloc(Val);
798 }
800  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
801  if (!HExpr)
802  return false;
803  return HExpr->s27_2_reloc();
804 }
805 
807  MCInst Nop;
808  Nop.setOpcode(Hexagon::A2_nop);
809  assert(isBundle(MCB));
810  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
814  MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
815 }
816 
819  if (!isPredicated(MCII, MCI))
820  return {0, 0, false};
821  MCInstrDesc const &Desc = getDesc(MCII, MCI);
822  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
823  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
824  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
825  return {0, 0, false};
826 }
827 
829  MCInst const &MCI) {
830  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
832 }
833 
834 /// return true if instruction has hasTmpDst attribute.
835 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
836  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
838 }
839 
841  DuplexCandidate Candidate) {
842  assert(Candidate.packetIndexI < MCB.size());
843  assert(Candidate.packetIndexJ < MCB.size());
844  assert(isBundle(MCB));
845  MCInst *Duplex =
846  deriveDuplex(Context, Candidate.iClass,
847  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
848  *MCB.getOperand(Candidate.packetIndexI).getInst());
849  assert(Duplex != nullptr);
850  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
851  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
852 }
853 
855  assert(isBundle(MCI));
856  MCOperand &Operand = MCI.getOperand(0);
857  Operand.setImm(Operand.getImm() | innerLoopMask);
858 }
859 
861  assert(isBundle(MCI));
862  MCOperand &Operand = MCI.getOperand(0);
863  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
865 }
866 
868  assert(isBundle(MCI));
869  MCOperand &Operand = MCI.getOperand(0);
870  Operand.setImm(Operand.getImm() | outerLoopMask);
871 }
872 
873 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
874  unsigned Producer,
875  unsigned Producer2) {
876  // If we're a single vector consumer of a double producer, set subreg bit
877  // based on if we're accessing the lower or upper register component
878  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
879  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
880  return (Consumer - Hexagon::V0) & 0x1;
881  if (Producer2 != Hexagon::NoRegister)
882  return Consumer == Producer;
883  return 0;
884 }
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const & operator*() const
iterator end()
Definition: MCInst.h:193
iterator begin()
Definition: MCInst.h:191
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
bool isImm() const
Definition: MCInst.h:58
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool s27_2_reloc() const
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void setInst(const MCInst *Val)
Definition: MCInst.h:110
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isIntRegForSubInst(unsigned Reg)
unsigned Reg
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
bool isReg() const
Definition: MCInst.h:57
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
#define R2(n)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:276
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const FeatureBitset & getFeatureBits() const
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void erase(iterator I)
Definition: MCInst.h:189
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool s27_2_reloc(MCExpr const &Expr)
void padEndloop(MCInst &MCI, MCContext &Context)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:62
MCInst const & instruction(MCInst const &MCB, size_t Index)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
const MCInst * getInst() const
Definition: MCInst.h:105
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const MCExpr * getExpr() const
Definition: MCInst.h:95
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:311
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void setS27_2_reloc(bool Val=true)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:75
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
void setImm(int64_t Val)
Definition: MCInst.h:80
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool mustExtend(MCExpr const &Expr)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
int64_t const memReorderDisabledMask
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
cl::opt< bool > HexagonDisableCompound
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isExpr() const
Definition: MCInst.h:60
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:50
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
bool mustNotExtend() const
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
size_t const bundleInstructionsOffset
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
#define HEXAGON_PACKET_INNER_SIZE
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
SMLoc getLoc() const
Definition: MCInst.h:177
unsigned const TypeCVI_FIRST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const TypeCVI_LAST
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:143
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
#define HEXAGON_PACKET_OUTER_SIZE
MCExpr const & getExpr(MCExpr const &Expr)
size_t size() const
Definition: MCInst.h:190
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
const InstrStage HexagonStages[]
bool mustExtend() const
uint16_t LastStage
Index of last + 1 stage in itinerary.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool check(bool FullCheck=true)
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_SIZE
LLVM Value Representation.
Definition: Value.h:72
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:171
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)