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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Hexagon.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/Support/Casting.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <limits>
33 
34 using namespace llvm;
35 
37  return Register != Hexagon::NoRegister;
38 }
39 
41  MCInst const &Inst)
42  : MCII(MCII), BundleCurrent(Inst.begin() +
43  HexagonMCInstrInfo::bundleInstructionsOffset),
44  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
45 
47  MCInst const &Inst, std::nullptr_t)
48  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
49  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
50 
52  if (DuplexCurrent != DuplexEnd) {
53  ++DuplexCurrent;
54  if (DuplexCurrent == DuplexEnd) {
55  DuplexCurrent = BundleEnd;
56  DuplexEnd = BundleEnd;
57  ++BundleCurrent;
58  }
59  return *this;
60  }
61  ++BundleCurrent;
62  if (BundleCurrent != BundleEnd) {
63  MCInst const &Inst = *BundleCurrent->getInst();
64  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
65  DuplexCurrent = Inst.begin();
66  DuplexEnd = Inst.end();
67  }
68  }
69  return *this;
70 }
71 
73  if (DuplexCurrent != DuplexEnd)
74  return *DuplexCurrent->getInst();
75  return *BundleCurrent->getInst();
76 }
77 
79  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
80  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
81 }
82 
84  MCContext &Context) {
86 }
87 
89  MCInstrInfo const &MCII, MCInst &MCB,
90  MCInst const &MCI) {
92  MCOperand const &exOp =
94 
95  // Create the extender.
96  MCInst *XMCI =
97  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
98  XMCI->setLoc(MCI.getLoc());
99 
101 }
102 
105  MCInst const &MCI) {
106  assert(isBundle(MCI));
107  return make_range(Hexagon::PacketIterator(MCII, MCI),
108  Hexagon::PacketIterator(MCII, MCI, nullptr));
109 }
110 
113  assert(isBundle(MCI));
114  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
115 }
116 
119  return (MCI.size() - bundleInstructionsOffset);
120  else
121  return (1);
122 }
123 
125  MCSubtargetInfo const &STI,
126  MCContext &Context, MCInst &MCB,
128  // Check the bundle for errors.
129  bool CheckOk = Check ? Check->check(false) : true;
130  if (!CheckOk)
131  return false;
132  // Examine the packet and convert pairs of instructions to compound
133  // instructions when possible.
135  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
136  HexagonMCShuffle(Context, false, MCII, STI, MCB);
137  // Examine the packet and convert pairs of instructions to duplex
138  // instructions when possible.
139  MCInst InstBundlePreDuplex = MCInst(MCB);
140  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
141  SmallVector<DuplexCandidate, 8> possibleDuplexes;
142  possibleDuplexes =
144  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
145  }
146  // Examines packet and pad the packet, if needed, when an
147  // end-loop is in the bundle.
148  HexagonMCInstrInfo::padEndloop(MCB, Context);
149  // If compounding and duplexing didn't reduce the size below
150  // 4 or less we have a packet that is too big.
152  return false;
153  // Check the bundle for errors.
154  CheckOk = Check ? Check->check(true) : true;
155  if (!CheckOk)
156  return false;
157  HexagonMCShuffle(Context, true, MCII, STI, MCB);
158  return true;
159 }
160 
162  MCContext &Context, MCInst &MCI) {
164  HexagonMCInstrInfo::isExtended(MCII, MCI));
165  MCOperand &exOp =
167  // If the extended value is a constant, then use it for the extended and
168  // for the extender instructions, masking off the lower 6 bits and
169  // including the assumed bits.
170  int64_t Value;
171  if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
172  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
174  MCConstantExpr::create((Value & 0x3f) << Shift, Context), Context));
175  }
176 }
177 
179  MCInst const &Inst,
180  MCOperand const &MO) {
182  HexagonMCInstrInfo::isExtended(MCII, Inst));
183 
184  MCInst XMI;
185  XMI.setOpcode(Hexagon::A4_ext);
186  if (MO.isImm())
187  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
188  else if (MO.isExpr())
190  else
191  llvm_unreachable("invalid extendable operand");
192  return XMI;
193 }
194 
196  MCInst const &inst0,
197  MCInst const &inst1) {
198  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
199  MCInst *duplexInst = new (Context) MCInst;
200  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
201 
202  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
203  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
204  duplexInst->addOperand(MCOperand::createInst(SubInst0));
205  duplexInst->addOperand(MCOperand::createInst(SubInst1));
206  return duplexInst;
207 }
208 
210  size_t Index) {
211  assert(Index <= bundleSize(MCB));
212  if (Index == 0)
213  return nullptr;
214  MCInst const *Inst =
215  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
216  if (isImmext(*Inst))
217  return Inst;
218  return nullptr;
219 }
220 
222  MCInstrInfo const &MCII, MCInst &MCB,
223  MCInst const &MCI) {
224  if (isConstExtended(MCII, MCI))
225  addConstExtender(Context, MCII, MCB, MCI);
226 }
227 
229  MCInst const &MCI) {
230  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
233 }
234 
236  MCInst const &MCI) {
237  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
238  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
240 }
241 
243  MCInst const &MCI) {
244  return MCII.get(MCI.getOpcode());
245 }
246 
248  using namespace Hexagon;
249 
250  switch (Reg) {
251  default:
252  llvm_unreachable("unknown duplex register");
253  // Rs Rss
254  case R0:
255  case D0:
256  return 0;
257  case R1:
258  case D1:
259  return 1;
260  case R2:
261  case D2:
262  return 2;
263  case R3:
264  case D3:
265  return 3;
266  case R4:
267  case D8:
268  return 4;
269  case R5:
270  case D9:
271  return 5;
272  case R6:
273  case D10:
274  return 6;
275  case R7:
276  case D11:
277  return 7;
278  case R16:
279  return 8;
280  case R17:
281  return 9;
282  case R18:
283  return 10;
284  case R19:
285  return 11;
286  case R20:
287  return 12;
288  case R21:
289  return 13;
290  case R22:
291  return 14;
292  case R23:
293  return 15;
294  }
295 }
296 
298  const auto &HExpr = cast<HexagonMCExpr>(Expr);
299  assert(HExpr.getExpr());
300  return *HExpr.getExpr();
301 }
302 
304  MCInst const &MCI) {
305  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
307 }
308 
309 MCOperand const &
311  MCInst const &MCI) {
312  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
313  MCOperand const &MO = MCI.getOperand(O);
314 
316  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
317  (MO.isImm() || MO.isExpr()));
318  return (MO);
319 }
320 
322  MCInst const &MCI) {
323  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
325 }
326 
328  MCInst const &MCI) {
329  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
331 }
332 
333 /// Return the maximum value of an extendable operand.
335  MCInst const &MCI) {
336  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
338 
340  HexagonMCInstrInfo::isExtended(MCII, MCI));
341 
342  if (S) // if value is signed
343  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
344  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
345 }
346 
347 /// Return the minimum value of an extendable operand.
349  MCInst const &MCI) {
350  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
352 
354  HexagonMCInstrInfo::isExtended(MCII, MCI));
355 
356  if (S) // if value is signed
357  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
358  return 0;
359 }
360 
362  MCInst const &MCI) {
363  return MCII.getName(MCI.getOpcode());
364 }
365 
367  MCInst const &MCI) {
368  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
370 }
371 
373  MCInst const &MCI) {
374  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
375  // VTMP doesn't actually exist in the encodings for these 184
376  // 3 instructions so go ahead and create it here.
377  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
378  return (MCO);
379  } else {
380  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
381  MCOperand const &MCO = MCI.getOperand(O);
382 
384  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
385  MCO.isReg());
386  return (MCO);
387  }
388 }
389 
390 /// Return the new value or the newly produced value.
392  MCInst const &MCI) {
393  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
395 }
396 
397 MCOperand const &
399  MCInst const &MCI) {
400  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
401  MCOperand const &MCO = MCI.getOperand(O);
402 
404  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
405  MCO.isReg());
406  return (MCO);
407 }
408 
409 /// Return the Hexagon ISA class for the insn.
411  MCInst const &MCI) {
412  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
413  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
414 }
415 
416 /// Return the slots this instruction can execute out of
418  MCSubtargetInfo const &STI,
419  MCInst const &MCI) {
421  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
422  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
423 }
424 
425 /// Return the slots this instruction consumes in addition to
426 /// the slot(s) it can execute out of
427 
429  MCSubtargetInfo const &STI,
430  MCInst const &MCI) {
432  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
433  unsigned Slots = 0;
434 
435  // FirstStage are slots that this instruction can execute in.
436  // FirstStage+1 are slots that are also consumed by this instruction.
437  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
438  for (unsigned Stage = II[SchedClass].FirstStage + 1;
439  Stage < II[SchedClass].LastStage; ++Stage) {
440  unsigned Units = (Stage + HexagonStages)->getUnits();
441  if (Units > HexagonGetLastSlot())
442  break;
443  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
444  Slots |= Units;
445  }
446 
447  // if 0 is returned, then no additional slots are consumed by this inst.
448  return Slots;
449 }
450 
451 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
453  return false;
454 
455  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
456  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
457  return true;
458  }
459 
460  return false;
461 }
462 
464  return extenderForIndex(MCB, Index) != nullptr;
465 }
466 
469  return false;
470 
471  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
472  if (isImmext(*I.getInst()))
473  return true;
474  }
475 
476  return false;
477 }
478 
479 /// Return whether the insn produces a value.
481  MCInst const &MCI) {
482  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
484 }
485 
486 /// Return whether the insn produces a second value.
488  MCInst const &MCI) {
489  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
491 }
492 
494  assert(isBundle(MCB));
495  assert(Index < HEXAGON_PACKET_SIZE);
496  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
497 }
498 
499 /// Return where the instruction is an accumulator.
501  MCInst const &MCI) {
502  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
504 }
505 
507  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
508  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
509  return Result;
510 }
511 
513  MCInst const &MCI) {
514  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
515  return true;
516  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
517  return false;
519  if (isa<HexagonMCExpr>(MO.getExpr()) &&
521  return true;
522  // Branch insns are handled as necessary by relaxation.
523  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
525  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
528  return false;
529  // Otherwise loop instructions and other CR insts are handled by relaxation
530  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
531  (MCI.getOpcode() != Hexagon::C4_addipc))
532  return false;
533 
534  assert(!MO.isImm());
535  if (isa<HexagonMCExpr>(MO.getExpr()) &&
537  return false;
538  int64_t Value;
539  if (!MO.getExpr()->evaluateAsAbsolute(Value))
540  return true;
541  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
542  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
543  return (MinValue > Value || Value > MaxValue);
544 }
545 
546 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
547  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
548  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
549 }
550 
551 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
552  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
554 }
555 
557  MCInst const &MCI) {
558  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
560 }
561 
563  MCInst const &MCI) {
564  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
566 }
567 
569  MCInst const &MCI) {
570  return (getType(MCII, MCI) == HexagonII::TypeCJ);
571 }
572 
573 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
574  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
576 }
577 
579  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
580  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
581 }
582 
583 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
585 }
586 
588  MCInst const &MCI) {
589  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
591 }
592 
594  MCInst const &MCI) {
595  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
597 }
598 
599 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
600  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
601  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
602 }
603 
604 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
605  const uint64_t V = getType(MCII, MCI);
607 }
608 
610  return MCI.getOpcode() == Hexagon::A4_ext;
611 }
612 
614  assert(isBundle(MCI));
615  int64_t Flags = MCI.getOperand(0).getImm();
616  return (Flags & innerLoopMask) != 0;
617 }
618 
620  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
621 }
622 
624  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
625  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
626 }
627 
628 /// Return whether the insn expects newly produced value.
630  MCInst const &MCI) {
631  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
633 }
634 
635 /// Return whether the operand is extendable.
637  MCInst const &MCI, unsigned short O) {
638  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
639 }
640 
642  assert(isBundle(MCI));
643  int64_t Flags = MCI.getOperand(0).getImm();
644  return (Flags & outerLoopMask) != 0;
645 }
646 
648  MCInst const &MCI) {
649  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
651 }
652 
653 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
655 }
656 
658  MCInst const &MCI) {
659  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
661 }
662 
663 /// Return whether the insn is newly predicated.
665  MCInst const &MCI) {
666  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
668 }
669 
671  MCInst const &MCI) {
672  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
673  return (
675 }
676 
678  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
679 }
680 
681 /// Return whether the insn can be packaged only with A and X-type insns.
682 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
683  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
685 }
686 
687 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
689  MCInst const &MCI) {
690  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
691  return ((F >> HexagonII::RestrictSlot1AOKPos) &
693 }
694 
696  MCInst const &MCI) {
697  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
698  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
700 }
701 
702 /// Return whether the insn is solo, i.e., cannot be in a packet.
703 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
704  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
705  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
706 }
707 
709  assert(isBundle(MCI));
710  auto Flags = MCI.getOperand(0).getImm();
711  return (Flags & memReorderDisabledMask) != 0;
712 }
713 
715  switch (MCI.getOpcode()) {
716  default:
717  return false;
718  case Hexagon::SA1_addi:
719  case Hexagon::SA1_addrx:
720  case Hexagon::SA1_addsp:
721  case Hexagon::SA1_and1:
722  case Hexagon::SA1_clrf:
723  case Hexagon::SA1_clrfnew:
724  case Hexagon::SA1_clrt:
725  case Hexagon::SA1_clrtnew:
726  case Hexagon::SA1_cmpeqi:
727  case Hexagon::SA1_combine0i:
728  case Hexagon::SA1_combine1i:
729  case Hexagon::SA1_combine2i:
730  case Hexagon::SA1_combine3i:
731  case Hexagon::SA1_combinerz:
732  case Hexagon::SA1_combinezr:
733  case Hexagon::SA1_dec:
734  case Hexagon::SA1_inc:
735  case Hexagon::SA1_seti:
736  case Hexagon::SA1_setin1:
737  case Hexagon::SA1_sxtb:
738  case Hexagon::SA1_sxth:
739  case Hexagon::SA1_tfr:
740  case Hexagon::SA1_zxtb:
741  case Hexagon::SA1_zxth:
742  case Hexagon::SL1_loadri_io:
743  case Hexagon::SL1_loadrub_io:
744  case Hexagon::SL2_deallocframe:
745  case Hexagon::SL2_jumpr31:
746  case Hexagon::SL2_jumpr31_f:
747  case Hexagon::SL2_jumpr31_fnew:
748  case Hexagon::SL2_jumpr31_t:
749  case Hexagon::SL2_jumpr31_tnew:
750  case Hexagon::SL2_loadrb_io:
751  case Hexagon::SL2_loadrd_sp:
752  case Hexagon::SL2_loadrh_io:
753  case Hexagon::SL2_loadri_sp:
754  case Hexagon::SL2_loadruh_io:
755  case Hexagon::SL2_return:
756  case Hexagon::SL2_return_f:
757  case Hexagon::SL2_return_fnew:
758  case Hexagon::SL2_return_t:
759  case Hexagon::SL2_return_tnew:
760  case Hexagon::SS1_storeb_io:
761  case Hexagon::SS1_storew_io:
762  case Hexagon::SS2_allocframe:
763  case Hexagon::SS2_storebi0:
764  case Hexagon::SS2_storebi1:
765  case Hexagon::SS2_stored_sp:
766  case Hexagon::SS2_storeh_io:
767  case Hexagon::SS2_storew_sp:
768  case Hexagon::SS2_storewi0:
769  case Hexagon::SS2_storewi1:
770  return true;
771  }
772 }
773 
774 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
775  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
776  (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
777  return true;
778  return false;
779 }
780 
781 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
782  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
783  << 8;
784  if (MCI.size() <= Index)
785  return Sentinal;
786  MCOperand const &MCO = MCI.getOperand(Index);
787  if (!MCO.isExpr())
788  return Sentinal;
789  int64_t Value;
790  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
791  return Sentinal;
792  return Value;
793 }
794 
795 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
796  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
797  HExpr.setMustExtend(Val);
798 }
799 
801  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
802  return HExpr.mustExtend();
803 }
804 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
805  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
806  HExpr.setMustNotExtend(Val);
807 }
809  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
810  return HExpr.mustNotExtend();
811 }
812 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
813  HexagonMCExpr &HExpr =
814  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
815  HExpr.setS27_2_reloc(Val);
816 }
818  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
819  if (!HExpr)
820  return false;
821  return HExpr->s27_2_reloc();
822 }
823 
825  MCInst Nop;
826  Nop.setOpcode(Hexagon::A2_nop);
827  assert(isBundle(MCB));
828  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
832  MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
833 }
834 
837  if (!isPredicated(MCII, MCI))
838  return {0, 0, false};
839  MCInstrDesc const &Desc = getDesc(MCII, MCI);
840  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
841  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
842  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
843  return {0, 0, false};
844 }
845 
847  MCInst const &MCI) {
848  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
850 }
851 
852 /// return true if instruction has hasTmpDst attribute.
853 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
854  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
856 }
857 
859  DuplexCandidate Candidate) {
860  assert(Candidate.packetIndexI < MCB.size());
861  assert(Candidate.packetIndexJ < MCB.size());
862  assert(isBundle(MCB));
863  MCInst *Duplex =
864  deriveDuplex(Context, Candidate.iClass,
865  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
866  *MCB.getOperand(Candidate.packetIndexI).getInst());
867  assert(Duplex != nullptr);
868  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
869  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
870 }
871 
873  assert(isBundle(MCI));
874  MCOperand &Operand = MCI.getOperand(0);
875  Operand.setImm(Operand.getImm() | innerLoopMask);
876 }
877 
879  assert(isBundle(MCI));
880  MCOperand &Operand = MCI.getOperand(0);
881  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
883 }
884 
886  assert(isBundle(MCI));
887  MCOperand &Operand = MCI.getOperand(0);
888  Operand.setImm(Operand.getImm() | outerLoopMask);
889 }
890 
891 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
892  unsigned Producer,
893  unsigned Producer2) {
894  // If we're a single vector consumer of a double producer, set subreg bit
895  // based on if we're accessing the lower or upper register component
896  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
897  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
898  return (Consumer - Hexagon::V0) & 0x1;
899  if (Producer2 != Hexagon::NoRegister)
900  return Consumer == Producer;
901  return 0;
902 }
#define HEXAGON_PACKET_INNER_SIZE
Definition: Hexagon.h:36
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const & operator*() const
iterator end()
Definition: MCInst.h:194
iterator begin()
Definition: MCInst.h:192
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
bool isImm() const
Definition: MCInst.h:59
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:236
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool s27_2_reloc() const
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void setInst(const MCInst *Val)
Definition: MCInst.h:111
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isIntRegForSubInst(unsigned Reg)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
bool isReg() const
Definition: MCInst.h:58
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
#define R2(n)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:270
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
void erase(iterator I)
Definition: MCInst.h:190
Reg
All possible values of the reg field in the ModR/M byte.
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool s27_2_reloc(MCExpr const &Expr)
void padEndloop(MCInst &MCI, MCContext &Context)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:61
MCInst const & instruction(MCInst const &MCB, size_t Index)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
const MCInst * getInst() const
Definition: MCInst.h:106
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const MCExpr * getExpr() const
Definition: MCInst.h:96
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
void setS27_2_reloc(bool Val=true)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:76
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
void setImm(int64_t Val)
Definition: MCInst.h:81
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
bool mustExtend(MCExpr const &Expr)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
int64_t const memReorderDisabledMask
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
cl::opt< bool > HexagonDisableCompound
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isExpr() const
Definition: MCInst.h:61
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
bool mustNotExtend() const
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
void setLoc(SMLoc loc)
Definition: MCInst.h:177
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:171
size_t const bundleInstructionsOffset
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
unsigned LastStage
Index of last + 1 stage in itinerary.
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
SMLoc getLoc() const
Definition: MCInst.h:178
unsigned const TypeCVI_FIRST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const TypeCVI_LAST
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
Definition: Hexagon.h:37
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
MCExpr const & getExpr(MCExpr const &Expr)
size_t size() const
Definition: MCInst.h:191
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
MCSubtargetInfo - Generic base class for all target subtargets.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
const InstrStage HexagonStages[]
bool mustExtend() const
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool check(bool FullCheck=true)
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
LLVM Value Representation.
Definition: Value.h:73
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:172
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
void setExpr(const MCExpr *Val)
Definition: MCInst.h:101
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)