LLVM  11.0.0git
HexagonMCTargetDesc.cpp
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1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonArch.h"
14 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCObjectWriter.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCStreamer.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <mutex>
41 #include <new>
42 #include <string>
43 #include <unordered_map>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_MC_DESC
48 #include "HexagonGenInstrInfo.inc"
49 
50 #define GET_SUBTARGETINFO_MC_DESC
51 #include "HexagonGenSubtargetInfo.inc"
52 
53 #define GET_REGINFO_MC_DESC
54 #include "HexagonGenRegisterInfo.inc"
55 
57  ("mno-compound",
58  cl::desc("Disable looking for compound instructions for Hexagon"));
59 
61  ("mno-pairing",
62  cl::desc("Disable looking for duplex instructions for Hexagon"));
63 
64 namespace { // These flags are to be deprecated
65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
66  cl::init(false));
67 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
68  cl::init(false));
69 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
70  cl::init(false));
71 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
72  cl::init(false));
73 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
74  cl::init(false));
75 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
76  cl::init(false));
77 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
78  cl::init(false));
79 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
80  cl::init(false));
81 
83  EnableHVX("mhvx",
84  cl::desc("Enable Hexagon Vector eXtensions"),
85  cl::values(
86  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
87  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
88  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
89  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
90  clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
91  // Sentinel for no value specified.
93  // Sentinel for flag not present.
95 } // namespace
96 
97 static cl::opt<bool>
98  DisableHVX("mno-hvx", cl::Hidden,
99  cl::desc("Disable Hexagon Vector eXtensions"));
100 
101 
102 static StringRef DefaultArch = "hexagonv60";
103 
105  if (MV5)
106  return "hexagonv5";
107  if (MV55)
108  return "hexagonv55";
109  if (MV60)
110  return "hexagonv60";
111  if (MV62)
112  return "hexagonv62";
113  if (MV65)
114  return "hexagonv65";
115  if (MV66)
116  return "hexagonv66";
117  if (MV67)
118  return "hexagonv67";
119  if (MV67T)
120  return "hexagonv67t";
121  return "";
122 }
123 
126  if (!ArchV.empty() && !CPU.empty()) {
127  // Tiny cores have a "t" suffix that is discarded when creating a secondary
128  // non-tiny subtarget. See: addArchSubtarget
129  std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
130  std::pair<StringRef,StringRef> CPUP = CPU.split('t');
131  if (!ArchP.first.equals(CPUP.first))
132  report_fatal_error("conflicting architectures specified.");
133  return CPU;
134  }
135  if (ArchV.empty()) {
136  if (CPU.empty())
137  CPU = DefaultArch;
138  return CPU;
139  }
140  return ArchV;
141 }
142 
143 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
144 
145 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
146  enum {
147  CVI_NONE = 0,
148  CVI_XLANE = 1 << 0,
149  CVI_SHIFT = 1 << 1,
150  CVI_MPY0 = 1 << 2,
151  CVI_MPY1 = 1 << 3,
152  CVI_ZW = 1 << 4
153  };
154 
155  if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
156  ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
157  return (*Lanes = 4, CVI_XLANE);
158  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
159  ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
160  return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
161  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
162  return (*Lanes = 2, CVI_MPY0);
163  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
164  return (*Lanes = 2, CVI_XLANE);
165  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
166  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
167  ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
168  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
169  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
170  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
171  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
172  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
173  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
174  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
175  return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
176  else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
177  return (*Lanes = 1, CVI_ZW);
178  else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
179  return (*Lanes = 1, CVI_XLANE);
180  else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
181  return (*Lanes = 1, CVI_SHIFT);
182 
183  return (*Lanes = 0, CVI_NONE);
184 }
185 
186 
187 namespace llvm {
188 namespace HexagonFUnits {
189 bool isSlot0Only(unsigned units) {
190  return HexagonItinerariesV62FU::SLOT0 == units;
191 }
192 } // namespace HexagonFUnits
193 } // namespace llvm
194 
195 namespace {
196 
197 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
198 public:
199  HexagonTargetAsmStreamer(MCStreamer &S,
201  bool isVerboseAsm,
202  MCInstPrinter &IP)
203  : HexagonTargetStreamer(S) {}
204 
205  void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
206  const MCInst &Inst, const MCSubtargetInfo &STI,
207  raw_ostream &OS) override {
210  std::string Buffer;
211  {
212  raw_string_ostream TempStream(Buffer);
213  InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
214  }
215  StringRef Contents(Buffer);
216  auto PacketBundle = Contents.rsplit('\n');
217  auto HeadTail = PacketBundle.first.split('\n');
218  StringRef Separator = "\n";
219  StringRef Indent = "\t";
220  OS << "\t{\n";
221  while (!HeadTail.first.empty()) {
222  StringRef InstTxt;
223  auto Duplex = HeadTail.first.split('\v');
224  if (!Duplex.second.empty()) {
225  OS << Indent << Duplex.first << Separator;
226  InstTxt = Duplex.second;
227  } else if (!HeadTail.first.trim().startswith("immext")) {
228  InstTxt = Duplex.first;
229  }
230  if (!InstTxt.empty())
231  OS << Indent << InstTxt << Separator;
232  HeadTail = HeadTail.second.split('\n');
233  }
234 
236  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
237  else
238  OS << "\t}" << PacketBundle.second;
239  }
240 };
241 
242 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
243 public:
244  MCELFStreamer &getStreamer() {
245  return static_cast<MCELFStreamer &>(Streamer);
246  }
247  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
248  : HexagonTargetStreamer(S) {
249  MCAssembler &MCA = getStreamer().getAssembler();
251  }
252 
253 
254  void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
255  unsigned ByteAlignment,
256  unsigned AccessSize) override {
257  HexagonMCELFStreamer &HexagonELFStreamer =
258  static_cast<HexagonMCELFStreamer &>(getStreamer());
259  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
260  AccessSize);
261  }
262 
263  void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
264  unsigned ByteAlignment,
265  unsigned AccessSize) override {
266  HexagonMCELFStreamer &HexagonELFStreamer =
267  static_cast<HexagonMCELFStreamer &>(getStreamer());
268  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
269  Symbol, Size, ByteAlignment, AccessSize);
270  }
271 };
272 
273 } // end anonymous namespace
274 
276  MCInstrInfo *X = new MCInstrInfo();
277  InitHexagonMCInstrInfo(X);
278  return X;
279 }
280 
283  InitHexagonMCRegisterInfo(X, Hexagon::R31);
284  return X;
285 }
286 
288  const Triple &TT,
289  const MCTargetOptions &Options) {
290  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
291 
292  // VirtualFP = (R30 + #0).
294  nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
295  MAI->addInitialFrameState(Inst);
296 
297  return MAI;
298 }
299 
301  unsigned SyntaxVariant,
302  const MCAsmInfo &MAI,
303  const MCInstrInfo &MII,
304  const MCRegisterInfo &MRI)
305 {
306  if (SyntaxVariant == 0)
307  return new HexagonInstPrinter(MAI, MII, MRI);
308  else
309  return nullptr;
310 }
311 
312 static MCTargetStreamer *
314  MCInstPrinter *IP, bool IsVerboseAsm) {
315  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
316 }
317 
319  std::unique_ptr<MCAsmBackend> &&MAB,
320  std::unique_ptr<MCObjectWriter> &&OW,
321  std::unique_ptr<MCCodeEmitter> &&Emitter,
322  bool RelaxAll) {
323  return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
324  std::move(Emitter));
325 }
326 
327 static MCTargetStreamer *
329  return new HexagonTargetELFStreamer(S, STI);
330 }
331 
333  if (STI->getFeatureBits()[F])
334  STI->ToggleFeature(F);
335 }
336 
338  return STI->getFeatureBits()[F];
339 }
340 
341 namespace {
342 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
344  if (!FS.empty())
345  Result.push_back(FS);
346 
347  switch (EnableHVX) {
350  break;
352  Result.push_back("+hvxv60");
353  break;
355  Result.push_back("+hvxv62");
356  break;
358  Result.push_back("+hvxv65");
359  break;
361  Result.push_back("+hvxv66");
362  break;
364  Result.push_back("+hvxv67");
365  break;
368  .Case("hexagonv60", "+hvxv60")
369  .Case("hexagonv62", "+hvxv62")
370  .Case("hexagonv65", "+hvxv65")
371  .Case("hexagonv66", "+hvxv66")
372  .Case("hexagonv67", "+hvxv67")
373  .Case("hexagonv67t", "+hvxv67"));
374  break;
375  }
377  // Sentinel if -mhvx isn't specified
378  break;
379  }
380  return join(Result.begin(), Result.end(), ",");
381 }
382 }
383 
384 static bool isCPUValid(const std::string &CPU) {
385  return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
386 }
387 
388 namespace {
389 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
390  StringRef FS) {
391  std::pair<std::string, std::string> Result;
392  Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
393  Result.second = selectHexagonFS(Result.first, FS);
394  return Result;
395 }
396 std::mutex ArchSubtargetMutex;
397 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
398  ArchSubtarget;
399 } // namespace
400 
401 MCSubtargetInfo const *
403  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
404  auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
405  if (Existing == ArchSubtarget.end())
406  return nullptr;
407  return Existing->second.get();
408 }
409 
411  using namespace Hexagon;
412  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
413  // turns on hvxvNN, corresponding to the existing ArchVNN.
414  FeatureBitset FB = S;
415  unsigned CpuArch = ArchV5;
416  for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55,
417  ArchV5}) {
418  if (!FB.test(F))
419  continue;
420  CpuArch = F;
421  break;
422  }
423  bool UseHvx = false;
424  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
425  if (!FB.test(F))
426  continue;
427  UseHvx = true;
428  break;
429  }
430  bool HasHvxVer = false;
431  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
432  ExtensionHVXV66, ExtensionHVXV67}) {
433  if (!FB.test(F))
434  continue;
435  HasHvxVer = true;
436  UseHvx = true;
437  break;
438  }
439 
440  if (!UseHvx || HasHvxVer)
441  return FB;
442 
443  // HasHvxVer is false, and UseHvx is true.
444  switch (CpuArch) {
445  case ArchV67:
446  FB.set(ExtensionHVXV67);
448  case ArchV66:
449  FB.set(ExtensionHVXV66);
451  case ArchV65:
452  FB.set(ExtensionHVXV65);
454  case ArchV62:
455  FB.set(ExtensionHVXV62);
457  case ArchV60:
458  FB.set(ExtensionHVXV60);
459  break;
460  }
461  return FB;
462 }
463 
465  StringRef CPU,
466  StringRef FS) {
467  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
468  StringRef CPUName = Features.first;
469  StringRef ArchFS = Features.second;
470 
471  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
472  if (X != nullptr && (CPUName == "hexagonv67t"))
473  addArchSubtarget(X, ArchFS);
474 
475  if (CPU.equals("help"))
476  exit(0);
477 
478  if (!isCPUValid(CPUName.str())) {
479  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
480  << "\" specified\n";
481  return nullptr;
482  }
483 
484  if (HexagonDisableDuplex) {
485  llvm::FeatureBitset Features = X->getFeatureBits();
486  X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
487  }
488 
490 
491  // The Z-buffer instructions are grandfathered in for current
492  // architectures but omitted for new ones. Future instruction
493  // sets may introduce new/conflicting z-buffer instructions.
494  const bool ZRegOnDefault =
495  (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
496  if (ZRegOnDefault) {
497  llvm::FeatureBitset Features = X->getFeatureBits();
498  X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
499  }
500 
501  return X;
502 }
503 
505  StringRef FS) {
506  assert(STI != nullptr);
507  if (STI->getCPU().contains("t")) {
508  auto ArchSTI = createHexagonMCSubtargetInfo(
509  STI->getTargetTriple(),
510  STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
511  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
512  ArchSubtarget[std::string(STI->getCPU())] =
513  std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
514  }
515 }
516 
518  static std::map<StringRef,unsigned> ElfFlags = {
519  {"hexagonv5", ELF::EF_HEXAGON_MACH_V5},
520  {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
521  {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
522  {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
523  {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
524  {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
525  {"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
526  {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T},
527  };
528 
529  auto F = ElfFlags.find(STI.getCPU());
530  assert(F != ElfFlags.end() && "Unrecognized Architecture");
531  return F->second;
532 }
533 
535  return makeArrayRef(VectRegRev);
536 }
537 
538 namespace {
539 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
540 public:
541  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
542 
543  bool isUnconditionalBranch(MCInst const &Inst) const override {
544  //assert(!HexagonMCInstrInfo::isBundle(Inst));
546  }
547 
548  bool isConditionalBranch(MCInst const &Inst) const override {
549  //assert(!HexagonMCInstrInfo::isBundle(Inst));
551  }
552 
553  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
554  uint64_t Size, uint64_t &Target) const override {
555  if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
556  isConditionalBranch(Inst)))
557  return false;
558 
559  //assert(!HexagonMCInstrInfo::isBundle(Inst));
560  if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
561  return false;
562  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
563  assert(Extended.isExpr());
564  int64_t Value;
565  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
566  return false;
567  Target = Value;
568  return true;
569  }
570 };
571 }
572 
574  return new HexagonMCInstrAnalysis(Info);
575 }
576 
577 // Force static initialization.
579  // Register the MC asm info.
581 
582  // Register the MC instruction info.
585 
586  // Register the MC register info.
589 
590  // Register the MC subtarget info.
593 
594  // Register the MC Code Emitter
597 
598  // Register the asm backend
601 
602 
603  // Register the MC instruction analyzer.
606 
607  // Register the obj streamer
610 
611  // Register the obj target streamer
614 
615  // Register the asm streamer
618 
619  // Register the MC Inst Printer
622 }
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:248
LLVMContext & Context
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setFeatureBits(const FeatureBitset &FeatureBits_)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:485
Target specific streamer interface.
Definition: MCStreamer.h:90
virtual bool isConditionalBranch(const MCInst &Inst) const
bool isBundle(MCInst const &MCI)
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
unsigned HexagonGetLastSlot()
static sys::Mutex Lock
LLVM_NODISCARD std::pair< StringRef, StringRef > rsplit(StringRef Separator) const
Split into two substrings around the last occurrence of a separator string.
Definition: StringRef.h:763
F(f)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
const Triple & getTargetTriple() const
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
const FeatureBitset & getFeatureBits() const
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:458
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
std::string join(IteratorT Begin, IteratorT End, StringRef Separator)
Joins the strings in the range [Begin, End), adding Separator between the elements.
Definition: StringExtras.h:390
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:612
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
Context object for machine code objects.
Definition: MCContext.h:66
virtual bool isUnconditionalBranch(const MCInst &Inst) const
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
constexpr bool test(unsigned I) const
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
static StringRef DefaultArch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:210
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
MCInstrInfo * createHexagonMCInstrInfo()
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Analysis containing CSE Info
Definition: CSEInfo.cpp:25
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
StringRef selectHexagonCPU(StringRef CPU)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:434
Streaming machine code generation interface.
Definition: MCStreamer.h:196
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
static const std::map< std::string, ArchEnum > CpuTable
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:690
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
cl::opt< bool > HexagonDisableCompound
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:187
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:465
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
bool isSlot0Only(unsigned units)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:73
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:883
static bool isCPUValid(const std::string &CPU)
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:730
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
StringRef getCPU() const
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
bool isMemReorderDisabled(MCInst const &MCI)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:665
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:190
static StringRef HexagonGetArchVariant()
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:42
constexpr FeatureBitset & reset(unsigned I)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
size_t bundleSize(MCInst const &MCI)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:521
#define HEXAGON_PACKET_SIZE
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
FeatureBitset & set()
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)