LLVM  9.0.0svn
HexagonMCTargetDesc.cpp
Go to the documentation of this file.
1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "Hexagon.h"
15 #include "HexagonDepArch.h"
16 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCObjectWriter.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCStreamer.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <new>
41 #include <string>
42 
43 using namespace llvm;
44 
45 #define GET_INSTRINFO_MC_DESC
46 #include "HexagonGenInstrInfo.inc"
47 
48 #define GET_SUBTARGETINFO_MC_DESC
49 #include "HexagonGenSubtargetInfo.inc"
50 
51 #define GET_REGINFO_MC_DESC
52 #include "HexagonGenRegisterInfo.inc"
53 
55  ("mno-compound",
56  cl::desc("Disable looking for compound instructions for Hexagon"));
57 
59  ("mno-pairing",
60  cl::desc("Disable looking for duplex instructions for Hexagon"));
61 
62 namespace { // These flags are to be deprecated
63 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
64  cl::init(false));
65 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
66  cl::init(false));
67 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
68  cl::init(false));
69 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
70  cl::init(false));
71 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
72  cl::init(false));
73 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
74  cl::init(false));
75 } // namespace
76 
78  EnableHVX("mhvx",
79  cl::desc("Enable Hexagon Vector eXtensions"),
80  cl::values(
81  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
82  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
83  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
84  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
85  // Sentinel for no value specified.
87  // Sentinel for flag not present.
89 
90 static cl::opt<bool>
91  DisableHVX("mno-hvx", cl::Hidden,
92  cl::desc("Disable Hexagon Vector eXtensions"));
93 
94 
95 static StringRef DefaultArch = "hexagonv60";
96 
98  if (MV5)
99  return "hexagonv5";
100  if (MV55)
101  return "hexagonv55";
102  if (MV60)
103  return "hexagonv60";
104  if (MV62)
105  return "hexagonv62";
106  if (MV65)
107  return "hexagonv65";
108  if (MV66)
109  return "hexagonv66";
110  return "";
111 }
112 
115  if (!ArchV.empty() && !CPU.empty()) {
116  if (ArchV != CPU)
117  report_fatal_error("conflicting architectures specified.");
118  return CPU;
119  }
120  if (ArchV.empty()) {
121  if (CPU.empty())
122  CPU = DefaultArch;
123  return CPU;
124  }
125  return ArchV;
126 }
127 
128 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
129 
130 namespace {
131 
132 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
133 public:
134  HexagonTargetAsmStreamer(MCStreamer &S,
136  bool isVerboseAsm,
137  MCInstPrinter &IP)
138  : HexagonTargetStreamer(S) {}
139 
140  void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
141  const MCInst &Inst, const MCSubtargetInfo &STI) override {
144  std::string Buffer;
145  {
146  raw_string_ostream TempStream(Buffer);
147  InstPrinter.printInst(&Inst, TempStream, "", STI);
148  }
149  StringRef Contents(Buffer);
150  auto PacketBundle = Contents.rsplit('\n');
151  auto HeadTail = PacketBundle.first.split('\n');
152  StringRef Separator = "\n";
153  StringRef Indent = "\t";
154  OS << "\t{\n";
155  while (!HeadTail.first.empty()) {
156  StringRef InstTxt;
157  auto Duplex = HeadTail.first.split('\v');
158  if (!Duplex.second.empty()) {
159  OS << Indent << Duplex.first << Separator;
160  InstTxt = Duplex.second;
161  } else if (!HeadTail.first.trim().startswith("immext")) {
162  InstTxt = Duplex.first;
163  }
164  if (!InstTxt.empty())
165  OS << Indent << InstTxt << Separator;
166  HeadTail = HeadTail.second.split('\n');
167  }
168 
170  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
171  else
172  OS << "\t}" << PacketBundle.second;
173  }
174 };
175 
176 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
177 public:
178  MCELFStreamer &getStreamer() {
179  return static_cast<MCELFStreamer &>(Streamer);
180  }
181  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
182  : HexagonTargetStreamer(S) {
183  MCAssembler &MCA = getStreamer().getAssembler();
185  }
186 
187 
188  void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
189  unsigned ByteAlignment,
190  unsigned AccessSize) override {
191  HexagonMCELFStreamer &HexagonELFStreamer =
192  static_cast<HexagonMCELFStreamer &>(getStreamer());
193  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
194  AccessSize);
195  }
196 
197  void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
198  unsigned ByteAlignment,
199  unsigned AccessSize) override {
200  HexagonMCELFStreamer &HexagonELFStreamer =
201  static_cast<HexagonMCELFStreamer &>(getStreamer());
202  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
203  Symbol, Size, ByteAlignment, AccessSize);
204  }
205 };
206 
207 } // end anonymous namespace
208 
210  MCInstrInfo *X = new MCInstrInfo();
211  InitHexagonMCInstrInfo(X);
212  return X;
213 }
214 
217  InitHexagonMCRegisterInfo(X, Hexagon::R31);
218  return X;
219 }
220 
222  const Triple &TT) {
223  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
224 
225  // VirtualFP = (R30 + #0).
226  MCCFIInstruction Inst =
228  MRI.getDwarfRegNum(Hexagon::R30, true), 0);
229  MAI->addInitialFrameState(Inst);
230 
231  return MAI;
232 }
233 
235  unsigned SyntaxVariant,
236  const MCAsmInfo &MAI,
237  const MCInstrInfo &MII,
238  const MCRegisterInfo &MRI)
239 {
240  if (SyntaxVariant == 0)
241  return new HexagonInstPrinter(MAI, MII, MRI);
242  else
243  return nullptr;
244 }
245 
246 static MCTargetStreamer *
248  MCInstPrinter *IP, bool IsVerboseAsm) {
249  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
250 }
251 
253  std::unique_ptr<MCAsmBackend> &&MAB,
254  std::unique_ptr<MCObjectWriter> &&OW,
255  std::unique_ptr<MCCodeEmitter> &&Emitter,
256  bool RelaxAll) {
257  return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
258  std::move(Emitter));
259 }
260 
261 static MCTargetStreamer *
263  return new HexagonTargetELFStreamer(S, STI);
264 }
265 
267  uint64_t FB = STI->getFeatureBits().to_ullong();
268  if (FB & (1ULL << F))
269  STI->ToggleFeature(F);
270 }
271 
273  uint64_t FB = STI->getFeatureBits().to_ullong();
274  return (FB & (1ULL << F)) != 0;
275 }
276 
277 namespace {
278 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
280  if (!FS.empty())
281  Result.push_back(FS);
282 
283  switch (EnableHVX) {
286  break;
288  Result.push_back("+hvxv60");
289  break;
291  Result.push_back("+hvxv62");
292  break;
294  Result.push_back("+hvxv65");
295  break;
297  Result.push_back("+hvxv66");
298  break;
301  .Case("hexagonv60", "+hvxv60")
302  .Case("hexagonv62", "+hvxv62")
303  .Case("hexagonv65", "+hvxv65")
304  .Case("hexagonv66", "+hvxv66"));
305  break;
306  }
308  // Sentinal if -mhvx isn't specified
309  break;
310  }
311  return join(Result.begin(), Result.end(), ",");
312 }
313 }
314 
315 static bool isCPUValid(std::string CPU)
316 {
317  std::vector<std::string> table {
318  "generic", "hexagonv5", "hexagonv55", "hexagonv60",
319  "hexagonv62", "hexagonv65", "hexagonv66",
320  };
321 
322  return std::find(table.begin(), table.end(), CPU) != table.end();
323 }
324 
325 namespace {
326 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
327  StringRef FS) {
328  std::pair<std::string, std::string> Result;
329  Result.first = Hexagon_MC::selectHexagonCPU(CPU);
330  Result.second = selectHexagonFS(Result.first, FS);
331  return Result;
332 }
333 }
334 
336  using namespace Hexagon;
337  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
338  // turns on hvxvNN, corresponding to the existing ArchVNN.
339  FeatureBitset FB = S;
340  unsigned CpuArch = ArchV5;
341  for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
342  if (!FB.test(F))
343  continue;
344  CpuArch = F;
345  break;
346  }
347  bool UseHvx = false;
348  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
349  if (!FB.test(F))
350  continue;
351  UseHvx = true;
352  break;
353  }
354  bool HasHvxVer = false;
355  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
356  ExtensionHVXV66}) {
357  if (!FB.test(F))
358  continue;
359  HasHvxVer = true;
360  UseHvx = true;
361  break;
362  }
363 
364  if (!UseHvx || HasHvxVer)
365  return FB;
366 
367  // HasHvxVer is false, and UseHvx is true.
368  switch (CpuArch) {
369  case ArchV66:
370  FB.set(ExtensionHVXV66);
372  case ArchV65:
373  FB.set(ExtensionHVXV65);
375  case ArchV62:
376  FB.set(ExtensionHVXV62);
378  case ArchV60:
379  FB.set(ExtensionHVXV60);
380  break;
381  }
382  return FB;
383 }
384 
386  StringRef CPU,
387  StringRef FS) {
388  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
389  StringRef CPUName = Features.first;
390  StringRef ArchFS = Features.second;
391 
392  if (!isCPUValid(CPUName.str())) {
393  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
394  << "\" specified\n";
395  return nullptr;
396  }
397 
398  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
399  if (HexagonDisableDuplex) {
400  llvm::FeatureBitset Features = X->getFeatureBits();
401  X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
402  }
403 
405  return X;
406 }
407 
409  static std::map<StringRef,unsigned> ElfFlags = {
410  {"hexagonv5", ELF::EF_HEXAGON_MACH_V5},
411  {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
412  {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
413  {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
414  {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
415  {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
416  };
417 
418  auto F = ElfFlags.find(STI.getCPU());
419  assert(F != ElfFlags.end() && "Unrecognized Architecture");
420  return F->second;
421 }
422 
423 namespace {
424 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
425 public:
426  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
427 
428  bool isUnconditionalBranch(MCInst const &Inst) const override {
429  //assert(!HexagonMCInstrInfo::isBundle(Inst));
431  }
432 
433  bool isConditionalBranch(MCInst const &Inst) const override {
434  //assert(!HexagonMCInstrInfo::isBundle(Inst));
436  }
437 
438  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
439  uint64_t Size, uint64_t &Target) const override {
440  //assert(!HexagonMCInstrInfo::isBundle(Inst));
441  if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
442  return false;
443  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
444  assert(Extended.isExpr());
445  int64_t Value;
446  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
447  return false;
448  Target = Value;
449  return true;
450  }
451 };
452 }
453 
455  return new HexagonMCInstrAnalysis(Info);
456 }
457 
458 // Force static initialization.
459 extern "C" void LLVMInitializeHexagonTargetMC() {
460  // Register the MC asm info.
462 
463  // Register the MC instruction info.
466 
467  // Register the MC register info.
470 
471  // Register the MC subtarget info.
474 
475  // Register the MC Code Emitter
478 
479  // Register the asm backend
482 
483 
484  // Register the MC instruction analyzer.
487 
488  // Register the obj streamer
491 
492  // Register the obj target streamer
495 
496  // Register the asm streamer
499 
500  // Register the MC Inst Printer
503 }
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
LLVMContext & Context
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setFeatureBits(const FeatureBitset &FeatureBits_)
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
Target specific streamer interface.
Definition: MCStreamer.h:83
virtual bool isConditionalBranch(const MCInst &Inst) const
const FeatureBitset Features
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
LLVM_NODISCARD std::pair< StringRef, StringRef > rsplit(StringRef Separator) const
Split into two substrings around the last occurrence of a separator string.
Definition: StringRef.h:729
F(f)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
void LLVMInitializeHexagonTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
const FeatureBitset & getFeatureBits() const
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
std::string join(IteratorT Begin, IteratorT End, StringRef Separator)
Joins the strings in the range [Begin, End), adding Separator between the elements.
Definition: StringExtras.h:370
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Context object for machine code objects.
Definition: MCContext.h:62
virtual bool isUnconditionalBranch(const MCInst &Inst) const
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
static StringRef DefaultArch
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:600
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:208
MCInstrInfo * createHexagonMCInstrInfo()
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
StringRef selectHexagonCPU(StringRef CPU)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
Streaming machine code generation interface.
Definition: MCStreamer.h:188
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:642
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
cl::opt< bool > HexagonDisableCompound
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1206
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
static bool isCPUValid(std::string CPU)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
StringRef getCPU() const
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
bool isMemReorderDisabled(MCInst const &MCI)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:617
static StringRef HexagonGetArchVariant()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
size_t bundleSize(MCInst const &MCI)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
Definition: JSON.cpp:597
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
#define HEXAGON_PACKET_SIZE
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
LLVM Value Representation.
Definition: Value.h:72
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
cl::opt< Hexagon::ArchEnum > EnableHVX("mhvx", cl::desc("Enable Hexagon Vector eXtensions"), cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::Generic, "", "")), cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)