LLVM  6.0.0svn
HexagonMCTargetDesc.h
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1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Hexagon specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
16 
18 #include <cstdint>
19 
20 namespace llvm {
21 
22 struct InstrItinerary;
23 struct InstrStage;
24 class MCAsmBackend;
25 class MCCodeEmitter;
26 class MCContext;
27 class MCInstrInfo;
28 class MCObjectWriter;
29 class MCRegisterInfo;
30 class MCSubtargetInfo;
31 class MCTargetOptions;
32 class Target;
33 class Triple;
34 class StringRef;
35 class raw_ostream;
36 class raw_pwrite_stream;
37 
38 Target &getTheHexagonTarget();
39 extern cl::opt<bool> HexagonDisableCompound;
40 extern cl::opt<bool> HexagonDisableDuplex;
41 extern const InstrStage HexagonStages[];
42 
43 MCInstrInfo *createHexagonMCInstrInfo();
44 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
45 
46 namespace Hexagon_MC {
49 
50  /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
51  /// etc. do not need to go through TargetRegistry.
53  StringRef FS);
54  unsigned GetELFFlags(const MCSubtargetInfo &STI);
55 }
56 
58  const MCRegisterInfo &MRI,
59  MCContext &MCT);
60 
62  const MCRegisterInfo &MRI,
63  const Triple &TT, StringRef CPU,
64  const MCTargetOptions &Options);
65 
66 std::unique_ptr<MCObjectWriter>
68  StringRef CPU);
69 
70 unsigned HexagonGetLastSlot();
71 
72 } // End llvm namespace
73 
74 // Define symbolic names for Hexagon registers. This defines a mapping from
75 // register name to register number.
76 //
77 #define GET_REGINFO_ENUM
78 #include "HexagonGenRegisterInfo.inc"
79 
80 // Defines symbolic names for the Hexagon instructions.
81 //
82 #define GET_INSTRINFO_ENUM
83 #include "HexagonGenInstrInfo.inc"
84 
85 #define GET_SUBTARGETINFO_ENUM
86 #include "HexagonGenSubtargetInfo.inc"
87 
88 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
std::unique_ptr< MCObjectWriter > createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
StringRef selectHexagonCPU(const Triple &TT, StringRef CPU)
unsigned HexagonGetLastSlot()
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Context object for machine code objects.
Definition: MCContext.h:59
MCInstrInfo * createHexagonMCInstrInfo()
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
cl::opt< bool > HexagonDisableCompound
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Target - Wrapper for Target specific information.
MCSubtargetInfo - Generic base class for all target subtargets.
const InstrStage HexagonStages[]
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:337
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:35
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
StringRef ParseHexagonTriple(const Triple &TT, StringRef CPU)
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex