LLVM  6.0.0svn
HexagonMCTargetDesc.h
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1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Hexagon specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
16 
18 #include <cstdint>
19 #include <string>
20 
21 namespace llvm {
22 
23 struct InstrItinerary;
24 struct InstrStage;
25 class FeatureBitset;
26 class MCAsmBackend;
27 class MCCodeEmitter;
28 class MCContext;
29 class MCInstrInfo;
30 class MCObjectWriter;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class Target;
35 class Triple;
36 class StringRef;
37 class raw_ostream;
38 class raw_pwrite_stream;
39 
40 Target &getTheHexagonTarget();
41 extern cl::opt<bool> HexagonDisableCompound;
42 extern cl::opt<bool> HexagonDisableDuplex;
43 extern const InstrStage HexagonStages[];
44 
45 MCInstrInfo *createHexagonMCInstrInfo();
46 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
47 
48 namespace Hexagon_MC {
50 
52  /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
53  /// etc. do not need to go through TargetRegistry.
55  StringRef FS);
56  unsigned GetELFFlags(const MCSubtargetInfo &STI);
57 }
58 
60  const MCRegisterInfo &MRI,
61  MCContext &MCT);
62 
64  const MCRegisterInfo &MRI,
65  const Triple &TT, StringRef CPU,
66  const MCTargetOptions &Options);
67 
68 std::unique_ptr<MCObjectWriter>
70  StringRef CPU);
71 
72 unsigned HexagonGetLastSlot();
73 
74 } // End llvm namespace
75 
76 // Define symbolic names for Hexagon registers. This defines a mapping from
77 // register name to register number.
78 //
79 #define GET_REGINFO_ENUM
80 #include "HexagonGenRegisterInfo.inc"
81 
82 // Defines symbolic names for the Hexagon instructions.
83 //
84 #define GET_INSTRINFO_ENUM
85 #define GET_INSTRINFO_SCHED_ENUM
86 #include "HexagonGenInstrInfo.inc"
87 
88 #define GET_SUBTARGETINFO_ENUM
89 #include "HexagonGenSubtargetInfo.inc"
90 
91 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
std::unique_ptr< MCObjectWriter > createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned HexagonGetLastSlot()
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Context object for machine code objects.
Definition: MCContext.h:59
MCInstrInfo * createHexagonMCInstrInfo()
StringRef selectHexagonCPU(StringRef CPU)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
cl::opt< bool > HexagonDisableCompound
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Target - Wrapper for Target specific information.
MCSubtargetInfo - Generic base class for all target subtargets.
const InstrStage HexagonStages[]
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:337
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:40
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex