LLVM  7.0.0svn
HexagonNewValueJump.cpp
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1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new value jump
20 // intstructions.
21 //
22 //===----------------------------------------------------------------------===//
23 
24 #include "Hexagon.h"
25 #include "HexagonInstrInfo.h"
26 #include "HexagonRegisterInfo.h"
27 #include "HexagonSubtarget.h"
28 #include "llvm/ADT/Statistic.h"
40 #include "llvm/IR/DebugLoc.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Pass.h"
45 #include "llvm/Support/Debug.h"
49 #include <cassert>
50 #include <cstdint>
51 #include <iterator>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "hexagon-nvj"
56 
57 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
58 
59 static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
60  cl::desc("Maximum number of predicated jumps to be converted to "
61  "New Value Jump"));
62 
63 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
64  cl::ZeroOrMore, cl::init(false),
65  cl::desc("Disable New Value Jumps"));
66 
67 namespace llvm {
68 
71 
72 } // end namespace llvm
73 
74 namespace {
75 
76  struct HexagonNewValueJump : public MachineFunctionPass {
77  static char ID;
78 
79  HexagonNewValueJump() : MachineFunctionPass(ID) {}
80 
81  void getAnalysisUsage(AnalysisUsage &AU) const override {
84  }
85 
86  StringRef getPassName() const override { return "Hexagon NewValueJump"; }
87 
88  bool runOnMachineFunction(MachineFunction &Fn) override;
89 
90  MachineFunctionProperties getRequiredProperties() const override {
93  }
94 
95  private:
96  const HexagonInstrInfo *QII;
97  const HexagonRegisterInfo *QRI;
98 
99  /// A handle to the branch probability pass.
100  const MachineBranchProbabilityInfo *MBPI;
101 
102  bool isNewValueJumpCandidate(const MachineInstr &MI) const;
103  };
104 
105 } // end anonymous namespace
106 
107 char HexagonNewValueJump::ID = 0;
108 
109 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
110  "Hexagon NewValueJump", false, false)
112 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
113  "Hexagon NewValueJump", false, false)
114 
115 // We have identified this II could be feeder to NVJ,
116 // verify that it can be.
119  MachineBasicBlock::iterator II,
120  MachineBasicBlock::iterator end,
121  MachineBasicBlock::iterator skip,
122  MachineFunction &MF) {
123  // Predicated instruction can not be feeder to NVJ.
124  if (QII->isPredicated(*II))
125  return false;
126 
127  // Bail out if feederReg is a paired register (double regs in
128  // our case). One would think that we can check to see if a given
129  // register cmpReg1 or cmpReg2 is a sub register of feederReg
130  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
131  // before the callsite of this function
132  // But we can not as it comes in the following fashion.
133  // %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
134  // %r0 = KILL %r0, implicit killed %d0
135  // %p0 = CMPEQri killed %r0, 0
136  // Hence, we need to check if it's a KILL instruction.
137  if (II->getOpcode() == TargetOpcode::KILL)
138  return false;
139 
140  if (II->isImplicitDef())
141  return false;
142 
143  if (QII->isSolo(*II))
144  return false;
145 
146  if (QII->isFloat(*II))
147  return false;
148 
149  // Make sure that the (unique) def operand is a register from IntRegs.
150  bool HadDef = false;
151  for (const MachineOperand &Op : II->operands()) {
152  if (!Op.isReg() || !Op.isDef())
153  continue;
154  if (HadDef)
155  return false;
156  HadDef = true;
157  if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
158  return false;
159  }
160  assert(HadDef);
161 
162  // Make sure there is no 'def' or 'use' of any of the uses of
163  // feeder insn between its definition, this MI and jump, jmpInst
164  // skipping compare, cmpInst.
165  // Here's the example.
166  // r21=memub(r22+r24<<#0)
167  // p0 = cmp.eq(r21, #0)
168  // r4=memub(r3+r21<<#0)
169  // if (p0.new) jump:t .LBB29_45
170  // Without this check, it will be converted into
171  // r4=memub(r3+r21<<#0)
172  // r21=memub(r22+r24<<#0)
173  // p0 = cmp.eq(r21, #0)
174  // if (p0.new) jump:t .LBB29_45
175  // and result WAR hazards if converted to New Value Jump.
176  for (unsigned i = 0; i < II->getNumOperands(); ++i) {
177  if (II->getOperand(i).isReg() &&
178  (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
179  MachineBasicBlock::iterator localII = II;
180  ++localII;
181  unsigned Reg = II->getOperand(i).getReg();
182  for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
183  ++localBegin) {
184  if (localBegin == skip)
185  continue;
186  // Check for Subregisters too.
187  if (localBegin->modifiesRegister(Reg, TRI) ||
188  localBegin->readsRegister(Reg, TRI))
189  return false;
190  }
191  }
192  }
193  return true;
194 }
195 
196 // These are the common checks that need to performed
197 // to determine if
198 // 1. compare instruction can be moved before jump.
199 // 2. feeder to the compare instruction can be moved before jump.
200 static bool commonChecksToProhibitNewValueJump(bool afterRA,
202  // If store in path, bail out.
203  if (MII->mayStore())
204  return false;
205 
206  // if call in path, bail out.
207  if (MII->isCall())
208  return false;
209 
210  // if NVJ is running prior to RA, do the following checks.
211  if (!afterRA) {
212  // The following Target Opcode instructions are spurious
213  // to new value jump. If they are in the path, bail out.
214  // KILL sets kill flag on the opcode. It also sets up a
215  // single register, out of pair.
216  // %d0 = S2_lsr_r_p killed %d0, killed %r2
217  // %r0 = KILL %r0, implicit killed %d0
218  // %p0 = C2_cmpeqi killed %r0, 0
219  // PHI can be anything after RA.
220  // COPY can remateriaze things in between feeder, compare and nvj.
221  if (MII->getOpcode() == TargetOpcode::KILL ||
222  MII->getOpcode() == TargetOpcode::PHI ||
223  MII->getOpcode() == TargetOpcode::COPY)
224  return false;
225 
226  // The following pseudo Hexagon instructions sets "use" and "def"
227  // of registers by individual passes in the backend. At this time,
228  // we don't know the scope of usage and definitions of these
229  // instructions.
230  if (MII->getOpcode() == Hexagon::LDriw_pred ||
231  MII->getOpcode() == Hexagon::STriw_pred)
232  return false;
233  }
234 
235  return true;
236 }
237 
239  const TargetRegisterInfo *TRI,
241  unsigned pReg,
242  bool secondReg,
243  bool optLocation,
245  MachineFunction &MF) {
246  MachineInstr &MI = *II;
247 
248  // If the second operand of the compare is an imm, make sure it's in the
249  // range specified by the arch.
250  if (!secondReg) {
251  const MachineOperand &Op2 = MI.getOperand(2);
252  if (!Op2.isImm())
253  return false;
254 
255  int64_t v = Op2.getImm();
256  bool Valid = false;
257 
258  switch (MI.getOpcode()) {
259  case Hexagon::C2_cmpeqi:
260  case Hexagon::C4_cmpneqi:
261  case Hexagon::C2_cmpgti:
262  case Hexagon::C4_cmpltei:
263  Valid = (isUInt<5>(v) || v == -1);
264  break;
265  case Hexagon::C2_cmpgtui:
266  case Hexagon::C4_cmplteui:
267  Valid = isUInt<5>(v);
268  break;
269  case Hexagon::S2_tstbit_i:
270  case Hexagon::S4_ntstbit_i:
271  Valid = (v == 0);
272  break;
273  }
274 
275  if (!Valid)
276  return false;
277  }
278 
279  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
280  cmpReg1 = MI.getOperand(1).getReg();
281 
282  if (secondReg) {
283  cmpOp2 = MI.getOperand(2).getReg();
284 
285  // If the same register appears as both operands, we cannot generate a new
286  // value compare. Only one operand may use the .new suffix.
287  if (cmpReg1 == cmpOp2)
288  return false;
289 
290  // Make sure that the second register is not from COPY
291  // at machine code level, we don't need this, but if we decide
292  // to move new value jump prior to RA, we would be needing this.
294  if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
295  MachineInstr *def = MRI.getVRegDef(cmpOp2);
296  if (def->getOpcode() == TargetOpcode::COPY)
297  return false;
298  }
299  }
300 
301  // Walk the instructions after the compare (predicate def) to the jump,
302  // and satisfy the following conditions.
303  ++II;
304  for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
305  if (localII->isDebugInstr())
306  continue;
307 
308  // Check 1.
309  // If "common" checks fail, bail out.
310  if (!commonChecksToProhibitNewValueJump(optLocation, localII))
311  return false;
312 
313  // Check 2.
314  // If there is a def or use of predicate (result of compare), bail out.
315  if (localII->modifiesRegister(pReg, TRI) ||
316  localII->readsRegister(pReg, TRI))
317  return false;
318 
319  // Check 3.
320  // If there is a def of any of the use of the compare (operands of compare),
321  // bail out.
322  // Eg.
323  // p0 = cmp.eq(r2, r0)
324  // r2 = r4
325  // if (p0.new) jump:t .LBB28_3
326  if (localII->modifiesRegister(cmpReg1, TRI) ||
327  (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
328  return false;
329  }
330  return true;
331 }
332 
333 // Given a compare operator, return a matching New Value Jump compare operator.
334 // Make sure that MI here is included in isNewValueJumpCandidate.
335 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
336  bool secondRegNewified,
337  MachineBasicBlock *jmpTarget,
339  *MBPI) {
340  bool taken = false;
341  MachineBasicBlock *Src = MI->getParent();
342  const BranchProbability Prediction =
343  MBPI->getEdgeProbability(Src, jmpTarget);
344 
345  if (Prediction >= BranchProbability(1,2))
346  taken = true;
347 
348  switch (MI->getOpcode()) {
349  case Hexagon::C2_cmpeq:
350  return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
351  : Hexagon::J4_cmpeq_t_jumpnv_nt;
352 
353  case Hexagon::C2_cmpeqi:
354  if (reg >= 0)
355  return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
356  : Hexagon::J4_cmpeqi_t_jumpnv_nt;
357  return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
358  : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
359 
360  case Hexagon::C4_cmpneqi:
361  if (reg >= 0)
362  return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
363  : Hexagon::J4_cmpeqi_f_jumpnv_nt;
364  return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
365  Hexagon::J4_cmpeqn1_f_jumpnv_nt;
366 
367  case Hexagon::C2_cmpgt:
368  if (secondRegNewified)
369  return taken ? Hexagon::J4_cmplt_t_jumpnv_t
370  : Hexagon::J4_cmplt_t_jumpnv_nt;
371  return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
372  : Hexagon::J4_cmpgt_t_jumpnv_nt;
373 
374  case Hexagon::C2_cmpgti:
375  if (reg >= 0)
376  return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
377  : Hexagon::J4_cmpgti_t_jumpnv_nt;
378  return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
379  : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
380 
381  case Hexagon::C2_cmpgtu:
382  if (secondRegNewified)
383  return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
384  : Hexagon::J4_cmpltu_t_jumpnv_nt;
385  return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
386  : Hexagon::J4_cmpgtu_t_jumpnv_nt;
387 
388  case Hexagon::C2_cmpgtui:
389  return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
390  : Hexagon::J4_cmpgtui_t_jumpnv_nt;
391 
392  case Hexagon::C4_cmpneq:
393  return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
394  : Hexagon::J4_cmpeq_f_jumpnv_nt;
395 
396  case Hexagon::C4_cmplte:
397  if (secondRegNewified)
398  return taken ? Hexagon::J4_cmplt_f_jumpnv_t
399  : Hexagon::J4_cmplt_f_jumpnv_nt;
400  return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
401  : Hexagon::J4_cmpgt_f_jumpnv_nt;
402 
403  case Hexagon::C4_cmplteu:
404  if (secondRegNewified)
405  return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
406  : Hexagon::J4_cmpltu_f_jumpnv_nt;
407  return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
408  : Hexagon::J4_cmpgtu_f_jumpnv_nt;
409 
410  case Hexagon::C4_cmpltei:
411  if (reg >= 0)
412  return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
413  : Hexagon::J4_cmpgti_f_jumpnv_nt;
414  return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
415  : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
416 
417  case Hexagon::C4_cmplteui:
418  return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
419  : Hexagon::J4_cmpgtui_f_jumpnv_nt;
420 
421  default:
422  llvm_unreachable("Could not find matching New Value Jump instruction.");
423  }
424  // return *some value* to avoid compiler warning
425  return 0;
426 }
427 
428 bool HexagonNewValueJump::isNewValueJumpCandidate(
429  const MachineInstr &MI) const {
430  switch (MI.getOpcode()) {
431  case Hexagon::C2_cmpeq:
432  case Hexagon::C2_cmpeqi:
433  case Hexagon::C2_cmpgt:
434  case Hexagon::C2_cmpgti:
435  case Hexagon::C2_cmpgtu:
436  case Hexagon::C2_cmpgtui:
437  case Hexagon::C4_cmpneq:
438  case Hexagon::C4_cmpneqi:
439  case Hexagon::C4_cmplte:
440  case Hexagon::C4_cmplteu:
441  case Hexagon::C4_cmpltei:
442  case Hexagon::C4_cmplteui:
443  return true;
444 
445  default:
446  return false;
447  }
448 }
449 
450 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
451  LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
452  << "********** Function: " << MF.getName() << "\n");
453 
454  if (skipFunction(MF.getFunction()))
455  return false;
456 
457  // If we move NewValueJump before register allocation we'll need live variable
458  // analysis here too.
459 
460  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
461  QRI = static_cast<const HexagonRegisterInfo *>(
463  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
464 
465  if (DisableNewValueJumps ||
467  return false;
468 
469  int nvjCount = DbgNVJCount;
470  int nvjGenerated = 0;
471 
472  // Loop through all the bb's of the function
473  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
474  MBBb != MBBe; ++MBBb) {
475  MachineBasicBlock *MBB = &*MBBb;
476 
477  LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
478  LLVM_DEBUG(MBB->dump());
479  LLVM_DEBUG(dbgs() << "\n"
480  << "********** dumping instr bottom up **********\n");
481  bool foundJump = false;
482  bool foundCompare = false;
483  bool invertPredicate = false;
484  unsigned predReg = 0; // predicate reg of the jump.
485  unsigned cmpReg1 = 0;
486  int cmpOp2 = 0;
489  MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
490  MachineBasicBlock *jmpTarget = nullptr;
491  bool afterRA = false;
492  bool isSecondOpReg = false;
493  bool isSecondOpNewified = false;
494  // Traverse the basic block - bottom up
495  for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
496  MII != E;) {
497  MachineInstr &MI = *--MII;
498  if (MI.isDebugInstr()) {
499  continue;
500  }
501 
502  if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
503  break;
504 
505  LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
506 
507  if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
508  MI.getOpcode() == Hexagon::J2_jumptpt ||
509  MI.getOpcode() == Hexagon::J2_jumpf ||
510  MI.getOpcode() == Hexagon::J2_jumpfpt ||
511  MI.getOpcode() == Hexagon::J2_jumptnewpt ||
512  MI.getOpcode() == Hexagon::J2_jumptnew ||
513  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
514  MI.getOpcode() == Hexagon::J2_jumpfnew)) {
515  // This is where you would insert your compare and
516  // instr that feeds compare
517  jmpPos = MII;
518  jmpInstr = &MI;
519  predReg = MI.getOperand(0).getReg();
520  afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
521 
522  // If ifconverter had not messed up with the kill flags of the
523  // operands, the following check on the kill flag would suffice.
524  // if(!jmpInstr->getOperand(0).isKill()) break;
525 
526  // This predicate register is live out of BB
527  // this would only work if we can actually use Live
528  // variable analysis on phy regs - but LLVM does not
529  // provide LV analysis on phys regs.
530  //if(LVs.isLiveOut(predReg, *MBB)) break;
531 
532  // Get all the successors of this block - which will always
533  // be 2. Check if the predicate register is live-in in those
534  // successor. If yes, we can not delete the predicate -
535  // I am doing this only because LLVM does not provide LiveOut
536  // at the BB level.
537  bool predLive = false;
539  SIE = MBB->succ_end();
540  SI != SIE; ++SI) {
541  MachineBasicBlock *succMBB = *SI;
542  if (succMBB->isLiveIn(predReg))
543  predLive = true;
544  }
545  if (predLive)
546  break;
547 
548  if (!MI.getOperand(1).isMBB())
549  continue;
550  jmpTarget = MI.getOperand(1).getMBB();
551  foundJump = true;
552  if (MI.getOpcode() == Hexagon::J2_jumpf ||
553  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
554  MI.getOpcode() == Hexagon::J2_jumpfnew) {
555  invertPredicate = true;
556  }
557  continue;
558  }
559 
560  // No new value jump if there is a barrier. A barrier has to be in its
561  // own packet. A barrier has zero operands. We conservatively bail out
562  // here if we see any instruction with zero operands.
563  if (foundJump && MI.getNumOperands() == 0)
564  break;
565 
566  if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
567  MI.getOperand(0).getReg() == predReg) {
568  // Not all compares can be new value compare. Arch Spec: 7.6.1.1
569  if (isNewValueJumpCandidate(MI)) {
570  assert(
571  (MI.getDesc().isCompare()) &&
572  "Only compare instruction can be collapsed into New Value Jump");
573  isSecondOpReg = MI.getOperand(2).isReg();
574 
575  if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
576  afterRA, jmpPos, MF))
577  break;
578 
579  cmpInstr = &MI;
580  cmpPos = MII;
581  foundCompare = true;
582 
583  // We need cmpReg1 and cmpOp2(imm or reg) while building
584  // new value jump instruction.
585  cmpReg1 = MI.getOperand(1).getReg();
586 
587  if (isSecondOpReg)
588  cmpOp2 = MI.getOperand(2).getReg();
589  else
590  cmpOp2 = MI.getOperand(2).getImm();
591  continue;
592  }
593  }
594 
595  if (foundCompare && foundJump) {
596  // If "common" checks fail, bail out on this BB.
597  if (!commonChecksToProhibitNewValueJump(afterRA, MII))
598  break;
599 
600  bool foundFeeder = false;
601  MachineBasicBlock::iterator feederPos = MII;
602  if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
603  (MI.getOperand(0).getReg() == cmpReg1 ||
604  (isSecondOpReg &&
605  MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
606 
607  unsigned feederReg = MI.getOperand(0).getReg();
608 
609  // First try to see if we can get the feeder from the first operand
610  // of the compare. If we can not, and if secondOpReg is true
611  // (second operand of the compare is also register), try that one.
612  // TODO: Try to come up with some heuristic to figure out which
613  // feeder would benefit.
614 
615  if (feederReg == cmpReg1) {
616  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
617  if (!isSecondOpReg)
618  break;
619  else
620  continue;
621  } else
622  foundFeeder = true;
623  }
624 
625  if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
626  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
627  break;
628 
629  if (isSecondOpReg) {
630  // In case of CMPLT, or CMPLTU, or EQ with the second register
631  // to newify, swap the operands.
632  unsigned COp = cmpInstr->getOpcode();
633  if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
634  (feederReg == (unsigned)cmpOp2)) {
635  unsigned tmp = cmpReg1;
636  cmpReg1 = cmpOp2;
637  cmpOp2 = tmp;
638  }
639 
640  // Now we have swapped the operands, all we need to check is,
641  // if the second operand (after swap) is the feeder.
642  // And if it is, make a note.
643  if (feederReg == (unsigned)cmpOp2)
644  isSecondOpNewified = true;
645  }
646 
647  // Now that we are moving feeder close the jump,
648  // make sure we are respecting the kill values of
649  // the operands of the feeder.
650 
651  auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
652  for (MachineOperand &MO : MI.operands()) {
653  if (!MO.isReg() || !MO.isUse())
654  continue;
655  unsigned UseR = MO.getReg();
656  for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
657  if (I == cmpPos)
658  continue;
659  for (MachineOperand &Op : I->operands()) {
660  if (!Op.isReg() || !Op.isUse() || !Op.isKill())
661  continue;
662  if (Op.getReg() != UseR)
663  continue;
664  // We found that there is kill of a use register
665  // Set up a kill flag on the register
666  Op.setIsKill(false);
667  MO.setIsKill(true);
668  return;
669  }
670  }
671  }
672  };
673 
674  TransferKills(*feederPos);
675  TransferKills(*cmpPos);
676  bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
677  bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
678 
679  MBB->splice(jmpPos, MI.getParent(), MI);
680  MBB->splice(jmpPos, MI.getParent(), cmpInstr);
681  DebugLoc dl = MI.getDebugLoc();
682  MachineInstr *NewMI;
683 
684  assert((isNewValueJumpCandidate(*cmpInstr)) &&
685  "This compare is not a New Value Jump candidate.");
686  unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
687  isSecondOpNewified,
688  jmpTarget, MBPI);
689  if (invertPredicate)
690  opc = QII->getInvertedPredicatedOpcode(opc);
691 
692  if (isSecondOpReg)
693  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
694  .addReg(cmpReg1, getKillRegState(MO1IsKill))
695  .addReg(cmpOp2, getKillRegState(MO2IsKill))
696  .addMBB(jmpTarget);
697 
698  else
699  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
700  .addReg(cmpReg1, getKillRegState(MO1IsKill))
701  .addImm(cmpOp2)
702  .addMBB(jmpTarget);
703 
704  assert(NewMI && "New Value Jump Instruction Not created!");
705  (void)NewMI;
706  if (cmpInstr->getOperand(0).isReg() &&
707  cmpInstr->getOperand(0).isKill())
708  cmpInstr->getOperand(0).setIsKill(false);
709  if (cmpInstr->getOperand(1).isReg() &&
710  cmpInstr->getOperand(1).isKill())
711  cmpInstr->getOperand(1).setIsKill(false);
712  cmpInstr->eraseFromParent();
713  jmpInstr->eraseFromParent();
714  ++nvjGenerated;
715  ++NumNVJGenerated;
716  break;
717  }
718  }
719  }
720  }
721 
722  return true;
723 }
724 
726  return new HexagonNewValueJump();
727 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:250
MachineBasicBlock * getMBB() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
void skip(CollectionType &C)
Definition: YAMLParser.h:389
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:361
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
return AArch64::GPR64RegClass contains(Reg)
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:305
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
void initializeHexagonNewValueJumpPass(PassRegistry &)
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
static bool commonChecksToProhibitNewValueJump(bool afterRA, MachineBasicBlock::iterator MII)
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, bool secondRegNewified, MachineBasicBlock *jmpTarget, const MachineBranchProbabilityInfo *MBPI)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1164
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
Definition: MachineInstr.h:851
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
hexagon Hexagon static false bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF)
void setIsKill(bool Val=true)
FunctionPass * createHexagonNewValueJump()
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
static cl::opt< int > DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc("Maximum number of predicated jumps to be converted to " "New Value Jump"))
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", "Hexagon NewValueJump", false, false) INITIALIZE_PASS_END(HexagonNewValueJump
static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF)
#define I(x, y, z)
Definition: MD5.cpp:58
hexagon Hexagon NewValueJump
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
hexagon nvj
Properties which a MachineFunction may have at a given point in time.
static cl::opt< bool > DisableNewValueJumps("disable-nvjump", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable New Value Jumps"))