LLVM  6.0.0svn
HexagonNewValueJump.cpp
Go to the documentation of this file.
1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //===----------------------------------------------------------------------===//
23 
24 #include "Hexagon.h"
25 #include "HexagonInstrInfo.h"
26 #include "HexagonRegisterInfo.h"
27 #include "llvm/ADT/Statistic.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Pass.h"
44 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <cstdint>
50 #include <iterator>
51 
52 using namespace llvm;
53 
54 #define DEBUG_TYPE "hexagon-nvj"
55 
56 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
57 
58 static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
59  cl::desc("Maximum number of predicated jumps to be converted to "
60  "New Value Jump"));
61 
62 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
63  cl::ZeroOrMore, cl::init(false),
64  cl::desc("Disable New Value Jumps"));
65 
66 namespace llvm {
67 
70 
71 } // end namespace llvm
72 
73 namespace {
74 
75  struct HexagonNewValueJump : public MachineFunctionPass {
76  static char ID;
77 
78  HexagonNewValueJump() : MachineFunctionPass(ID) {}
79 
80  void getAnalysisUsage(AnalysisUsage &AU) const override {
83  }
84 
85  StringRef getPassName() const override { return "Hexagon NewValueJump"; }
86 
87  bool runOnMachineFunction(MachineFunction &Fn) override;
88 
89  MachineFunctionProperties getRequiredProperties() const override {
92  }
93 
94  private:
95  const HexagonInstrInfo *QII;
96  const HexagonRegisterInfo *QRI;
97 
98  /// \brief A handle to the branch probability pass.
99  const MachineBranchProbabilityInfo *MBPI;
100 
101  bool isNewValueJumpCandidate(const MachineInstr &MI) const;
102  };
103 
104 } // end anonymous namespace
105 
106 char HexagonNewValueJump::ID = 0;
107 
108 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
109  "Hexagon NewValueJump", false, false)
111 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
112  "Hexagon NewValueJump", false, false)
113 
114 // We have identified this II could be feeder to NVJ,
115 // verify that it can be.
118  MachineBasicBlock::iterator II,
119  MachineBasicBlock::iterator end,
120  MachineBasicBlock::iterator skip,
121  MachineFunction &MF) {
122  // Predicated instruction can not be feeder to NVJ.
123  if (QII->isPredicated(*II))
124  return false;
125 
126  // Bail out if feederReg is a paired register (double regs in
127  // our case). One would think that we can check to see if a given
128  // register cmpReg1 or cmpReg2 is a sub register of feederReg
129  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
130  // before the callsite of this function
131  // But we can not as it comes in the following fashion.
132  // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
133  // %R0<def> = KILL %R0, %D0<imp-use,kill>
134  // %P0<def> = CMPEQri %R0<kill>, 0
135  // Hence, we need to check if it's a KILL instruction.
136  if (II->getOpcode() == TargetOpcode::KILL)
137  return false;
138 
139  if (II->isImplicitDef())
140  return false;
141 
142  // Make sure there there is no 'def' or 'use' of any of the uses of
143  // feeder insn between it's definition, this MI and jump, jmpInst
144  // skipping compare, cmpInst.
145  // Here's the example.
146  // r21=memub(r22+r24<<#0)
147  // p0 = cmp.eq(r21, #0)
148  // r4=memub(r3+r21<<#0)
149  // if (p0.new) jump:t .LBB29_45
150  // Without this check, it will be converted into
151  // r4=memub(r3+r21<<#0)
152  // r21=memub(r22+r24<<#0)
153  // p0 = cmp.eq(r21, #0)
154  // if (p0.new) jump:t .LBB29_45
155  // and result WAR hazards if converted to New Value Jump.
156  for (unsigned i = 0; i < II->getNumOperands(); ++i) {
157  if (II->getOperand(i).isReg() &&
158  (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
159  MachineBasicBlock::iterator localII = II;
160  ++localII;
161  unsigned Reg = II->getOperand(i).getReg();
162  for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
163  ++localBegin) {
164  if (localBegin == skip)
165  continue;
166  // Check for Subregisters too.
167  if (localBegin->modifiesRegister(Reg, TRI) ||
168  localBegin->readsRegister(Reg, TRI))
169  return false;
170  }
171  }
172  }
173  return true;
174 }
175 
176 // These are the common checks that need to performed
177 // to determine if
178 // 1. compare instruction can be moved before jump.
179 // 2. feeder to the compare instruction can be moved before jump.
180 static bool commonChecksToProhibitNewValueJump(bool afterRA,
182  // If store in path, bail out.
183  if (MII->mayStore())
184  return false;
185 
186  // if call in path, bail out.
187  if (MII->isCall())
188  return false;
189 
190  // if NVJ is running prior to RA, do the following checks.
191  if (!afterRA) {
192  // The following Target Opcode instructions are spurious
193  // to new value jump. If they are in the path, bail out.
194  // KILL sets kill flag on the opcode. It also sets up a
195  // single register, out of pair.
196  // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill>
197  // %R0<def> = KILL %R0, %D0<imp-use,kill>
198  // %P0<def> = C2_cmpeqi %R0<kill>, 0
199  // PHI can be anything after RA.
200  // COPY can remateriaze things in between feeder, compare and nvj.
201  if (MII->getOpcode() == TargetOpcode::KILL ||
202  MII->getOpcode() == TargetOpcode::PHI ||
203  MII->getOpcode() == TargetOpcode::COPY)
204  return false;
205 
206  // The following pseudo Hexagon instructions sets "use" and "def"
207  // of registers by individual passes in the backend. At this time,
208  // we don't know the scope of usage and definitions of these
209  // instructions.
210  if (MII->getOpcode() == Hexagon::LDriw_pred ||
211  MII->getOpcode() == Hexagon::STriw_pred)
212  return false;
213  }
214 
215  return true;
216 }
217 
219  const TargetRegisterInfo *TRI,
221  unsigned pReg,
222  bool secondReg,
223  bool optLocation,
225  MachineFunction &MF) {
226  MachineInstr &MI = *II;
227 
228  // If the second operand of the compare is an imm, make sure it's in the
229  // range specified by the arch.
230  if (!secondReg) {
231  const MachineOperand &Op2 = MI.getOperand(2);
232  if (!Op2.isImm())
233  return false;
234 
235  int64_t v = Op2.getImm();
236  bool Valid = false;
237 
238  switch (MI.getOpcode()) {
239  case Hexagon::C2_cmpeqi:
240  case Hexagon::C4_cmpneqi:
241  case Hexagon::C2_cmpgti:
242  case Hexagon::C4_cmpltei:
243  Valid = (isUInt<5>(v) || v == -1);
244  break;
245  case Hexagon::C2_cmpgtui:
246  case Hexagon::C4_cmplteui:
247  Valid = isUInt<5>(v);
248  break;
249  case Hexagon::S2_tstbit_i:
250  case Hexagon::S4_ntstbit_i:
251  Valid = (v == 0);
252  break;
253  }
254 
255  if (!Valid)
256  return false;
257  }
258 
259  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
260  cmpReg1 = MI.getOperand(1).getReg();
261 
262  if (secondReg) {
263  cmpOp2 = MI.getOperand(2).getReg();
264 
265  // If the same register appears as both operands, we cannot generate a new
266  // value compare. Only one operand may use the .new suffix.
267  if (cmpReg1 == cmpOp2)
268  return false;
269 
270  // Make sure that that second register is not from COPY
271  // At machine code level, we don't need this, but if we decide
272  // to move new value jump prior to RA, we would be needing this.
274  if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
275  MachineInstr *def = MRI.getVRegDef(cmpOp2);
276  if (def->getOpcode() == TargetOpcode::COPY)
277  return false;
278  }
279  }
280 
281  // Walk the instructions after the compare (predicate def) to the jump,
282  // and satisfy the following conditions.
283  ++II;
284  for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
285  if (localII->isDebugValue())
286  continue;
287 
288  // Check 1.
289  // If "common" checks fail, bail out.
290  if (!commonChecksToProhibitNewValueJump(optLocation, localII))
291  return false;
292 
293  // Check 2.
294  // If there is a def or use of predicate (result of compare), bail out.
295  if (localII->modifiesRegister(pReg, TRI) ||
296  localII->readsRegister(pReg, TRI))
297  return false;
298 
299  // Check 3.
300  // If there is a def of any of the use of the compare (operands of compare),
301  // bail out.
302  // Eg.
303  // p0 = cmp.eq(r2, r0)
304  // r2 = r4
305  // if (p0.new) jump:t .LBB28_3
306  if (localII->modifiesRegister(cmpReg1, TRI) ||
307  (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
308  return false;
309  }
310  return true;
311 }
312 
313 // Given a compare operator, return a matching New Value Jump compare operator.
314 // Make sure that MI here is included in isNewValueJumpCandidate.
315 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
316  bool secondRegNewified,
317  MachineBasicBlock *jmpTarget,
319  *MBPI) {
320  bool taken = false;
321  MachineBasicBlock *Src = MI->getParent();
322  const BranchProbability Prediction =
323  MBPI->getEdgeProbability(Src, jmpTarget);
324 
325  if (Prediction >= BranchProbability(1,2))
326  taken = true;
327 
328  switch (MI->getOpcode()) {
329  case Hexagon::C2_cmpeq:
330  return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
331  : Hexagon::J4_cmpeq_t_jumpnv_nt;
332 
333  case Hexagon::C2_cmpeqi:
334  if (reg >= 0)
335  return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
336  : Hexagon::J4_cmpeqi_t_jumpnv_nt;
337  return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
338  : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
339 
340  case Hexagon::C4_cmpneqi:
341  if (reg >= 0)
342  return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
343  : Hexagon::J4_cmpeqi_f_jumpnv_nt;
344  return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
345  Hexagon::J4_cmpeqn1_f_jumpnv_nt;
346 
347  case Hexagon::C2_cmpgt:
348  if (secondRegNewified)
349  return taken ? Hexagon::J4_cmplt_t_jumpnv_t
350  : Hexagon::J4_cmplt_t_jumpnv_nt;
351  return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
352  : Hexagon::J4_cmpgt_t_jumpnv_nt;
353 
354  case Hexagon::C2_cmpgti:
355  if (reg >= 0)
356  return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
357  : Hexagon::J4_cmpgti_t_jumpnv_nt;
358  return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
359  : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
360 
361  case Hexagon::C2_cmpgtu:
362  if (secondRegNewified)
363  return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
364  : Hexagon::J4_cmpltu_t_jumpnv_nt;
365  return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
366  : Hexagon::J4_cmpgtu_t_jumpnv_nt;
367 
368  case Hexagon::C2_cmpgtui:
369  return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
370  : Hexagon::J4_cmpgtui_t_jumpnv_nt;
371 
372  case Hexagon::C4_cmpneq:
373  return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
374  : Hexagon::J4_cmpeq_f_jumpnv_nt;
375 
376  case Hexagon::C4_cmplte:
377  if (secondRegNewified)
378  return taken ? Hexagon::J4_cmplt_f_jumpnv_t
379  : Hexagon::J4_cmplt_f_jumpnv_nt;
380  return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
381  : Hexagon::J4_cmpgt_f_jumpnv_nt;
382 
383  case Hexagon::C4_cmplteu:
384  if (secondRegNewified)
385  return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
386  : Hexagon::J4_cmpltu_f_jumpnv_nt;
387  return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
388  : Hexagon::J4_cmpgtu_f_jumpnv_nt;
389 
390  case Hexagon::C4_cmpltei:
391  if (reg >= 0)
392  return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
393  : Hexagon::J4_cmpgti_f_jumpnv_nt;
394  return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
395  : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
396 
397  case Hexagon::C4_cmplteui:
398  return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
399  : Hexagon::J4_cmpgtui_f_jumpnv_nt;
400 
401  default:
402  llvm_unreachable("Could not find matching New Value Jump instruction.");
403  }
404  // return *some value* to avoid compiler warning
405  return 0;
406 }
407 
408 bool HexagonNewValueJump::isNewValueJumpCandidate(
409  const MachineInstr &MI) const {
410  switch (MI.getOpcode()) {
411  case Hexagon::C2_cmpeq:
412  case Hexagon::C2_cmpeqi:
413  case Hexagon::C2_cmpgt:
414  case Hexagon::C2_cmpgti:
415  case Hexagon::C2_cmpgtu:
416  case Hexagon::C2_cmpgtui:
417  case Hexagon::C4_cmpneq:
418  case Hexagon::C4_cmpneqi:
419  case Hexagon::C4_cmplte:
420  case Hexagon::C4_cmplteu:
421  case Hexagon::C4_cmpltei:
422  case Hexagon::C4_cmplteui:
423  return true;
424 
425  default:
426  return false;
427  }
428 }
429 
430 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
431  DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
432  << "********** Function: " << MF.getName() << "\n");
433 
434  if (skipFunction(*MF.getFunction()))
435  return false;
436 
437  // If we move NewValueJump before register allocation we'll need live variable
438  // analysis here too.
439 
440  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
441  QRI = static_cast<const HexagonRegisterInfo *>(
443  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
444 
445  if (DisableNewValueJumps) {
446  return false;
447  }
448 
449  int nvjCount = DbgNVJCount;
450  int nvjGenerated = 0;
451 
452  // Loop through all the bb's of the function
453  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
454  MBBb != MBBe; ++MBBb) {
455  MachineBasicBlock *MBB = &*MBBb;
456 
457  DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
458  DEBUG(MBB->dump());
459  DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
460  bool foundJump = false;
461  bool foundCompare = false;
462  bool invertPredicate = false;
463  unsigned predReg = 0; // predicate reg of the jump.
464  unsigned cmpReg1 = 0;
465  int cmpOp2 = 0;
468  MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
469  MachineBasicBlock *jmpTarget = nullptr;
470  bool afterRA = false;
471  bool isSecondOpReg = false;
472  bool isSecondOpNewified = false;
473  // Traverse the basic block - bottom up
474  for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
475  MII != E;) {
476  MachineInstr &MI = *--MII;
477  if (MI.isDebugValue()) {
478  continue;
479  }
480 
481  if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
482  break;
483 
484  DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
485 
486  if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
487  MI.getOpcode() == Hexagon::J2_jumptpt ||
488  MI.getOpcode() == Hexagon::J2_jumpf ||
489  MI.getOpcode() == Hexagon::J2_jumpfpt ||
490  MI.getOpcode() == Hexagon::J2_jumptnewpt ||
491  MI.getOpcode() == Hexagon::J2_jumptnew ||
492  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
493  MI.getOpcode() == Hexagon::J2_jumpfnew)) {
494  // This is where you would insert your compare and
495  // instr that feeds compare
496  jmpPos = MII;
497  jmpInstr = &MI;
498  predReg = MI.getOperand(0).getReg();
499  afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
500 
501  // If ifconverter had not messed up with the kill flags of the
502  // operands, the following check on the kill flag would suffice.
503  // if(!jmpInstr->getOperand(0).isKill()) break;
504 
505  // This predicate register is live out out of BB
506  // this would only work if we can actually use Live
507  // variable analysis on phy regs - but LLVM does not
508  // provide LV analysis on phys regs.
509  //if(LVs.isLiveOut(predReg, *MBB)) break;
510 
511  // Get all the successors of this block - which will always
512  // be 2. Check if the predicate register is live-in in those
513  // successor. If yes, we can not delete the predicate -
514  // I am doing this only because LLVM does not provide LiveOut
515  // at the BB level.
516  bool predLive = false;
518  SIE = MBB->succ_end();
519  SI != SIE; ++SI) {
520  MachineBasicBlock *succMBB = *SI;
521  if (succMBB->isLiveIn(predReg))
522  predLive = true;
523  }
524  if (predLive)
525  break;
526 
527  if (!MI.getOperand(1).isMBB())
528  continue;
529  jmpTarget = MI.getOperand(1).getMBB();
530  foundJump = true;
531  if (MI.getOpcode() == Hexagon::J2_jumpf ||
532  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
533  MI.getOpcode() == Hexagon::J2_jumpfnew) {
534  invertPredicate = true;
535  }
536  continue;
537  }
538 
539  // No new value jump if there is a barrier. A barrier has to be in its
540  // own packet. A barrier has zero operands. We conservatively bail out
541  // here if we see any instruction with zero operands.
542  if (foundJump && MI.getNumOperands() == 0)
543  break;
544 
545  if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
546  MI.getOperand(0).getReg() == predReg) {
547  // Not all compares can be new value compare. Arch Spec: 7.6.1.1
548  if (isNewValueJumpCandidate(MI)) {
549  assert(
550  (MI.getDesc().isCompare()) &&
551  "Only compare instruction can be collapsed into New Value Jump");
552  isSecondOpReg = MI.getOperand(2).isReg();
553 
554  if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
555  afterRA, jmpPos, MF))
556  break;
557 
558  cmpInstr = &MI;
559  cmpPos = MII;
560  foundCompare = true;
561 
562  // We need cmpReg1 and cmpOp2(imm or reg) while building
563  // new value jump instruction.
564  cmpReg1 = MI.getOperand(1).getReg();
565 
566  if (isSecondOpReg)
567  cmpOp2 = MI.getOperand(2).getReg();
568  else
569  cmpOp2 = MI.getOperand(2).getImm();
570  continue;
571  }
572  }
573 
574  if (foundCompare && foundJump) {
575  // If "common" checks fail, bail out on this BB.
576  if (!commonChecksToProhibitNewValueJump(afterRA, MII))
577  break;
578 
579  bool foundFeeder = false;
580  MachineBasicBlock::iterator feederPos = MII;
581  if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
582  (MI.getOperand(0).getReg() == cmpReg1 ||
583  (isSecondOpReg &&
584  MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
585 
586  unsigned feederReg = MI.getOperand(0).getReg();
587 
588  // First try to see if we can get the feeder from the first operand
589  // of the compare. If we can not, and if secondOpReg is true
590  // (second operand of the compare is also register), try that one.
591  // TODO: Try to come up with some heuristic to figure out which
592  // feeder would benefit.
593 
594  if (feederReg == cmpReg1) {
595  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
596  if (!isSecondOpReg)
597  break;
598  else
599  continue;
600  } else
601  foundFeeder = true;
602  }
603 
604  if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
605  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
606  break;
607 
608  if (isSecondOpReg) {
609  // In case of CMPLT, or CMPLTU, or EQ with the second register
610  // to newify, swap the operands.
611  unsigned COp = cmpInstr->getOpcode();
612  if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
613  (feederReg == (unsigned)cmpOp2)) {
614  unsigned tmp = cmpReg1;
615  cmpReg1 = cmpOp2;
616  cmpOp2 = tmp;
617  }
618 
619  // Now we have swapped the operands, all we need to check is,
620  // if the second operand (after swap) is the feeder.
621  // And if it is, make a note.
622  if (feederReg == (unsigned)cmpOp2)
623  isSecondOpNewified = true;
624  }
625 
626  // Now that we are moving feeder close the jump,
627  // make sure we are respecting the kill values of
628  // the operands of the feeder.
629 
630  auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
631  for (MachineOperand &MO : MI.operands()) {
632  if (!MO.isReg() || !MO.isUse())
633  continue;
634  unsigned UseR = MO.getReg();
635  for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
636  if (I == cmpPos)
637  continue;
638  for (MachineOperand &Op : I->operands()) {
639  if (!Op.isReg() || !Op.isUse() || !Op.isKill())
640  continue;
641  if (Op.getReg() != UseR)
642  continue;
643  // We found that there is kill of a use register
644  // Set up a kill flag on the register
645  Op.setIsKill(false);
646  MO.setIsKill(true);
647  return;
648  }
649  }
650  }
651  };
652 
653  TransferKills(*feederPos);
654  TransferKills(*cmpPos);
655  bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
656  bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
657 
658  MBB->splice(jmpPos, MI.getParent(), MI);
659  MBB->splice(jmpPos, MI.getParent(), cmpInstr);
660  DebugLoc dl = MI.getDebugLoc();
661  MachineInstr *NewMI;
662 
663  assert((isNewValueJumpCandidate(*cmpInstr)) &&
664  "This compare is not a New Value Jump candidate.");
665  unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
666  isSecondOpNewified,
667  jmpTarget, MBPI);
668  if (invertPredicate)
669  opc = QII->getInvertedPredicatedOpcode(opc);
670 
671  if (isSecondOpReg)
672  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
673  .addReg(cmpReg1, getKillRegState(MO1IsKill))
674  .addReg(cmpOp2, getKillRegState(MO2IsKill))
675  .addMBB(jmpTarget);
676 
677  else
678  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
679  .addReg(cmpReg1, getKillRegState(MO1IsKill))
680  .addImm(cmpOp2)
681  .addMBB(jmpTarget);
682 
683  assert(NewMI && "New Value Jump Instruction Not created!");
684  (void)NewMI;
685  if (cmpInstr->getOperand(0).isReg() &&
686  cmpInstr->getOperand(0).isKill())
687  cmpInstr->getOperand(0).setIsKill(false);
688  if (cmpInstr->getOperand(1).isReg() &&
689  cmpInstr->getOperand(1).isKill())
690  cmpInstr->getOperand(1).setIsKill(false);
691  cmpInstr->eraseFromParent();
692  jmpInstr->eraseFromParent();
693  ++nvjGenerated;
694  ++NumNVJGenerated;
695  break;
696  }
697  }
698  }
699  }
700 
701  return true;
702 }
703 
705  return new HexagonNewValueJump();
706 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
MachineBasicBlock * getMBB() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
void skip(CollectionType &C)
Definition: YAMLParser.h:379
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:304
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
void initializeHexagonNewValueJumpPass(PassRegistry &)
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
static bool commonChecksToProhibitNewValueJump(bool afterRA, MachineBasicBlock::iterator MII)
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, bool secondRegNewified, MachineBasicBlock *jmpTarget, const MachineBranchProbabilityInfo *MBPI)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1164
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
hexagon Hexagon static false bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF)
void setIsKill(bool Val=true)
FunctionPass * createHexagonNewValueJump()
Iterator for intrusive lists based on ilist_node.
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
static cl::opt< int > DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc("Maximum number of predicated jumps to be converted to " "New Value Jump"))
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", "Hexagon NewValueJump", false, false) INITIALIZE_PASS_END(HexagonNewValueJump
static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF)
#define I(x, y, z)
Definition: MD5.cpp:58
hexagon Hexagon NewValueJump
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
hexagon nvj
Properties which a MachineFunction may have at a given point in time.
static cl::opt< bool > DisableNewValueJumps("disable-nvjump", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable New Value Jumps"))