LLVM  7.0.0svn
HexagonNewValueJump.cpp
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1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //===----------------------------------------------------------------------===//
23 
24 #include "Hexagon.h"
25 #include "HexagonInstrInfo.h"
26 #include "HexagonRegisterInfo.h"
27 #include "llvm/ADT/Statistic.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Pass.h"
44 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <cstdint>
50 #include <iterator>
51 
52 using namespace llvm;
53 
54 #define DEBUG_TYPE "hexagon-nvj"
55 
56 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
57 
58 static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
59  cl::desc("Maximum number of predicated jumps to be converted to "
60  "New Value Jump"));
61 
62 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
63  cl::ZeroOrMore, cl::init(false),
64  cl::desc("Disable New Value Jumps"));
65 
66 namespace llvm {
67 
70 
71 } // end namespace llvm
72 
73 namespace {
74 
75  struct HexagonNewValueJump : public MachineFunctionPass {
76  static char ID;
77 
78  HexagonNewValueJump() : MachineFunctionPass(ID) {}
79 
80  void getAnalysisUsage(AnalysisUsage &AU) const override {
83  }
84 
85  StringRef getPassName() const override { return "Hexagon NewValueJump"; }
86 
87  bool runOnMachineFunction(MachineFunction &Fn) override;
88 
89  MachineFunctionProperties getRequiredProperties() const override {
92  }
93 
94  private:
95  const HexagonInstrInfo *QII;
96  const HexagonRegisterInfo *QRI;
97 
98  /// \brief A handle to the branch probability pass.
99  const MachineBranchProbabilityInfo *MBPI;
100 
101  bool isNewValueJumpCandidate(const MachineInstr &MI) const;
102  };
103 
104 } // end anonymous namespace
105 
106 char HexagonNewValueJump::ID = 0;
107 
108 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
109  "Hexagon NewValueJump", false, false)
111 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
112  "Hexagon NewValueJump", false, false)
113 
114 // We have identified this II could be feeder to NVJ,
115 // verify that it can be.
118  MachineBasicBlock::iterator II,
119  MachineBasicBlock::iterator end,
120  MachineBasicBlock::iterator skip,
121  MachineFunction &MF) {
122  // Predicated instruction can not be feeder to NVJ.
123  if (QII->isPredicated(*II))
124  return false;
125 
126  // Bail out if feederReg is a paired register (double regs in
127  // our case). One would think that we can check to see if a given
128  // register cmpReg1 or cmpReg2 is a sub register of feederReg
129  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
130  // before the callsite of this function
131  // But we can not as it comes in the following fashion.
132  // %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
133  // %r0 = KILL %r0, implicit killed %d0
134  // %p0 = CMPEQri killed %r0, 0
135  // Hence, we need to check if it's a KILL instruction.
136  if (II->getOpcode() == TargetOpcode::KILL)
137  return false;
138 
139  if (II->isImplicitDef())
140  return false;
141 
142  if (QII->isSolo(*II))
143  return false;
144 
145  if (QII->isFloat(*II))
146  return false;
147 
148  // Make sure that the (unique) def operand is a register from IntRegs.
149  bool HadDef = false;
150  for (const MachineOperand &Op : II->operands()) {
151  if (!Op.isReg() || !Op.isDef())
152  continue;
153  if (HadDef)
154  return false;
155  HadDef = true;
156  if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
157  return false;
158  }
159  assert(HadDef);
160 
161  // Make sure there there is no 'def' or 'use' of any of the uses of
162  // feeder insn between it's definition, this MI and jump, jmpInst
163  // skipping compare, cmpInst.
164  // Here's the example.
165  // r21=memub(r22+r24<<#0)
166  // p0 = cmp.eq(r21, #0)
167  // r4=memub(r3+r21<<#0)
168  // if (p0.new) jump:t .LBB29_45
169  // Without this check, it will be converted into
170  // r4=memub(r3+r21<<#0)
171  // r21=memub(r22+r24<<#0)
172  // p0 = cmp.eq(r21, #0)
173  // if (p0.new) jump:t .LBB29_45
174  // and result WAR hazards if converted to New Value Jump.
175  for (unsigned i = 0; i < II->getNumOperands(); ++i) {
176  if (II->getOperand(i).isReg() &&
177  (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
178  MachineBasicBlock::iterator localII = II;
179  ++localII;
180  unsigned Reg = II->getOperand(i).getReg();
181  for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
182  ++localBegin) {
183  if (localBegin == skip)
184  continue;
185  // Check for Subregisters too.
186  if (localBegin->modifiesRegister(Reg, TRI) ||
187  localBegin->readsRegister(Reg, TRI))
188  return false;
189  }
190  }
191  }
192  return true;
193 }
194 
195 // These are the common checks that need to performed
196 // to determine if
197 // 1. compare instruction can be moved before jump.
198 // 2. feeder to the compare instruction can be moved before jump.
199 static bool commonChecksToProhibitNewValueJump(bool afterRA,
201  // If store in path, bail out.
202  if (MII->mayStore())
203  return false;
204 
205  // if call in path, bail out.
206  if (MII->isCall())
207  return false;
208 
209  // if NVJ is running prior to RA, do the following checks.
210  if (!afterRA) {
211  // The following Target Opcode instructions are spurious
212  // to new value jump. If they are in the path, bail out.
213  // KILL sets kill flag on the opcode. It also sets up a
214  // single register, out of pair.
215  // %d0 = S2_lsr_r_p killed %d0, killed %r2
216  // %r0 = KILL %r0, implicit killed %d0
217  // %p0 = C2_cmpeqi killed %r0, 0
218  // PHI can be anything after RA.
219  // COPY can remateriaze things in between feeder, compare and nvj.
220  if (MII->getOpcode() == TargetOpcode::KILL ||
221  MII->getOpcode() == TargetOpcode::PHI ||
222  MII->getOpcode() == TargetOpcode::COPY)
223  return false;
224 
225  // The following pseudo Hexagon instructions sets "use" and "def"
226  // of registers by individual passes in the backend. At this time,
227  // we don't know the scope of usage and definitions of these
228  // instructions.
229  if (MII->getOpcode() == Hexagon::LDriw_pred ||
230  MII->getOpcode() == Hexagon::STriw_pred)
231  return false;
232  }
233 
234  return true;
235 }
236 
238  const TargetRegisterInfo *TRI,
240  unsigned pReg,
241  bool secondReg,
242  bool optLocation,
244  MachineFunction &MF) {
245  MachineInstr &MI = *II;
246 
247  // If the second operand of the compare is an imm, make sure it's in the
248  // range specified by the arch.
249  if (!secondReg) {
250  const MachineOperand &Op2 = MI.getOperand(2);
251  if (!Op2.isImm())
252  return false;
253 
254  int64_t v = Op2.getImm();
255  bool Valid = false;
256 
257  switch (MI.getOpcode()) {
258  case Hexagon::C2_cmpeqi:
259  case Hexagon::C4_cmpneqi:
260  case Hexagon::C2_cmpgti:
261  case Hexagon::C4_cmpltei:
262  Valid = (isUInt<5>(v) || v == -1);
263  break;
264  case Hexagon::C2_cmpgtui:
265  case Hexagon::C4_cmplteui:
266  Valid = isUInt<5>(v);
267  break;
268  case Hexagon::S2_tstbit_i:
269  case Hexagon::S4_ntstbit_i:
270  Valid = (v == 0);
271  break;
272  }
273 
274  if (!Valid)
275  return false;
276  }
277 
278  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
279  cmpReg1 = MI.getOperand(1).getReg();
280 
281  if (secondReg) {
282  cmpOp2 = MI.getOperand(2).getReg();
283 
284  // If the same register appears as both operands, we cannot generate a new
285  // value compare. Only one operand may use the .new suffix.
286  if (cmpReg1 == cmpOp2)
287  return false;
288 
289  // Make sure that that second register is not from COPY
290  // At machine code level, we don't need this, but if we decide
291  // to move new value jump prior to RA, we would be needing this.
293  if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
294  MachineInstr *def = MRI.getVRegDef(cmpOp2);
295  if (def->getOpcode() == TargetOpcode::COPY)
296  return false;
297  }
298  }
299 
300  // Walk the instructions after the compare (predicate def) to the jump,
301  // and satisfy the following conditions.
302  ++II;
303  for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
304  if (localII->isDebugValue())
305  continue;
306 
307  // Check 1.
308  // If "common" checks fail, bail out.
309  if (!commonChecksToProhibitNewValueJump(optLocation, localII))
310  return false;
311 
312  // Check 2.
313  // If there is a def or use of predicate (result of compare), bail out.
314  if (localII->modifiesRegister(pReg, TRI) ||
315  localII->readsRegister(pReg, TRI))
316  return false;
317 
318  // Check 3.
319  // If there is a def of any of the use of the compare (operands of compare),
320  // bail out.
321  // Eg.
322  // p0 = cmp.eq(r2, r0)
323  // r2 = r4
324  // if (p0.new) jump:t .LBB28_3
325  if (localII->modifiesRegister(cmpReg1, TRI) ||
326  (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
327  return false;
328  }
329  return true;
330 }
331 
332 // Given a compare operator, return a matching New Value Jump compare operator.
333 // Make sure that MI here is included in isNewValueJumpCandidate.
334 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
335  bool secondRegNewified,
336  MachineBasicBlock *jmpTarget,
338  *MBPI) {
339  bool taken = false;
340  MachineBasicBlock *Src = MI->getParent();
341  const BranchProbability Prediction =
342  MBPI->getEdgeProbability(Src, jmpTarget);
343 
344  if (Prediction >= BranchProbability(1,2))
345  taken = true;
346 
347  switch (MI->getOpcode()) {
348  case Hexagon::C2_cmpeq:
349  return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
350  : Hexagon::J4_cmpeq_t_jumpnv_nt;
351 
352  case Hexagon::C2_cmpeqi:
353  if (reg >= 0)
354  return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
355  : Hexagon::J4_cmpeqi_t_jumpnv_nt;
356  return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
357  : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
358 
359  case Hexagon::C4_cmpneqi:
360  if (reg >= 0)
361  return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
362  : Hexagon::J4_cmpeqi_f_jumpnv_nt;
363  return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
364  Hexagon::J4_cmpeqn1_f_jumpnv_nt;
365 
366  case Hexagon::C2_cmpgt:
367  if (secondRegNewified)
368  return taken ? Hexagon::J4_cmplt_t_jumpnv_t
369  : Hexagon::J4_cmplt_t_jumpnv_nt;
370  return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
371  : Hexagon::J4_cmpgt_t_jumpnv_nt;
372 
373  case Hexagon::C2_cmpgti:
374  if (reg >= 0)
375  return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
376  : Hexagon::J4_cmpgti_t_jumpnv_nt;
377  return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
378  : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
379 
380  case Hexagon::C2_cmpgtu:
381  if (secondRegNewified)
382  return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
383  : Hexagon::J4_cmpltu_t_jumpnv_nt;
384  return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
385  : Hexagon::J4_cmpgtu_t_jumpnv_nt;
386 
387  case Hexagon::C2_cmpgtui:
388  return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
389  : Hexagon::J4_cmpgtui_t_jumpnv_nt;
390 
391  case Hexagon::C4_cmpneq:
392  return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
393  : Hexagon::J4_cmpeq_f_jumpnv_nt;
394 
395  case Hexagon::C4_cmplte:
396  if (secondRegNewified)
397  return taken ? Hexagon::J4_cmplt_f_jumpnv_t
398  : Hexagon::J4_cmplt_f_jumpnv_nt;
399  return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
400  : Hexagon::J4_cmpgt_f_jumpnv_nt;
401 
402  case Hexagon::C4_cmplteu:
403  if (secondRegNewified)
404  return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
405  : Hexagon::J4_cmpltu_f_jumpnv_nt;
406  return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
407  : Hexagon::J4_cmpgtu_f_jumpnv_nt;
408 
409  case Hexagon::C4_cmpltei:
410  if (reg >= 0)
411  return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
412  : Hexagon::J4_cmpgti_f_jumpnv_nt;
413  return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
414  : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
415 
416  case Hexagon::C4_cmplteui:
417  return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
418  : Hexagon::J4_cmpgtui_f_jumpnv_nt;
419 
420  default:
421  llvm_unreachable("Could not find matching New Value Jump instruction.");
422  }
423  // return *some value* to avoid compiler warning
424  return 0;
425 }
426 
427 bool HexagonNewValueJump::isNewValueJumpCandidate(
428  const MachineInstr &MI) const {
429  switch (MI.getOpcode()) {
430  case Hexagon::C2_cmpeq:
431  case Hexagon::C2_cmpeqi:
432  case Hexagon::C2_cmpgt:
433  case Hexagon::C2_cmpgti:
434  case Hexagon::C2_cmpgtu:
435  case Hexagon::C2_cmpgtui:
436  case Hexagon::C4_cmpneq:
437  case Hexagon::C4_cmpneqi:
438  case Hexagon::C4_cmplte:
439  case Hexagon::C4_cmplteu:
440  case Hexagon::C4_cmpltei:
441  case Hexagon::C4_cmplteui:
442  return true;
443 
444  default:
445  return false;
446  }
447 }
448 
449 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
450  DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
451  << "********** Function: " << MF.getName() << "\n");
452 
453  if (skipFunction(MF.getFunction()))
454  return false;
455 
456  // If we move NewValueJump before register allocation we'll need live variable
457  // analysis here too.
458 
459  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
460  QRI = static_cast<const HexagonRegisterInfo *>(
462  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
463 
464  if (DisableNewValueJumps) {
465  return false;
466  }
467 
468  int nvjCount = DbgNVJCount;
469  int nvjGenerated = 0;
470 
471  // Loop through all the bb's of the function
472  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
473  MBBb != MBBe; ++MBBb) {
474  MachineBasicBlock *MBB = &*MBBb;
475 
476  DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
477  DEBUG(MBB->dump());
478  DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
479  bool foundJump = false;
480  bool foundCompare = false;
481  bool invertPredicate = false;
482  unsigned predReg = 0; // predicate reg of the jump.
483  unsigned cmpReg1 = 0;
484  int cmpOp2 = 0;
487  MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
488  MachineBasicBlock *jmpTarget = nullptr;
489  bool afterRA = false;
490  bool isSecondOpReg = false;
491  bool isSecondOpNewified = false;
492  // Traverse the basic block - bottom up
493  for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
494  MII != E;) {
495  MachineInstr &MI = *--MII;
496  if (MI.isDebugValue()) {
497  continue;
498  }
499 
500  if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
501  break;
502 
503  DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
504 
505  if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
506  MI.getOpcode() == Hexagon::J2_jumptpt ||
507  MI.getOpcode() == Hexagon::J2_jumpf ||
508  MI.getOpcode() == Hexagon::J2_jumpfpt ||
509  MI.getOpcode() == Hexagon::J2_jumptnewpt ||
510  MI.getOpcode() == Hexagon::J2_jumptnew ||
511  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
512  MI.getOpcode() == Hexagon::J2_jumpfnew)) {
513  // This is where you would insert your compare and
514  // instr that feeds compare
515  jmpPos = MII;
516  jmpInstr = &MI;
517  predReg = MI.getOperand(0).getReg();
518  afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
519 
520  // If ifconverter had not messed up with the kill flags of the
521  // operands, the following check on the kill flag would suffice.
522  // if(!jmpInstr->getOperand(0).isKill()) break;
523 
524  // This predicate register is live out out of BB
525  // this would only work if we can actually use Live
526  // variable analysis on phy regs - but LLVM does not
527  // provide LV analysis on phys regs.
528  //if(LVs.isLiveOut(predReg, *MBB)) break;
529 
530  // Get all the successors of this block - which will always
531  // be 2. Check if the predicate register is live-in in those
532  // successor. If yes, we can not delete the predicate -
533  // I am doing this only because LLVM does not provide LiveOut
534  // at the BB level.
535  bool predLive = false;
537  SIE = MBB->succ_end();
538  SI != SIE; ++SI) {
539  MachineBasicBlock *succMBB = *SI;
540  if (succMBB->isLiveIn(predReg))
541  predLive = true;
542  }
543  if (predLive)
544  break;
545 
546  if (!MI.getOperand(1).isMBB())
547  continue;
548  jmpTarget = MI.getOperand(1).getMBB();
549  foundJump = true;
550  if (MI.getOpcode() == Hexagon::J2_jumpf ||
551  MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
552  MI.getOpcode() == Hexagon::J2_jumpfnew) {
553  invertPredicate = true;
554  }
555  continue;
556  }
557 
558  // No new value jump if there is a barrier. A barrier has to be in its
559  // own packet. A barrier has zero operands. We conservatively bail out
560  // here if we see any instruction with zero operands.
561  if (foundJump && MI.getNumOperands() == 0)
562  break;
563 
564  if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
565  MI.getOperand(0).getReg() == predReg) {
566  // Not all compares can be new value compare. Arch Spec: 7.6.1.1
567  if (isNewValueJumpCandidate(MI)) {
568  assert(
569  (MI.getDesc().isCompare()) &&
570  "Only compare instruction can be collapsed into New Value Jump");
571  isSecondOpReg = MI.getOperand(2).isReg();
572 
573  if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
574  afterRA, jmpPos, MF))
575  break;
576 
577  cmpInstr = &MI;
578  cmpPos = MII;
579  foundCompare = true;
580 
581  // We need cmpReg1 and cmpOp2(imm or reg) while building
582  // new value jump instruction.
583  cmpReg1 = MI.getOperand(1).getReg();
584 
585  if (isSecondOpReg)
586  cmpOp2 = MI.getOperand(2).getReg();
587  else
588  cmpOp2 = MI.getOperand(2).getImm();
589  continue;
590  }
591  }
592 
593  if (foundCompare && foundJump) {
594  // If "common" checks fail, bail out on this BB.
595  if (!commonChecksToProhibitNewValueJump(afterRA, MII))
596  break;
597 
598  bool foundFeeder = false;
599  MachineBasicBlock::iterator feederPos = MII;
600  if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
601  (MI.getOperand(0).getReg() == cmpReg1 ||
602  (isSecondOpReg &&
603  MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
604 
605  unsigned feederReg = MI.getOperand(0).getReg();
606 
607  // First try to see if we can get the feeder from the first operand
608  // of the compare. If we can not, and if secondOpReg is true
609  // (second operand of the compare is also register), try that one.
610  // TODO: Try to come up with some heuristic to figure out which
611  // feeder would benefit.
612 
613  if (feederReg == cmpReg1) {
614  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
615  if (!isSecondOpReg)
616  break;
617  else
618  continue;
619  } else
620  foundFeeder = true;
621  }
622 
623  if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
624  if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
625  break;
626 
627  if (isSecondOpReg) {
628  // In case of CMPLT, or CMPLTU, or EQ with the second register
629  // to newify, swap the operands.
630  unsigned COp = cmpInstr->getOpcode();
631  if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
632  (feederReg == (unsigned)cmpOp2)) {
633  unsigned tmp = cmpReg1;
634  cmpReg1 = cmpOp2;
635  cmpOp2 = tmp;
636  }
637 
638  // Now we have swapped the operands, all we need to check is,
639  // if the second operand (after swap) is the feeder.
640  // And if it is, make a note.
641  if (feederReg == (unsigned)cmpOp2)
642  isSecondOpNewified = true;
643  }
644 
645  // Now that we are moving feeder close the jump,
646  // make sure we are respecting the kill values of
647  // the operands of the feeder.
648 
649  auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
650  for (MachineOperand &MO : MI.operands()) {
651  if (!MO.isReg() || !MO.isUse())
652  continue;
653  unsigned UseR = MO.getReg();
654  for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
655  if (I == cmpPos)
656  continue;
657  for (MachineOperand &Op : I->operands()) {
658  if (!Op.isReg() || !Op.isUse() || !Op.isKill())
659  continue;
660  if (Op.getReg() != UseR)
661  continue;
662  // We found that there is kill of a use register
663  // Set up a kill flag on the register
664  Op.setIsKill(false);
665  MO.setIsKill(true);
666  return;
667  }
668  }
669  }
670  };
671 
672  TransferKills(*feederPos);
673  TransferKills(*cmpPos);
674  bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
675  bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
676 
677  MBB->splice(jmpPos, MI.getParent(), MI);
678  MBB->splice(jmpPos, MI.getParent(), cmpInstr);
679  DebugLoc dl = MI.getDebugLoc();
680  MachineInstr *NewMI;
681 
682  assert((isNewValueJumpCandidate(*cmpInstr)) &&
683  "This compare is not a New Value Jump candidate.");
684  unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
685  isSecondOpNewified,
686  jmpTarget, MBPI);
687  if (invertPredicate)
688  opc = QII->getInvertedPredicatedOpcode(opc);
689 
690  if (isSecondOpReg)
691  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
692  .addReg(cmpReg1, getKillRegState(MO1IsKill))
693  .addReg(cmpOp2, getKillRegState(MO2IsKill))
694  .addMBB(jmpTarget);
695 
696  else
697  NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
698  .addReg(cmpReg1, getKillRegState(MO1IsKill))
699  .addImm(cmpOp2)
700  .addMBB(jmpTarget);
701 
702  assert(NewMI && "New Value Jump Instruction Not created!");
703  (void)NewMI;
704  if (cmpInstr->getOperand(0).isReg() &&
705  cmpInstr->getOperand(0).isKill())
706  cmpInstr->getOperand(0).setIsKill(false);
707  if (cmpInstr->getOperand(1).isReg() &&
708  cmpInstr->getOperand(1).isKill())
709  cmpInstr->getOperand(1).setIsKill(false);
710  cmpInstr->eraseFromParent();
711  jmpInstr->eraseFromParent();
712  ++nvjGenerated;
713  ++NumNVJGenerated;
714  break;
715  }
716  }
717  }
718  }
719 
720  return true;
721 }
722 
724  return new HexagonNewValueJump();
725 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
MachineBasicBlock * getMBB() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
unsigned getReg() const
getReg - Returns the register number.
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
void skip(CollectionType &C)
Definition: YAMLParser.h:381
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
return AArch64::GPR64RegClass contains(Reg)
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:304
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
void initializeHexagonNewValueJumpPass(PassRegistry &)
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
static bool commonChecksToProhibitNewValueJump(bool afterRA, MachineBasicBlock::iterator MII)
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, bool secondRegNewified, MachineBasicBlock *jmpTarget, const MachineBranchProbabilityInfo *MBPI)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1164
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
hexagon Hexagon static false bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF)
void setIsKill(bool Val=true)
FunctionPass * createHexagonNewValueJump()
Iterator for intrusive lists based on ilist_node.
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
static cl::opt< int > DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc("Maximum number of predicated jumps to be converted to " "New Value Jump"))
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", "Hexagon NewValueJump", false, false) INITIALIZE_PASS_END(HexagonNewValueJump
static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF)
#define I(x, y, z)
Definition: MD5.cpp:58
hexagon Hexagon NewValueJump
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
hexagon nvj
Properties which a MachineFunction may have at a given point in time.
static cl::opt< bool > DisableNewValueJumps("disable-nvjump", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable New Value Jumps"))