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HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
33 #include "llvm/Support/Debug.h"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "HexagonGenRegisterInfo.inc"
41 
42 using namespace llvm;
43 
45  : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
46  0/*PC*/, HwMode) {}
47 
48 
50  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
51  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
52 }
53 
54 const MCPhysReg *
56  const TargetRegisterClass *RC) const {
57  using namespace Hexagon;
58 
59  static const MCPhysReg Int32[] = {
60  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
61  };
62  static const MCPhysReg Int64[] = {
63  D0, D1, D2, D3, D4, D5, D6, D7, 0
64  };
65  static const MCPhysReg Pred[] = {
66  P0, P1, P2, P3, 0
67  };
68  static const MCPhysReg VecSgl[] = {
69  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
70  V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
71  V28, V29, V30, V31, 0
72  };
73  static const MCPhysReg VecDbl[] = {
74  W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
75  };
76 
77  switch (RC->getID()) {
78  case IntRegsRegClassID:
79  return Int32;
80  case DoubleRegsRegClassID:
81  return Int64;
82  case PredRegsRegClassID:
83  return Pred;
84  case HvxVRRegClassID:
85  return VecSgl;
86  case HvxWRRegClassID:
87  return VecDbl;
88  default:
89  break;
90  }
91 
92  static const MCPhysReg Empty[] = { 0 };
93 #ifndef NDEBUG
94  dbgs() << "Register class: " << getRegClassName(RC) << "\n";
95 #endif
96  llvm_unreachable("Unexpected register class");
97  return Empty;
98 }
99 
100 
101 const MCPhysReg *
103  static const MCPhysReg CalleeSavedRegsV3[] = {
104  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
105  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
106  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
107  };
108 
109  // Functions that contain a call to __builtin_eh_return also save the first 4
110  // parameter registers.
111  static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
112  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
113  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
114  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
115  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
116  };
117 
118  bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
119 
126  return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
127  }
128 
129  llvm_unreachable("Callee saved registers requested for unknown architecture "
130  "version");
131 }
132 
133 
135  const MachineFunction &MF, CallingConv::ID) const {
136  return HexagonCSR_RegMask;
137 }
138 
139 
141  const {
142  BitVector Reserved(getNumRegs());
143  Reserved.set(Hexagon::R29);
144  Reserved.set(Hexagon::R30);
145  Reserved.set(Hexagon::R31);
146  // Control registers.
147  Reserved.set(Hexagon::SA0); // C0
148  Reserved.set(Hexagon::LC0); // C1
149  Reserved.set(Hexagon::SA1); // C2
150  Reserved.set(Hexagon::LC1); // C3
151  Reserved.set(Hexagon::P3_0); // C4
152  Reserved.set(Hexagon::USR); // C8
153  Reserved.set(Hexagon::PC); // C9
154  Reserved.set(Hexagon::UGP); // C10
155  Reserved.set(Hexagon::GP); // C11
156  Reserved.set(Hexagon::CS0); // C12
157  Reserved.set(Hexagon::CS1); // C13
158  Reserved.set(Hexagon::UPCYCLELO); // C14
159  Reserved.set(Hexagon::UPCYCLEHI); // C15
160  Reserved.set(Hexagon::FRAMELIMIT); // C16
161  Reserved.set(Hexagon::FRAMEKEY); // C17
162  Reserved.set(Hexagon::PKTCOUNTLO); // C18
163  Reserved.set(Hexagon::PKTCOUNTHI); // C19
164  Reserved.set(Hexagon::UTIMERLO); // C30
165  Reserved.set(Hexagon::UTIMERHI); // C31
166  // Out of the control registers, only C8 is explicitly defined in
167  // HexagonRegisterInfo.td. If others are defined, make sure to add
168  // them here as well.
169  Reserved.set(Hexagon::C8);
170  Reserved.set(Hexagon::USR_OVF);
171 
172  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
173  markSuperRegs(Reserved, x);
174 
175  return Reserved;
176 }
177 
178 
180  int SPAdj, unsigned FIOp,
181  RegScavenger *RS) const {
182  //
183  // Hexagon_TODO: Do we need to enforce this for Hexagon?
184  assert(SPAdj == 0 && "Unexpected");
185 
186  MachineInstr &MI = *II;
187  MachineBasicBlock &MB = *MI.getParent();
188  MachineFunction &MF = *MB.getParent();
189  auto &HST = MF.getSubtarget<HexagonSubtarget>();
190  auto &HII = *HST.getInstrInfo();
191  auto &HFI = *HST.getFrameLowering();
192 
193  unsigned BP = 0;
194  int FI = MI.getOperand(FIOp).getIndex();
195  // Select the base pointer (BP) and calculate the actual offset from BP
196  // to the beginning of the object at index FI.
197  int Offset = HFI.getFrameIndexReference(MF, FI, BP);
198  // Add the offset from the instruction.
199  int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
200  bool IsKill = false;
201 
202  unsigned Opc = MI.getOpcode();
203  switch (Opc) {
204  case Hexagon::PS_fia:
205  MI.setDesc(HII.get(Hexagon::A2_addi));
206  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
207  MI.RemoveOperand(FIOp+1);
208  return;
209  case Hexagon::PS_fi:
210  // Set up the instruction for updating below.
211  MI.setDesc(HII.get(Hexagon::A2_addi));
212  break;
213  }
214 
215  if (!HII.isValidOffset(Opc, RealOffset, this)) {
216  // If the offset is not valid, calculate the address in a temporary
217  // register and use it with offset 0.
218  auto &MRI = MF.getRegInfo();
219  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
220  const DebugLoc &DL = MI.getDebugLoc();
221  BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
222  .addReg(BP)
223  .addImm(RealOffset);
224  BP = TmpR;
225  RealOffset = 0;
226  IsKill = true;
227  }
228 
229  MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
230  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
231 }
232 
233 
235  return Hexagon::R31;
236 }
237 
238 
240  &MF) const {
241  const HexagonFrameLowering *TFI = getFrameLowering(MF);
242  if (TFI->hasFP(MF))
243  return getFrameRegister();
244  return getStackRegister();
245 }
246 
247 
249  return Hexagon::R30;
250 }
251 
252 
254  return Hexagon::R29;
255 }
256 
257 
259  const TargetRegisterClass &RC, unsigned GenIdx) const {
260  assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
261 
262  static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
263  static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
264 
265  switch (RC.getID()) {
266  case Hexagon::CtrRegs64RegClassID:
267  case Hexagon::DoubleRegsRegClassID:
268  return ISub[GenIdx];
269  case Hexagon::HvxWRRegClassID:
270  return VSub[GenIdx];
271  }
272 
273  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
274  return getHexagonSubRegIndex(*SuperRC, GenIdx);
275 
276  llvm_unreachable("Invalid register class");
277 }
278 
280  const {
281  return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
282 }
283 
284 
286  return Hexagon::R6;
287 }
288 
BitVector & set()
Definition: BitVector.h:398
#define R4(n)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
Hexagon target-specific information for each MachineFunction.
const Hexagon::ArchEnum & getHexagonArchVersion() const
A debug info location.
Definition: DebugLoc.h:34
#define R2(n)
bool isEHReturnCalleeSaveReg(unsigned Reg) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
unsigned getID() const
Return the register class ID number.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
HexagonRegisterInfo(unsigned HwMode)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
unsigned getFirstCallerSavedNonParamReg() const
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...