39 #define GET_REGINFO_TARGET_DESC 40 #include "HexagonGenRegisterInfo.inc" 50 return R == Hexagon::R0 || R == Hexagon::R1 || R ==
Hexagon::R2 ||
51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
57 using namespace Hexagon;
60 R0, R1,
R2, R3,
R4, R5,
R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
63 D0, D1, D2, D3, D4, D5, D6, D7, 0
69 V0, V1,
V2, V3,
V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
74 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
77 switch (RC->
getID()) {
78 case IntRegsRegClassID:
80 case DoubleRegsRegClassID:
82 case PredRegsRegClassID:
94 dbgs() <<
"Register class: " << getRegClassName(RC) <<
"\n";
103 static const MCPhysReg CalleeSavedRegsV3[] = {
104 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
105 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
106 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
111 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
112 Hexagon::R0, Hexagon::R1,
Hexagon::R2, Hexagon::R3,
113 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
114 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
115 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
120 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
126 return HexagonCSR_RegMask;
133 Reserved.
set(Hexagon::R29);
134 Reserved.
set(Hexagon::R30);
135 Reserved.
set(Hexagon::R31);
136 Reserved.
set(Hexagon::VTMP);
139 Reserved.
set(Hexagon::GELR);
140 Reserved.
set(Hexagon::GSR);
141 Reserved.
set(Hexagon::GOSP);
142 Reserved.
set(Hexagon::G3);
145 Reserved.
set(Hexagon::SA0);
146 Reserved.
set(Hexagon::LC0);
147 Reserved.
set(Hexagon::SA1);
148 Reserved.
set(Hexagon::LC1);
149 Reserved.
set(Hexagon::P3_0);
150 Reserved.
set(Hexagon::USR);
151 Reserved.
set(Hexagon::PC);
152 Reserved.
set(Hexagon::UGP);
153 Reserved.
set(Hexagon::GP);
154 Reserved.
set(Hexagon::CS0);
155 Reserved.
set(Hexagon::CS1);
156 Reserved.
set(Hexagon::UPCYCLELO);
157 Reserved.
set(Hexagon::UPCYCLEHI);
158 Reserved.
set(Hexagon::FRAMELIMIT);
159 Reserved.
set(Hexagon::FRAMEKEY);
160 Reserved.
set(Hexagon::PKTCOUNTLO);
161 Reserved.
set(Hexagon::PKTCOUNTHI);
162 Reserved.
set(Hexagon::UTIMERLO);
163 Reserved.
set(Hexagon::UTIMERHI);
167 Reserved.
set(Hexagon::C8);
168 Reserved.
set(Hexagon::USR_OVF);
171 Reserved.
set(Hexagon::R19);
174 markSuperRegs(Reserved, x);
181 int SPAdj,
unsigned FIOp,
185 assert(SPAdj == 0 &&
"Unexpected");
192 auto &HFI = *HST.getFrameLowering();
198 int Offset = HFI.getFrameIndexReference(MF, FI, BP);
205 case Hexagon::PS_fia:
206 MI.
setDesc(HII.get(Hexagon::A2_addi));
212 MI.
setDesc(HII.get(Hexagon::A2_addi));
216 if (!HII.isValidOffset(Opc, RealOffset,
this)) {
220 unsigned TmpR =
MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
222 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
245 if (!HST.
useHVXOps() || NewRC->
getID() != Hexagon::HvxWRRegClass.getID())
247 bool SmallSrc = SrcRC->
getID() == Hexagon::HvxVRRegClass.getID();
248 bool SmallDst = DstRC->
getID() == Hexagon::HvxVRRegClass.getID();
249 if (!SmallSrc && !SmallDst)
256 for (
SlotIndex I = S.start.getBaseIndex(),
E = S.end.getBaseIndex();
257 I !=
E;
I =
I.getNextIndex()) {
265 if (SmallSrc == SmallDst) {
277 unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
278 unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
312 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
313 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
314 static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
316 switch (RC.
getID()) {
317 case Hexagon::CtrRegs64RegClassID:
318 case Hexagon::DoubleRegsRegClassID:
320 case Hexagon::HvxWRRegClassID:
322 case Hexagon::HvxVQRRegClassID:
339 unsigned Kind)
const {
340 return &Hexagon::IntRegsRegClass;
bool isCall(QueryType Type=AnyInBundle) const
This class represents lattice values for constants.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
unsigned getReg() const
getReg - Returns the register number.
Hexagon target-specific information for each MachineFunction.
This represents a simple continuous liveness interval for a value.
unsigned getStackRegister() const
bool isEHReturnCalleeSaveReg(unsigned Reg) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getID() const
Return the register class ID number.
bool hasReservedR19() const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
HexagonRegisterInfo(unsigned HwMode)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
unsigned getFirstCallerSavedNonParamReg() const
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineBasicBlock * getParent() const
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
unsigned getRARegister() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SlotIndexes * getSlotIndexes() const
BitVector getReservedRegs(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineOperand & getOperand(unsigned i) const
SlotIndex - An opaque wrapper around machine indexes.
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
unsigned getFrameRegister() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...