LLVM  8.0.0svn
HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
34 #include "llvm/Support/Debug.h"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "HexagonGenRegisterInfo.inc"
42 
43 using namespace llvm;
44 
46  : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
47  0/*PC*/, HwMode) {}
48 
49 
51  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
52  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
53 }
54 
55 const MCPhysReg *
57  const TargetRegisterClass *RC) const {
58  using namespace Hexagon;
59 
60  static const MCPhysReg Int32[] = {
61  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
62  };
63  static const MCPhysReg Int64[] = {
64  D0, D1, D2, D3, D4, D5, D6, D7, 0
65  };
66  static const MCPhysReg Pred[] = {
67  P0, P1, P2, P3, 0
68  };
69  static const MCPhysReg VecSgl[] = {
70  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
71  V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
72  V28, V29, V30, V31, 0
73  };
74  static const MCPhysReg VecDbl[] = {
75  W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
76  };
77 
78  switch (RC->getID()) {
79  case IntRegsRegClassID:
80  return Int32;
81  case DoubleRegsRegClassID:
82  return Int64;
83  case PredRegsRegClassID:
84  return Pred;
85  case HvxVRRegClassID:
86  return VecSgl;
87  case HvxWRRegClassID:
88  return VecDbl;
89  default:
90  break;
91  }
92 
93  static const MCPhysReg Empty[] = { 0 };
94 #ifndef NDEBUG
95  dbgs() << "Register class: " << getRegClassName(RC) << "\n";
96 #endif
97  llvm_unreachable("Unexpected register class");
98  return Empty;
99 }
100 
101 
102 const MCPhysReg *
104  static const MCPhysReg CalleeSavedRegsV3[] = {
105  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
106  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
107  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
108  };
109 
110  // Functions that contain a call to __builtin_eh_return also save the first 4
111  // parameter registers.
112  static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
113  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
114  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
115  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
116  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
117  };
118 
119  bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
120 
121  return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
122 }
123 
124 
126  const MachineFunction &MF, CallingConv::ID) const {
127  return HexagonCSR_RegMask;
128 }
129 
130 
132  const {
133  BitVector Reserved(getNumRegs());
134  Reserved.set(Hexagon::R29);
135  Reserved.set(Hexagon::R30);
136  Reserved.set(Hexagon::R31);
137  Reserved.set(Hexagon::VTMP);
138 
139  // Guest registers.
140  Reserved.set(Hexagon::GELR); // G0
141  Reserved.set(Hexagon::GSR); // G1
142  Reserved.set(Hexagon::GOSP); // G2
143  Reserved.set(Hexagon::G3); // G3
144 
145  // Control registers.
146  Reserved.set(Hexagon::SA0); // C0
147  Reserved.set(Hexagon::LC0); // C1
148  Reserved.set(Hexagon::SA1); // C2
149  Reserved.set(Hexagon::LC1); // C3
150  Reserved.set(Hexagon::P3_0); // C4
151  Reserved.set(Hexagon::USR); // C8
152  Reserved.set(Hexagon::PC); // C9
153  Reserved.set(Hexagon::UGP); // C10
154  Reserved.set(Hexagon::GP); // C11
155  Reserved.set(Hexagon::CS0); // C12
156  Reserved.set(Hexagon::CS1); // C13
157  Reserved.set(Hexagon::UPCYCLELO); // C14
158  Reserved.set(Hexagon::UPCYCLEHI); // C15
159  Reserved.set(Hexagon::FRAMELIMIT); // C16
160  Reserved.set(Hexagon::FRAMEKEY); // C17
161  Reserved.set(Hexagon::PKTCOUNTLO); // C18
162  Reserved.set(Hexagon::PKTCOUNTHI); // C19
163  Reserved.set(Hexagon::UTIMERLO); // C30
164  Reserved.set(Hexagon::UTIMERHI); // C31
165  // Out of the control registers, only C8 is explicitly defined in
166  // HexagonRegisterInfo.td. If others are defined, make sure to add
167  // them here as well.
168  Reserved.set(Hexagon::C8);
169  Reserved.set(Hexagon::USR_OVF);
170 
172  Reserved.set(Hexagon::R19);
173 
174  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
175  markSuperRegs(Reserved, x);
176 
177  return Reserved;
178 }
179 
180 
182  int SPAdj, unsigned FIOp,
183  RegScavenger *RS) const {
184  //
185  // Hexagon_TODO: Do we need to enforce this for Hexagon?
186  assert(SPAdj == 0 && "Unexpected");
187 
188  MachineInstr &MI = *II;
189  MachineBasicBlock &MB = *MI.getParent();
190  MachineFunction &MF = *MB.getParent();
191  auto &HST = MF.getSubtarget<HexagonSubtarget>();
192  auto &HII = *HST.getInstrInfo();
193  auto &HFI = *HST.getFrameLowering();
194 
195  unsigned BP = 0;
196  int FI = MI.getOperand(FIOp).getIndex();
197  // Select the base pointer (BP) and calculate the actual offset from BP
198  // to the beginning of the object at index FI.
199  int Offset = HFI.getFrameIndexReference(MF, FI, BP);
200  // Add the offset from the instruction.
201  int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
202  bool IsKill = false;
203 
204  unsigned Opc = MI.getOpcode();
205  switch (Opc) {
206  case Hexagon::PS_fia:
207  MI.setDesc(HII.get(Hexagon::A2_addi));
208  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
209  MI.RemoveOperand(FIOp+1);
210  return;
211  case Hexagon::PS_fi:
212  // Set up the instruction for updating below.
213  MI.setDesc(HII.get(Hexagon::A2_addi));
214  break;
215  }
216 
217  if (!HII.isValidOffset(Opc, RealOffset, this)) {
218  // If the offset is not valid, calculate the address in a temporary
219  // register and use it with offset 0.
220  auto &MRI = MF.getRegInfo();
221  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
222  const DebugLoc &DL = MI.getDebugLoc();
223  BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
224  .addReg(BP)
225  .addImm(RealOffset);
226  BP = TmpR;
227  RealOffset = 0;
228  IsKill = true;
229  }
230 
231  MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
232  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
233 }
234 
235 
237  const TargetRegisterClass *SrcRC, unsigned SubReg,
238  const TargetRegisterClass *DstRC, unsigned DstSubReg,
239  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
240  // Coalescing will extend the live interval of the destination register.
241  // If the destination register is a vector pair, avoid introducing function
242  // calls into the interval, since it could result in a spilling of a pair
243  // instead of a single vector.
244  MachineFunction &MF = *MI->getParent()->getParent();
246  if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
247  return true;
248  bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
249  bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
250  if (!SmallSrc && !SmallDst)
251  return true;
252 
253  unsigned DstReg = MI->getOperand(0).getReg();
254  unsigned SrcReg = MI->getOperand(1).getReg();
255  const SlotIndexes &Indexes = *LIS.getSlotIndexes();
256  auto HasCall = [&Indexes] (const LiveInterval::Segment &S) {
257  for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
258  I != E; I = I.getNextIndex()) {
259  if (const MachineInstr *MI = Indexes.getInstructionFromIndex(I))
260  if (MI->isCall())
261  return true;
262  }
263  return false;
264  };
265 
266  if (SmallSrc == SmallDst) {
267  // Both must be true, because the case for both being false was
268  // checked earlier. Both registers will be coalesced into a register
269  // of a wider class (HvxWR), and we don't want its live range to
270  // span over calls.
271  return !any_of(LIS.getInterval(DstReg), HasCall) &&
272  !any_of(LIS.getInterval(SrcReg), HasCall);
273  }
274 
275  // If one register is large (HvxWR) and the other is small (HvxVR), then
276  // coalescing is ok if the large is already live across a function call,
277  // or if the small one is not.
278  unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
279  unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
280  return any_of(LIS.getInterval(LargeReg), HasCall) ||
281  !any_of(LIS.getInterval(SmallReg), HasCall);
282 }
283 
284 
286  return Hexagon::R31;
287 }
288 
289 
291  &MF) const {
292  const HexagonFrameLowering *TFI = getFrameLowering(MF);
293  if (TFI->hasFP(MF))
294  return getFrameRegister();
295  return getStackRegister();
296 }
297 
298 
300  return Hexagon::R30;
301 }
302 
303 
305  return Hexagon::R29;
306 }
307 
308 
310  const TargetRegisterClass &RC, unsigned GenIdx) const {
311  assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
312 
313  static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
314  static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
315  static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
316 
317  switch (RC.getID()) {
318  case Hexagon::CtrRegs64RegClassID:
319  case Hexagon::DoubleRegsRegClassID:
320  return ISub[GenIdx];
321  case Hexagon::HvxWRRegClassID:
322  return VSub[GenIdx];
323  case Hexagon::HvxVQRRegClassID:
324  return WSub[GenIdx];
325  }
326 
327  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
328  return getHexagonSubRegIndex(*SuperRC, GenIdx);
329 
330  llvm_unreachable("Invalid register class");
331 }
332 
334  const {
335  return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
336 }
337 
338 const TargetRegisterClass *
340  unsigned Kind) const {
341  return &Hexagon::IntRegsRegClass;
342 }
343 
345  return Hexagon::R6;
346 }
347 
BitVector & set()
Definition: BitVector.h:398
#define R4(n)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
This class represents lattice values for constants.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
unsigned getReg() const
getReg - Returns the register number.
Hexagon target-specific information for each MachineFunction.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
A debug info location.
Definition: DebugLoc.h:34
#define R2(n)
bool isEHReturnCalleeSaveReg(unsigned Reg) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
unsigned SubReg
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
unsigned getID() const
Return the register class ID number.
SlotIndexes pass.
Definition: SlotIndexes.h:331
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:430
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1187
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
HexagonRegisterInfo(unsigned HwMode)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
unsigned getFirstCallerSavedNonParamReg() const
LiveInterval & getInterval(unsigned Reg)
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
#define I(x, y, z)
Definition: MD5.cpp:58
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SlotIndexes * getSlotIndexes() const
BitVector getReservedRegs(const MachineFunction &MF) const override
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...