LLVM  8.0.0svn
HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
34 #include "llvm/Support/Debug.h"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "HexagonGenRegisterInfo.inc"
42 
43 using namespace llvm;
44 
46  : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
47  0/*PC*/, HwMode) {}
48 
49 
51  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
52  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
53 }
54 
55 const MCPhysReg *
57  const TargetRegisterClass *RC) const {
58  using namespace Hexagon;
59 
60  static const MCPhysReg Int32[] = {
61  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
62  };
63  static const MCPhysReg Int64[] = {
64  D0, D1, D2, D3, D4, D5, D6, D7, 0
65  };
66  static const MCPhysReg Pred[] = {
67  P0, P1, P2, P3, 0
68  };
69  static const MCPhysReg VecSgl[] = {
70  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
71  V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
72  V28, V29, V30, V31, 0
73  };
74  static const MCPhysReg VecDbl[] = {
75  W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
76  };
77 
78  switch (RC->getID()) {
79  case IntRegsRegClassID:
80  return Int32;
81  case DoubleRegsRegClassID:
82  return Int64;
83  case PredRegsRegClassID:
84  return Pred;
85  case HvxVRRegClassID:
86  return VecSgl;
87  case HvxWRRegClassID:
88  return VecDbl;
89  default:
90  break;
91  }
92 
93  static const MCPhysReg Empty[] = { 0 };
94 #ifndef NDEBUG
95  dbgs() << "Register class: " << getRegClassName(RC) << "\n";
96 #endif
97  llvm_unreachable("Unexpected register class");
98  return Empty;
99 }
100 
101 
102 const MCPhysReg *
104  static const MCPhysReg CalleeSavedRegsV3[] = {
105  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
106  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
107  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
108  };
109 
110  // Functions that contain a call to __builtin_eh_return also save the first 4
111  // parameter registers.
112  static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
113  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
114  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
115  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
116  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
117  };
118 
119  bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
120 
128  return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
129  }
130 
131  llvm_unreachable("Callee saved registers requested for unknown architecture "
132  "version");
133 }
134 
135 
137  const MachineFunction &MF, CallingConv::ID) const {
138  return HexagonCSR_RegMask;
139 }
140 
141 
143  const {
144  BitVector Reserved(getNumRegs());
145  Reserved.set(Hexagon::R29);
146  Reserved.set(Hexagon::R30);
147  Reserved.set(Hexagon::R31);
148  Reserved.set(Hexagon::VTMP);
149 
150  // Guest registers.
151  Reserved.set(Hexagon::GELR); // G0
152  Reserved.set(Hexagon::GSR); // G1
153  Reserved.set(Hexagon::GOSP); // G2
154  Reserved.set(Hexagon::G3); // G3
155 
156  // Control registers.
157  Reserved.set(Hexagon::SA0); // C0
158  Reserved.set(Hexagon::LC0); // C1
159  Reserved.set(Hexagon::SA1); // C2
160  Reserved.set(Hexagon::LC1); // C3
161  Reserved.set(Hexagon::P3_0); // C4
162  Reserved.set(Hexagon::USR); // C8
163  Reserved.set(Hexagon::PC); // C9
164  Reserved.set(Hexagon::UGP); // C10
165  Reserved.set(Hexagon::GP); // C11
166  Reserved.set(Hexagon::CS0); // C12
167  Reserved.set(Hexagon::CS1); // C13
168  Reserved.set(Hexagon::UPCYCLELO); // C14
169  Reserved.set(Hexagon::UPCYCLEHI); // C15
170  Reserved.set(Hexagon::FRAMELIMIT); // C16
171  Reserved.set(Hexagon::FRAMEKEY); // C17
172  Reserved.set(Hexagon::PKTCOUNTLO); // C18
173  Reserved.set(Hexagon::PKTCOUNTHI); // C19
174  Reserved.set(Hexagon::UTIMERLO); // C30
175  Reserved.set(Hexagon::UTIMERHI); // C31
176  // Out of the control registers, only C8 is explicitly defined in
177  // HexagonRegisterInfo.td. If others are defined, make sure to add
178  // them here as well.
179  Reserved.set(Hexagon::C8);
180  Reserved.set(Hexagon::USR_OVF);
181 
183  Reserved.set(Hexagon::R19);
184 
185  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
186  markSuperRegs(Reserved, x);
187 
188  return Reserved;
189 }
190 
191 
193  int SPAdj, unsigned FIOp,
194  RegScavenger *RS) const {
195  //
196  // Hexagon_TODO: Do we need to enforce this for Hexagon?
197  assert(SPAdj == 0 && "Unexpected");
198 
199  MachineInstr &MI = *II;
200  MachineBasicBlock &MB = *MI.getParent();
201  MachineFunction &MF = *MB.getParent();
202  auto &HST = MF.getSubtarget<HexagonSubtarget>();
203  auto &HII = *HST.getInstrInfo();
204  auto &HFI = *HST.getFrameLowering();
205 
206  unsigned BP = 0;
207  int FI = MI.getOperand(FIOp).getIndex();
208  // Select the base pointer (BP) and calculate the actual offset from BP
209  // to the beginning of the object at index FI.
210  int Offset = HFI.getFrameIndexReference(MF, FI, BP);
211  // Add the offset from the instruction.
212  int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
213  bool IsKill = false;
214 
215  unsigned Opc = MI.getOpcode();
216  switch (Opc) {
217  case Hexagon::PS_fia:
218  MI.setDesc(HII.get(Hexagon::A2_addi));
219  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
220  MI.RemoveOperand(FIOp+1);
221  return;
222  case Hexagon::PS_fi:
223  // Set up the instruction for updating below.
224  MI.setDesc(HII.get(Hexagon::A2_addi));
225  break;
226  }
227 
228  if (!HII.isValidOffset(Opc, RealOffset, this)) {
229  // If the offset is not valid, calculate the address in a temporary
230  // register and use it with offset 0.
231  auto &MRI = MF.getRegInfo();
232  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
233  const DebugLoc &DL = MI.getDebugLoc();
234  BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
235  .addReg(BP)
236  .addImm(RealOffset);
237  BP = TmpR;
238  RealOffset = 0;
239  IsKill = true;
240  }
241 
242  MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
243  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
244 }
245 
246 
248  const TargetRegisterClass *SrcRC, unsigned SubReg,
249  const TargetRegisterClass *DstRC, unsigned DstSubReg,
250  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
251  // Coalescing will extend the live interval of the destination register.
252  // If the destination register is a vector pair, avoid introducing function
253  // calls into the interval, since it could result in a spilling of a pair
254  // instead of a single vector.
255  MachineFunction &MF = *MI->getParent()->getParent();
257  if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
258  return true;
259  bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
260  bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
261  if (!SmallSrc && !SmallDst)
262  return true;
263 
264  unsigned DstReg = MI->getOperand(0).getReg();
265  unsigned SrcReg = MI->getOperand(1).getReg();
266  const SlotIndexes &Indexes = *LIS.getSlotIndexes();
267  auto HasCall = [&Indexes] (const LiveInterval::Segment &S) {
268  for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
269  I != E; I = I.getNextIndex()) {
270  if (const MachineInstr *MI = Indexes.getInstructionFromIndex(I))
271  if (MI->isCall())
272  return true;
273  }
274  return false;
275  };
276 
277  if (SmallSrc == SmallDst) {
278  // Both must be true, because the case for both being false was
279  // checked earlier. Both registers will be coalesced into a register
280  // of a wider class (HvxWR), and we don't want its live range to
281  // span over calls.
282  return !any_of(LIS.getInterval(DstReg), HasCall) &&
283  !any_of(LIS.getInterval(SrcReg), HasCall);
284  }
285 
286  // If one register is large (HvxWR) and the other is small (HvxVR), then
287  // coalescing is ok if the large is already live across a function call,
288  // or if the small one is not.
289  unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
290  unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
291  return any_of(LIS.getInterval(LargeReg), HasCall) ||
292  !any_of(LIS.getInterval(SmallReg), HasCall);
293 }
294 
295 
297  return Hexagon::R31;
298 }
299 
300 
302  &MF) const {
303  const HexagonFrameLowering *TFI = getFrameLowering(MF);
304  if (TFI->hasFP(MF))
305  return getFrameRegister();
306  return getStackRegister();
307 }
308 
309 
311  return Hexagon::R30;
312 }
313 
314 
316  return Hexagon::R29;
317 }
318 
319 
321  const TargetRegisterClass &RC, unsigned GenIdx) const {
322  assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
323 
324  static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
325  static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
326 
327  switch (RC.getID()) {
328  case Hexagon::CtrRegs64RegClassID:
329  case Hexagon::DoubleRegsRegClassID:
330  return ISub[GenIdx];
331  case Hexagon::HvxWRRegClassID:
332  return VSub[GenIdx];
333  }
334 
335  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
336  return getHexagonSubRegIndex(*SuperRC, GenIdx);
337 
338  llvm_unreachable("Invalid register class");
339 }
340 
342  const {
343  return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
344 }
345 
346 const TargetRegisterClass *
348  unsigned Kind) const {
349  return &Hexagon::IntRegsRegClass;
350 }
351 
353  return Hexagon::R6;
354 }
355 
BitVector & set()
Definition: BitVector.h:398
#define R4(n)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:619
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:377
unsigned getReg() const
getReg - Returns the register number.
Hexagon target-specific information for each MachineFunction.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
const Hexagon::ArchEnum & getHexagonArchVersion() const
A debug info location.
Definition: DebugLoc.h:34
#define R2(n)
bool isEHReturnCalleeSaveReg(unsigned Reg) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
unsigned SubReg
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:403
unsigned getID() const
Return the register class ID number.
SlotIndexes pass.
Definition: SlotIndexes.h:331
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:424
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1025
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
HexagonRegisterInfo(unsigned HwMode)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
unsigned getFirstCallerSavedNonParamReg() const
LiveInterval & getInterval(unsigned Reg)
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:248
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
#define I(x, y, z)
Definition: MD5.cpp:58
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SlotIndexes * getSlotIndexes() const
BitVector getReservedRegs(const MachineFunction &MF) const override
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:408
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, unsigned GenIdx) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...