LLVM  8.0.0svn
HexagonRegisterInfo.h
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1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
17 
19 
20 #define GET_REGINFO_HEADER
21 #include "HexagonGenRegisterInfo.inc"
22 
23 namespace llvm {
24 
25 namespace Hexagon {
26  // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
27  enum { ps_sub_lo = 0, ps_sub_hi = 1 };
28 }
29 
31 public:
32  HexagonRegisterInfo(unsigned HwMode);
33 
34  /// Code Generation virtual methods...
35  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
36  const override;
37  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
38  CallingConv::ID) const override;
39 
40  BitVector getReservedRegs(const MachineFunction &MF) const override;
41 
42  bool enableMultipleCopyHints() const override { return true; }
43 
44  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
45  unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
46 
47  /// Returns true since we may need scavenging for a temporary register
48  /// when generating hardware loop instructions.
49  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
50  return true;
51  }
52 
53  /// Returns true. Spill code for predicate registers might need an extra
54  /// register.
55  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
56  return true;
57  }
58 
59  /// Returns true if the frame pointer is valid.
60  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
61 
62  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
63  return true;
64  }
65 
66  bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
67  unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
68  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
69 
70  // Debug information queries.
71  unsigned getRARegister() const;
72  unsigned getFrameRegister(const MachineFunction &MF) const override;
73  unsigned getFrameRegister() const;
74  unsigned getStackRegister() const;
75 
76  unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
77  unsigned GenIdx) const;
78 
79  const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
80  const TargetRegisterClass *RC) const;
81 
82  unsigned getFirstCallerSavedNonParamReg() const;
83 
84  const TargetRegisterClass *
85  getPointerRegClass(const MachineFunction &MF,
86  unsigned Kind = 0) const override;
87 
88  bool isEHReturnCalleeSaveReg(unsigned Reg) const;
89 };
90 
91 } // end namespace llvm
92 
93 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned Reg
unsigned SubReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool enableMultipleCopyHints() const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Returns true since we may need scavenging for a temporary register when generating hardware loop inst...
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
const unsigned Kind
IRTranslator LLVM IR MI
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Returns true.