LLVM  6.0.0svn
HexagonRegisterInfo.h
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1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
17 
19 
20 #define GET_REGINFO_HEADER
21 #include "HexagonGenRegisterInfo.inc"
22 
23 namespace llvm {
24 
25 namespace Hexagon {
26  // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
27  enum { ps_sub_lo = 0, ps_sub_hi = 1 };
28 }
29 
31 public:
32  HexagonRegisterInfo(unsigned HwMode);
33 
34  /// Code Generation virtual methods...
35  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
36  const override;
37  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
38  CallingConv::ID) const override;
39 
40  BitVector getReservedRegs(const MachineFunction &MF) const override;
41 
42  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
43  unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
44 
45  /// Returns true since we may need scavenging for a temporary register
46  /// when generating hardware loop instructions.
47  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
48  return true;
49  }
50 
51  /// Returns true. Spill code for predicate registers might need an extra
52  /// register.
53  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
54  return true;
55  }
56 
57  /// Returns true if the frame pointer is valid.
58  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
59 
60  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
61  return true;
62  }
63 
64  // Debug information queries.
65  unsigned getRARegister() const;
66  unsigned getFrameRegister(const MachineFunction &MF) const override;
67  unsigned getFrameRegister() const;
68  unsigned getStackRegister() const;
69 
70  unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
71  unsigned GenIdx) const;
72 
73  const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
74  const TargetRegisterClass *RC) const;
75 
76  unsigned getFirstCallerSavedNonParamReg() const;
77 
78  bool isEHReturnCalleeSaveReg(unsigned Reg) const;
79 };
80 
81 } // end namespace llvm
82 
83 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Reg
All possible values of the reg field in the ModR/M byte.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Returns true since we may need scavenging for a temporary register when generating hardware loop inst...
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Returns true.