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HexagonShuffler.h
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1 //===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the shuffling of insns inside a bundle according to the
11 // packet formation rules of the Hexagon ISA.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
16 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
17 
18 #include "Hexagon.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
23 #include "llvm/Support/SMLoc.h"
24 #include <cstdint>
25 #include <utility>
26 
27 namespace llvm {
28 
29 class MCContext;
30 class MCInst;
31 class MCInstrInfo;
32 class MCSubtargetInfo;
33 
34 // Insn resources.
36  // Mask of the slots or units that may execute the insn and
37  // the weight or priority that the insn requires to be assigned a slot.
38  unsigned Slots, Weight;
39 
40 public:
41  HexagonResource(unsigned s) { setUnits(s); }
42 
43  void setUnits(unsigned s) {
44  Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
45  setWeight(s);
46  }
47 
48  unsigned setWeight(unsigned s);
49 
50  unsigned getUnits() const { return (Slots); }
51  unsigned getWeight() const { return (Weight); }
52 
53  // Check if the resources are in ascending slot order.
54  static bool lessUnits(const HexagonResource &A, const HexagonResource &B) {
55  return (countPopulation(A.getUnits()) < countPopulation(B.getUnits()));
56  }
57 
58  // Check if the resources are in ascending weight order.
59  static bool lessWeight(const HexagonResource &A, const HexagonResource &B) {
60  return (A.getWeight() < B.getWeight());
61  }
62 };
63 
64 // HVX insn resources.
66 public:
67  using UnitsAndLanes = std::pair<unsigned, unsigned>;
69 
70 private:
71  // Available HVX slots.
72  enum {
73  CVI_NONE = 0,
74  CVI_XLANE = 1 << 0,
75  CVI_SHIFT = 1 << 1,
76  CVI_MPY0 = 1 << 2,
77  CVI_MPY1 = 1 << 3
78  };
79 
80  // Count of adjacent slots that the insn requires to be executed.
81  unsigned Lanes;
82  // Flag whether the insn is a load or a store.
83  bool Load, Store;
84  // Flag whether the HVX resources are valid.
85  bool Valid;
86 
87  void setLanes(unsigned l) { Lanes = l; }
88  void setLoad(bool f = true) { Load = f; }
89  void setStore(bool f = true) { Store = f; }
90 
91 public:
93  unsigned s, MCInst const *id);
94 
95  static void SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU);
96 
97  bool isValid() const { return Valid; }
98  unsigned getLanes() const { return Lanes; }
99  bool mayLoad() const { return Load; }
100  bool mayStore() const { return Store; }
101 };
102 
103 // Handle to an insn used by the shuffling algorithm.
105  friend class HexagonShuffler;
106 
107  MCInst const *ID;
108  MCInst const *Extender;
109  HexagonResource Core;
110  HexagonCVIResource CVI;
111 
112 public:
114  MCInstrInfo const &MCII, MCInst const *id,
115  MCInst const *Extender, unsigned s)
116  : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {}
117 
118  MCInst const &getDesc() const { return *ID; }
119  MCInst const *getExtender() const { return Extender; }
120 
121  // Check if the handles are in ascending order for shuffling purposes.
122  bool operator<(const HexagonInstr &B) const {
123  return (HexagonResource::lessWeight(B.Core, Core));
124  }
125 
126  // Check if the handles are in ascending order by core slots.
127  static bool lessCore(const HexagonInstr &A, const HexagonInstr &B) {
128  return (HexagonResource::lessUnits(A.Core, B.Core));
129  }
130 
131  // Check if the handles are in ascending order by HVX slots.
132  static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B) {
133  return (HexagonResource::lessUnits(A.CVI, B.CVI));
134  }
135 };
136 
137 // Bundle shuffler.
139  using HexagonPacket =
141 
142  // Insn handles in a bundle.
143  HexagonPacket Packet;
144  HexagonPacket PacketSave;
145 
147 
148 protected:
150  int64_t BundleFlags;
155 
156 public:
158 
159  HexagonShuffler(MCContext &Context, bool ReportErrors,
160  MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
161 
162  // Reset to initial state.
163  void reset();
164  // Check if the bundle may be validly shuffled.
165  bool check();
166  // Reorder the insn handles in the bundle.
167  bool shuffle();
168 
169  unsigned size() const { return (Packet.size()); }
170 
171  iterator begin() { return (Packet.begin()); }
172  iterator end() { return (Packet.end()); }
173 
174  // Add insn handle to the bundle .
175  void append(MCInst const &ID, MCInst const *Extender, unsigned S);
176 
177  // Return the error code for the last check or shuffling of the bundle.
178  void reportError(Twine const &Msg);
179 };
180 
181 } // end namespace llvm
182 
183 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
static bool lessCore(const HexagonInstr &A, const HexagonInstr &B)
void setUnits(unsigned s)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
HexagonResource(unsigned s)
unsigned getLanes() const
unsigned setWeight(unsigned s)
unsigned size() const
static bool lessWeight(const HexagonResource &A, const HexagonResource &B)
void append(SmallVectorImpl< char > &path, const Twine &a, const Twine &b="", const Twine &c="", const Twine &d="")
Append to path.
Definition: Path.cpp:465
HexagonInstr(HexagonCVIResource::TypeUnitsAndLanes *T, MCInstrInfo const &MCII, MCInst const *id, MCInst const *Extender, unsigned s)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
Context object for machine code objects.
Definition: MCContext.h:59
HexagonPacket::iterator iterator
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned getWeight() const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
MCSubtargetInfo const & STI
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:512
MCInstrInfo const & MCII
MCInst const * getExtender() const
typename SuperClass::iterator iterator
Definition: SmallVector.h:328
static int reportError(const char *ProgName, Twine Msg)
Definition: Main.cpp:49
std::pair< unsigned, unsigned > UnitsAndLanes
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
static bool lessUnits(const HexagonResource &A, const HexagonResource &B)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
MCSubtargetInfo - Generic base class for all target subtargets.
unsigned getUnits() const
MCInst const & getDesc() const
static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Represents a location in source code.
Definition: SMLoc.h:24
bool operator<(const HexagonInstr &B) const