LLVM  8.0.0svn
HexagonSubtarget.cpp
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1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <map>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "hexagon-subtarget"
37 
38 #define GET_SUBTARGETINFO_CTOR
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #include "HexagonGenSubtargetInfo.inc"
41 
42 
43 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
45 
46 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
48 
49 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
51  cl::desc("Enable the scheduler to generate .cur"));
52 
53 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
55  cl::desc("Disable Hexagon MI Scheduling"));
56 
57 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
59  cl::desc("Enable subregister liveness tracking for Hexagon"));
60 
61 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
63  cl::desc("If present, forces/disables the use of long calls"));
64 
65 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
67  cl::desc("Consider calls to be predicable"));
68 
69 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
71 
72 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
74 
75 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
77  cl::desc("Enable checking for cache bank conflicts"));
78 
79 
81  StringRef FS, const TargetMachine &TM)
82  : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
83  CPUString(Hexagon_MC::selectHexagonCPU(CPU)),
84  InstrInfo(initializeSubtargetDependencies(CPU, FS)),
85  RegInfo(getHwMode()), TLInfo(TM, *this),
86  InstrItins(getInstrItineraryForCPU(CPUString)) {
87  // Beware of the default constructor of InstrItineraryData: it will
88  // reset all members to 0.
89  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
90 }
91 
94  static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
95  {"generic", Hexagon::ArchEnum::V60},
96  {"hexagonv4", Hexagon::ArchEnum::V4},
97  {"hexagonv5", Hexagon::ArchEnum::V5},
98  {"hexagonv55", Hexagon::ArchEnum::V55},
99  {"hexagonv60", Hexagon::ArchEnum::V60},
100  {"hexagonv62", Hexagon::ArchEnum::V62},
101  {"hexagonv65", Hexagon::ArchEnum::V65},
102  };
103 
104  auto FoundIt = CpuTable.find(CPUString);
105  if (FoundIt != CpuTable.end())
106  HexagonArchVersion = FoundIt->second;
107  else
108  llvm_unreachable("Unrecognized Hexagon processor version");
109 
110  UseHVX128BOps = false;
111  UseHVX64BOps = false;
112  UseLongCalls = false;
113 
115 
116  ParseSubtargetFeatures(CPUString, FS);
117 
118  if (OverrideLongCalls.getPosition())
119  UseLongCalls = OverrideLongCalls;
120 
121  FeatureBitset Features = getFeatureBits();
123  setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
124  setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
125 
126  return *this;
127 }
128 
130  for (SUnit &SU : DAG->SUnits) {
131  if (!SU.isInstr())
132  continue;
133  SmallVector<SDep, 4> Erase;
134  for (auto &D : SU.Preds)
135  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
136  Erase.push_back(D);
137  for (auto &E : Erase)
138  SU.removePred(E);
139  }
140 }
141 
143  for (SUnit &SU : DAG->SUnits) {
144  // Update the latency of chain edges between v60 vector load or store
145  // instructions to be 1. These instruction cannot be scheduled in the
146  // same packet.
147  MachineInstr &MI1 = *SU.getInstr();
148  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
149  bool IsStoreMI1 = MI1.mayStore();
150  bool IsLoadMI1 = MI1.mayLoad();
151  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
152  continue;
153  for (SDep &SI : SU.Succs) {
154  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
155  continue;
156  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
157  if (!QII->isHVXVec(MI2))
158  continue;
159  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
160  SI.setLatency(1);
161  SU.setHeightDirty();
162  // Change the dependence in the opposite direction too.
163  for (SDep &PI : SI.getSUnit()->Preds) {
164  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
165  continue;
166  PI.setLatency(1);
167  SI.getSUnit()->setDepthDirty();
168  }
169  }
170  }
171  }
172 }
173 
174 // Check if a call and subsequent A2_tfrpi instructions should maintain
175 // scheduling affinity. We are looking for the TFRI to be consumed in
176 // the next instruction. This should help reduce the instances of
177 // double register pairs being allocated and scheduled before a call
178 // when not used until after the call. This situation is exacerbated
179 // by the fact that we allocate the pair from the callee saves list,
180 // leading to excess spills and restores.
181 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
182  const HexagonInstrInfo &HII, const SUnit &Inst1,
183  const SUnit &Inst2) const {
184  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
185  return false;
186 
187  // TypeXTYPE are 64 bit operations.
188  unsigned Type = HII.getType(*Inst2.getInstr());
189  return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
190  Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
191 }
192 
194  ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
195  SUnit* LastSequentialCall = nullptr;
196  // Map from virtual register to physical register from the copy.
197  DenseMap<unsigned, unsigned> VRegHoldingReg;
198  // Map from the physical register to the instruction that uses virtual
199  // register. This is used to create the barrier edge.
200  DenseMap<unsigned, SUnit *> LastVRegUse;
201  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
202  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
203 
204  // Currently we only catch the situation when compare gets scheduled
205  // before preceding call.
206  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
207  // Remember the call.
208  if (DAG->SUnits[su].getInstr()->isCall())
209  LastSequentialCall = &DAG->SUnits[su];
210  // Look for a compare that defines a predicate.
211  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
212  DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
213  // Look for call and tfri* instructions.
214  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
215  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
216  DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
217  // Prevent redundant register copies due to reads and writes of physical
218  // registers. The original motivation for this was the code generated
219  // between two calls, which are caused both the return value and the
220  // argument for the next call being in %r0.
221  // Example:
222  // 1: <call1>
223  // 2: %vreg = COPY %r0
224  // 3: <use of %vreg>
225  // 4: %r0 = ...
226  // 5: <call2>
227  // The scheduler would often swap 3 and 4, so an additional register is
228  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
229  // this.
230  // The code below checks for all the physical registers, not just R0/D0/V0.
231  else if (SchedRetvalOptimization) {
232  const MachineInstr *MI = DAG->SUnits[su].getInstr();
233  if (MI->isCopy() &&
235  // %vregX = COPY %r0
236  VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
237  LastVRegUse.erase(MI->getOperand(1).getReg());
238  } else {
239  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
240  const MachineOperand &MO = MI->getOperand(i);
241  if (!MO.isReg())
242  continue;
243  if (MO.isUse() && !MI->isCopy() &&
244  VRegHoldingReg.count(MO.getReg())) {
245  // <use of %vregX>
246  LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
247  } else if (MO.isDef() &&
249  for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
250  ++AI) {
251  if (LastVRegUse.count(*AI) &&
252  LastVRegUse[*AI] != &DAG->SUnits[su])
253  // %r0 = ...
254  DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
255  LastVRegUse.erase(*AI);
256  }
257  }
258  }
259  }
260  }
261  }
262 }
263 
266  return;
267 
268  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
269 
270  // Create artificial edges between loads that could likely cause a bank
271  // conflict. Since such loads would normally not have any dependency
272  // between them, we cannot rely on existing edges.
273  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
274  SUnit &S0 = DAG->SUnits[i];
275  MachineInstr &L0 = *S0.getInstr();
276  if (!L0.mayLoad() || L0.mayStore() ||
278  continue;
279  int Offset0;
280  unsigned Size0;
281  unsigned Base0 = HII.getBaseAndOffset(L0, Offset0, Size0);
282  // Is the access size is longer than the L1 cache line, skip the check.
283  if (Base0 == 0 || Size0 >= 32)
284  continue;
285  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
286  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
287  SUnit &S1 = DAG->SUnits[j];
288  MachineInstr &L1 = *S1.getInstr();
289  if (!L1.mayLoad() || L1.mayStore() ||
291  continue;
292  int Offset1;
293  unsigned Size1;
294  unsigned Base1 = HII.getBaseAndOffset(L1, Offset1, Size1);
295  if (Base1 == 0 || Size1 >= 32 || Base0 != Base1)
296  continue;
297  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
298  // is unlikely.
299  if (((Offset0 ^ Offset1) & 0x18) != 0)
300  continue;
301  // Bits 3 and 4 are the same, add an artificial edge and set extra
302  // latency.
303  SDep A(&S0, SDep::Artificial);
304  A.setLatency(1);
305  S1.addPred(A, true);
306  }
307  }
308 }
309 
310 /// Enable use of alias analysis during code generation (during MI
311 /// scheduling, DAGCombine, etc.).
313  if (OptLevel != CodeGenOpt::None)
314  return true;
315  return false;
316 }
317 
318 /// Perform target specific adjustments to the latency of a schedule
319 /// dependency.
321  SDep &Dep) const {
322  MachineInstr *SrcInst = Src->getInstr();
323  MachineInstr *DstInst = Dst->getInstr();
324  if (!Src->isInstr() || !Dst->isInstr())
325  return;
326 
327  const HexagonInstrInfo *QII = getInstrInfo();
328 
329  // Instructions with .new operands have zero latency.
330  SmallSet<SUnit *, 4> ExclSrc;
331  SmallSet<SUnit *, 4> ExclDst;
332  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
333  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
334  Dep.setLatency(0);
335  return;
336  }
337 
338  if (!hasV60Ops())
339  return;
340 
341  // Set the latency for a copy to zero since we hope that is will get removed.
342  if (DstInst->isCopy())
343  Dep.setLatency(0);
344 
345  // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
346  // the correct latency.
347  if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {
348  unsigned DReg = DstInst->getOperand(0).getReg();
349  MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
350  unsigned UseIdx = -1;
351  for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
352  const MachineOperand &MO = DDst->getOperand(OpNum);
353  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
354  UseIdx = OpNum;
355  break;
356  }
357  }
358  int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
359  0, *DDst, UseIdx));
360  DLatency = std::max(DLatency, 0);
361  Dep.setLatency((unsigned)DLatency);
362  }
363 
364  // Try to schedule uses near definitions to generate .cur.
365  ExclSrc.clear();
366  ExclDst.clear();
367  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
368  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
369  Dep.setLatency(0);
370  return;
371  }
372 
373  updateLatency(*SrcInst, *DstInst, Dep);
374 }
375 
377  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
378  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
379  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
380  Mutations.push_back(llvm::make_unique<BankConflictMutation>());
381 }
382 
384  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
385  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
386  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
387 }
388 
389 // Pin the vtable to this file.
390 void HexagonSubtarget::anchor() {}
391 
393  if (DisableHexagonMISched.getNumOccurrences())
394  return !DisableHexagonMISched;
395  return true;
396 }
397 
399  return EnablePredicatedCalls;
400 }
401 
402 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
403  MachineInstr &DstInst, SDep &Dep) const {
404  if (Dep.isArtificial()) {
405  Dep.setLatency(1);
406  return;
407  }
408 
409  if (!hasV60Ops())
410  return;
411 
412  auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
413 
414  // BSB scheduling.
415  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
416  Dep.setLatency((Dep.getLatency() + 1) >> 1);
417 }
418 
419 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
420  MachineInstr *SrcI = Src->getInstr();
421  for (auto &I : Src->Succs) {
422  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
423  continue;
424  unsigned DepR = I.getReg();
425  int DefIdx = -1;
426  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
427  const MachineOperand &MO = SrcI->getOperand(OpNum);
428  if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
429  DefIdx = OpNum;
430  }
431  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
432  MachineInstr *DstI = Dst->getInstr();
433  SDep T = I;
434  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
435  const MachineOperand &MO = DstI->getOperand(OpNum);
436  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
437  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
438  DefIdx, *DstI, OpNum));
439 
440  // For some instructions (ex: COPY), we might end up with < 0 latency
441  // as they don't have any Itinerary class associated with them.
442  Latency = std::max(Latency, 0);
443 
444  I.setLatency(Latency);
445  updateLatency(*SrcI, *DstI, I);
446  }
447  }
448 
449  // Update the latency of opposite edge too.
450  T.setSUnit(Src);
451  auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
452  assert(F != Dst->Preds.end());
453  F->setLatency(I.getLatency());
454  }
455 }
456 
457 /// Change the latency between the two SUnits.
458 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
459  const {
460  for (auto &I : Src->Succs) {
461  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
462  continue;
463  SDep T = I;
464  I.setLatency(Lat);
465 
466  // Update the latency of opposite edge too.
467  T.setSUnit(Src);
468  auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
469  assert(F != Dst->Preds.end());
470  F->setLatency(Lat);
471  }
472 }
473 
474 /// If the SUnit has a zero latency edge, return the other SUnit.
476  for (auto &I : Deps)
477  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
478  !I.getSUnit()->getInstr()->isPseudo())
479  return I.getSUnit();
480  return nullptr;
481 }
482 
483 // Return true if these are the best two instructions to schedule
484 // together with a zero latency. Only one dependence should have a zero
485 // latency. If there are multiple choices, choose the best, and change
486 // the others, if needed.
487 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
488  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
489  SmallSet<SUnit*, 4> &ExclDst) const {
490  MachineInstr &SrcInst = *Src->getInstr();
491  MachineInstr &DstInst = *Dst->getInstr();
492 
493  // Ignore Boundary SU nodes as these have null instructions.
494  if (Dst->isBoundaryNode())
495  return false;
496 
497  if (SrcInst.isPHI() || DstInst.isPHI())
498  return false;
499 
500  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
501  !TII->canExecuteInBundle(SrcInst, DstInst))
502  return false;
503 
504  // The architecture doesn't allow three dependent instructions in the same
505  // packet. So, if the destination has a zero latency successor, then it's
506  // not a candidate for a zero latency predecessor.
507  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
508  return false;
509 
510  // Check if the Dst instruction is the best candidate first.
511  SUnit *Best = nullptr;
512  SUnit *DstBest = nullptr;
513  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
514  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
515  // Check that Src doesn't have a better candidate.
516  DstBest = getZeroLatency(Src, Src->Succs);
517  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
518  Best = Dst;
519  }
520  if (Best != Dst)
521  return false;
522 
523  // The caller frequently adds the same dependence twice. If so, then
524  // return true for this case too.
525  if ((Src == SrcBest && Dst == DstBest ) ||
526  (SrcBest == nullptr && Dst == DstBest) ||
527  (Src == SrcBest && Dst == nullptr))
528  return true;
529 
530  // Reassign the latency for the previous bests, which requires setting
531  // the dependence edge in both directions.
532  if (SrcBest != nullptr) {
533  if (!hasV60Ops())
534  changeLatency(SrcBest, Dst, 1);
535  else
536  restoreLatency(SrcBest, Dst);
537  }
538  if (DstBest != nullptr) {
539  if (!hasV60Ops())
540  changeLatency(Src, DstBest, 1);
541  else
542  restoreLatency(Src, DstBest);
543  }
544 
545  // Attempt to find another opprotunity for zero latency in a different
546  // dependence.
547  if (SrcBest && DstBest)
548  // If there is an edge from SrcBest to DstBst, then try to change that
549  // to 0 now.
550  changeLatency(SrcBest, DstBest, 0);
551  else if (DstBest) {
552  // Check if the previous best destination instruction has a new zero
553  // latency dependence opportunity.
554  ExclSrc.insert(Src);
555  for (auto &I : DstBest->Preds)
556  if (ExclSrc.count(I.getSUnit()) == 0 &&
557  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
558  changeLatency(I.getSUnit(), DstBest, 0);
559  } else if (SrcBest) {
560  // Check if previous best source instruction has a new zero latency
561  // dependence opportunity.
562  ExclDst.insert(Dst);
563  for (auto &I : SrcBest->Succs)
564  if (ExclDst.count(I.getSUnit()) == 0 &&
565  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
566  changeLatency(SrcBest, I.getSUnit(), 0);
567  }
568 
569  return true;
570 }
571 
573  return 32;
574 }
575 
577  return 32;
578 }
579 
581  return EnableSubregLiveness;
582 }
void apply(ScheduleDAGInstrs *DAG) override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getReg() const
getReg - Returns the register number.
Hexagon::ArchEnum HexagonArchVersion
bool isRegSequence() const
void setSUnit(SUnit *SU)
Definition: ScheduleDAG.h:487
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
unsigned const TargetRegisterInfo * TRI
F(f)
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
bool isPHI() const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:260
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:564
unsigned NumSuccs
of SDep::Data sucss.
Definition: ScheduleDAG.h:271
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:143
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
const InstrItinerary * Itineraries
Array of itineraries selected.
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:56
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
void clear()
Definition: SmallSet.h:219
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
#define T
SUnit * getSUnit() const
Definition: ScheduleDAG.h:484
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
Definition: ScheduleDAG.h:348
StringRef selectHexagonCPU(StringRef CPU)
Scheduling dependency.
Definition: ScheduleDAG.h:50
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
void setDepthDirty()
Sets a flag in this node to indicate that its stored Depth value will require recomputation the next ...
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:377
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn&#39;t necessary for c...
Definition: ScheduleDAG.h:201
Container class for subtarget features.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void apply(ScheduleDAGInstrs *DAG) override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
CodeGenOpt::Level OptLevel
unsigned getAddrMode(const MachineInstr &MI) const
void apply(ScheduleDAGInstrs *DAG) override
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
void apply(ScheduleDAGInstrs *DAG) override
MCRegAliasIterator enumerates all registers aliasing Reg.
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Consider calls to be predicable"))
bool isCopy() const
Any other ordering dependency.
Definition: ScheduleDAG.h:57
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1063
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true))
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
An unknown scheduling barrier.
Definition: ScheduleDAG.h:70
bool enableMachineScheduler() const override
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::ZeroOrMore, cl::init(true))
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
uint64_t getType(const MachineInstr &MI) const
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:148
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:562
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:490
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:141
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:268
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
const HexagonInstrInfo * getInstrInfo() const override
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:261
const FeatureBitset Features
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:73
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:566
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:366
cl::opt< bool > HexagonDisableDuplex
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:246
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165