LLVM  11.0.0git
HexagonSubtarget.cpp
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1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Hexagon.h"
14 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <map>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "hexagon-subtarget"
36 
37 #define GET_SUBTARGETINFO_CTOR
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #include "HexagonGenSubtargetInfo.inc"
40 
41 
42 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
44 
45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
47 
48 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
50  cl::desc("Enable the scheduler to generate .cur"));
51 
52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
54  cl::desc("Disable Hexagon MI Scheduling"));
55 
56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
58  cl::desc("Enable subregister liveness tracking for Hexagon"));
59 
60 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
62  cl::desc("If present, forces/disables the use of long calls"));
63 
64 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
66  cl::desc("Consider calls to be predicable"));
67 
68 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
70 
71 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
73 
74 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
76  cl::desc("Enable checking for cache bank conflicts"));
77 
79  StringRef FS, const TargetMachine &TM)
80  : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
81  CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
82  TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
83  RegInfo(getHwMode()), TLInfo(TM, *this),
84  InstrItins(getInstrItineraryForCPU(CPUString)) {
86  // Beware of the default constructor of InstrItineraryData: it will
87  // reset all members to 0.
88  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
89 }
90 
95  if (ArchVer)
96  HexagonArchVersion = *ArchVer;
97  else
98  llvm_unreachable("Unrecognized Hexagon processor version");
99 
100  UseHVX128BOps = false;
101  UseHVX64BOps = false;
102  UseAudioOps = false;
103  UseLongCalls = false;
104 
106 
107  ParseSubtargetFeatures(CPUString, FS);
108 
109  if (OverrideLongCalls.getPosition())
110  UseLongCalls = OverrideLongCalls;
111 
112  if (isTinyCore()) {
113  // Tiny core has a single thread, so back-to-back scheduling is enabled by
114  // default.
115  if (!EnableBSBSched.getPosition())
116  UseBSBScheduling = false;
117  }
118 
119  FeatureBitset Features = getFeatureBits();
121  setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
122  setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
123 
124  return *this;
125 }
126 
128  for (SUnit &SU : DAG->SUnits) {
129  if (!SU.isInstr())
130  continue;
131  SmallVector<SDep, 4> Erase;
132  for (auto &D : SU.Preds)
133  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
134  Erase.push_back(D);
135  for (auto &E : Erase)
136  SU.removePred(E);
137  }
138 }
139 
141  for (SUnit &SU : DAG->SUnits) {
142  // Update the latency of chain edges between v60 vector load or store
143  // instructions to be 1. These instruction cannot be scheduled in the
144  // same packet.
145  MachineInstr &MI1 = *SU.getInstr();
146  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
147  bool IsStoreMI1 = MI1.mayStore();
148  bool IsLoadMI1 = MI1.mayLoad();
149  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
150  continue;
151  for (SDep &SI : SU.Succs) {
152  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
153  continue;
154  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
155  if (!QII->isHVXVec(MI2))
156  continue;
157  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
158  SI.setLatency(1);
159  SU.setHeightDirty();
160  // Change the dependence in the opposite direction too.
161  for (SDep &PI : SI.getSUnit()->Preds) {
162  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
163  continue;
164  PI.setLatency(1);
165  SI.getSUnit()->setDepthDirty();
166  }
167  }
168  }
169  }
170 }
171 
172 // Check if a call and subsequent A2_tfrpi instructions should maintain
173 // scheduling affinity. We are looking for the TFRI to be consumed in
174 // the next instruction. This should help reduce the instances of
175 // double register pairs being allocated and scheduled before a call
176 // when not used until after the call. This situation is exacerbated
177 // by the fact that we allocate the pair from the callee saves list,
178 // leading to excess spills and restores.
179 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
180  const HexagonInstrInfo &HII, const SUnit &Inst1,
181  const SUnit &Inst2) const {
182  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
183  return false;
184 
185  // TypeXTYPE are 64 bit operations.
186  unsigned Type = HII.getType(*Inst2.getInstr());
187  return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
188  Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
189 }
190 
192  ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
193  SUnit* LastSequentialCall = nullptr;
194  // Map from virtual register to physical register from the copy.
195  DenseMap<unsigned, unsigned> VRegHoldingReg;
196  // Map from the physical register to the instruction that uses virtual
197  // register. This is used to create the barrier edge.
198  DenseMap<unsigned, SUnit *> LastVRegUse;
199  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
200  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
201 
202  // Currently we only catch the situation when compare gets scheduled
203  // before preceding call.
204  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
205  // Remember the call.
206  if (DAG->SUnits[su].getInstr()->isCall())
207  LastSequentialCall = &DAG->SUnits[su];
208  // Look for a compare that defines a predicate.
209  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
210  DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
211  // Look for call and tfri* instructions.
212  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
213  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
214  DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
215  // Prevent redundant register copies due to reads and writes of physical
216  // registers. The original motivation for this was the code generated
217  // between two calls, which are caused both the return value and the
218  // argument for the next call being in %r0.
219  // Example:
220  // 1: <call1>
221  // 2: %vreg = COPY %r0
222  // 3: <use of %vreg>
223  // 4: %r0 = ...
224  // 5: <call2>
225  // The scheduler would often swap 3 and 4, so an additional register is
226  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
227  // this.
228  // The code below checks for all the physical registers, not just R0/D0/V0.
229  else if (SchedRetvalOptimization) {
230  const MachineInstr *MI = DAG->SUnits[su].getInstr();
231  if (MI->isCopy() &&
233  // %vregX = COPY %r0
234  VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
235  LastVRegUse.erase(MI->getOperand(1).getReg());
236  } else {
237  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238  const MachineOperand &MO = MI->getOperand(i);
239  if (!MO.isReg())
240  continue;
241  if (MO.isUse() && !MI->isCopy() &&
242  VRegHoldingReg.count(MO.getReg())) {
243  // <use of %vregX>
244  LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
245  } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
246  for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
247  ++AI) {
248  if (LastVRegUse.count(*AI) &&
249  LastVRegUse[*AI] != &DAG->SUnits[su])
250  // %r0 = ...
251  DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
252  LastVRegUse.erase(*AI);
253  }
254  }
255  }
256  }
257  }
258  }
259 }
260 
263  return;
264 
265  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
266 
267  // Create artificial edges between loads that could likely cause a bank
268  // conflict. Since such loads would normally not have any dependency
269  // between them, we cannot rely on existing edges.
270  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
271  SUnit &S0 = DAG->SUnits[i];
272  MachineInstr &L0 = *S0.getInstr();
273  if (!L0.mayLoad() || L0.mayStore() ||
275  continue;
276  int64_t Offset0;
277  unsigned Size0;
278  MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
279  // Is the access size is longer than the L1 cache line, skip the check.
280  if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
281  continue;
282  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
283  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
284  SUnit &S1 = DAG->SUnits[j];
285  MachineInstr &L1 = *S1.getInstr();
286  if (!L1.mayLoad() || L1.mayStore() ||
288  continue;
289  int64_t Offset1;
290  unsigned Size1;
291  MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
292  if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
293  BaseOp0->getReg() != BaseOp1->getReg())
294  continue;
295  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
296  // is unlikely.
297  if (((Offset0 ^ Offset1) & 0x18) != 0)
298  continue;
299  // Bits 3 and 4 are the same, add an artificial edge and set extra
300  // latency.
301  SDep A(&S0, SDep::Artificial);
302  A.setLatency(1);
303  S1.addPred(A, true);
304  }
305  }
306 }
307 
308 /// Enable use of alias analysis during code generation (during MI
309 /// scheduling, DAGCombine, etc.).
311  if (OptLevel != CodeGenOpt::None)
312  return true;
313  return false;
314 }
315 
316 /// Perform target specific adjustments to the latency of a schedule
317 /// dependency.
319  SUnit *Dst, int DstOpIdx,
320  SDep &Dep) const {
321  if (!Src->isInstr() || !Dst->isInstr())
322  return;
323 
324  MachineInstr *SrcInst = Src->getInstr();
325  MachineInstr *DstInst = Dst->getInstr();
326  const HexagonInstrInfo *QII = getInstrInfo();
327 
328  // Instructions with .new operands have zero latency.
329  SmallSet<SUnit *, 4> ExclSrc;
330  SmallSet<SUnit *, 4> ExclDst;
331  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
332  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
333  Dep.setLatency(0);
334  return;
335  }
336 
337  if (!hasV60Ops())
338  return;
339 
340  // Set the latency for a copy to zero since we hope that is will get removed.
341  if (DstInst->isCopy())
342  Dep.setLatency(0);
343 
344  // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
345  // the correct latency.
346  if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {
347  Register DReg = DstInst->getOperand(0).getReg();
348  MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
349  unsigned UseIdx = -1;
350  for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
351  const MachineOperand &MO = DDst->getOperand(OpNum);
352  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
353  UseIdx = OpNum;
354  break;
355  }
356  }
357  int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
358  0, *DDst, UseIdx));
359  DLatency = std::max(DLatency, 0);
360  Dep.setLatency((unsigned)DLatency);
361  }
362 
363  // Try to schedule uses near definitions to generate .cur.
364  ExclSrc.clear();
365  ExclDst.clear();
366  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
367  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
368  Dep.setLatency(0);
369  return;
370  }
371 
372  updateLatency(*SrcInst, *DstInst, Dep);
373 }
374 
376  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
377  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
378  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
379  Mutations.push_back(std::make_unique<BankConflictMutation>());
380 }
381 
383  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
384  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
385  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
386 }
387 
388 // Pin the vtable to this file.
389 void HexagonSubtarget::anchor() {}
390 
392  if (DisableHexagonMISched.getNumOccurrences())
393  return !DisableHexagonMISched;
394  return true;
395 }
396 
398  return EnablePredicatedCalls;
399 }
400 
401 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
402  MachineInstr &DstInst, SDep &Dep) const {
403  if (Dep.isArtificial()) {
404  Dep.setLatency(1);
405  return;
406  }
407 
408  if (!hasV60Ops())
409  return;
410 
411  auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
412 
413  // BSB scheduling.
414  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
415  Dep.setLatency((Dep.getLatency() + 1) >> 1);
416 }
417 
418 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
419  MachineInstr *SrcI = Src->getInstr();
420  for (auto &I : Src->Succs) {
421  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
422  continue;
423  unsigned DepR = I.getReg();
424  int DefIdx = -1;
425  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
426  const MachineOperand &MO = SrcI->getOperand(OpNum);
427  bool IsSameOrSubReg = false;
428  if (MO.isReg()) {
429  unsigned MOReg = MO.getReg();
430  if (Register::isVirtualRegister(DepR)) {
431  IsSameOrSubReg = (MOReg == DepR);
432  } else {
433  IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
434  }
435  if (MO.isDef() && IsSameOrSubReg)
436  DefIdx = OpNum;
437  }
438  }
439  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
440  MachineInstr *DstI = Dst->getInstr();
441  SDep T = I;
442  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
443  const MachineOperand &MO = DstI->getOperand(OpNum);
444  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
445  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
446  DefIdx, *DstI, OpNum));
447 
448  // For some instructions (ex: COPY), we might end up with < 0 latency
449  // as they don't have any Itinerary class associated with them.
450  Latency = std::max(Latency, 0);
451 
452  I.setLatency(Latency);
453  updateLatency(*SrcI, *DstI, I);
454  }
455  }
456 
457  // Update the latency of opposite edge too.
458  T.setSUnit(Src);
459  auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
460  assert(F != Dst->Preds.end());
461  F->setLatency(I.getLatency());
462  }
463 }
464 
465 /// Change the latency between the two SUnits.
466 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
467  const {
468  for (auto &I : Src->Succs) {
469  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
470  continue;
471  SDep T = I;
472  I.setLatency(Lat);
473 
474  // Update the latency of opposite edge too.
475  T.setSUnit(Src);
476  auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
477  assert(F != Dst->Preds.end());
478  F->setLatency(Lat);
479  }
480 }
481 
482 /// If the SUnit has a zero latency edge, return the other SUnit.
484  for (auto &I : Deps)
485  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
486  !I.getSUnit()->getInstr()->isPseudo())
487  return I.getSUnit();
488  return nullptr;
489 }
490 
491 // Return true if these are the best two instructions to schedule
492 // together with a zero latency. Only one dependence should have a zero
493 // latency. If there are multiple choices, choose the best, and change
494 // the others, if needed.
495 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
496  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
497  SmallSet<SUnit*, 4> &ExclDst) const {
498  MachineInstr &SrcInst = *Src->getInstr();
499  MachineInstr &DstInst = *Dst->getInstr();
500 
501  // Ignore Boundary SU nodes as these have null instructions.
502  if (Dst->isBoundaryNode())
503  return false;
504 
505  if (SrcInst.isPHI() || DstInst.isPHI())
506  return false;
507 
508  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
509  !TII->canExecuteInBundle(SrcInst, DstInst))
510  return false;
511 
512  // The architecture doesn't allow three dependent instructions in the same
513  // packet. So, if the destination has a zero latency successor, then it's
514  // not a candidate for a zero latency predecessor.
515  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
516  return false;
517 
518  // Check if the Dst instruction is the best candidate first.
519  SUnit *Best = nullptr;
520  SUnit *DstBest = nullptr;
521  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
522  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
523  // Check that Src doesn't have a better candidate.
524  DstBest = getZeroLatency(Src, Src->Succs);
525  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
526  Best = Dst;
527  }
528  if (Best != Dst)
529  return false;
530 
531  // The caller frequently adds the same dependence twice. If so, then
532  // return true for this case too.
533  if ((Src == SrcBest && Dst == DstBest ) ||
534  (SrcBest == nullptr && Dst == DstBest) ||
535  (Src == SrcBest && Dst == nullptr))
536  return true;
537 
538  // Reassign the latency for the previous bests, which requires setting
539  // the dependence edge in both directions.
540  if (SrcBest != nullptr) {
541  if (!hasV60Ops())
542  changeLatency(SrcBest, Dst, 1);
543  else
544  restoreLatency(SrcBest, Dst);
545  }
546  if (DstBest != nullptr) {
547  if (!hasV60Ops())
548  changeLatency(Src, DstBest, 1);
549  else
550  restoreLatency(Src, DstBest);
551  }
552 
553  // Attempt to find another opprotunity for zero latency in a different
554  // dependence.
555  if (SrcBest && DstBest)
556  // If there is an edge from SrcBest to DstBst, then try to change that
557  // to 0 now.
558  changeLatency(SrcBest, DstBest, 0);
559  else if (DstBest) {
560  // Check if the previous best destination instruction has a new zero
561  // latency dependence opportunity.
562  ExclSrc.insert(Src);
563  for (auto &I : DstBest->Preds)
564  if (ExclSrc.count(I.getSUnit()) == 0 &&
565  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
566  changeLatency(I.getSUnit(), DstBest, 0);
567  } else if (SrcBest) {
568  // Check if previous best source instruction has a new zero latency
569  // dependence opportunity.
570  ExclDst.insert(Dst);
571  for (auto &I : SrcBest->Succs)
572  if (ExclDst.count(I.getSUnit()) == 0 &&
573  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
574  changeLatency(SrcBest, I.getSUnit(), 0);
575  }
576 
577  return true;
578 }
579 
581  return 32;
582 }
583 
585  return 32;
586 }
587 
589  return EnableSubregLiveness;
590 }
void apply(ScheduleDAGInstrs *DAG) override
llvm::Optional< ArchEnum > GetCpu(ArchCont const &ArchList, Val CPUString)
Definition: HexagonArch.h:28
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
DEBUG_TYPE to vector
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Hexagon::ArchEnum HexagonArchVersion
bool isRegSequence() const
void setSUnit(SUnit *SU)
Definition: ScheduleDAG.h:483
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
unsigned const TargetRegisterInfo * TRI
F(f)
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
bool isPHI() const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
Definition: BitVector.h:959
unsigned NumSuccs
of SDep::Data sucss.
Definition: ScheduleDAG.h:267
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:435
const InstrItinerary * Itineraries
Array of itineraries selected.
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
const HexagonRegisterInfo * getRegisterInfo() const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:432
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
void clear()
Definition: SmallSet.h:218
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
Definition: ScheduleDAG.h:344
StringRef selectHexagonCPU(StringRef CPU)
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
Scheduling dependency.
Definition: ScheduleDAG.h:49
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:883
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:434
void setDepthDirty()
Sets a flag in this node to indicate that its stored Depth value will require recomputation the next ...
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn&#39;t necessary for c...
Definition: ScheduleDAG.h:200
Container class for subtarget features.
static const std::map< std::string, ArchEnum > CpuTable
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void apply(ScheduleDAGInstrs *DAG) override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
CodeGenOpt::Level OptLevel
unsigned getAddrMode(const MachineInstr &MI) const
void apply(ScheduleDAGInstrs *DAG) override
void apply(ScheduleDAGInstrs *DAG) override
MCRegAliasIterator enumerates all registers aliasing Reg.
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
constexpr double e
Definition: MathExtras.h:58
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Consider calls to be predicable"))
bool isCopy() const
Any other ordering dependency.
Definition: ScheduleDAG.h:56
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true))
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
An unknown scheduling barrier.
Definition: ScheduleDAG.h:69
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
bool enableMachineScheduler() const override
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::ZeroOrMore, cl::init(true))
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:883
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1503
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
uint64_t getType(const MachineInstr &MI) const
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool enableSubRegLiveness() const override
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:62
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
constexpr FeatureBitset & reset(unsigned I)
#define I(x, y, z)
Definition: MD5.cpp:59
#define N
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:486
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:264
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:870
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
const HexagonInstrInfo * getInstrInfo() const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:72
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
Register getReg() const
getReg - Returns the register number.
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:437
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
cl::opt< bool > HexagonDisableDuplex
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164