LLVM  7.0.0svn
HexagonSubtarget.cpp
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1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <map>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "hexagon-subtarget"
36 
37 #define GET_SUBTARGETINFO_CTOR
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #include "HexagonGenSubtargetInfo.inc"
40 
41 static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
43  cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
44 
45 static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
47  cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
48 
49 static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
51  cl::desc("Generate non-chopped conversion from fp to int."));
52 
53 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
55 
56 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
58 
59 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
61  cl::desc("Enable the scheduler to generate .cur"));
62 
63 static cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched",
65 
66 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
68  cl::desc("Disable Hexagon MI Scheduling"));
69 
70 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
72  cl::desc("Enable subregister liveness tracking for Hexagon"));
73 
74 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
76  cl::desc("If present, forces/disables the use of long calls"));
77 
78 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
80  cl::desc("Consider calls to be predicable"));
81 
82 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
84 
85 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
87 
88 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
90  cl::desc("Enable checking for cache bank conflicts"));
91 
92 
94  StringRef FS, const TargetMachine &TM)
95  : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
96  CPUString(Hexagon_MC::selectHexagonCPU(CPU)),
97  InstrInfo(initializeSubtargetDependencies(CPU, FS)),
98  RegInfo(getHwMode()), TLInfo(TM, *this),
99  InstrItins(getInstrItineraryForCPU(CPUString)) {
100  // Beware of the default constructor of InstrItineraryData: it will
101  // reset all members to 0.
102  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
103 }
104 
107  static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
108  {"hexagonv4", Hexagon::ArchEnum::V4},
109  {"hexagonv5", Hexagon::ArchEnum::V5},
110  {"hexagonv55", Hexagon::ArchEnum::V55},
111  {"hexagonv60", Hexagon::ArchEnum::V60},
112  {"hexagonv62", Hexagon::ArchEnum::V62},
113  {"hexagonv65", Hexagon::ArchEnum::V65},
114  };
115 
116  auto FoundIt = CpuTable.find(CPUString);
117  if (FoundIt != CpuTable.end())
118  HexagonArchVersion = FoundIt->second;
119  else
120  llvm_unreachable("Unrecognized Hexagon processor version");
121 
122  UseHVX128BOps = false;
123  UseHVX64BOps = false;
124  UseLongCalls = false;
125 
126  UseMemOps = DisableMemOps ? false : EnableMemOps;
127  ModeIEEERndNear = EnableIEEERndNear;
129 
130  ParseSubtargetFeatures(CPUString, FS);
131 
132  if (OverrideLongCalls.getPosition())
133  UseLongCalls = OverrideLongCalls;
134 
135  FeatureBitset Features = getFeatureBits();
137  setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
138  setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
139 
140  return *this;
141 }
142 
144  for (SUnit &SU : DAG->SUnits) {
145  if (!SU.isInstr())
146  continue;
147  SmallVector<SDep, 4> Erase;
148  for (auto &D : SU.Preds)
149  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
150  Erase.push_back(D);
151  for (auto &E : Erase)
152  SU.removePred(E);
153  }
154 }
155 
157  for (SUnit &SU : DAG->SUnits) {
158  // Update the latency of chain edges between v60 vector load or store
159  // instructions to be 1. These instruction cannot be scheduled in the
160  // same packet.
161  MachineInstr &MI1 = *SU.getInstr();
162  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
163  bool IsStoreMI1 = MI1.mayStore();
164  bool IsLoadMI1 = MI1.mayLoad();
165  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
166  continue;
167  for (SDep &SI : SU.Succs) {
168  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
169  continue;
170  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
171  if (!QII->isHVXVec(MI2))
172  continue;
173  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
174  SI.setLatency(1);
175  SU.setHeightDirty();
176  // Change the dependence in the opposite direction too.
177  for (SDep &PI : SI.getSUnit()->Preds) {
178  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
179  continue;
180  PI.setLatency(1);
181  SI.getSUnit()->setDepthDirty();
182  }
183  }
184  }
185  }
186 }
187 
188 // Check if a call and subsequent A2_tfrpi instructions should maintain
189 // scheduling affinity. We are looking for the TFRI to be consumed in
190 // the next instruction. This should help reduce the instances of
191 // double register pairs being allocated and scheduled before a call
192 // when not used until after the call. This situation is exacerbated
193 // by the fact that we allocate the pair from the callee saves list,
194 // leading to excess spills and restores.
195 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
196  const HexagonInstrInfo &HII, const SUnit &Inst1,
197  const SUnit &Inst2) const {
198  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
199  return false;
200 
201  // TypeXTYPE are 64 bit operations.
202  unsigned Type = HII.getType(*Inst2.getInstr());
203  return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
204  Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
205 }
206 
208  SUnit* LastSequentialCall = nullptr;
209  unsigned VRegHoldingRet = 0;
210  unsigned RetRegister;
211  SUnit* LastUseOfRet = nullptr;
212  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
213  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
214 
215  // Currently we only catch the situation when compare gets scheduled
216  // before preceding call.
217  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
218  // Remember the call.
219  if (DAG->SUnits[su].getInstr()->isCall())
220  LastSequentialCall = &DAG->SUnits[su];
221  // Look for a compare that defines a predicate.
222  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
223  DAG->SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
224  // Look for call and tfri* instructions.
225  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
226  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
227  DAG->SUnits[su].addPred(SDep(&DAG->SUnits[su-1], SDep::Barrier));
228  // Prevent redundant register copies between two calls, which are caused by
229  // both the return value and the argument for the next call being in %r0.
230  // Example:
231  // 1: <call1>
232  // 2: %vreg = COPY %r0
233  // 3: <use of %vreg>
234  // 4: %r0 = ...
235  // 5: <call2>
236  // The scheduler would often swap 3 and 4, so an additional register is
237  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
238  // this. The same applies for %d0 and %v0/%w0, which are also handled.
239  else if (SchedRetvalOptimization) {
240  const MachineInstr *MI = DAG->SUnits[su].getInstr();
241  if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) ||
242  MI->readsRegister(Hexagon::V0, &TRI))) {
243  // %vreg = COPY %r0
244  VRegHoldingRet = MI->getOperand(0).getReg();
245  RetRegister = MI->getOperand(1).getReg();
246  LastUseOfRet = nullptr;
247  } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet))
248  // <use of %X>
249  LastUseOfRet = &DAG->SUnits[su];
250  else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI))
251  // %r0 = ...
252  DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier));
253  }
254  }
255 }
256 
259  return;
260 
261  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
262 
263  // Create artificial edges between loads that could likely cause a bank
264  // conflict. Since such loads would normally not have any dependency
265  // between them, we cannot rely on existing edges.
266  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
267  SUnit &S0 = DAG->SUnits[i];
268  MachineInstr &L0 = *S0.getInstr();
269  if (!L0.mayLoad() || L0.mayStore() ||
271  continue;
272  int Offset0;
273  unsigned Size0;
274  unsigned Base0 = HII.getBaseAndOffset(L0, Offset0, Size0);
275  // Is the access size is longer than the L1 cache line, skip the check.
276  if (Base0 == 0 || Size0 >= 32)
277  continue;
278  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
279  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
280  SUnit &S1 = DAG->SUnits[j];
281  MachineInstr &L1 = *S1.getInstr();
282  if (!L1.mayLoad() || L1.mayStore() ||
284  continue;
285  int Offset1;
286  unsigned Size1;
287  unsigned Base1 = HII.getBaseAndOffset(L1, Offset1, Size1);
288  if (Base1 == 0 || Size1 >= 32 || Base0 != Base1)
289  continue;
290  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
291  // is unlikely.
292  if (((Offset0 ^ Offset1) & 0x18) != 0)
293  continue;
294  // Bits 3 and 4 are the same, add an artificial edge and set extra
295  // latency.
296  SDep A(&S0, SDep::Artificial);
297  A.setLatency(1);
298  S1.addPred(A, true);
299  }
300  }
301 }
302 
303 /// \brief Enable use of alias analysis during code generation (during MI
304 /// scheduling, DAGCombine, etc.).
306  if (OptLevel != CodeGenOpt::None)
307  return true;
308  return false;
309 }
310 
311 /// \brief Perform target specific adjustments to the latency of a schedule
312 /// dependency.
314  SDep &Dep) const {
315  MachineInstr *SrcInst = Src->getInstr();
316  MachineInstr *DstInst = Dst->getInstr();
317  if (!Src->isInstr() || !Dst->isInstr())
318  return;
319 
320  const HexagonInstrInfo *QII = getInstrInfo();
321 
322  // Instructions with .new operands have zero latency.
323  SmallSet<SUnit *, 4> ExclSrc;
324  SmallSet<SUnit *, 4> ExclDst;
325  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
326  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
327  Dep.setLatency(0);
328  return;
329  }
330 
331  if (!hasV60TOps())
332  return;
333 
334  // If it's a REG_SEQUENCE, use its destination instruction to determine
335  // the correct latency.
336  if (DstInst->isRegSequence() && Dst->NumSuccs == 1) {
337  unsigned RSeqReg = DstInst->getOperand(0).getReg();
338  MachineInstr *RSeqDst = Dst->Succs[0].getSUnit()->getInstr();
339  unsigned UseIdx = -1;
340  for (unsigned OpNum = 0; OpNum < RSeqDst->getNumOperands(); OpNum++) {
341  const MachineOperand &MO = RSeqDst->getOperand(OpNum);
342  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == RSeqReg) {
343  UseIdx = OpNum;
344  break;
345  }
346  }
347  unsigned RSeqLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
348  0, *RSeqDst, UseIdx));
349  Dep.setLatency(RSeqLatency);
350  }
351 
352  // Try to schedule uses near definitions to generate .cur.
353  ExclSrc.clear();
354  ExclDst.clear();
355  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
356  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
357  Dep.setLatency(0);
358  return;
359  }
360 
361  updateLatency(*SrcInst, *DstInst, Dep);
362 }
363 
365  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
366  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
367  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
368  Mutations.push_back(llvm::make_unique<BankConflictMutation>());
369 }
370 
372  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
373  Mutations.push_back(llvm::make_unique<UsrOverflowMutation>());
374  Mutations.push_back(llvm::make_unique<HVXMemLatencyMutation>());
375 }
376 
377 // Pin the vtable to this file.
378 void HexagonSubtarget::anchor() {}
379 
381  if (DisableHexagonMISched.getNumOccurrences())
382  return !DisableHexagonMISched;
383  return true;
384 }
385 
387  return EnablePredicatedCalls;
388 }
389 
390 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
391  MachineInstr &DstInst, SDep &Dep) const {
392  if (Dep.isArtificial()) {
393  Dep.setLatency(1);
394  return;
395  }
396 
397  if (!hasV60TOps())
398  return;
399 
400  auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
401 
402  // BSB scheduling.
403  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
404  Dep.setLatency((Dep.getLatency() + 1) >> 1);
405 }
406 
407 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
408  MachineInstr *SrcI = Src->getInstr();
409  for (auto &I : Src->Succs) {
410  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
411  continue;
412  unsigned DepR = I.getReg();
413  int DefIdx = -1;
414  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
415  const MachineOperand &MO = SrcI->getOperand(OpNum);
416  if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
417  DefIdx = OpNum;
418  }
419  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
420  MachineInstr *DstI = Dst->getInstr();
421  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
422  const MachineOperand &MO = DstI->getOperand(OpNum);
423  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
424  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
425  DefIdx, *DstI, OpNum));
426 
427  // For some instructions (ex: COPY), we might end up with < 0 latency
428  // as they don't have any Itinerary class associated with them.
429  if (Latency <= 0)
430  Latency = 1;
431 
432  I.setLatency(Latency);
433  updateLatency(*SrcI, *DstI, I);
434  }
435  }
436 
437  // Update the latency of opposite edge too.
438  for (auto &J : Dst->Preds) {
439  if (J.getSUnit() != Src)
440  continue;
441  J.setLatency(I.getLatency());
442  }
443  }
444 }
445 
446 /// Change the latency between the two SUnits.
447 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
448  const {
449  for (auto &I : Src->Succs) {
450  if (I.getSUnit() != Dst)
451  continue;
452  SDep T = I;
453  I.setLatency(Lat);
454 
455  // Update the latency of opposite edge too.
456  T.setSUnit(Src);
457  auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
458  assert(F != Dst->Preds.end());
459  F->setLatency(I.getLatency());
460  }
461 }
462 
463 /// If the SUnit has a zero latency edge, return the other SUnit.
465  for (auto &I : Deps)
466  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
467  !I.getSUnit()->getInstr()->isPseudo())
468  return I.getSUnit();
469  return nullptr;
470 }
471 
472 // Return true if these are the best two instructions to schedule
473 // together with a zero latency. Only one dependence should have a zero
474 // latency. If there are multiple choices, choose the best, and change
475 // the others, if needed.
476 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
477  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
478  SmallSet<SUnit*, 4> &ExclDst) const {
479  MachineInstr &SrcInst = *Src->getInstr();
480  MachineInstr &DstInst = *Dst->getInstr();
481 
482  // Ignore Boundary SU nodes as these have null instructions.
483  if (Dst->isBoundaryNode())
484  return false;
485 
486  if (SrcInst.isPHI() || DstInst.isPHI())
487  return false;
488 
489  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
490  !TII->canExecuteInBundle(SrcInst, DstInst))
491  return false;
492 
493  // The architecture doesn't allow three dependent instructions in the same
494  // packet. So, if the destination has a zero latency successor, then it's
495  // not a candidate for a zero latency predecessor.
496  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
497  return false;
498 
499  // Check if the Dst instruction is the best candidate first.
500  SUnit *Best = nullptr;
501  SUnit *DstBest = nullptr;
502  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
503  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
504  // Check that Src doesn't have a better candidate.
505  DstBest = getZeroLatency(Src, Src->Succs);
506  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
507  Best = Dst;
508  }
509  if (Best != Dst)
510  return false;
511 
512  // The caller frequently adds the same dependence twice. If so, then
513  // return true for this case too.
514  if ((Src == SrcBest && Dst == DstBest ) ||
515  (SrcBest == nullptr && Dst == DstBest) ||
516  (Src == SrcBest && Dst == nullptr))
517  return true;
518 
519  // Reassign the latency for the previous bests, which requires setting
520  // the dependence edge in both directions.
521  if (SrcBest != nullptr) {
522  if (!hasV60TOps())
523  changeLatency(SrcBest, Dst, 1);
524  else
525  restoreLatency(SrcBest, Dst);
526  }
527  if (DstBest != nullptr) {
528  if (!hasV60TOps())
529  changeLatency(Src, DstBest, 1);
530  else
531  restoreLatency(Src, DstBest);
532  }
533 
534  // Attempt to find another opprotunity for zero latency in a different
535  // dependence.
536  if (SrcBest && DstBest)
537  // If there is an edge from SrcBest to DstBst, then try to change that
538  // to 0 now.
539  changeLatency(SrcBest, DstBest, 0);
540  else if (DstBest) {
541  // Check if the previous best destination instruction has a new zero
542  // latency dependence opportunity.
543  ExclSrc.insert(Src);
544  for (auto &I : DstBest->Preds)
545  if (ExclSrc.count(I.getSUnit()) == 0 &&
546  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
547  changeLatency(I.getSUnit(), DstBest, 0);
548  } else if (SrcBest) {
549  // Check if previous best source instruction has a new zero latency
550  // dependence opportunity.
551  ExclDst.insert(Dst);
552  for (auto &I : SrcBest->Succs)
553  if (ExclDst.count(I.getSUnit()) == 0 &&
554  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
555  changeLatency(SrcBest, I.getSUnit(), 0);
556  }
557 
558  return true;
559 }
560 
562  return 32;
563 }
564 
566  return 32;
567 }
568 
570  return EnableSubregLiveness;
571 }
void apply(ScheduleDAGInstrs *DAG) override
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Function Alias Analysis false
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getReg() const
getReg - Returns the register number.
Hexagon::ArchEnum HexagonArchVersion
bool isRegSequence() const
Definition: MachineInstr.h:852
void setSUnit(SUnit *SU)
Definition: ScheduleDAG.h:493
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
F(f)
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
static cl::opt< bool > EnableIEEERndNear("enable-hexagon-ieee-rnd-near", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Generate non-chopped conversion from fp to int."))
bool isPHI() const
Definition: MachineInstr.h:829
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:261
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
unsigned NumSuccs
of SDep::Data sucss.
Definition: ScheduleDAG.h:272
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:143
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
const InstrItinerary * Itineraries
Array of itineraries selected.
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:56
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
void clear()
Definition: SmallSet.h:119
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
#define T
static cl::opt< bool > DisableMemOps("disable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false), cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"))
static cl::opt< bool > EnableMemOps("enable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true), cl::desc("Generate V4 MEMOP in code generation for Hexagon target"))
SUnit * getSUnit() const
Definition: ScheduleDAG.h:490
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
Definition: ScheduleDAG.h:349
StringRef selectHexagonCPU(StringRef CPU)
Scheduling dependency.
Definition: ScheduleDAG.h:50
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:642
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void setDepthDirty()
Sets a flag in this node to indicate that its stored Depth value will require recomputation the next ...
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:378
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn&#39;t necessary for c...
Definition: ScheduleDAG.h:201
Container class for subtarget features.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:940
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void apply(ScheduleDAGInstrs *DAG) override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
CodeGenOpt::Level OptLevel
unsigned getAddrMode(const MachineInstr &MI) const
void apply(ScheduleDAGInstrs *DAG) override
void apply(ScheduleDAGInstrs *DAG) override
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:962
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Consider calls to be predicable"))
bool isCopy() const
Definition: MachineInstr.h:860
Any other ordering dependency.
Definition: ScheduleDAG.h:57
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:835
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true))
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
An unknown scheduling barrier.
Definition: ScheduleDAG.h:70
bool enableMachineScheduler() const override
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::ZeroOrMore, cl::init(true))
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
uint64_t getType(const MachineInstr &MI) const
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool enableSubRegLiveness() const override
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:932
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:148
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:60
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
static cl::opt< bool > EnableVecFrwdSched("enable-evec-frwd-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:496
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:269
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:629
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
const HexagonInstrInfo * getInstrInfo() const override
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:262
const FeatureBitset Features
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:73
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:572
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:367
cl::opt< bool > HexagonDisableDuplex
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65