LLVM  8.0.0svn
HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
16 
17 #include "HexagonDepArch.h"
18 #include "HexagonFrameLowering.h"
19 #include "HexagonISelLowering.h"
20 #include "HexagonInstrInfo.h"
21 #include "HexagonRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/StringRef.h"
28 #include <memory>
29 #include <string>
30 #include <vector>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
34 
35 namespace llvm {
36 
37 class MachineInstr;
38 class SDep;
39 class SUnit;
40 class TargetMachine;
41 class Triple;
42 
44  virtual void anchor();
45 
46  bool UseHVX64BOps = false;
47  bool UseHVX128BOps = false;
48 
49  bool UseLongCalls = false;
50  bool UseMemops = false;
51  bool UsePackets = false;
52  bool UseNewValueJumps = false;
53  bool UseNewValueStores = false;
54  bool UseSmallData = false;
55 
56  bool HasMemNoShuf = false;
57  bool EnableDuplex = false;
58  bool ReservedR19 = false;
59 
60 public:
64  /// True if the target should use Back-Skip-Back scheduling. This is the
65  /// default for V60.
67 
69  void apply(ScheduleDAGInstrs *DAG) override;
70  };
72  void apply(ScheduleDAGInstrs *DAG) override;
73  };
75  void apply(ScheduleDAGInstrs *DAG) override;
76  private:
77  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
78  const SUnit &Inst1, const SUnit &Inst2) const;
79  };
81  void apply(ScheduleDAGInstrs *DAG) override;
82  };
83 
84 private:
85  std::string CPUString;
86  HexagonInstrInfo InstrInfo;
87  HexagonRegisterInfo RegInfo;
88  HexagonTargetLowering TLInfo;
90  HexagonFrameLowering FrameLowering;
91  InstrItineraryData InstrItins;
92 
93 public:
94  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
95  const TargetMachine &TM);
96 
97  /// getInstrItins - Return the instruction itineraries based on subtarget
98  /// selection.
99  const InstrItineraryData *getInstrItineraryData() const override {
100  return &InstrItins;
101  }
102  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
103  const HexagonRegisterInfo *getRegisterInfo() const override {
104  return &RegInfo;
105  }
106  const HexagonTargetLowering *getTargetLowering() const override {
107  return &TLInfo;
108  }
109  const HexagonFrameLowering *getFrameLowering() const override {
110  return &FrameLowering;
111  }
113  return &TSInfo;
114  }
115 
117  StringRef FS);
118 
119  /// ParseSubtargetFeatures - Parses features string setting specified
120  /// subtarget options. Definition of function is auto generated by tblgen.
122 
123  bool hasV5Ops() const {
125  }
126  bool hasV5OpsOnly() const {
128  }
129  bool hasV55Ops() const {
131  }
132  bool hasV55OpsOnly() const {
134  }
135  bool hasV60Ops() const {
137  }
138  bool hasV60OpsOnly() const {
140  }
141  bool hasV62Ops() const {
143  }
144  bool hasV62OpsOnly() const {
146  }
147  bool hasV65Ops() const {
149  }
150  bool hasV65OpsOnly() const {
152  }
153 
154  bool useLongCalls() const { return UseLongCalls; }
155  bool useMemops() const { return UseMemops; }
156  bool usePackets() const { return UsePackets; }
157  bool useNewValueJumps() const { return UseNewValueJumps; }
158  bool useNewValueStores() const { return UseNewValueStores; }
159  bool useSmallData() const { return UseSmallData; }
160 
161  bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
162  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
163  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
164 
165  bool hasMemNoShuf() const { return HasMemNoShuf; }
166  bool hasReservedR19() const { return ReservedR19; }
167  bool usePredicatedCalls() const;
168 
169  bool useBSBScheduling() const { return UseBSBScheduling; }
170  bool enableMachineScheduler() const override;
171 
172  // Always use the TargetLowering default scheduler.
173  // FIXME: This will use the vliw scheduler which is probably just hurting
174  // compiler time and will be removed eventually anyway.
175  bool enableMachineSchedDefaultSched() const override { return false; }
176 
177  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
178  bool enablePostRAScheduler() const override { return true; }
179 
180  bool enableSubRegLiveness() const override;
181 
182  const std::string &getCPUString () const { return CPUString; }
183 
185  return HexagonArchVersion;
186  }
187 
188  void getPostRAMutations(
189  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
190  const override;
191 
192  void getSMSMutations(
193  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
194  const override;
195 
196  /// Enable use of alias analysis during code generation (during MI
197  /// scheduling, DAGCombine, etc.).
198  bool useAA() const override;
199 
200  /// Perform target specific adjustments to the latency of a schedule
201  /// dependency.
202  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
203 
204  unsigned getVectorLength() const {
205  assert(useHVXOps());
206  if (useHVX64BOps())
207  return 64;
208  if (useHVX128BOps())
209  return 128;
210  llvm_unreachable("Invalid HVX vector length settings");
211  }
212 
214  static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
215  return makeArrayRef(Types);
216  }
217 
218  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
219  if (!VecTy.isVector() || !useHVXOps())
220  return false;
221  MVT ElemTy = VecTy.getVectorElementType();
222  if (!IncludeBool && ElemTy == MVT::i1)
223  return false;
224 
225  unsigned HwLen = getVectorLength();
226  unsigned NumElems = VecTy.getVectorNumElements();
227  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
228 
229  if (IncludeBool && ElemTy == MVT::i1) {
230  // Special case for the v512i1, etc.
231  if (8*HwLen == NumElems)
232  return true;
233  // Boolean HVX vector types are formed from regular HVX vector types
234  // by replacing the element type with i1.
235  for (MVT T : ElemTypes)
236  if (NumElems * T.getSizeInBits() == 8*HwLen)
237  return true;
238  return false;
239  }
240 
241  unsigned VecWidth = VecTy.getSizeInBits();
242  if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
243  return false;
244  return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
245  }
246 
247  unsigned getTypeAlignment(MVT Ty) const {
248  if (isHVXVectorType(Ty, true))
249  return getVectorLength();
250  return Ty.getSizeInBits() / 8;
251  }
252 
253  unsigned getL1CacheLineSize() const;
254  unsigned getL1PrefetchDistance() const;
255 
256 private:
257  // Helper function responsible for increasing the latency only.
258  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
259  const;
260  void restoreLatency(SUnit *Src, SUnit *Dst) const;
261  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
262  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
263  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
264 };
265 
266 } // end namespace llvm
267 
268 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
AntiDepBreakMode getAntiDepBreakMode() const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isVector() const
Return true if this is a vector value type.
Hexagon::ArchEnum HexagonArchVersion
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
Mutate the DAG as a postpass after normal DAG building.
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
const Hexagon::ArchEnum & getHexagonArchVersion() const
const HexagonFrameLowering * getFrameLowering() const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
bool enablePostRAScheduler() const override
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
const HexagonRegisterInfo * getRegisterInfo() const override
Hexagon::ArchEnum HexagonHVXVersion
unsigned getSizeInBits() const
const HexagonTargetLowering * getTargetLowering() const override
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
#define T
const std::string & getCPUString() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
MVT getVectorElementType() const
Scheduling dependency.
Definition: ScheduleDAG.h:50
Machine Value Type.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
CodeGenOpt::Level OptLevel
void apply(ScheduleDAGInstrs *DAG) override
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1049
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
bool enableMachineScheduler() const override
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool enableMachineSchedDefaultSched() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getVectorLength() const
unsigned getTypeAlignment(MVT Ty) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
pgo instr use
bool useNewValueStores() const
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:246