LLVM  6.0.0svn
HexagonSubtarget.h
Go to the documentation of this file.
1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
16 
17 #include "HexagonDepArch.h"
18 #include "HexagonFrameLowering.h"
19 #include "HexagonISelLowering.h"
20 #include "HexagonInstrInfo.h"
21 #include "HexagonRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/StringRef.h"
28 #include <memory>
29 #include <string>
30 #include <vector>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
34 
35 #define Hexagon_SMALL_DATA_THRESHOLD 8
36 #define Hexagon_SLOTS 4
37 
38 namespace llvm {
39 
40 class MachineInstr;
41 class SDep;
42 class SUnit;
43 class TargetMachine;
44 class Triple;
45 
47  virtual void anchor();
48 
49  bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
50  bool UseLongCalls;
51  bool ModeIEEERndNear;
52 
53 public:
56  /// True if the target should use Back-Skip-Back scheduling. This is the
57  /// default for V60.
59 
61  void apply(ScheduleDAGInstrs *DAG) override;
62  };
64  void apply(ScheduleDAGInstrs *DAG) override;
65  };
67  void apply(ScheduleDAGInstrs *DAG) override;
68  private:
69  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
70  const SUnit &Inst1, const SUnit &Inst2) const;
71  };
73  void apply(ScheduleDAGInstrs *DAG) override;
74  };
75 
76 private:
77  std::string CPUString;
78  HexagonInstrInfo InstrInfo;
79  HexagonRegisterInfo RegInfo;
80  HexagonTargetLowering TLInfo;
82  HexagonFrameLowering FrameLowering;
83  InstrItineraryData InstrItins;
84 
85 public:
86  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
87  const TargetMachine &TM);
88 
89  /// getInstrItins - Return the instruction itineraries based on subtarget
90  /// selection.
91  const InstrItineraryData *getInstrItineraryData() const override {
92  return &InstrItins;
93  }
94  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
95  const HexagonRegisterInfo *getRegisterInfo() const override {
96  return &RegInfo;
97  }
98  const HexagonTargetLowering *getTargetLowering() const override {
99  return &TLInfo;
100  }
101  const HexagonFrameLowering *getFrameLowering() const override {
102  return &FrameLowering;
103  }
105  return &TSInfo;
106  }
107 
109  StringRef FS);
110 
111  /// ParseSubtargetFeatures - Parses features string setting specified
112  /// subtarget options. Definition of function is auto generated by tblgen.
114 
115  bool useMemOps() const { return UseMemOps; }
116  bool hasV5TOps() const {
118  }
119  bool hasV5TOpsOnly() const {
121  }
122  bool hasV55TOps() const {
124  }
125  bool hasV55TOpsOnly() const {
127  }
128  bool hasV60TOps() const {
130  }
131  bool hasV60TOpsOnly() const {
133  }
134  bool hasV62TOps() const {
136  }
137  bool hasV62TOpsOnly() const {
139  }
140 
141  bool modeIEEERndNear() const { return ModeIEEERndNear; }
142  bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
143  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
144  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
145  bool useLongCalls() const { return UseLongCalls; }
146  bool usePredicatedCalls() const;
147 
148  bool useBSBScheduling() const { return UseBSBScheduling; }
149  bool enableMachineScheduler() const override;
150 
151  // Always use the TargetLowering default scheduler.
152  // FIXME: This will use the vliw scheduler which is probably just hurting
153  // compiler time and will be removed eventually anyway.
154  bool enableMachineSchedDefaultSched() const override { return false; }
155 
156  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
157  bool enablePostRAScheduler() const override { return true; }
158 
159  bool enableSubRegLiveness() const override;
160 
161  const std::string &getCPUString () const { return CPUString; }
162 
163  // Threshold for small data section
164  unsigned getSmallDataThreshold() const {
166  }
167 
169  return HexagonArchVersion;
170  }
171 
172  void getPostRAMutations(
173  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
174  const override;
175 
176  void getSMSMutations(
177  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
178  const override;
179 
180  /// \brief Perform target specific adjustments to the latency of a schedule
181  /// dependency.
182  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
183 
184  unsigned getVectorLength() const {
185  assert(useHVXOps());
186  if (useHVX64BOps())
187  return 64;
188  if (useHVX128BOps())
189  return 128;
190  llvm_unreachable("Invalid HVX vector length settings");
191  }
192 
193  unsigned getL1CacheLineSize() const;
194  unsigned getL1PrefetchDistance() const;
195 
196 private:
197  // Helper function responsible for increasing the latency only.
198  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
199  const;
200  void restoreLatency(SUnit *Src, SUnit *Dst) const;
201  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
202  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
203  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
204 };
205 
206 } // end namespace llvm
207 
208 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
AntiDepBreakMode getAntiDepBreakMode() const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Hexagon::ArchEnum HexagonArchVersion
Mutate the DAG as a postpass after normal DAG building.
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
const Hexagon::ArchEnum & getHexagonArchVersion() const
const HexagonFrameLowering * getFrameLowering() const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
bool enablePostRAScheduler() const override
const HexagonInstrInfo * TII
const HexagonRegisterInfo * getRegisterInfo() const override
Hexagon::ArchEnum HexagonHVXVersion
const HexagonTargetLowering * getTargetLowering() const override
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
const std::string & getCPUString() const
Itinerary data supplied by a subtarget to be used by a target.
unsigned getSmallDataThreshold() const
Scheduling dependency.
Definition: ScheduleDAG.h:50
#define Hexagon_SMALL_DATA_THRESHOLD
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
void apply(ScheduleDAGInstrs *DAG) override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool enableMachineScheduler() const override
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:59
bool enableMachineSchedDefaultSched() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getVectorLength() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
pgo instr use
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247