LLVM  7.0.0svn
HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
16 
17 #include "HexagonDepArch.h"
18 #include "HexagonFrameLowering.h"
19 #include "HexagonISelLowering.h"
20 #include "HexagonInstrInfo.h"
21 #include "HexagonRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/StringRef.h"
28 #include <memory>
29 #include <string>
30 #include <vector>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
34 
35 #define Hexagon_SMALL_DATA_THRESHOLD 8
36 #define Hexagon_SLOTS 4
37 
38 namespace llvm {
39 
40 class MachineInstr;
41 class SDep;
42 class SUnit;
43 class TargetMachine;
44 class Triple;
45 
47  virtual void anchor();
48 
49  bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
50  bool UseLongCalls;
51  bool ModeIEEERndNear;
52 
53  bool HasMemNoShuf = false;
54  bool EnableDuplex = false;
55 public:
59  /// True if the target should use Back-Skip-Back scheduling. This is the
60  /// default for V60.
62 
64  void apply(ScheduleDAGInstrs *DAG) override;
65  };
67  void apply(ScheduleDAGInstrs *DAG) override;
68  };
70  void apply(ScheduleDAGInstrs *DAG) override;
71  private:
72  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
73  const SUnit &Inst1, const SUnit &Inst2) const;
74  };
76  void apply(ScheduleDAGInstrs *DAG) override;
77  };
78 
79 private:
80  std::string CPUString;
81  HexagonInstrInfo InstrInfo;
82  HexagonRegisterInfo RegInfo;
83  HexagonTargetLowering TLInfo;
85  HexagonFrameLowering FrameLowering;
86  InstrItineraryData InstrItins;
87 
88 public:
89  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
90  const TargetMachine &TM);
91 
92  /// getInstrItins - Return the instruction itineraries based on subtarget
93  /// selection.
94  const InstrItineraryData *getInstrItineraryData() const override {
95  return &InstrItins;
96  }
97  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
98  const HexagonRegisterInfo *getRegisterInfo() const override {
99  return &RegInfo;
100  }
101  const HexagonTargetLowering *getTargetLowering() const override {
102  return &TLInfo;
103  }
104  const HexagonFrameLowering *getFrameLowering() const override {
105  return &FrameLowering;
106  }
108  return &TSInfo;
109  }
110 
112  StringRef FS);
113 
114  /// ParseSubtargetFeatures - Parses features string setting specified
115  /// subtarget options. Definition of function is auto generated by tblgen.
117 
118  bool useMemOps() const { return UseMemOps; }
119  bool hasV5TOps() const {
121  }
122  bool hasV5TOpsOnly() const {
124  }
125  bool hasV55TOps() const {
127  }
128  bool hasV55TOpsOnly() const {
130  }
131  bool hasV60TOps() const {
133  }
134  bool hasV60TOpsOnly() const {
136  }
137  bool hasV62TOps() const {
139  }
140  bool hasV62TOpsOnly() const {
142  }
143  bool hasV65TOps() const {
145  }
146  bool hasV65TOpsOnly() const {
148  }
149 
150  bool modeIEEERndNear() const { return ModeIEEERndNear; }
151  bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
152  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
153  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
154  bool hasMemNoShuf() const { return HasMemNoShuf; }
155  bool useLongCalls() const { return UseLongCalls; }
156  bool usePredicatedCalls() const;
157 
158  bool useBSBScheduling() const { return UseBSBScheduling; }
159  bool enableMachineScheduler() const override;
160 
161  // Always use the TargetLowering default scheduler.
162  // FIXME: This will use the vliw scheduler which is probably just hurting
163  // compiler time and will be removed eventually anyway.
164  bool enableMachineSchedDefaultSched() const override { return false; }
165 
166  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
167  bool enablePostRAScheduler() const override { return true; }
168 
169  bool enableSubRegLiveness() const override;
170 
171  const std::string &getCPUString () const { return CPUString; }
172 
173  // Threshold for small data section
174  unsigned getSmallDataThreshold() const {
176  }
177 
179  return HexagonArchVersion;
180  }
181 
182  void getPostRAMutations(
183  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
184  const override;
185 
186  void getSMSMutations(
187  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
188  const override;
189 
190  /// \brief Enable use of alias analysis during code generation (during MI
191  /// scheduling, DAGCombine, etc.).
192  bool useAA() const override;
193 
194  /// \brief Perform target specific adjustments to the latency of a schedule
195  /// dependency.
196  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
197 
198  unsigned getVectorLength() const {
199  assert(useHVXOps());
200  if (useHVX64BOps())
201  return 64;
202  if (useHVX128BOps())
203  return 128;
204  llvm_unreachable("Invalid HVX vector length settings");
205  }
206 
208  static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
209  return makeArrayRef(Types);
210  }
211 
212  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
213  if (!VecTy.isVector() || !useHVXOps())
214  return false;
215  MVT ElemTy = VecTy.getVectorElementType();
216  if (!IncludeBool && ElemTy == MVT::i1)
217  return false;
218 
219  unsigned HwLen = getVectorLength();
220  unsigned NumElems = VecTy.getVectorNumElements();
221  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
222 
223  if (IncludeBool && ElemTy == MVT::i1) {
224  // Special case for the v512i1, etc.
225  if (8*HwLen == NumElems)
226  return true;
227  // Boolean HVX vector types are formed from regular HVX vector types
228  // by replacing the element type with i1.
229  for (MVT T : ElemTypes)
230  if (NumElems * T.getSizeInBits() == 8*HwLen)
231  return true;
232  return false;
233  }
234 
235  unsigned VecWidth = VecTy.getSizeInBits();
236  if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
237  return false;
238  return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
239  }
240 
241  unsigned getL1CacheLineSize() const;
242  unsigned getL1PrefetchDistance() const;
243 
244 private:
245  // Helper function responsible for increasing the latency only.
246  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
247  const;
248  void restoreLatency(SUnit *Src, SUnit *Dst) const;
249  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
250  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
251  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
252 };
253 
254 } // end namespace llvm
255 
256 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
AntiDepBreakMode getAntiDepBreakMode() const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isVector() const
Return true if this is a vector value type.
Hexagon::ArchEnum HexagonArchVersion
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
Mutate the DAG as a postpass after normal DAG building.
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
const Hexagon::ArchEnum & getHexagonArchVersion() const
const HexagonFrameLowering * getFrameLowering() const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
unsigned getL1CacheLineSize() const
bool enablePostRAScheduler() const override
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
const HexagonRegisterInfo * getRegisterInfo() const override
Hexagon::ArchEnum HexagonHVXVersion
unsigned getSizeInBits() const
const HexagonTargetLowering * getTargetLowering() const override
unsigned getL1PrefetchDistance() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
#define T
const std::string & getCPUString() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
MVT getVectorElementType() const
unsigned getSmallDataThreshold() const
Scheduling dependency.
Definition: ScheduleDAG.h:50
Machine Value Type.
#define Hexagon_SMALL_DATA_THRESHOLD
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
CodeGenOpt::Level OptLevel
void apply(ScheduleDAGInstrs *DAG) override
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:821
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
bool enableMachineScheduler() const override
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
A ScheduleDAG for scheduling lists of MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool enableMachineSchedDefaultSched() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getVectorLength() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
pgo instr use
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247