LLVM  12.0.0git
HexagonTargetMachine.cpp
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1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
22 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/Module.h"
30 #include "llvm/Transforms/Scalar.h"
31 
32 using namespace llvm;
33 
35  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
36 
38  cl::init(true), cl::desc("Enable RDF-based optimizations"));
39 
40 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
41  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
42 
43 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
45  cl::desc("Disable Hexagon Addressing Mode Optimization"));
46 
47 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
49  cl::desc("Disable Hexagon CFG Optimization"));
50 
51 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
52  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
53 
54 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
55  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
56 
57 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
59  cl::desc("Early expansion of MUX"));
60 
61 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
62  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
63 
64 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
65  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
66 
67 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
68  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
69 
70 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
71  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
72 
73 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
74  cl::desc("Enable converting conditional transfers into MUX instructions"));
75 
76 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
77  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
78  "predicate instructions"));
79 
80 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
82  cl::desc("Enable loop data prefetch on Hexagon"));
83 
84 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
85  cl::desc("Disable splitting double registers"));
86 
87 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
88  cl::Hidden, cl::desc("Bit simplification"));
89 
90 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
91  cl::Hidden, cl::desc("Loop rescheduling"));
92 
93 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
94  cl::Hidden, cl::desc("Disable backend optimizations"));
95 
96 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
98  cl::desc("Enable Hexagon Vector print instr pass"));
99 
100 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
101  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
102 
103 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
105  cl::desc("Simplify the CFG after atomic expansion pass"));
106 
107 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
108  cl::ZeroOrMore, cl::init(true),
109  cl::desc("Enable instsimplify"));
110 
111 /// HexagonTargetMachineModule - Note that this is used on hosts that
112 /// cannot link in a library unless there are references into the
113 /// library. In particular, it seems that it is not possible to get
114 /// things to work on Win32 without this. Though it is unused, do not
115 /// remove it.
117 int HexagonTargetMachineModule = 0;
118 
120  ScheduleDAGMILive *DAG =
121  new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
122  DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
123  DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
124  DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
126  return DAG;
127 }
128 
130 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
132 
133 namespace llvm {
134  extern char &HexagonExpandCondsetsID;
152 
169  CodeGenOpt::Level OptLevel);
174  FunctionPass *createHexagonPacketizer(bool Minimal);
182 } // end namespace llvm;
183 
185  if (!RM.hasValue())
186  return Reloc::Static;
187  return *RM;
188 }
189 
191  // Register the target.
193 
209 }
210 
212  StringRef CPU, StringRef FS,
213  const TargetOptions &Options,
216  CodeGenOpt::Level OL, bool JIT)
217  // Specify the vector alignment explicitly. For v512x1, the calculated
218  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
219  // the required minimum of 64 bytes.
221  T,
222  "e-m:e-p:32:32:32-a:0-n16:32-"
223  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
224  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
225  TT, CPU, FS, Options, getEffectiveRelocModel(RM),
226  getEffectiveCodeModel(CM, CodeModel::Small),
227  (HexagonNoOpt ? CodeGenOpt::None : OL)),
228  TLOF(std::make_unique<HexagonTargetObjectFile>()) {
230  initAsmInfo();
231 }
232 
233 const HexagonSubtarget *
235  AttributeList FnAttrs = F.getAttributes();
236  Attribute CPUAttr =
237  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
238  Attribute FSAttr =
239  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
240 
241  std::string CPU =
242  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
243  std::string FS =
244  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
245  // Append the preexisting target features last, so that +mattr overrides
246  // the "unsafe-fp-math" function attribute.
247  // Creating a separate target feature is not strictly necessary, it only
248  // exists to make "unsafe-fp-math" force creating a new subtarget.
249 
250  if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
251  F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
252  FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
253 
254  auto &I = SubtargetMap[CPU + FS];
255  if (!I) {
256  // This needs to be done before we create a new subtarget since any
257  // creation will depend on the TM and the code generation flags on the
258  // function that reside in TargetOptions.
260  I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
261  }
262  return I.get();
263 }
264 
266  PMB.addExtension(
268  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
270  });
271  PMB.addExtension(
273  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
275  });
276 }
277 
279  bool DebugPassManager) {
283  });
286  LoopPassManager LPM(DebugPassManager);
287  FunctionPassManager FPM(DebugPassManager);
291  });
292 }
293 
296  return TargetTransformInfo(HexagonTTIImpl(this, F));
297 }
298 
299 
301 
302 namespace {
303 /// Hexagon Code Generator Pass Configuration Options.
304 class HexagonPassConfig : public TargetPassConfig {
305 public:
306  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
307  : TargetPassConfig(TM, PM) {}
308 
309  HexagonTargetMachine &getHexagonTargetMachine() const {
310  return getTM<HexagonTargetMachine>();
311  }
312 
314  createMachineScheduler(MachineSchedContext *C) const override {
315  return createVLIWMachineSched(C);
316  }
317 
318  void addIRPasses() override;
319  bool addInstSelector() override;
320  void addPreRegAlloc() override;
321  void addPostRegAlloc() override;
322  void addPreSched2() override;
323  void addPreEmitPass() override;
324 };
325 } // namespace
326 
328  return new HexagonPassConfig(*this, PM);
329 }
330 
331 void HexagonPassConfig::addIRPasses() {
333  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
334 
335  if (!NoOpt) {
336  if (EnableInstSimplify)
337  addPass(createInstSimplifyLegacyPass());
339  }
340 
341  addPass(createAtomicExpandPass());
342 
343  if (!NoOpt) {
346  .forwardSwitchCondToPhi(true)
347  .convertSwitchToLookupTable(true)
348  .needCanonicalLoops(false)
349  .hoistCommonInsts(true)
350  .sinkCommonInsts(true)));
351  if (EnableLoopPrefetch)
352  addPass(createLoopDataPrefetchPass());
353  if (EnableCommGEP)
354  addPass(createHexagonCommonGEP());
355  // Replace certain combinations of shifts and ands with extracts.
356  if (EnableGenExtract)
357  addPass(createHexagonGenExtract());
358  }
359 }
360 
361 bool HexagonPassConfig::addInstSelector() {
362  HexagonTargetMachine &TM = getHexagonTargetMachine();
363  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
364 
365  if (!NoOpt)
367 
368  addPass(createHexagonISelDag(TM, getOptLevel()));
369 
370  if (!NoOpt) {
371  if (EnableVExtractOpt)
372  addPass(createHexagonVExtract());
373  // Create logical operations on predicate registers.
374  if (EnableGenPred)
375  addPass(createHexagonGenPredicate());
376  // Rotate loops to expose bit-simplification opportunities.
377  if (EnableLoopResched)
379  // Split double registers.
380  if (!DisableHSDR)
381  addPass(createHexagonSplitDoubleRegs());
382  // Bit simplification.
383  if (EnableBitSimplify)
384  addPass(createHexagonBitSimplify());
385  addPass(createHexagonPeephole());
386  // Constant propagation.
387  if (!DisableHCP) {
390  }
391  if (EnableGenInsert)
392  addPass(createHexagonGenInsert());
393  if (EnableEarlyIf)
395  }
396 
397  return false;
398 }
399 
400 void HexagonPassConfig::addPreRegAlloc() {
401  if (getOptLevel() != CodeGenOpt::None) {
402  if (EnableCExtOpt)
403  addPass(createHexagonConstExtenders());
407  addPass(createHexagonStoreWidening());
409  addPass(createHexagonHardwareLoops());
410  }
411  if (TM->getOptLevel() >= CodeGenOpt::Default)
412  addPass(&MachinePipelinerID);
413 }
414 
415 void HexagonPassConfig::addPostRegAlloc() {
416  if (getOptLevel() != CodeGenOpt::None) {
417  if (EnableRDFOpt)
418  addPass(createHexagonRDFOpt());
420  addPass(createHexagonCFGOptimizer());
421  if (!DisableAModeOpt)
422  addPass(createHexagonOptAddrMode());
423  }
424 }
425 
426 void HexagonPassConfig::addPreSched2() {
427  addPass(createHexagonCopyToCombine());
428  if (getOptLevel() != CodeGenOpt::None)
429  addPass(&IfConverterID);
431 }
432 
433 void HexagonPassConfig::addPreEmitPass() {
434  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
435 
436  if (!NoOpt)
437  addPass(createHexagonNewValueJump());
438 
440 
441  if (!NoOpt) {
443  addPass(createHexagonFixupHwLoops());
444  // Generate MUX from pairs of conditional transfers.
445  if (EnableGenMux)
446  addPass(createHexagonGenMux());
447  }
448 
449  // Packetization is mandatory: it handles gather/scatter at all opt levels.
450  addPass(createHexagonPacketizer(NoOpt), false);
451 
452  if (EnableVectorPrint)
453  addPass(createHexagonVectorPrint(), false);
454 
455  // Add CFI instructions if necessary.
456  addPass(createHexagonCallFrameInformation(), false);
457 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:77
void registerOptimizerLastEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:604
const NoneType None
Definition: None.h:23
uint64_t CallInst * C
FunctionPass * createHexagonCopyToCombine()
Interfaces for registering analysis passes, producing common pass manager configurations, and parsing of pass pipelines.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
char & HexagonExpandCondsetsID
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \xtract\instructions"))
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
void initializeHexagonRDFOptPass(PassRegistry &)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:248
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createHexagonVectorPrint()
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:85
void initializeHexagonHardwareLoopsPass(PassRegistry &)
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable instsimplify"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
F(f)
FunctionPass * createHexagonHardwareLoops()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createHexagonGenPredicate()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCommonGEP()
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
Definition: BitVector.h:941
void initializeHexagonGenMuxPass(PassRegistry &Registry)
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()
FunctionPass * createHexagonOptimizeSZextends()
This class provides access to building LLVM&#39;s passes.
Definition: PassBuilder.h:120
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
Hexagon Vector Loop Carried Reuse Pass.
std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT Pass)
Definition: PassManager.h:553
Target-Independent Code Generator Pass Configuration Options.
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
void initializeHexagonConstExtendersPass(PassRegistry &)
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:181
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeHexagonNewValueJumpPass(PassRegistry &)
FunctionPass * createHexagonConstExtenders()
void initializeHexagonPacketizerPass(PassRegistry &)
FunctionPass * createHexagonBitSimplify()
FunctionPass * createInstSimplifyLegacyPass()
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:239
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:543
FunctionPass * createHexagonConstPropagationPass()
void initializeHexagonVExtractPass(PassRegistry &)
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine...
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:151
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
FunctionPass * createHexagonEarlyIfConversion()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
ModuleToFunctionPassAdaptor< FunctionPassT > createModuleToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1296
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
Pass * createHexagonVectorLoopCarriedReuseLegacyPass()
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonLoopRescheduling()
FunctionPass * createHexagonStoreWidening()
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
FunctionPass * createHexagonBranchRelaxation()
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonNewValueJump()
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
FunctionPass * createHexagonRDFOpt()
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"))
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonPeephole()
void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
FunctionToLoopPassAdaptor< LoopPassT > createFunctionToLoopPassAdaptor(LoopPassT Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool DebugLogging=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
constexpr bool hasValue() const
Definition: Optional.h:262
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
FunctionPass * createHexagonVExtract()
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
FunctionPass * createHexagonGenInsert()
Target - Wrapper for Target specific information.
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
FunctionPass * createHexagonCallFrameInformation()
std::string TargetCPU
Definition: TargetMachine.h:86
void initializeHexagonOptAddrModePass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
FunctionPass * createHexagonSplitConst32AndConst64()
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
Manages a sequence of passes over a particular unit of IR.
Definition: PassManager.h:466
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:275
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:59
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Pass * createHexagonLoopIdiomPass()
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
std::string TargetFS
Definition: TargetMachine.h:87
bool hasFnAttribute(Attribute::AttrKind Kind) const
Equivalent to hasAttribute(AttributeList::FunctionIndex, Kind) but may be faster. ...
LLVM-provided high-level optimization levels.
Definition: PassBuilder.h:157
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonPacketizer(bool Minimal)
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
FunctionPass * createHexagonOptAddrMode()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:349
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1556
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
void adjustPassManager(PassManagerBuilder &PMB) override
Allow the target to modify the pass manager, e.g.
void registerPassBuilderCallbacks(PassBuilder &PB, bool DebugPassManager) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
EP_LateLoopOptimizations - This extension point allows adding late loop canonicalization and simplifi...
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \nsert\instructions"))
void initializeHexagonExpandCondsetsPass(PassRegistry &)
Target & getTheHexagonTarget()
EP_LoopOptimizerEnd - This extension point allows adding loop passes to the end of the loop optimizer...
FunctionPass * createHexagonCFGOptimizer()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Level
Definition: Debugify.cpp:34