LLVM  7.0.0svn
HexagonTargetMachine.cpp
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1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
20 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/IR/Module.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
32  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
35  cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
42  cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
46  cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
56  cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71  cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75  "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
79  cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82  cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85  cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88  cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91  cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
95  cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 /// HexagonTargetMachineModule - Note that this is used on hosts that
101 /// cannot link in a library unless there are references into the
102 /// library. In particular, it seems that it is not possible to get
103 /// things to work on Win32 without this. Though it is unused, do not
104 /// remove it.
106 int HexagonTargetMachineModule = 0;
107 
109  ScheduleDAGMILive *DAG =
110  new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
111  DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
112  DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
113  DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
115  return DAG;
116 }
117 
119 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
121 
122 namespace llvm {
123  extern char &HexagonExpandCondsetsID;
141 
159  CodeGenOpt::Level OptLevel);
172 } // end namespace llvm;
173 
175  if (!RM.hasValue())
176  return Reloc::Static;
177  return *RM;
178 }
179 
181  if (CM)
182  return *CM;
183  return CodeModel::Small;
184 }
185 
186 extern "C" void LLVMInitializeHexagonTarget() {
187  // Register the target.
189 
205 }
206 
208  StringRef CPU, StringRef FS,
209  const TargetOptions &Options,
212  CodeGenOpt::Level OL, bool JIT)
213  // Specify the vector alignment explicitly. For v512x1, the calculated
214  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
215  // the required minimum of 64 bytes.
217  T,
218  "e-m:e-p:32:32:32-a:0-n16:32-"
219  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
220  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
221  TT, CPU, FS, Options, getEffectiveRelocModel(RM),
222  getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
225  initAsmInfo();
226 }
227 
228 const HexagonSubtarget *
230  AttributeList FnAttrs = F.getAttributes();
231  Attribute CPUAttr =
232  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
233  Attribute FSAttr =
234  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
235 
236  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
237  ? CPUAttr.getValueAsString().str()
238  : TargetCPU;
239  std::string FS = !FSAttr.hasAttribute(Attribute::None)
240  ? FSAttr.getValueAsString().str()
241  : TargetFS;
242 
243  auto &I = SubtargetMap[CPU + FS];
244  if (!I) {
245  // This needs to be done before we create a new subtarget since any
246  // creation will depend on the TM and the code generation flags on the
247  // function that reside in TargetOptions.
249  I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
250  }
251  return I.get();
252 }
253 
255  PMB.addExtension(
257  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
259  });
260  PMB.addExtension(
262  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
264  });
265 }
266 
269  return TargetTransformInfo(HexagonTTIImpl(this, F));
270 }
271 
272 
274 
275 namespace {
276 /// Hexagon Code Generator Pass Configuration Options.
277 class HexagonPassConfig : public TargetPassConfig {
278 public:
279  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
280  : TargetPassConfig(TM, PM) {}
281 
282  HexagonTargetMachine &getHexagonTargetMachine() const {
283  return getTM<HexagonTargetMachine>();
284  }
285 
287  createMachineScheduler(MachineSchedContext *C) const override {
288  return createVLIWMachineSched(C);
289  }
290 
291  void addIRPasses() override;
292  bool addInstSelector() override;
293  void addPreRegAlloc() override;
294  void addPostRegAlloc() override;
295  void addPreSched2() override;
296  void addPreEmitPass() override;
297 };
298 } // namespace
299 
301  return new HexagonPassConfig(*this, PM);
302 }
303 
304 void HexagonPassConfig::addIRPasses() {
306  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
307 
308  if (!NoOpt) {
311  }
312 
313  addPass(createAtomicExpandPass());
314  if (!NoOpt) {
315  if (EnableLoopPrefetch)
316  addPass(createLoopDataPrefetchPass());
317  if (EnableCommGEP)
318  addPass(createHexagonCommonGEP());
319  // Replace certain combinations of shifts and ands with extracts.
320  if (EnableGenExtract)
321  addPass(createHexagonGenExtract());
322  }
323 }
324 
325 bool HexagonPassConfig::addInstSelector() {
326  HexagonTargetMachine &TM = getHexagonTargetMachine();
327  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
328 
329  if (!NoOpt)
331 
332  addPass(createHexagonISelDag(TM, getOptLevel()));
333 
334  if (!NoOpt) {
335  if (EnableVExtractOpt)
336  addPass(createHexagonVExtract());
337  // Create logical operations on predicate registers.
338  if (EnableGenPred)
339  addPass(createHexagonGenPredicate());
340  // Rotate loops to expose bit-simplification opportunities.
341  if (EnableLoopResched)
343  // Split double registers.
344  if (!DisableHSDR)
345  addPass(createHexagonSplitDoubleRegs());
346  // Bit simplification.
347  if (EnableBitSimplify)
348  addPass(createHexagonBitSimplify());
349  addPass(createHexagonPeephole());
350  // Constant propagation.
351  if (!DisableHCP) {
354  }
355  if (EnableGenInsert)
356  addPass(createHexagonGenInsert());
357  if (EnableEarlyIf)
359  }
360 
361  return false;
362 }
363 
364 void HexagonPassConfig::addPreRegAlloc() {
365  if (getOptLevel() != CodeGenOpt::None) {
366  if (EnableCExtOpt)
367  addPass(createHexagonConstExtenders());
371  addPass(createHexagonStoreWidening());
373  addPass(createHexagonHardwareLoops());
374  }
375  if (TM->getOptLevel() >= CodeGenOpt::Default)
376  addPass(&MachinePipelinerID);
377 }
378 
379 void HexagonPassConfig::addPostRegAlloc() {
380  if (getOptLevel() != CodeGenOpt::None) {
381  if (EnableRDFOpt)
382  addPass(createHexagonRDFOpt());
384  addPass(createHexagonCFGOptimizer());
385  if (!DisableAModeOpt)
386  addPass(createHexagonOptAddrMode());
387  }
388 }
389 
390 void HexagonPassConfig::addPreSched2() {
391  addPass(createHexagonCopyToCombine());
392  if (getOptLevel() != CodeGenOpt::None)
393  addPass(&IfConverterID);
395 }
396 
397 void HexagonPassConfig::addPreEmitPass() {
398  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
399 
400  if (!NoOpt)
401  addPass(createHexagonNewValueJump());
402 
404 
405  // Create Packets.
406  if (!NoOpt) {
408  addPass(createHexagonFixupHwLoops());
409  // Generate MUX from pairs of conditional transfers.
410  if (EnableGenMux)
411  addPass(createHexagonGenMux());
412  }
413 
414  // Create packets for 2 instructions that consitute a gather instruction.
415  // Do this regardless of the opt level.
416  addPass(createHexagonGatherPacketize(), false);
417 
418  if (!NoOpt)
419  addPass(createHexagonPacketizer(), false);
420 
421  if (EnableVectorPrint)
422  addPass(createHexagonVectorPrint(), false);
423 
424  // Add CFI instructions if necessary.
425  addPass(createHexagonCallFrameInformation(), false);
426 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const NoneType None
Definition: None.h:24
uint64_t CallInst * C
FunctionPass * createHexagonCopyToCombine()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
char & HexagonExpandCondsetsID
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \xtract\instructions"))
void initializeHexagonRDFOptPass(PassRegistry &)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createHexagonVectorPrint()
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
void initializeHexagonHardwareLoopsPass(PassRegistry &)
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
F(f)
FunctionPass * createHexagonHardwareLoops()
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1056
MachineSchedRegistry provides a selection of available machine instruction schedulers.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createHexagonGenPredicate()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCommonGEP()
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
void initializeHexagonGenMuxPass(PassRegistry &Registry)
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createConstantPropagationPass()
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
No attributes have been set.
Definition: Attributes.h:72
Target-Independent Code Generator Pass Configuration Options.
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
void initializeHexagonConstExtendersPass(PassRegistry &)
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:164
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeHexagonNewValueJumpPass(PassRegistry &)
FunctionPass * createHexagonConstExtenders()
void initializeHexagonPacketizerPass(PassRegistry &)
FunctionPass * createHexagonBitSimplify()
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
FunctionPass * createHexagonConstPropagationPass()
void initializeHexagonVExtractPass(PassRegistry &)
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine...
void initializeHexagonVectorLoopCarriedReusePass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
void initializeHexagonLoopIdiomRecognizePass(PassRegistry &)
FunctionPass * createHexagonEarlyIfConversion()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
FunctionPass * createHexagonPacketizer()
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonLoopRescheduling()
FunctionPass * createHexagonStoreWidening()
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createHexagonBranchRelaxation()
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonNewValueJump()
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
FunctionPass * createHexagonRDFOpt()
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"))
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonPeephole()
FunctionPass * createHexagonGatherPacketize()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
FunctionPass * createHexagonVExtract()
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
FunctionPass * createHexagonGenInsert()
Target - Wrapper for Target specific information.
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
FunctionPass * createHexagonCallFrameInformation()
std::string TargetCPU
Definition: TargetMachine.h:79
void initializeHexagonOptAddrModePass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:183
FunctionPass * createHexagonSplitConst32AndConst64()
Pass * createHexagonVectorLoopCarriedReusePass()
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:569
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Pass * createHexagonLoopIdiomPass()
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
std::string TargetFS
Definition: TargetMachine.h:80
FunctionPass * createHexagonGenExtract()
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
FunctionPass * createHexagonOptAddrMode()
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
void adjustPassManager(PassManagerBuilder &PMB) override
Allow the target to modify the pass manager, e.g.
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
EP_LateLoopOptimizations - This extension point allows adding late loop canonicalization and simplifi...
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \nsert\instructions"))
void initializeHexagonExpandCondsetsPass(PassRegistry &)
void LLVMInitializeHexagonTarget()
Target & getTheHexagonTarget()
EP_LoopOptimizerEnd - This extension point allows adding loop passes to the end of the loop optimizer...
FunctionPass * createHexagonCFGOptimizer()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.