LLVM  9.0.0svn
HexagonTargetMachine.cpp
Go to the documentation of this file.
1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
19 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/IR/Module.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
31  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
32 
34  cl::init(true), cl::desc("Enable RDF-based optimizations"));
35 
36 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
37  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
38 
39 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41  cl::desc("Disable Hexagon Addressing Mode Optimization"));
42 
43 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45  cl::desc("Disable Hexagon CFG Optimization"));
46 
47 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
48  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
49 
50 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
51  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
52 
53 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55  cl::desc("Early expansion of MUX"));
56 
57 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
58  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
59 
60 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
61  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
62 
63 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
64  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
65 
66 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
67  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
68 
69 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
70  cl::desc("Enable converting conditional transfers into MUX instructions"));
71 
72 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
73  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
74  "predicate instructions"));
75 
76 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78  cl::desc("Enable loop data prefetch on Hexagon"));
79 
80 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
81  cl::desc("Disable splitting double registers"));
82 
83 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
84  cl::Hidden, cl::desc("Bit simplification"));
85 
86 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
87  cl::Hidden, cl::desc("Loop rescheduling"));
88 
89 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
90  cl::Hidden, cl::desc("Disable backend optimizations"));
91 
92 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94  cl::desc("Enable Hexagon Vector print instr pass"));
95 
96 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
97  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
98 
99 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
101  cl::desc("Simplify the CFG after atomic expansion pass"));
102 
103 /// HexagonTargetMachineModule - Note that this is used on hosts that
104 /// cannot link in a library unless there are references into the
105 /// library. In particular, it seems that it is not possible to get
106 /// things to work on Win32 without this. Though it is unused, do not
107 /// remove it.
109 int HexagonTargetMachineModule = 0;
110 
112  ScheduleDAGMILive *DAG =
113  new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
114  DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
115  DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
116  DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
118  return DAG;
119 }
120 
122 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
124 
125 namespace llvm {
126  extern char &HexagonExpandCondsetsID;
144 
161  CodeGenOpt::Level OptLevel);
166  FunctionPass *createHexagonPacketizer(bool Minimal);
174 } // end namespace llvm;
175 
177  if (!RM.hasValue())
178  return Reloc::Static;
179  return *RM;
180 }
181 
182 extern "C" void LLVMInitializeHexagonTarget() {
183  // Register the target.
185 
201 }
202 
204  StringRef CPU, StringRef FS,
205  const TargetOptions &Options,
208  CodeGenOpt::Level OL, bool JIT)
209  // Specify the vector alignment explicitly. For v512x1, the calculated
210  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
211  // the required minimum of 64 bytes.
213  T,
214  "e-m:e-p:32:32:32-a:0-n16:32-"
215  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
216  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
217  TT, CPU, FS, Options, getEffectiveRelocModel(RM),
218  getEffectiveCodeModel(CM, CodeModel::Small),
219  (HexagonNoOpt ? CodeGenOpt::None : OL)),
222  initAsmInfo();
223 }
224 
225 const HexagonSubtarget *
227  AttributeList FnAttrs = F.getAttributes();
228  Attribute CPUAttr =
229  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
230  Attribute FSAttr =
231  FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
232 
233  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
234  ? CPUAttr.getValueAsString().str()
235  : TargetCPU;
236  std::string FS = !FSAttr.hasAttribute(Attribute::None)
237  ? FSAttr.getValueAsString().str()
238  : TargetFS;
239 
240  auto &I = SubtargetMap[CPU + FS];
241  if (!I) {
242  // This needs to be done before we create a new subtarget since any
243  // creation will depend on the TM and the code generation flags on the
244  // function that reside in TargetOptions.
246  I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
247  }
248  return I.get();
249 }
250 
252  PMB.addExtension(
254  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
256  });
257  PMB.addExtension(
259  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
261  });
262 }
263 
266  return TargetTransformInfo(HexagonTTIImpl(this, F));
267 }
268 
269 
271 
272 namespace {
273 /// Hexagon Code Generator Pass Configuration Options.
274 class HexagonPassConfig : public TargetPassConfig {
275 public:
276  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
277  : TargetPassConfig(TM, PM) {}
278 
279  HexagonTargetMachine &getHexagonTargetMachine() const {
280  return getTM<HexagonTargetMachine>();
281  }
282 
284  createMachineScheduler(MachineSchedContext *C) const override {
285  return createVLIWMachineSched(C);
286  }
287 
288  void addIRPasses() override;
289  bool addInstSelector() override;
290  void addPreRegAlloc() override;
291  void addPostRegAlloc() override;
292  void addPreSched2() override;
293  void addPreEmitPass() override;
294 };
295 } // namespace
296 
298  return new HexagonPassConfig(*this, PM);
299 }
300 
301 void HexagonPassConfig::addIRPasses() {
303  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
304 
305  if (!NoOpt) {
308  }
309 
310  addPass(createAtomicExpandPass());
311 
312  if (!NoOpt) {
314  addPass(createCFGSimplificationPass(1, true, true, false, true));
315  if (EnableLoopPrefetch)
316  addPass(createLoopDataPrefetchPass());
317  if (EnableCommGEP)
318  addPass(createHexagonCommonGEP());
319  // Replace certain combinations of shifts and ands with extracts.
320  if (EnableGenExtract)
321  addPass(createHexagonGenExtract());
322  }
323 }
324 
325 bool HexagonPassConfig::addInstSelector() {
326  HexagonTargetMachine &TM = getHexagonTargetMachine();
327  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
328 
329  if (!NoOpt)
331 
332  addPass(createHexagonISelDag(TM, getOptLevel()));
333 
334  if (!NoOpt) {
335  if (EnableVExtractOpt)
336  addPass(createHexagonVExtract());
337  // Create logical operations on predicate registers.
338  if (EnableGenPred)
339  addPass(createHexagonGenPredicate());
340  // Rotate loops to expose bit-simplification opportunities.
341  if (EnableLoopResched)
343  // Split double registers.
344  if (!DisableHSDR)
345  addPass(createHexagonSplitDoubleRegs());
346  // Bit simplification.
347  if (EnableBitSimplify)
348  addPass(createHexagonBitSimplify());
349  addPass(createHexagonPeephole());
350  // Constant propagation.
351  if (!DisableHCP) {
354  }
355  if (EnableGenInsert)
356  addPass(createHexagonGenInsert());
357  if (EnableEarlyIf)
359  }
360 
361  return false;
362 }
363 
364 void HexagonPassConfig::addPreRegAlloc() {
365  if (getOptLevel() != CodeGenOpt::None) {
366  if (EnableCExtOpt)
367  addPass(createHexagonConstExtenders());
371  addPass(createHexagonStoreWidening());
373  addPass(createHexagonHardwareLoops());
374  }
375  if (TM->getOptLevel() >= CodeGenOpt::Default)
376  addPass(&MachinePipelinerID);
377 }
378 
379 void HexagonPassConfig::addPostRegAlloc() {
380  if (getOptLevel() != CodeGenOpt::None) {
381  if (EnableRDFOpt)
382  addPass(createHexagonRDFOpt());
384  addPass(createHexagonCFGOptimizer());
385  if (!DisableAModeOpt)
386  addPass(createHexagonOptAddrMode());
387  }
388 }
389 
390 void HexagonPassConfig::addPreSched2() {
391  addPass(createHexagonCopyToCombine());
392  if (getOptLevel() != CodeGenOpt::None)
393  addPass(&IfConverterID);
395 }
396 
397 void HexagonPassConfig::addPreEmitPass() {
398  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
399 
400  if (!NoOpt)
401  addPass(createHexagonNewValueJump());
402 
404 
405  if (!NoOpt) {
407  addPass(createHexagonFixupHwLoops());
408  // Generate MUX from pairs of conditional transfers.
409  if (EnableGenMux)
410  addPass(createHexagonGenMux());
411  }
412 
413  // Packetization is mandatory: it handles gather/scatter at all opt levels.
414  addPass(createHexagonPacketizer(NoOpt), false);
415 
416  if (EnableVectorPrint)
417  addPass(createHexagonVectorPrint(), false);
418 
419  // Add CFI instructions if necessary.
420  addPass(createHexagonCallFrameInformation(), false);
421 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
const NoneType None
Definition: None.h:23
uint64_t CallInst * C
FunctionPass * createHexagonCopyToCombine()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
char & HexagonExpandCondsetsID
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \xtract\instructions"))
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
void initializeHexagonRDFOptPass(PassRegistry &)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createHexagonVectorPrint()
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
void initializeHexagonHardwareLoopsPass(PassRegistry &)
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
F(f)
FunctionPass * createHexagonHardwareLoops()
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1403
MachineSchedRegistry provides a selection of available machine instruction schedulers.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createHexagonGenPredicate()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCommonGEP()
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
void initializeHexagonGenMuxPass(PassRegistry &Registry)
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createConstantPropagationPass()
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
No attributes have been set.
Definition: Attributes.h:71
Target-Independent Code Generator Pass Configuration Options.
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
void initializeHexagonConstExtendersPass(PassRegistry &)
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:171
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeHexagonNewValueJumpPass(PassRegistry &)
FunctionPass * createHexagonConstExtenders()
void initializeHexagonPacketizerPass(PassRegistry &)
FunctionPass * createHexagonBitSimplify()
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
FunctionPass * createHexagonConstPropagationPass()
void initializeHexagonVExtractPass(PassRegistry &)
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine...
void initializeHexagonVectorLoopCarriedReusePass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
void initializeHexagonLoopIdiomRecognizePass(PassRegistry &)
FunctionPass * createHexagonEarlyIfConversion()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonLoopRescheduling()
FunctionPass * createHexagonStoreWidening()
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createHexagonBranchRelaxation()
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonNewValueJump()
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
FunctionPass * createHexagonRDFOpt()
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"))
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonPeephole()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
FunctionPass * createHexagonVExtract()
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
FunctionPass * createHexagonGenInsert()
Target - Wrapper for Target specific information.
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
FunctionPass * createHexagonCallFrameInformation()
std::string TargetCPU
Definition: TargetMachine.h:85
void initializeHexagonOptAddrModePass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
FunctionPass * createHexagonSplitConst32AndConst64()
Pass * createHexagonVectorLoopCarriedReusePass()
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Pass * createHexagonLoopIdiomPass()
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonPacketizer(bool Minimal)
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
FunctionPass * createHexagonOptAddrMode()
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
void adjustPassManager(PassManagerBuilder &PMB) override
Allow the target to modify the pass manager, e.g.
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
EP_LateLoopOptimizations - This extension point allows adding late loop canonicalization and simplifi...
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \nsert\instructions"))
void initializeHexagonExpandCondsetsPass(PassRegistry &)
void LLVMInitializeHexagonTarget()
Target & getTheHexagonTarget()
EP_LoopOptimizerEnd - This extension point allows adding loop passes to the end of the loop optimizer...
FunctionPass * createHexagonCFGOptimizer()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.