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IRTranslator.h
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the IRTranslator pass.
10 /// This pass is responsible for translating LLVM IR into MachineInstr.
11 /// It uses target hooks to lower the ABI but aside from that, the pass
12 /// generated code is generic. This is the default translator used for
13 /// GlobalISel.
14 ///
15 /// \todo Replace the comments with actual doxygen comments.
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
19 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
20 
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/Support/Allocator.h"
30 #include <memory>
31 #include <utility>
32 
33 namespace llvm {
34 
35 class AllocaInst;
36 class BasicBlock;
37 class CallInst;
38 class CallLowering;
39 class Constant;
40 class DataLayout;
41 class FunctionLoweringInfo;
42 class Instruction;
43 class MachineBasicBlock;
44 class MachineFunction;
45 class MachineInstr;
46 class MachineRegisterInfo;
47 class OptimizationRemarkEmitter;
48 class PHINode;
49 class TargetPassConfig;
50 class User;
51 class Value;
52 
53 // Technically the pass should run on an hypothetical MachineModule,
54 // since it should translate Global into some sort of MachineGlobal.
55 // The MachineGlobal should ultimately just be a transfer of ownership of
56 // the interesting bits that are relevant to represent a global value.
57 // That being said, we could investigate what would it cost to just duplicate
58 // the information from the LLVM IR.
59 // The idea is that ultimately we would be able to free up the memory used
60 // by the LLVM IR as soon as the translation is over.
62 public:
63  static char ID;
64 
65 private:
66  /// Interface used to lower the everything related to calls.
67  const CallLowering *CLI;
68 
69  /// This class contains the mapping between the Values to vreg related data.
70  class ValueToVRegInfo {
71  public:
72  ValueToVRegInfo() = default;
73 
74  using VRegListT = SmallVector<Register, 1>;
75  using OffsetListT = SmallVector<uint64_t, 1>;
76 
77  using const_vreg_iterator =
79  using const_offset_iterator =
81 
82  inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); }
83 
84  VRegListT *getVRegs(const Value &V) {
85  auto It = ValToVRegs.find(&V);
86  if (It != ValToVRegs.end())
87  return It->second;
88 
89  return insertVRegs(V);
90  }
91 
92  OffsetListT *getOffsets(const Value &V) {
93  auto It = TypeToOffsets.find(V.getType());
94  if (It != TypeToOffsets.end())
95  return It->second;
96 
97  return insertOffsets(V);
98  }
99 
100  const_vreg_iterator findVRegs(const Value &V) const {
101  return ValToVRegs.find(&V);
102  }
103 
104  bool contains(const Value &V) const {
105  return ValToVRegs.find(&V) != ValToVRegs.end();
106  }
107 
108  void reset() {
109  ValToVRegs.clear();
110  TypeToOffsets.clear();
111  VRegAlloc.DestroyAll();
112  OffsetAlloc.DestroyAll();
113  }
114 
115  private:
116  VRegListT *insertVRegs(const Value &V) {
117  assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists");
118 
119  // We placement new using our fast allocator since we never try to free
120  // the vectors until translation is finished.
121  auto *VRegList = new (VRegAlloc.Allocate()) VRegListT();
122  ValToVRegs[&V] = VRegList;
123  return VRegList;
124  }
125 
126  OffsetListT *insertOffsets(const Value &V) {
127  assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() &&
128  "Type already exists");
129 
130  auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT();
131  TypeToOffsets[V.getType()] = OffsetList;
132  return OffsetList;
133  }
136 
137  // We store pointers to vectors here since references may be invalidated
138  // while we hold them if we stored the vectors directly.
141  };
142 
143  /// Mapping of the values of the current LLVM IR function to the related
144  /// virtual registers and offsets.
145  ValueToVRegInfo VMap;
146 
147  // N.b. it's not completely obvious that this will be sufficient for every
148  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
149  // lives.
151 
152  // One BasicBlock can be translated to multiple MachineBasicBlocks. For such
153  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
154  // a mapping between the edges arriving at the BasicBlock to the corresponding
155  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
156  // single MachineBasicBlock may also end up in this Map.
157  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
159 
160  // List of stubbed PHI instructions, for values and basic blocks to be filled
161  // in once all MachineBasicBlocks have been created.
163  PendingPHIs;
164 
165  /// Record of what frame index has been allocated to specified allocas for
166  /// this function.
168 
169  SwiftErrorValueTracking SwiftError;
170 
171  /// \name Methods for translating form LLVM IR to MachineInstr.
172  /// \see ::translate for general information on the translate methods.
173  /// @{
174 
175  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
176  /// Insert the newly translated instruction(s) right where the CurBuilder
177  /// is set.
178  ///
179  /// The general algorithm is:
180  /// 1. Look for a virtual register for each operand or
181  /// create one.
182  /// 2 Update the VMap accordingly.
183  /// 2.alt. For constant arguments, if they are compile time constants,
184  /// produce an immediate in the right operand and do not touch
185  /// ValToReg. Actually we will go with a virtual register for each
186  /// constants because it may be expensive to actually materialize the
187  /// constant. Moreover, if the constant spans on several instructions,
188  /// CSE may not catch them.
189  /// => Update ValToVReg and remember that we saw a constant in Constants.
190  /// We will materialize all the constants in finalize.
191  /// Note: we would need to do something so that we can recognize such operand
192  /// as constants.
193  /// 3. Create the generic instruction.
194  ///
195  /// \return true if the translation succeeded.
196  bool translate(const Instruction &Inst);
197 
198  /// Materialize \p C into virtual-register \p Reg. The generic instructions
199  /// performing this materialization will be inserted into the entry block of
200  /// the function.
201  ///
202  /// \return true if the materialization succeeded.
203  bool translate(const Constant &C, Register Reg);
204 
205  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
206  /// emitted.
207  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
208 
209  /// Translate an LLVM load instruction into generic IR.
210  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
211 
212  /// Translate an LLVM store instruction into generic IR.
213  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
214 
215  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
216  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
217  unsigned ID);
218 
219  void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
220 
221  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
222  MachineIRBuilder &MIRBuilder);
223 
224  /// Helper function for translateSimpleIntrinsic.
225  /// \return The generic opcode for \p IntrinsicID if \p IntrinsicID is a
226  /// simple intrinsic (ceil, fabs, etc.). Otherwise, returns
227  /// Intrinsic::not_intrinsic.
228  unsigned getSimpleIntrinsicOpcode(Intrinsic::ID ID);
229 
230  /// Translates the intrinsics defined in getSimpleIntrinsicOpcode.
231  /// \return true if the translation succeeded.
232  bool translateSimpleIntrinsic(const CallInst &CI, Intrinsic::ID ID,
233  MachineIRBuilder &MIRBuilder);
234 
235  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
236  MachineIRBuilder &MIRBuilder);
237 
238  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
239 
240  /// Returns true if the value should be split into multiple LLTs.
241  /// If \p Offsets is given then the split type's offsets will be stored in it.
242  /// If \p Offsets is not empty it will be cleared first.
243  bool valueIsSplit(const Value &V,
245 
246  /// Translate call instruction.
247  /// \pre \p U is a call instruction.
248  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
249 
250  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
251 
252  bool translateCallBr(const User &U, MachineIRBuilder &MIRBuilder);
253 
254  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
255 
256  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
257  /// given generic Opcode.
258  bool translateCast(unsigned Opcode, const User &U,
259  MachineIRBuilder &MIRBuilder);
260 
261  /// Translate a phi instruction.
262  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
263 
264  /// Translate a comparison (icmp or fcmp) instruction or constant.
265  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
266 
267  /// Translate an integer compare instruction (or constant).
268  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
269  return translateCompare(U, MIRBuilder);
270  }
271 
272  /// Translate a floating-point compare instruction (or constant).
273  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
274  return translateCompare(U, MIRBuilder);
275  }
276 
277  /// Add remaining operands onto phis we've translated. Executed after all
278  /// MachineBasicBlocks for the function have been created.
279  void finishPendingPhis();
280 
281  /// Translate \p Inst into a binary operation \p Opcode.
282  /// \pre \p U is a binary operation.
283  bool translateBinaryOp(unsigned Opcode, const User &U,
284  MachineIRBuilder &MIRBuilder);
285 
286  /// Translate branch (br) instruction.
287  /// \pre \p U is a branch instruction.
288  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
289 
290  // Begin switch lowering functions.
291  bool emitJumpTableHeader(SwitchCG::JumpTable &JT,
293  MachineBasicBlock *HeaderBB);
294  void emitJumpTable(SwitchCG::JumpTable &JT, MachineBasicBlock *MBB);
295 
296  void emitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB,
297  MachineIRBuilder &MIB);
298 
299  bool lowerJumpTableWorkItem(SwitchCG::SwitchWorkListItem W,
300  MachineBasicBlock *SwitchMBB,
301  MachineBasicBlock *CurMBB,
302  MachineBasicBlock *DefaultMBB,
303  MachineIRBuilder &MIB,
305  BranchProbability UnhandledProbs,
307  MachineBasicBlock *Fallthrough,
308  bool FallthroughUnreachable);
309 
310  bool lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I,
311  Value *Cond,
312  MachineBasicBlock *Fallthrough,
313  bool FallthroughUnreachable,
314  BranchProbability UnhandledProbs,
315  MachineBasicBlock *CurMBB,
316  MachineIRBuilder &MIB,
317  MachineBasicBlock *SwitchMBB);
318 
319  bool lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W, Value *Cond,
320  MachineBasicBlock *SwitchMBB,
321  MachineBasicBlock *DefaultMBB,
322  MachineIRBuilder &MIB);
323 
324  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
325  // End switch lowering section.
326 
327  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
328 
329  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
330 
331  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
332 
333  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
334 
335  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
336 
337  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
338 
339  /// Translate return (ret) instruction.
340  /// The target needs to implement CallLowering::lowerReturn for
341  /// this to succeed.
342  /// \pre \p U is a return instruction.
343  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
344 
345  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
346 
347  bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
348 
349  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
350  return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
351  }
352  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
353  return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
354  }
355  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
356  return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
357  }
358  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
359  return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
360  }
361  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
362  return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
363  }
364  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
365  return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
366  }
367 
368  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
369  return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
370  }
371  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
372  return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
373  }
374  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
375  return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
376  }
377  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
378  return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
379  }
380  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
381  return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
382  }
383  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
384  return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
385  }
386  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
387  return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
388  }
389  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
390  return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
391  }
392  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
393  return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
394  }
395  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
396  return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
397  }
398  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
399  return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
400  }
401  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
402  return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
403  }
404  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
405  return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
406  }
407  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
408  return true;
409  }
410  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
411  return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
412  }
413 
414  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
415  return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
416  }
417 
418  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
419  return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
420  }
421  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
422  return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
423  }
424  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
425  return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
426  }
427 
428  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
429  return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
430  }
431  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
432  return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
433  }
434  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
435  return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
436  }
437  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
438  return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
439  }
440 
441  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
442 
443  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
444 
445  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
446 
447  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
448 
449  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
450  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
451  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder);
452 
453  // Stubs to keep the compiler happy while we implement the rest of the
454  // translation.
455  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
456  return false;
457  }
458  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
459  return false;
460  }
461  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
462  return false;
463  }
464  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
465  return false;
466  }
467  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
468  return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
469  }
470  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
471  return false;
472  }
473  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
474  return false;
475  }
476  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
477  return false;
478  }
479  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
480  return false;
481  }
482 
483  /// @}
484 
485  // Builder for machine instruction a la IRBuilder.
486  // I.e., compared to regular MIBuilder, this one also inserts the instruction
487  // in the current block, it can creates block, etc., basically a kind of
488  // IRBuilder, but for Machine IR.
489  // CSEMIRBuilder CurBuilder;
490  std::unique_ptr<MachineIRBuilder> CurBuilder;
491 
492  // Builder set to the entry block (just after ABI lowering instructions). Used
493  // as a convenient location for Constants.
494  // CSEMIRBuilder EntryBuilder;
495  std::unique_ptr<MachineIRBuilder> EntryBuilder;
496 
497  // The MachineFunction currently being translated.
498  MachineFunction *MF;
499 
500  /// MachineRegisterInfo used to create virtual registers.
501  MachineRegisterInfo *MRI = nullptr;
502 
503  const DataLayout *DL;
504 
505  /// Current target configuration. Controls how the pass handles errors.
506  const TargetPassConfig *TPC;
507 
508  /// Current optimization remark emitter. Used to report failures.
509  std::unique_ptr<OptimizationRemarkEmitter> ORE;
510 
511  FunctionLoweringInfo FuncInfo;
512 
513  // True when either the Target Machine specifies no optimizations or the
514  // function has the optnone attribute.
515  bool EnableOpts = false;
516 
517  /// Switch analysis and optimization.
518  class GISelSwitchLowering : public SwitchCG::SwitchLowering {
519  public:
520  GISelSwitchLowering(IRTranslator *irt, FunctionLoweringInfo &funcinfo)
521  : SwitchLowering(funcinfo), IRT(irt) {
522  assert(irt && "irt is null!");
523  }
524 
525  virtual void addSuccessorWithProb(
528  IRT->addSuccessorWithProb(Src, Dst, Prob);
529  }
530 
531  virtual ~GISelSwitchLowering() = default;
532 
533  private:
534  IRTranslator *IRT;
535  };
536 
537  std::unique_ptr<GISelSwitchLowering> SL;
538 
539  // * Insert all the code needed to materialize the constants
540  // at the proper place. E.g., Entry block or dominator block
541  // of each constant depending on how fancy we want to be.
542  // * Clear the different maps.
543  void finalizeFunction();
544 
545  // Handle emitting jump tables for each basic block.
546  void finalizeBasicBlock();
547 
548  /// Get the VRegs that represent \p Val.
549  /// Non-aggregate types have just one corresponding VReg and the list can be
550  /// used as a single "unsigned". Aggregates get flattened. If such VRegs do
551  /// not exist, they are created.
552  ArrayRef<Register> getOrCreateVRegs(const Value &Val);
553 
554  Register getOrCreateVReg(const Value &Val) {
555  auto Regs = getOrCreateVRegs(Val);
556  if (Regs.empty())
557  return 0;
558  assert(Regs.size() == 1 &&
559  "attempt to get single VReg for aggregate or void");
560  return Regs[0];
561  }
562 
563  /// Allocate some vregs and offsets in the VMap. Then populate just the
564  /// offsets while leaving the vregs empty.
565  ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
566 
567  /// Get the frame index that represents \p Val.
568  /// If such VReg does not exist, it is created.
569  int getOrCreateFrameIndex(const AllocaInst &AI);
570 
571  /// Get the alignment of the given memory operation instruction. This will
572  /// either be the explicitly specified value or the ABI-required alignment for
573  /// the type being accessed (according to the Module's DataLayout).
574  unsigned getMemOpAlignment(const Instruction &I);
575 
576  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
577  /// returned will be the head of the translated block (suitable for branch
578  /// destinations).
579  MachineBasicBlock &getMBB(const BasicBlock &BB);
580 
581  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
582  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
583  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
584  /// represented simply by the IR-level CFG.
585  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
586 
587  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
588  /// this is just the single MachineBasicBlock corresponding to the predecessor
589  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
590  /// preceding the original though (e.g. switch instructions).
591  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
592  auto RemappedEdge = MachinePreds.find(Edge);
593  if (RemappedEdge != MachinePreds.end())
594  return RemappedEdge->second;
595  return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
596  }
597 
598  /// Return branch probability calculated by BranchProbabilityInfo for IR
599  /// blocks.
600  BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
601  const MachineBasicBlock *Dst) const;
602 
603  void addSuccessorWithProb(MachineBasicBlock *Src, MachineBasicBlock *Dst,
604  BranchProbability Prob);
605 
606 public:
607  // Ctor, nothing fancy.
608  IRTranslator();
609 
610  StringRef getPassName() const override { return "IRTranslator"; }
611 
612  void getAnalysisUsage(AnalysisUsage &AU) const override;
613 
614  // Algo:
615  // CallLowering = MF.subtarget.getCallLowering()
616  // F = MF.getParent()
617  // MIRBuilder.reset(MF)
618  // getMBB(F.getEntryBB())
619  // CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
620  // for each bb in F
621  // getMBB(bb)
622  // for each inst in bb
623  // if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
624  // report_fatal_error("Don't know how to translate input");
625  // finalize()
626  bool runOnMachineFunction(MachineFunction &MF) override;
627 };
628 
629 } // end namespace llvm
630 
631 #endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
CaseClusterVector::iterator CaseClusterIt
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Various leaf nodes.
Definition: ISDOpcodes.h:59
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1100
This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: IRTranslator.h:610
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
return AArch64::GPR64RegClass contains(Reg)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Target-Independent Code Generator Pass Configuration Options.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
BasicBlockListType::iterator iterator
unsigned const MachineRegisterInfo * MRI
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
This is an important base class in LLVM.
Definition: Constant.h:41
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
Helper class to build MachineInstr.
Represent the analysis usage information of a pass.
static BranchProbability getUnknown()
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
A BumpPtrAllocator that allows only elements of a specific type to be allocated.
Definition: Allocator.h:441
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
static char ID
Definition: IRTranslator.h:63
could "use" a pointer
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
an instruction to allocate memory on the stack
Definition: Instructions.h:59