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IRTranslator.h
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the IRTranslator pass.
10 /// This pass is responsible for translating LLVM IR into MachineInstr.
11 /// It uses target hooks to lower the ABI but aside from that, the pass
12 /// generated code is generic. This is the default translator used for
13 /// GlobalISel.
14 ///
15 /// \todo Replace the comments with actual doxygen comments.
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
19 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
20 
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include "llvm/Support/Allocator.h"
28 #include <memory>
29 #include <utility>
30 
31 namespace llvm {
32 
33 class AllocaInst;
34 class BasicBlock;
35 class CallInst;
36 class CallLowering;
37 class Constant;
38 class DataLayout;
39 class Instruction;
40 class MachineBasicBlock;
41 class MachineFunction;
42 class MachineInstr;
43 class MachineRegisterInfo;
44 class OptimizationRemarkEmitter;
45 class PHINode;
46 class TargetPassConfig;
47 class User;
48 class Value;
49 
50 // Technically the pass should run on an hypothetical MachineModule,
51 // since it should translate Global into some sort of MachineGlobal.
52 // The MachineGlobal should ultimately just be a transfer of ownership of
53 // the interesting bits that are relevant to represent a global value.
54 // That being said, we could investigate what would it cost to just duplicate
55 // the information from the LLVM IR.
56 // The idea is that ultimately we would be able to free up the memory used
57 // by the LLVM IR as soon as the translation is over.
59 public:
60  static char ID;
61 
62 private:
63  /// Interface used to lower the everything related to calls.
64  const CallLowering *CLI;
65 
66  /// This class contains the mapping between the Values to vreg related data.
67  class ValueToVRegInfo {
68  public:
69  ValueToVRegInfo() = default;
70 
71  using VRegListT = SmallVector<unsigned, 1>;
72  using OffsetListT = SmallVector<uint64_t, 1>;
73 
74  using const_vreg_iterator =
76  using const_offset_iterator =
78 
79  inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); }
80 
81  VRegListT *getVRegs(const Value &V) {
82  auto It = ValToVRegs.find(&V);
83  if (It != ValToVRegs.end())
84  return It->second;
85 
86  return insertVRegs(V);
87  }
88 
89  OffsetListT *getOffsets(const Value &V) {
90  auto It = TypeToOffsets.find(V.getType());
91  if (It != TypeToOffsets.end())
92  return It->second;
93 
94  return insertOffsets(V);
95  }
96 
97  const_vreg_iterator findVRegs(const Value &V) const {
98  return ValToVRegs.find(&V);
99  }
100 
101  bool contains(const Value &V) const {
102  return ValToVRegs.find(&V) != ValToVRegs.end();
103  }
104 
105  void reset() {
106  ValToVRegs.clear();
107  TypeToOffsets.clear();
108  VRegAlloc.DestroyAll();
109  OffsetAlloc.DestroyAll();
110  }
111 
112  private:
113  VRegListT *insertVRegs(const Value &V) {
114  assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists");
115 
116  // We placement new using our fast allocator since we never try to free
117  // the vectors until translation is finished.
118  auto *VRegList = new (VRegAlloc.Allocate()) VRegListT();
119  ValToVRegs[&V] = VRegList;
120  return VRegList;
121  }
122 
123  OffsetListT *insertOffsets(const Value &V) {
124  assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() &&
125  "Type already exists");
126 
127  auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT();
128  TypeToOffsets[V.getType()] = OffsetList;
129  return OffsetList;
130  }
133 
134  // We store pointers to vectors here since references may be invalidated
135  // while we hold them if we stored the vectors directly.
138  };
139 
140  /// Mapping of the values of the current LLVM IR function to the related
141  /// virtual registers and offsets.
142  ValueToVRegInfo VMap;
143 
144  // N.b. it's not completely obvious that this will be sufficient for every
145  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
146  // lives.
148 
149  // One BasicBlock can be translated to multiple MachineBasicBlocks. For such
150  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
151  // a mapping between the edges arriving at the BasicBlock to the corresponding
152  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
153  // single MachineBasicBlock may also end up in this Map.
154  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
156 
157  // List of stubbed PHI instructions, for values and basic blocks to be filled
158  // in once all MachineBasicBlocks have been created.
160  PendingPHIs;
161 
162  /// Record of what frame index has been allocated to specified allocas for
163  /// this function.
165 
166  /// \name Methods for translating form LLVM IR to MachineInstr.
167  /// \see ::translate for general information on the translate methods.
168  /// @{
169 
170  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
171  /// Insert the newly translated instruction(s) right where the CurBuilder
172  /// is set.
173  ///
174  /// The general algorithm is:
175  /// 1. Look for a virtual register for each operand or
176  /// create one.
177  /// 2 Update the VMap accordingly.
178  /// 2.alt. For constant arguments, if they are compile time constants,
179  /// produce an immediate in the right operand and do not touch
180  /// ValToReg. Actually we will go with a virtual register for each
181  /// constants because it may be expensive to actually materialize the
182  /// constant. Moreover, if the constant spans on several instructions,
183  /// CSE may not catch them.
184  /// => Update ValToVReg and remember that we saw a constant in Constants.
185  /// We will materialize all the constants in finalize.
186  /// Note: we would need to do something so that we can recognize such operand
187  /// as constants.
188  /// 3. Create the generic instruction.
189  ///
190  /// \return true if the translation succeeded.
191  bool translate(const Instruction &Inst);
192 
193  /// Materialize \p C into virtual-register \p Reg. The generic instructions
194  /// performing this materialization will be inserted into the entry block of
195  /// the function.
196  ///
197  /// \return true if the materialization succeeded.
198  bool translate(const Constant &C, unsigned Reg);
199 
200  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
201  /// emitted.
202  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
203 
204  /// Translate an LLVM load instruction into generic IR.
205  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
206 
207  /// Translate an LLVM store instruction into generic IR.
208  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
209 
210  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
211  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
212  unsigned ID);
213 
214  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
215 
216  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
217  MachineIRBuilder &MIRBuilder);
218 
219  /// Helper function for translateSimpleIntrinsic.
220  /// \return The generic opcode for \p IntrinsicID if \p IntrinsicID is a
221  /// simple intrinsic (ceil, fabs, etc.). Otherwise, returns
222  /// Intrinsic::not_intrinsic.
223  unsigned getSimpleIntrinsicOpcode(Intrinsic::ID ID);
224 
225  /// Translates the intrinsics defined in getSimpleIntrinsicOpcode.
226  /// \return true if the translation succeeded.
227  bool translateSimpleIntrinsic(const CallInst &CI, Intrinsic::ID ID,
228  MachineIRBuilder &MIRBuilder);
229 
230  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
231  MachineIRBuilder &MIRBuilder);
232 
233  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
234 
235  // FIXME: temporary function to expose previous interface to call lowering
236  // until it is refactored.
237  /// Combines all component registers of \p V into a single scalar with size
238  /// "max(Offsets) + last size".
239  unsigned packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
240 
241  void unpackRegs(const Value &V, unsigned Src, MachineIRBuilder &MIRBuilder);
242 
243  /// Returns true if the value should be split into multiple LLTs.
244  /// If \p Offsets is given then the split type's offsets will be stored in it.
245  /// If \p Offsets is not empty it will be cleared first.
246  bool valueIsSplit(const Value &V,
248 
249  /// Translate call instruction.
250  /// \pre \p U is a call instruction.
251  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
252 
253  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
254 
255  bool translateCallBr(const User &U, MachineIRBuilder &MIRBuilder);
256 
257  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
258 
259  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
260  /// given generic Opcode.
261  bool translateCast(unsigned Opcode, const User &U,
262  MachineIRBuilder &MIRBuilder);
263 
264  /// Translate a phi instruction.
265  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
266 
267  /// Translate a comparison (icmp or fcmp) instruction or constant.
268  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
269 
270  /// Translate an integer compare instruction (or constant).
271  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
272  return translateCompare(U, MIRBuilder);
273  }
274 
275  /// Translate a floating-point compare instruction (or constant).
276  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
277  return translateCompare(U, MIRBuilder);
278  }
279 
280  /// Add remaining operands onto phis we've translated. Executed after all
281  /// MachineBasicBlocks for the function have been created.
282  void finishPendingPhis();
283 
284  /// Translate \p Inst into a binary operation \p Opcode.
285  /// \pre \p U is a binary operation.
286  bool translateBinaryOp(unsigned Opcode, const User &U,
287  MachineIRBuilder &MIRBuilder);
288 
289  /// Translate branch (br) instruction.
290  /// \pre \p U is a branch instruction.
291  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
292 
293  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
294 
295  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
296 
297  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
298 
299  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
300 
301  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
302 
303  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
304 
305  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
306 
307  /// Translate return (ret) instruction.
308  /// The target needs to implement CallLowering::lowerReturn for
309  /// this to succeed.
310  /// \pre \p U is a return instruction.
311  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
312 
313  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
314 
315  bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
316 
317  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
318  return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
319  }
320  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
321  return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
322  }
323  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
324  return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
325  }
326  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
327  return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
328  }
329  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
330  return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
331  }
332  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
333  return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
334  }
335 
336  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
337  return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
338  }
339  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
340  return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
341  }
342  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
343  return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
344  }
345  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
346  return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
347  }
348  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
349  return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
350  }
351  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
352  return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
353  }
354  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
355  return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
356  }
357  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
358  return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
359  }
360  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
361  return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
362  }
363  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
364  return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
365  }
366  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
367  return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
368  }
369  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
370  return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
371  }
372  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
373  return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
374  }
375  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
376  return true;
377  }
378  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
379  return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
380  }
381 
382  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
383  return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
384  }
385 
386  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
387  return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
388  }
389  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
390  return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
391  }
392  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
393  return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
394  }
395 
396  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
397  return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
398  }
399  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
400  return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
401  }
402  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
403  return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
404  }
405  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
406  return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
407  }
408 
409  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
410 
411  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
412 
413  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
414 
415  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
416 
417  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
418  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
419 
420  // Stubs to keep the compiler happy while we implement the rest of the
421  // translation.
422  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
423  return false;
424  }
425  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
426  return false;
427  }
428  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
429  return false;
430  }
431  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
432  return false;
433  }
434  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
435  return false;
436  }
437  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
438  return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
439  }
440  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
441  return false;
442  }
443  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
444  return false;
445  }
446  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
447  return false;
448  }
449  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
450  return false;
451  }
452 
453  /// @}
454 
455  // Builder for machine instruction a la IRBuilder.
456  // I.e., compared to regular MIBuilder, this one also inserts the instruction
457  // in the current block, it can creates block, etc., basically a kind of
458  // IRBuilder, but for Machine IR.
459  // CSEMIRBuilder CurBuilder;
460  std::unique_ptr<MachineIRBuilder> CurBuilder;
461 
462  // Builder set to the entry block (just after ABI lowering instructions). Used
463  // as a convenient location for Constants.
464  // CSEMIRBuilder EntryBuilder;
465  std::unique_ptr<MachineIRBuilder> EntryBuilder;
466 
467  // The MachineFunction currently being translated.
468  MachineFunction *MF;
469 
470  /// MachineRegisterInfo used to create virtual registers.
471  MachineRegisterInfo *MRI = nullptr;
472 
473  const DataLayout *DL;
474 
475  /// Current target configuration. Controls how the pass handles errors.
476  const TargetPassConfig *TPC;
477 
478  /// Current optimization remark emitter. Used to report failures.
479  std::unique_ptr<OptimizationRemarkEmitter> ORE;
480 
481  // * Insert all the code needed to materialize the constants
482  // at the proper place. E.g., Entry block or dominator block
483  // of each constant depending on how fancy we want to be.
484  // * Clear the different maps.
485  void finalizeFunction();
486 
487  /// Get the VRegs that represent \p Val.
488  /// Non-aggregate types have just one corresponding VReg and the list can be
489  /// used as a single "unsigned". Aggregates get flattened. If such VRegs do
490  /// not exist, they are created.
491  ArrayRef<unsigned> getOrCreateVRegs(const Value &Val);
492 
493  unsigned getOrCreateVReg(const Value &Val) {
494  auto Regs = getOrCreateVRegs(Val);
495  if (Regs.empty())
496  return 0;
497  assert(Regs.size() == 1 &&
498  "attempt to get single VReg for aggregate or void");
499  return Regs[0];
500  }
501 
502  /// Allocate some vregs and offsets in the VMap. Then populate just the
503  /// offsets while leaving the vregs empty.
504  ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
505 
506  /// Get the frame index that represents \p Val.
507  /// If such VReg does not exist, it is created.
508  int getOrCreateFrameIndex(const AllocaInst &AI);
509 
510  /// Get the alignment of the given memory operation instruction. This will
511  /// either be the explicitly specified value or the ABI-required alignment for
512  /// the type being accessed (according to the Module's DataLayout).
513  unsigned getMemOpAlignment(const Instruction &I);
514 
515  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
516  /// returned will be the head of the translated block (suitable for branch
517  /// destinations).
518  MachineBasicBlock &getMBB(const BasicBlock &BB);
519 
520  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
521  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
522  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
523  /// represented simply by the IR-level CFG.
524  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
525 
526  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
527  /// this is just the single MachineBasicBlock corresponding to the predecessor
528  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
529  /// preceding the original though (e.g. switch instructions).
530  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
531  auto RemappedEdge = MachinePreds.find(Edge);
532  if (RemappedEdge != MachinePreds.end())
533  return RemappedEdge->second;
534  return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
535  }
536 
537 public:
538  // Ctor, nothing fancy.
539  IRTranslator();
540 
541  StringRef getPassName() const override { return "IRTranslator"; }
542 
543  void getAnalysisUsage(AnalysisUsage &AU) const override;
544 
545  // Algo:
546  // CallLowering = MF.subtarget.getCallLowering()
547  // F = MF.getParent()
548  // MIRBuilder.reset(MF)
549  // getMBB(F.getEntryBB())
550  // CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
551  // for each bb in F
552  // getMBB(bb)
553  // for each inst in bb
554  // if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
555  // report_fatal_error("Don't know how to translate input");
556  // finalize()
557  bool runOnMachineFunction(MachineFunction &MF) override;
558 };
559 
560 } // end namespace llvm
561 
562 #endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Various leaf nodes.
Definition: ISDOpcodes.h:59
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1026
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: IRTranslator.h:541
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
return AArch64::GPR64RegClass contains(Reg)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Target-Independent Code Generator Pass Configuration Options.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
unsigned const MachineRegisterInfo * MRI
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
This is an important base class in LLVM.
Definition: Constant.h:41
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
Helper class to build MachineInstr.
Represent the analysis usage information of a pass.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
A BumpPtrAllocator that allows only elements of a specific type to be allocated.
Definition: Allocator.h:441
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
static char ID
Definition: IRTranslator.h:60
could "use" a pointer
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define I(x, y, z)
Definition: MD5.cpp:58
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
an instruction to allocate memory on the stack
Definition: Instructions.h:59