LLVM  6.0.0svn
Macros | Functions | Variables
InstrEmitter.cpp File Reference
#include "InstrEmitter.h"
#include "SDNodeDbgValue.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSubtargetInfo.h"
Include dependency graph for InstrEmitter.cpp:

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Macros

#define DEBUG_TYPE   "instr-emitter"
 

Functions

static unsigned countOperands (SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
 countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chain operand, then an optional glue operand. More...
 

Variables

const unsigned MinRCSize = 4
 MinRCSize - Smallest register class we allow when constraining virtual registers. More...
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "instr-emitter"

Definition at line 34 of file InstrEmitter.cpp.

Function Documentation

◆ countOperands()

static unsigned countOperands ( SDNode Node,
unsigned  NumExpUses,
unsigned NumImpUses 
)
static

countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chain operand, then an optional glue operand.

Compute the number of actual operands that will go into the resulting MachineInstr.

Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding the chain and glue. These operands may be implicit on the machine instr.

Definition at line 61 of file InstrEmitter.cpp.

References llvm::MachineInstrBuilder::addBlockAddress(), llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addFPImm(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addJumpTableIndex(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addRegMask(), llvm::MachineInstrBuilder::addSym(), llvm::MachineInstrBuilder::addTargetIndex(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), C, llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::ISD::CopyFromReg, llvm::ISD::CopyToReg, llvm::InstrEmitter::CountResults(), llvm::HexagonISD::CP, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, DefMI, llvm::dyn_cast(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::erase(), F(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::MCInstrInfo::get(), llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::TargetRegisterClass::getCopyCost(), llvm::MachineFunction::getDataLayout(), llvm::SDValue::getDebugLoc(), llvm::SDNode::getDebugLoc(), llvm::getDebugRegState(), llvm::getDefRegState(), llvm::MachineInstr::getDesc(), llvm::getImplRegState(), llvm::getKillRegState(), llvm::SDValue::getMachineOpcode(), llvm::SDNode::getMachineOpcode(), llvm::TargetRegisterInfo::getMatchingSuperRegClass(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::SDValue::getNode(), llvm::MCInstrDesc::getNumDefs(), llvm::User::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::MachineInstr::getOperand(), llvm::SDNode::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::DataLayout::getPrefTypeAlignment(), getReg(), llvm::RegisterSDNode::getReg(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SDValue::getResNo(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::TargetRegisterInfo::getSubClassWithSubReg(), llvm::MCRegisterInfo::getSubReg(), llvm::DataLayout::getTypeAllocSize(), llvm::SDValue::getValueType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::TargetRegisterClass::hasSubClassEq(), I, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineBasicBlock::insert(), llvm::TargetRegisterClass::isAllocatable(), llvm::TargetInstrInfo::isCoalescableExtInstr(), llvm::MachineOperand::isImplicit(), llvm::SDValue::isMachineOpcode(), llvm::MCOperandInfo::isOptionalDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::TargetLoweringBase::isTypeLegal(), llvm::TargetRegisterInfo::isTypeLegalForClass(), llvm::MCInstrDesc::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::HexagonISD::JT, llvm_unreachable, N, llvm::MCInstrDesc::OpInfo, llvm::MVT::Other, llvm::NVPTX::PTXCvtMode::RM, llvm::NVPTX::PTXCvtMode::RN, llvm::MachineRegisterInfo::setRegClass(), llvm::MVT::SimpleTy, SubReg, llvm::MCOI::TIED_TO, llvm::SDNode::use_begin(), and llvm::SDNode::uses().

Referenced by llvm::InstrEmitter::EmitDbgValue().

Variable Documentation

◆ MinRCSize

const unsigned MinRCSize = 4

MinRCSize - Smallest register class we allow when constraining virtual registers.

If satisfying all register class constraints would require using a smaller register class, emit a COPY to a new virtual register instead.

Definition at line 40 of file InstrEmitter.cpp.