LLVM  7.0.0svn
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
12 // selection.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/Support/Debug.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "instr-emitter"
35 
36 /// MinRCSize - Smallest register class we allow when constraining virtual
37 /// registers. If satisfying all register class constraints would require
38 /// using a smaller register class, emit a COPY to a new virtual register
39 /// instead.
40 const unsigned MinRCSize = 4;
41 
42 /// CountResults - The results of target nodes have register or immediate
43 /// operands first, then an optional chain, and optional glue operands (which do
44 /// not go into the resulting MachineInstr).
46  unsigned N = Node->getNumValues();
47  while (N && Node->getValueType(N - 1) == MVT::Glue)
48  --N;
49  if (N && Node->getValueType(N - 1) == MVT::Other)
50  --N; // Skip over chain result.
51  return N;
52 }
53 
54 /// countOperands - The inputs to target nodes have any actual inputs first,
55 /// followed by an optional chain operand, then an optional glue operand.
56 /// Compute the number of actual operands that will go into the resulting
57 /// MachineInstr.
58 ///
59 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60 /// the chain and glue. These operands may be implicit on the machine instr.
61 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62  unsigned &NumImpUses) {
63  unsigned N = Node->getNumOperands();
64  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
65  --N;
66  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
67  --N; // Ignore chain if it exists.
68 
69  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
70  NumImpUses = N - NumExpUses;
71  for (unsigned I = N; I > NumExpUses; --I) {
72  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
73  continue;
74  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
76  continue;
77  NumImpUses = N - I;
78  break;
79  }
80 
81  return N;
82 }
83 
84 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
85 /// implicit physical register output.
86 void InstrEmitter::
87 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
88  unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89  unsigned VRBase = 0;
91  // Just use the input register directly!
92  SDValue Op(Node, ResNo);
93  if (IsClone)
94  VRBaseMap.erase(Op);
95  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
96  (void)isNew; // Silence compiler warning.
97  assert(isNew && "Node emitted out of order - early");
98  return;
99  }
100 
101  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102  // the CopyToReg'd destination register instead of creating a new vreg.
103  bool MatchReg = true;
104  const TargetRegisterClass *UseRC = nullptr;
105  MVT VT = Node->getSimpleValueType(ResNo);
106 
107  // Stick to the preferred register classes for legal types.
108  if (TLI->isTypeLegal(VT))
109  UseRC = TLI->getRegClassFor(VT);
110 
111  if (!IsClone && !IsCloned)
112  for (SDNode *User : Node->uses()) {
113  bool Match = true;
114  if (User->getOpcode() == ISD::CopyToReg &&
115  User->getOperand(2).getNode() == Node &&
116  User->getOperand(2).getResNo() == ResNo) {
117  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119  VRBase = DestReg;
120  Match = false;
121  } else if (DestReg != SrcReg)
122  Match = false;
123  } else {
124  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125  SDValue Op = User->getOperand(i);
126  if (Op.getNode() != Node || Op.getResNo() != ResNo)
127  continue;
128  MVT VT = Node->getSimpleValueType(Op.getResNo());
129  if (VT == MVT::Other || VT == MVT::Glue)
130  continue;
131  Match = false;
132  if (User->isMachineOpcode()) {
133  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134  const TargetRegisterClass *RC = nullptr;
135  if (i+II.getNumDefs() < II.getNumOperands()) {
136  RC = TRI->getAllocatableClass(
137  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
138  }
139  if (!UseRC)
140  UseRC = RC;
141  else if (RC) {
142  const TargetRegisterClass *ComRC =
143  TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
144  // If multiple uses expect disjoint register classes, we emit
145  // copies in AddRegisterOperand.
146  if (ComRC)
147  UseRC = ComRC;
148  }
149  }
150  }
151  }
152  MatchReg &= Match;
153  if (VRBase)
154  break;
155  }
156 
157  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
158  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 
160  // Figure out the register class to create for the destreg.
161  if (VRBase) {
162  DstRC = MRI->getRegClass(VRBase);
163  } else if (UseRC) {
164  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
165  "Incompatible phys register def and uses!");
166  DstRC = UseRC;
167  } else {
168  DstRC = TLI->getRegClassFor(VT);
169  }
170 
171  // If all uses are reading from the src physical register and copying the
172  // register is either impossible or very expensive, then don't create a copy.
173  if (MatchReg && SrcRC->getCopyCost() < 0) {
174  VRBase = SrcReg;
175  } else {
176  // Create the reg, emit the copy.
177  VRBase = MRI->createVirtualRegister(DstRC);
178  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
179  VRBase).addReg(SrcReg);
180  }
181 
182  SDValue Op(Node, ResNo);
183  if (IsClone)
184  VRBaseMap.erase(Op);
185  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
186  (void)isNew; // Silence compiler warning.
187  assert(isNew && "Node emitted out of order - early");
188 }
189 
190 /// getDstOfCopyToRegUse - If the only use of the specified result number of
191 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
192 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
193  unsigned ResNo) const {
194  if (!Node->hasOneUse())
195  return 0;
196 
197  SDNode *User = *Node->use_begin();
198  if (User->getOpcode() == ISD::CopyToReg &&
199  User->getOperand(2).getNode() == Node &&
200  User->getOperand(2).getResNo() == ResNo) {
201  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
203  return Reg;
204  }
205  return 0;
206 }
207 
208 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
209  MachineInstrBuilder &MIB,
210  const MCInstrDesc &II,
211  bool IsClone, bool IsCloned,
212  DenseMap<SDValue, unsigned> &VRBaseMap) {
213  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
214  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
215 
216  unsigned NumResults = CountResults(Node);
217  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
218  // If the specific node value is only used by a CopyToReg and the dest reg
219  // is a vreg in the same register class, use the CopyToReg'd destination
220  // register instead of creating a new vreg.
221  unsigned VRBase = 0;
222  const TargetRegisterClass *RC =
223  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
224  // Always let the value type influence the used register class. The
225  // constraints on the instruction may be too lax to represent the value
226  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
227  // the 32-bit float super-class (X86::FR32).
228  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
229  const TargetRegisterClass *VTRC =
230  TLI->getRegClassFor(Node->getSimpleValueType(i));
231  if (RC)
232  VTRC = TRI->getCommonSubClass(RC, VTRC);
233  if (VTRC)
234  RC = VTRC;
235  }
236 
237  if (II.OpInfo[i].isOptionalDef()) {
238  // Optional def must be a physical register.
239  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
241  MIB.addReg(VRBase, RegState::Define);
242  }
243 
244  if (!VRBase && !IsClone && !IsCloned)
245  for (SDNode *User : Node->uses()) {
246  if (User->getOpcode() == ISD::CopyToReg &&
247  User->getOperand(2).getNode() == Node &&
248  User->getOperand(2).getResNo() == i) {
249  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
251  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252  if (RegRC == RC) {
253  VRBase = Reg;
254  MIB.addReg(VRBase, RegState::Define);
255  break;
256  }
257  }
258  }
259  }
260 
261  // Create the result registers for this node and add the result regs to
262  // the machine instruction.
263  if (VRBase == 0) {
264  assert(RC && "Isn't a register operand!");
265  VRBase = MRI->createVirtualRegister(RC);
266  MIB.addReg(VRBase, RegState::Define);
267  }
268 
269  // If this def corresponds to a result of the SDNode insert the VRBase into
270  // the lookup map.
271  if (i < NumResults) {
272  SDValue Op(Node, i);
273  if (IsClone)
274  VRBaseMap.erase(Op);
275  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
276  (void)isNew; // Silence compiler warning.
277  assert(isNew && "Node emitted out of order - early");
278  }
279  }
280 }
281 
282 /// getVR - Return the virtual register corresponding to the specified result
283 /// of the specified node.
284 unsigned InstrEmitter::getVR(SDValue Op,
285  DenseMap<SDValue, unsigned> &VRBaseMap) {
286  if (Op.isMachineOpcode() &&
287  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
288  // Add an IMPLICIT_DEF instruction before every use.
289  unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
290  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
291  // does not include operand register class info.
292  if (!VReg) {
293  const TargetRegisterClass *RC =
295  VReg = MRI->createVirtualRegister(RC);
296  }
297  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
298  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
299  return VReg;
300  }
301 
303  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
304  return I->second;
305 }
306 
307 
308 /// AddRegisterOperand - Add the specified register as an operand to the
309 /// specified machine instr. Insert register copies if the register is
310 /// not in the required register class.
311 void
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
313  SDValue Op,
314  unsigned IIOpNum,
315  const MCInstrDesc *II,
316  DenseMap<SDValue, unsigned> &VRBaseMap,
317  bool IsDebug, bool IsClone, bool IsCloned) {
318  assert(Op.getValueType() != MVT::Other &&
319  Op.getValueType() != MVT::Glue &&
320  "Chain and glue operands should occur at end of operand list!");
321  // Get/emit the operand.
322  unsigned VReg = getVR(Op, VRBaseMap);
323 
324  const MCInstrDesc &MCID = MIB->getDesc();
325  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326  MCID.OpInfo[IIOpNum].isOptionalDef();
327 
328  // If the instruction requires a register in a different class, create
329  // a new virtual register and copy the value into it, but first attempt to
330  // shrink VReg's register class within reason. For example, if VReg == GR32
331  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
332  if (II) {
333  const TargetRegisterClass *OpRC = nullptr;
334  if (IIOpNum < II->getNumOperands())
335  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
336 
337  if (OpRC) {
338  const TargetRegisterClass *ConstrainedRC
339  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
340  if (!ConstrainedRC) {
341  OpRC = TRI->getAllocatableClass(OpRC);
342  assert(OpRC && "Constraints cannot be fulfilled for allocation");
343  unsigned NewVReg = MRI->createVirtualRegister(OpRC);
344  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
345  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
346  VReg = NewVReg;
347  } else {
348  assert(ConstrainedRC->isAllocatable() &&
349  "Constraining an allocatable VReg produced an unallocatable class?");
350  }
351  }
352  }
353 
354  // If this value has only one use, that use is a kill. This is a
355  // conservative approximation. InstrEmitter does trivial coalescing
356  // with CopyFromReg nodes, so don't emit kill flags for them.
357  // Avoid kill flags on Schedule cloned nodes, since there will be
358  // multiple uses.
359  // Tied operands are never killed, so we need to check that. And that
360  // means we need to determine the index of the operand.
361  bool isKill = Op.hasOneUse() &&
362  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
363  !IsDebug &&
364  !(IsClone || IsCloned);
365  if (isKill) {
366  unsigned Idx = MIB->getNumOperands();
367  while (Idx > 0 &&
368  MIB->getOperand(Idx-1).isReg() &&
369  MIB->getOperand(Idx-1).isImplicit())
370  --Idx;
371  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
372  if (isTied)
373  isKill = false;
374  }
375 
376  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
377  getDebugRegState(IsDebug));
378 }
379 
380 /// AddOperand - Add the specified operand to the specified machine instr. II
381 /// specifies the instruction information for the node, and IIOpNum is the
382 /// operand number (in the II) that we are adding.
383 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
384  SDValue Op,
385  unsigned IIOpNum,
386  const MCInstrDesc *II,
387  DenseMap<SDValue, unsigned> &VRBaseMap,
388  bool IsDebug, bool IsClone, bool IsCloned) {
389  if (Op.isMachineOpcode()) {
390  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
391  IsDebug, IsClone, IsCloned);
392  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
393  MIB.addImm(C->getSExtValue());
394  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
395  MIB.addFPImm(F->getConstantFPValue());
396  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
397  unsigned VReg = R->getReg();
398  MVT OpVT = Op.getSimpleValueType();
399  const TargetRegisterClass *OpRC =
400  TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr;
401  const TargetRegisterClass *IIRC =
402  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
403  : nullptr;
404 
405  if (OpRC && IIRC && OpRC != IIRC &&
407  unsigned NewVReg = MRI->createVirtualRegister(IIRC);
408  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
409  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
410  VReg = NewVReg;
411  }
412  // Turn additional physreg operands into implicit uses on non-variadic
413  // instructions. This is used by call and return instructions passing
414  // arguments in registers.
415  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
416  MIB.addReg(VReg, getImplRegState(Imp));
417  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
418  MIB.addRegMask(RM->getRegMask());
419  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
420  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
421  TGA->getTargetFlags());
422  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
423  MIB.addMBB(BBNode->getBasicBlock());
424  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
425  MIB.addFrameIndex(FI->getIndex());
426  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
427  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
428  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
429  int Offset = CP->getOffset();
430  unsigned Align = CP->getAlignment();
431  Type *Type = CP->getType();
432  // MachineConstantPool wants an explicit alignment.
433  if (Align == 0) {
434  Align = MF->getDataLayout().getPrefTypeAlignment(Type);
435  if (Align == 0) {
436  // Alignment of vector types. FIXME!
437  Align = MF->getDataLayout().getTypeAllocSize(Type);
438  }
439  }
440 
441  unsigned Idx;
443  if (CP->isMachineConstantPoolEntry())
444  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
445  else
446  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
447  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
448  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
449  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
450  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
451  MIB.addSym(SymNode->getMCSymbol());
452  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
453  MIB.addBlockAddress(BA->getBlockAddress(),
454  BA->getOffset(),
455  BA->getTargetFlags());
456  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
457  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
458  } else {
459  assert(Op.getValueType() != MVT::Other &&
460  Op.getValueType() != MVT::Glue &&
461  "Chain and glue operands should occur at end of operand list!");
462  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
463  IsDebug, IsClone, IsCloned);
464  }
465 }
466 
467 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
468  MVT VT, const DebugLoc &DL) {
469  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
470  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
471 
472  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
473  // within reason.
474  if (RC && RC != VRC)
475  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
476 
477  // VReg has been adjusted. It can be used with SubIdx operands now.
478  if (RC)
479  return VReg;
480 
481  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
482  // register instead.
483  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
484  assert(RC && "No legal register class for VT supports that SubIdx");
485  unsigned NewReg = MRI->createVirtualRegister(RC);
486  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
487  .addReg(VReg);
488  return NewReg;
489 }
490 
491 /// EmitSubregNode - Generate machine code for subreg nodes.
492 ///
493 void InstrEmitter::EmitSubregNode(SDNode *Node,
494  DenseMap<SDValue, unsigned> &VRBaseMap,
495  bool IsClone, bool IsCloned) {
496  unsigned VRBase = 0;
497  unsigned Opc = Node->getMachineOpcode();
498 
499  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
500  // the CopyToReg'd destination register instead of creating a new vreg.
501  for (SDNode *User : Node->uses()) {
502  if (User->getOpcode() == ISD::CopyToReg &&
503  User->getOperand(2).getNode() == Node) {
504  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
506  VRBase = DestReg;
507  break;
508  }
509  }
510  }
511 
512  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
513  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
514  // constraints on the %dst register, COPY can target all legal register
515  // classes.
516  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
517  const TargetRegisterClass *TRC =
518  TLI->getRegClassFor(Node->getSimpleValueType(0));
519 
520  unsigned Reg;
524  Reg = R->getReg();
525  DefMI = nullptr;
526  } else {
527  Reg = getVR(Node->getOperand(0), VRBaseMap);
528  DefMI = MRI->getVRegDef(Reg);
529  }
530 
531  unsigned SrcReg, DstReg, DefSubIdx;
532  if (DefMI &&
533  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
534  SubIdx == DefSubIdx &&
535  TRC == MRI->getRegClass(SrcReg)) {
536  // Optimize these:
537  // r1025 = s/zext r1024, 4
538  // r1026 = extract_subreg r1025, 4
539  // to a copy
540  // r1026 = copy r1024
541  VRBase = MRI->createVirtualRegister(TRC);
542  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
544  MRI->clearKillFlags(SrcReg);
545  } else {
546  // Reg may not support a SubIdx sub-register, and we may need to
547  // constrain its register class or issue a COPY to a compatible register
548  // class.
550  Reg = ConstrainForSubReg(Reg, SubIdx,
551  Node->getOperand(0).getSimpleValueType(),
552  Node->getDebugLoc());
553 
554  // Create the destreg if it is missing.
555  if (VRBase == 0)
556  VRBase = MRI->createVirtualRegister(TRC);
557 
558  // Create the extract_subreg machine instruction.
559  MachineInstrBuilder CopyMI =
560  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
561  TII->get(TargetOpcode::COPY), VRBase);
563  CopyMI.addReg(Reg, 0, SubIdx);
564  else
565  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
566  }
567  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
568  Opc == TargetOpcode::SUBREG_TO_REG) {
569  SDValue N0 = Node->getOperand(0);
570  SDValue N1 = Node->getOperand(1);
571  SDValue N2 = Node->getOperand(2);
572  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
573 
574  // Figure out the register class to create for the destreg. It should be
575  // the largest legal register class supporting SubIdx sub-registers.
576  // RegisterCoalescer will constrain it further if it decides to eliminate
577  // the INSERT_SUBREG instruction.
578  //
579  // %dst = INSERT_SUBREG %src, %sub, SubIdx
580  //
581  // is lowered by TwoAddressInstructionPass to:
582  //
583  // %dst = COPY %src
584  // %dst:SubIdx = COPY %sub
585  //
586  // There is no constraint on the %src register class.
587  //
588  const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
589  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
590  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
591 
592  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
593  VRBase = MRI->createVirtualRegister(SRC);
594 
595  // Create the insert_subreg or subreg_to_reg machine instruction.
596  MachineInstrBuilder MIB =
597  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
598 
599  // If creating a subreg_to_reg, then the first input operand
600  // is an implicit value immediate, otherwise it's a register
601  if (Opc == TargetOpcode::SUBREG_TO_REG) {
602  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
603  MIB.addImm(SD->getZExtValue());
604  } else
605  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
606  IsClone, IsCloned);
607  // Add the subregister being inserted
608  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
609  IsClone, IsCloned);
610  MIB.addImm(SubIdx);
611  MBB->insert(InsertPos, MIB);
612  } else
613  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
614 
615  SDValue Op(Node, 0);
616  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
617  (void)isNew; // Silence compiler warning.
618  assert(isNew && "Node emitted out of order - early");
619 }
620 
621 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
622 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
623 /// register is constrained to be in a particular register class.
624 ///
625 void
626 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
627  DenseMap<SDValue, unsigned> &VRBaseMap) {
628  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
629 
630  // Create the new VReg in the destination class and emit a copy.
631  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
632  const TargetRegisterClass *DstRC =
633  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
634  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
635  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
636  NewVReg).addReg(VReg);
637 
638  SDValue Op(Node, 0);
639  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
640  (void)isNew; // Silence compiler warning.
641  assert(isNew && "Node emitted out of order - early");
642 }
643 
644 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
645 ///
646 void InstrEmitter::EmitRegSequence(SDNode *Node,
647  DenseMap<SDValue, unsigned> &VRBaseMap,
648  bool IsClone, bool IsCloned) {
649  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
650  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
651  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
652  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
653  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
654  unsigned NumOps = Node->getNumOperands();
655  assert((NumOps & 1) == 1 &&
656  "REG_SEQUENCE must have an odd number of operands!");
657  for (unsigned i = 1; i != NumOps; ++i) {
658  SDValue Op = Node->getOperand(i);
659  if ((i & 1) == 0) {
661  // Skip physical registers as they don't have a vreg to get and we'll
662  // insert copies for them in TwoAddressInstructionPass anyway.
664  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
665  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
666  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
667  const TargetRegisterClass *SRC =
668  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
669  if (SRC && SRC != RC) {
670  MRI->setRegClass(NewVReg, SRC);
671  RC = SRC;
672  }
673  }
674  }
675  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
676  IsClone, IsCloned);
677  }
678 
679  MBB->insert(InsertPos, MIB);
680  SDValue Op(Node, 0);
681  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
682  (void)isNew; // Silence compiler warning.
683  assert(isNew && "Node emitted out of order - early");
684 }
685 
686 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
687 ///
688 MachineInstr *
690  DenseMap<SDValue, unsigned> &VRBaseMap) {
691  MDNode *Var = SD->getVariable();
692  MDNode *Expr = SD->getExpression();
693  DebugLoc DL = SD->getDebugLoc();
694  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
695  "Expected inlined-at fields to agree");
696 
697  if (SD->getKind() == SDDbgValue::FRAMEIX) {
698  // Stack address; this needs to be lowered in target-dependent fashion.
699  // EmitTargetCodeForFrameDebugValue is responsible for allocation.
700  return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
701  .addFrameIndex(SD->getFrameIx())
702  .addImm(0)
703  .addMetadata(Var)
704  .addMetadata(Expr);
705  }
706  // Otherwise, we're going to create an instruction here.
707  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
708  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
709  if (SD->getKind() == SDDbgValue::SDNODE) {
710  SDNode *Node = SD->getSDNode();
711  SDValue Op = SDValue(Node, SD->getResNo());
712  // It's possible we replaced this SDNode with other(s) and therefore
713  // didn't generate code for it. It's better to catch these cases where
714  // they happen and transfer the debug info, but trying to guarantee that
715  // in all cases would be very fragile; this is a safeguard for any
716  // that were missed.
718  if (I==VRBaseMap.end())
719  MIB.addReg(0U); // undef
720  else
721  AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
722  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
723  } else if (SD->getKind() == SDDbgValue::CONST) {
724  const Value *V = SD->getConst();
725  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
726  if (CI->getBitWidth() > 64)
727  MIB.addCImm(CI);
728  else
729  MIB.addImm(CI->getSExtValue());
730  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
731  MIB.addFPImm(CF);
732  } else {
733  // Could be an Undef. In any case insert an Undef so we can see what we
734  // dropped.
735  MIB.addReg(0U);
736  }
737  } else {
738  // Insert an Undef so we can see what we dropped.
739  MIB.addReg(0U);
740  }
741 
742  // Indirect addressing is indicated by an Imm as the second parameter.
743  if (SD->isIndirect())
744  MIB.addImm(0U);
745  else
746  MIB.addReg(0U, RegState::Debug);
747 
748  MIB.addMetadata(Var);
749  MIB.addMetadata(Expr);
750 
751  return &*MIB;
752 }
753 
754 /// EmitMachineNode - Generate machine code for a target-specific node and
755 /// needed dependencies.
756 ///
757 void InstrEmitter::
758 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
759  DenseMap<SDValue, unsigned> &VRBaseMap) {
760  unsigned Opc = Node->getMachineOpcode();
761 
762  // Handle subreg insert/extract specially
763  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
764  Opc == TargetOpcode::INSERT_SUBREG ||
765  Opc == TargetOpcode::SUBREG_TO_REG) {
766  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
767  return;
768  }
769 
770  // Handle COPY_TO_REGCLASS specially.
771  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
772  EmitCopyToRegClassNode(Node, VRBaseMap);
773  return;
774  }
775 
776  // Handle REG_SEQUENCE specially.
777  if (Opc == TargetOpcode::REG_SEQUENCE) {
778  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
779  return;
780  }
781 
782  if (Opc == TargetOpcode::IMPLICIT_DEF)
783  // We want a unique VR for each IMPLICIT_DEF use.
784  return;
785 
786  const MCInstrDesc &II = TII->get(Opc);
787  unsigned NumResults = CountResults(Node);
788  unsigned NumDefs = II.getNumDefs();
789  const MCPhysReg *ScratchRegs = nullptr;
790 
791  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
792  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
793  // Stackmaps do not have arguments and do not preserve their calling
794  // convention. However, to simplify runtime support, they clobber the same
795  // scratch registers as AnyRegCC.
796  unsigned CC = CallingConv::AnyReg;
797  if (Opc == TargetOpcode::PATCHPOINT) {
799  NumDefs = NumResults;
800  }
801  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
802  }
803 
804  unsigned NumImpUses = 0;
805  unsigned NodeOperands =
806  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
807  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
808 #ifndef NDEBUG
809  unsigned NumMIOperands = NodeOperands + NumResults;
810  if (II.isVariadic())
811  assert(NumMIOperands >= II.getNumOperands() &&
812  "Too few operands for a variadic node!");
813  else
814  assert(NumMIOperands >= II.getNumOperands() &&
815  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
816  NumImpUses &&
817  "#operands for dag node doesn't match .td file!");
818 #endif
819 
820  // Create the new machine instruction.
821  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
822 
823  // Add result register values for things that are defined by this
824  // instruction.
825  if (NumResults)
826  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
827 
828  // Emit all of the actual operands of this instruction, adding them to the
829  // instruction as appropriate.
830  bool HasOptPRefs = NumDefs > NumResults;
831  assert((!HasOptPRefs || !HasPhysRegOuts) &&
832  "Unable to cope with optional defs and phys regs defs!");
833  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
834  for (unsigned i = NumSkip; i != NodeOperands; ++i)
835  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
836  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
837 
838  // Add scratch registers as implicit def and early clobber
839  if (ScratchRegs)
840  for (unsigned i = 0; ScratchRegs[i]; ++i)
841  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
843 
844  // Transfer all of the memory reference descriptions of this instruction.
845  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
846  cast<MachineSDNode>(Node)->memoperands_end());
847 
848  // Insert the instruction into position in the block. This needs to
849  // happen before any custom inserter hook is called so that the
850  // hook knows where in the block to insert the replacement code.
851  MBB->insert(InsertPos, MIB);
852 
853  // The MachineInstr may also define physregs instead of virtregs. These
854  // physreg values can reach other instructions in different ways:
855  //
856  // 1. When there is a use of a Node value beyond the explicitly defined
857  // virtual registers, we emit a CopyFromReg for one of the implicitly
858  // defined physregs. This only happens when HasPhysRegOuts is true.
859  //
860  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
861  //
862  // 3. A glued instruction may implicitly use a physreg.
863  //
864  // 4. A glued instruction may use a RegisterSDNode operand.
865  //
866  // Collect all the used physreg defs, and make sure that any unused physreg
867  // defs are marked as dead.
868  SmallVector<unsigned, 8> UsedRegs;
869 
870  // Additional results must be physical register defs.
871  if (HasPhysRegOuts) {
872  for (unsigned i = NumDefs; i < NumResults; ++i) {
873  unsigned Reg = II.getImplicitDefs()[i - NumDefs];
874  if (!Node->hasAnyUseOfValue(i))
875  continue;
876  // This implicitly defined physreg has a use.
877  UsedRegs.push_back(Reg);
878  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
879  }
880  }
881 
882  // Scan the glue chain for any used physregs.
883  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
884  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
885  if (F->getOpcode() == ISD::CopyFromReg) {
886  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
887  continue;
888  } else if (F->getOpcode() == ISD::CopyToReg) {
889  // Skip CopyToReg nodes that are internal to the glue chain.
890  continue;
891  }
892  // Collect declared implicit uses.
893  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
894  UsedRegs.append(MCID.getImplicitUses(),
895  MCID.getImplicitUses() + MCID.getNumImplicitUses());
896  // In addition to declared implicit uses, we must also check for
897  // direct RegisterSDNode operands.
898  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
899  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
900  unsigned Reg = R->getReg();
902  UsedRegs.push_back(Reg);
903  }
904  }
905  }
906 
907  // Finally mark unused registers as dead.
908  if (!UsedRegs.empty() || II.getImplicitDefs())
909  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
910 
911  // Run post-isel target hook to adjust this instruction if needed.
912  if (II.hasPostISelHook())
913  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
914 }
915 
916 /// EmitSpecialNode - Generate machine code for a target-independent node and
917 /// needed dependencies.
918 void InstrEmitter::
919 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
920  DenseMap<SDValue, unsigned> &VRBaseMap) {
921  switch (Node->getOpcode()) {
922  default:
923 #ifndef NDEBUG
924  Node->dump();
925 #endif
926  llvm_unreachable("This target-independent node should have been selected!");
927  case ISD::EntryToken:
928  llvm_unreachable("EntryToken should have been excluded from the schedule!");
929  case ISD::MERGE_VALUES:
930  case ISD::TokenFactor: // fall thru
931  break;
932  case ISD::CopyToReg: {
933  unsigned SrcReg;
934  SDValue SrcVal = Node->getOperand(2);
935  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
936  SrcReg = R->getReg();
937  else
938  SrcReg = getVR(SrcVal, VRBaseMap);
939 
940  unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
941  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
942  break;
943 
944  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
945  DestReg).addReg(SrcReg);
946  break;
947  }
948  case ISD::CopyFromReg: {
949  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
950  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
951  break;
952  }
953  case ISD::EH_LABEL:
954  case ISD::ANNOTATION_LABEL: {
955  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
958  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
959  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
960  TII->get(Opc)).addSym(S);
961  break;
962  }
963 
964  case ISD::LIFETIME_START:
965  case ISD::LIFETIME_END: {
966  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
968 
970  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
971  .addFrameIndex(FI->getIndex());
972  break;
973  }
974 
975  case ISD::INLINEASM: {
976  unsigned NumOps = Node->getNumOperands();
977  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
978  --NumOps; // Ignore the glue operand.
979 
980  // Create the inline asm machine instruction.
981  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
983 
984  // Add the asm string as an external symbol operand.
985  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
986  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
987  MIB.addExternalSymbol(AsmStr);
988 
989  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
990  // bits.
991  int64_t ExtraInfo =
992  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
993  getZExtValue();
994  MIB.addImm(ExtraInfo);
995 
996  // Remember to operand index of the group flags.
997  SmallVector<unsigned, 8> GroupIdx;
998 
999  // Remember registers that are part of early-clobber defs.
1000  SmallVector<unsigned, 8> ECRegs;
1001 
1002  // Add all of the operand registers to the instruction.
1003  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1004  unsigned Flags =
1005  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1006  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1007 
1008  GroupIdx.push_back(MIB->getNumOperands());
1009  MIB.addImm(Flags);
1010  ++i; // Skip the ID value.
1011 
1012  switch (InlineAsm::getKind(Flags)) {
1013  default: llvm_unreachable("Bad flags!");
1015  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1016  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1017  // FIXME: Add dead flags for physical and virtual registers defined.
1018  // For now, mark physical register defs as implicit to help fast
1019  // regalloc. This makes inline asm look a lot like calls.
1020  MIB.addReg(Reg, RegState::Define |
1022  }
1023  break;
1026  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1027  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1030  ECRegs.push_back(Reg);
1031  }
1032  break;
1033  case InlineAsm::Kind_RegUse: // Use of register.
1034  case InlineAsm::Kind_Imm: // Immediate.
1035  case InlineAsm::Kind_Mem: // Addressing mode.
1036  // The addressing mode has been selected, just add all of the
1037  // operands to the machine instruction.
1038  for (unsigned j = 0; j != NumVals; ++j, ++i)
1039  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1040  /*IsDebug=*/false, IsClone, IsCloned);
1041 
1042  // Manually set isTied bits.
1044  unsigned DefGroup = 0;
1045  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1046  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1047  unsigned UseIdx = GroupIdx.back() + 1;
1048  for (unsigned j = 0; j != NumVals; ++j)
1049  MIB->tieOperands(DefIdx + j, UseIdx + j);
1050  }
1051  }
1052  break;
1053  }
1054  }
1055 
1056  // GCC inline assembly allows input operands to also be early-clobber
1057  // output operands (so long as the operand is written only after it's
1058  // used), but this does not match the semantics of our early-clobber flag.
1059  // If an early-clobber operand register is also an input operand register,
1060  // then remove the early-clobber flag.
1061  for (unsigned Reg : ECRegs) {
1062  if (MIB->readsRegister(Reg, TRI)) {
1063  MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
1064  assert(MO && "No def operand for clobbered register?");
1065  MO->setIsEarlyClobber(false);
1066  }
1067  }
1068 
1069  // Get the mdnode from the asm if it exists and add it to the instruction.
1071  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1072  if (MD)
1073  MIB.addMetadata(MD);
1074 
1075  MBB->insert(InsertPos, MIB);
1076  break;
1077  }
1078  }
1079 }
1080 
1081 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1082 /// at the given position in the given block.
1084  MachineBasicBlock::iterator insertpos)
1085  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1086  TII(MF->getSubtarget().getInstrInfo()),
1087  TRI(MF->getSubtarget().getRegisterInfo()),
1088  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1089  InsertPos(insertpos) {}
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:646
uint64_t CallInst * C
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:515
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
Definition: SmallVector.h:212
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:537
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:512
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Completely target-dependent object reference.
const Value * getConst() const
Returns the Value* for a constant.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:862
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
const DebugLoc & getDebugLoc() const
Return the source location info.
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:45
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
const DebugLoc & getDebugLoc() const
unsigned getResNo() const
Returns the ResNo for a register ref.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:191
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getFrameIx() const
Returns the FrameIx for a stack object.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:170
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:635
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void setIsEarlyClobber(bool Val=true)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
Value is contents of a stack location.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
DbgValueKind getKind() const
Returns the kind.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:249
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Value * getOperand(unsigned i) const
Definition: User.h:154
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getDebugRegState(bool B)
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:803
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getDefRegState(bool B)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
Machine Value Type.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool isMachineOpcode() const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
const SDValue & getOperand(unsigned Num) const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:734
unsigned getMachineOpcode() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
DebugLoc getDebugLoc() const
Returns the DebugLoc.
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:640
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
void dump() const
Dump this node, for debugging.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
unsigned getNumOperands() const
Definition: User.h:176
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
Value is a constant.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
Represents one node in the SelectionDAG.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the &#39;hasPostISelHook&#39; flag...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:932
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:396
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:422
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Value is the result of an expression.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getImplRegState(bool B)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getReg() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
LLVM Value Representation.
Definition: Value.h:73
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
static const Function * getParent(const Value *V)
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:198
unsigned getNumOperands() const
bool isIndirect() const
Returns whether this is an indirect value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Holds the information from a dbg_value node through SDISel.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This file describes how to lower LLVM code to machine code.
bool isImplicit() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.