14 #ifndef LLVM_LIB_CODEGEN_INTERFERENCECACHE_H 15 #define LLVM_LIB_CODEGEN_INTERFERENCECACHE_H 29 class MachineFunction;
30 class TargetRegisterInfo;
35 struct BlockInterference {
40 BlockInterference() {}
54 unsigned RefCount = 0;
98 void update(
unsigned MBBNum);
104 assert(!hasRefs() &&
"Cannot clear cache entry with references");
111 unsigned getPhysReg()
const {
return PhysReg; }
113 void addRef(
int Delta) { RefCount += Delta; }
115 bool hasRefs()
const {
return RefCount > 0; }
123 void reset(
unsigned physReg,
129 BlockInterference *
get(
unsigned MBBNum) {
130 if (Blocks[MBBNum].Tag != Tag)
132 return &Blocks[MBBNum];
139 enum { CacheEntries = 32 };
147 unsigned char* PhysRegEntries =
nullptr;
148 size_t PhysRegEntriesCount = 0;
151 unsigned RoundRobin = 0;
154 Entry Entries[CacheEntries];
157 Entry *
get(
unsigned PhysReg);
165 free(PhysRegEntries);
168 void reinitPhysRegEntries();
181 Entry *CacheEntry =
nullptr;
182 const BlockInterference *Current =
nullptr;
183 static const BlockInterference NoInterference;
185 void setEntry(Entry *
E) {
190 CacheEntry->addRef(-1);
193 CacheEntry->addRef(+1);
201 setEntry(O.CacheEntry);
205 setEntry(O.CacheEntry);
217 setEntry(Cache.get(PhysReg));
222 Current = CacheEntry ? CacheEntry->get(MBBNum) : &NoInterference;
227 return Current->First.isValid();
233 return Current->First;
239 return Current->Last;
246 #endif // LLVM_LIB_CODEGEN_INTERFERENCECACHE_H void setPhysReg(InterferenceCache &Cache, unsigned PhysReg)
setPhysReg - Point this cursor to PhysReg's interference.
This class represents lattice values for constants.
Segments::iterator iterator
unsigned const TargetRegisterInfo * TRI
void setMap(const IntervalMap &m)
setMap - Change the map iterated over.
This class represents the liveness of a register, stack slot, etc.
const Map & getMap() const
SlotIndex last()
last - Return the ending index of the last interfering range in the current block.
initializer< Ty > init(const Ty &Val)
Cursor - The primary query interface for the block interference cache.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasInterference()
hasInterference - Return true if the current block has any interference.
static void clear(coro::Shape &Shape)
void moveToBlock(unsigned MBBNum)
moveTo - Move cursor to basic block MBBNum.
Cursor & operator=(const Cursor &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getMaxCursors() const
getMaxCursors - Return the maximum number of concurrent cursors that can be supported.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex first()
first - Return the starting index of the first interfering range in the current block.