LLVM  9.0.0svn
LanaiISelLowering.h
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1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Lanai uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 
17 #include "Lanai.h"
18 #include "LanaiRegisterInfo.h"
21 
22 namespace llvm {
23 namespace LanaiISD {
24 enum {
26 
28 
29  // Return with a flag operand. Operand 0 is the chain operand.
31 
32  // CALL - These operations represent an abstract call instruction, which
33  // includes a bunch of information.
35 
36  // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
37  // is condition code and operand 4 is flag operand.
39 
40  // SETCC - Store the conditional code to a register.
42 
43  // SET_FLAG - Set flag compare.
45 
46  // SUBBF - Subtract with borrow that sets flags.
48 
49  // BR_CC - Used to glue together a conditional branch and comparison
51 
52  // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
53  // and TargetGlobalAddress.
55 
56  // Get the Higher/Lower 16 bits from a 32-bit immediate.
57  HI,
58  LO,
59 
60  // Small 21-bit immediate in global memory.
62 };
63 } // namespace LanaiISD
64 
65 class LanaiSubtarget;
66 
68 public:
70 
71  // LowerOperation - Provide custom lowering hooks for some operations.
72  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
73 
74  // getTargetNodeName - This method returns the name of a target specific
75  // DAG node.
76  const char *getTargetNodeName(unsigned Opcode) const override;
77 
78  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
79  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
88  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
92 
93  unsigned getRegisterByName(const char *RegName, EVT VT,
94  SelectionDAG &DAG) const override;
95  std::pair<unsigned, const TargetRegisterClass *>
96  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
97  StringRef Constraint, MVT VT) const override;
99  getSingleConstraintMatchWeight(AsmOperandInfo &Info,
100  const char *Constraint) const override;
101  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
102  std::vector<SDValue> &Ops,
103  SelectionDAG &DAG) const override;
104 
105  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
106 
107  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
108  const APInt &DemandedElts,
109  const SelectionDAG &DAG,
110  unsigned Depth = 0) const override;
111 
112 private:
113  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
114  CallingConv::ID CallConv, bool IsVarArg,
115  bool IsTailCall,
117  const SmallVectorImpl<SDValue> &OutVals,
119  const SDLoc &dl, SelectionDAG &DAG,
120  SmallVectorImpl<SDValue> &InVals) const;
121 
122  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
123  bool IsVarArg,
125  const SDLoc &DL, SelectionDAG &DAG,
126  SmallVectorImpl<SDValue> &InVals) const;
127 
128  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
129  CallingConv::ID CallConv, bool IsVarArg,
131  const SDLoc &DL, SelectionDAG &DAG,
132  SmallVectorImpl<SDValue> &InVals) const;
133 
135  SmallVectorImpl<SDValue> &InVals) const override;
136 
137  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
138  bool IsVarArg,
140  const SDLoc &DL, SelectionDAG &DAG,
141  SmallVectorImpl<SDValue> &InVals) const override;
142 
143  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
145  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
146  SelectionDAG &DAG) const override;
147 
148  const LanaiRegisterInfo *TRI;
149 };
150 } // namespace llvm
151 
152 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:876
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned const TargetRegisterInfo * TRI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This contains information for each constraint that we are lowering.
amdgpu Simplify well known AMD library false Value * Callee
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
#define N
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.