LLVM  8.0.0svn
LanaiISelLowering.h
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1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Lanai uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
17 
18 #include "Lanai.h"
19 #include "LanaiRegisterInfo.h"
22 
23 namespace llvm {
24 namespace LanaiISD {
25 enum {
27 
29 
30  // Return with a flag operand. Operand 0 is the chain operand.
32 
33  // CALL - These operations represent an abstract call instruction, which
34  // includes a bunch of information.
36 
37  // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
38  // is condition code and operand 4 is flag operand.
40 
41  // SETCC - Store the conditional code to a register.
43 
44  // SET_FLAG - Set flag compare.
46 
47  // SUBBF - Subtract with borrow that sets flags.
49 
50  // BR_CC - Used to glue together a conditional branch and comparison
52 
53  // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
54  // and TargetGlobalAddress.
56 
57  // Get the Higher/Lower 16 bits from a 32-bit immediate.
58  HI,
59  LO,
60 
61  // Small 21-bit immediate in global memory.
63 };
64 } // namespace LanaiISD
65 
66 class LanaiSubtarget;
67 
69 public:
71 
72  // LowerOperation - Provide custom lowering hooks for some operations.
73  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
74 
75  // getTargetNodeName - This method returns the name of a target specific
76  // DAG node.
77  const char *getTargetNodeName(unsigned Opcode) const override;
78 
79  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
81  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
93 
94  unsigned getRegisterByName(const char *RegName, EVT VT,
95  SelectionDAG &DAG) const override;
96  std::pair<unsigned, const TargetRegisterClass *>
97  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
98  StringRef Constraint, MVT VT) const override;
100  getSingleConstraintMatchWeight(AsmOperandInfo &Info,
101  const char *Constraint) const override;
102  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
103  std::vector<SDValue> &Ops,
104  SelectionDAG &DAG) const override;
105 
106  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
107 
108  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
109  const APInt &DemandedElts,
110  const SelectionDAG &DAG,
111  unsigned Depth = 0) const override;
112 
113 private:
114  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
115  CallingConv::ID CallConv, bool IsVarArg,
116  bool IsTailCall,
118  const SmallVectorImpl<SDValue> &OutVals,
120  const SDLoc &dl, SelectionDAG &DAG,
121  SmallVectorImpl<SDValue> &InVals) const;
122 
123  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
124  bool IsVarArg,
126  const SDLoc &DL, SelectionDAG &DAG,
127  SmallVectorImpl<SDValue> &InVals) const;
128 
129  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
130  CallingConv::ID CallConv, bool IsVarArg,
132  const SDLoc &DL, SelectionDAG &DAG,
133  SmallVectorImpl<SDValue> &InVals) const;
134 
136  SmallVectorImpl<SDValue> &InVals) const override;
137 
138  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
139  bool IsVarArg,
141  const SDLoc &DL, SelectionDAG &DAG,
142  SmallVectorImpl<SDValue> &InVals) const override;
143 
144  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
146  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
147  SelectionDAG &DAG) const override;
148 
149  const LanaiRegisterInfo *TRI;
150 };
151 } // namespace llvm
152 
153 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:846
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned const TargetRegisterInfo * TRI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This contains information for each constraint that we are lowering.
amdgpu Simplify well known AMD library false Value * Callee
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:70
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
#define N
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.