LLVM  9.0.0svn
LegalizationArtifactCombiner.h
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1 //===-- llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h -----*- C++ -*-//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // This file contains some helper functions which try to cleanup artifacts
9 // such as G_TRUNCs/G_[ZSA]EXTENDS that were created during legalization to make
10 // the types match. This file also contains some combines of merges that happens
11 // at the end of the legalization.
12 //===----------------------------------------------------------------------===//
13 
20 #include "llvm/Support/Debug.h"
21 
22 #define DEBUG_TYPE "legalizer"
23 using namespace llvm::MIPatternMatch;
24 
25 namespace llvm {
27  MachineIRBuilder &Builder;
29  const LegalizerInfo &LI;
30 
31 public:
33  const LegalizerInfo &LI)
34  : Builder(B), MRI(MRI), LI(LI) {}
35 
38  if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
39  return false;
40 
41  Builder.setInstr(MI);
42  unsigned DstReg = MI.getOperand(0).getReg();
43  unsigned SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
44 
45  // aext(trunc x) - > aext/copy/trunc x
46  unsigned TruncSrc;
47  if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
48  LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
49  Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
50  markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
51  return true;
52  }
53 
54  // aext([asz]ext x) -> [asz]ext x
55  unsigned ExtSrc;
56  MachineInstr *ExtMI;
57  if (mi_match(SrcReg, MRI,
58  m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)),
59  m_GSExt(m_Reg(ExtSrc)),
60  m_GZExt(m_Reg(ExtSrc)))))) {
61  Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
62  markInstAndDefDead(MI, *ExtMI, DeadInsts);
63  return true;
64  }
65  return tryFoldImplicitDef(MI, DeadInsts);
66  }
67 
70 
71  if (MI.getOpcode() != TargetOpcode::G_ZEXT)
72  return false;
73 
74  Builder.setInstr(MI);
75  unsigned DstReg = MI.getOperand(0).getReg();
76  unsigned SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
77 
78  // zext(trunc x) - > and (aext/copy/trunc x), mask
79  unsigned TruncSrc;
80  if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
81  LLT DstTy = MRI.getType(DstReg);
82  if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
83  isConstantUnsupported(DstTy))
84  return false;
85  LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
86  LLT SrcTy = MRI.getType(SrcReg);
87  APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
88  auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue());
89  Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
90  MIBMask);
91  markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
92  return true;
93  }
94  return tryFoldImplicitDef(MI, DeadInsts);
95  }
96 
99 
100  if (MI.getOpcode() != TargetOpcode::G_SEXT)
101  return false;
102 
103  Builder.setInstr(MI);
104  unsigned DstReg = MI.getOperand(0).getReg();
105  unsigned SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
106 
107  // sext(trunc x) - > ashr (shl (aext/copy/trunc x), c), c
108  unsigned TruncSrc;
109  if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
110  LLT DstTy = MRI.getType(DstReg);
111  // Guess on the RHS shift amount type, which should be re-legalized if
112  // applicable.
113  if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy, DstTy}}) ||
114  isInstUnsupported({TargetOpcode::G_ASHR, {DstTy, DstTy}}) ||
115  isConstantUnsupported(DstTy))
116  return false;
117  LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
118  LLT SrcTy = MRI.getType(SrcReg);
119  unsigned ShAmt = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();
120  auto MIBShAmt = Builder.buildConstant(DstTy, ShAmt);
121  auto MIBShl = Builder.buildInstr(
122  TargetOpcode::G_SHL, {DstTy},
123  {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), MIBShAmt});
124  Builder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {MIBShl, MIBShAmt});
125  markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
126  return true;
127  }
128  return tryFoldImplicitDef(MI, DeadInsts);
129  }
130 
131  /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
133  SmallVectorImpl<MachineInstr *> &DeadInsts) {
134  unsigned Opcode = MI.getOpcode();
135  if (Opcode != TargetOpcode::G_ANYEXT && Opcode != TargetOpcode::G_ZEXT &&
136  Opcode != TargetOpcode::G_SEXT)
137  return false;
138 
139  if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
140  MI.getOperand(1).getReg(), MRI)) {
141  Builder.setInstr(MI);
142  unsigned DstReg = MI.getOperand(0).getReg();
143  LLT DstTy = MRI.getType(DstReg);
144 
145  if (Opcode == TargetOpcode::G_ANYEXT) {
146  // G_ANYEXT (G_IMPLICIT_DEF) -> G_IMPLICIT_DEF
147  if (isInstUnsupported({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
148  return false;
149  LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
150  Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
151  } else {
152  // G_[SZ]EXT (G_IMPLICIT_DEF) -> G_CONSTANT 0 because the top
153  // bits will be 0 for G_ZEXT and 0/1 for the G_SEXT.
154  if (isConstantUnsupported(DstTy))
155  return false;
156  LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI;);
157  Builder.buildConstant(DstReg, 0);
158  }
159 
160  markInstAndDefDead(MI, *DefMI, DeadInsts);
161  return true;
162  }
163  return false;
164  }
165 
166  static unsigned getMergeOpcode(LLT OpTy, LLT DestTy) {
167  if (OpTy.isVector() && DestTy.isVector())
168  return TargetOpcode::G_CONCAT_VECTORS;
169 
170  if (OpTy.isVector() && !DestTy.isVector())
171  return TargetOpcode::G_BUILD_VECTOR;
172 
173  return TargetOpcode::G_MERGE_VALUES;
174  }
175 
177  SmallVectorImpl<MachineInstr *> &DeadInsts) {
178 
179  if (MI.getOpcode() != TargetOpcode::G_UNMERGE_VALUES)
180  return false;
181 
182  unsigned NumDefs = MI.getNumOperands() - 1;
183 
184  LLT OpTy = MRI.getType(MI.getOperand(NumDefs).getReg());
185  LLT DestTy = MRI.getType(MI.getOperand(0).getReg());
186 
187  unsigned MergingOpcode = getMergeOpcode(OpTy, DestTy);
188  MachineInstr *MergeI =
189  getOpcodeDef(MergingOpcode, MI.getOperand(NumDefs).getReg(), MRI);
190 
191  if (!MergeI)
192  return false;
193 
194  const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;
195 
196  if (NumMergeRegs < NumDefs) {
197  if (NumDefs % NumMergeRegs != 0)
198  return false;
199 
200  Builder.setInstr(MI);
201  // Transform to UNMERGEs, for example
202  // %1 = G_MERGE_VALUES %4, %5
203  // %9, %10, %11, %12 = G_UNMERGE_VALUES %1
204  // to
205  // %9, %10 = G_UNMERGE_VALUES %4
206  // %11, %12 = G_UNMERGE_VALUES %5
207 
208  const unsigned NewNumDefs = NumDefs / NumMergeRegs;
209  for (unsigned Idx = 0; Idx < NumMergeRegs; ++Idx) {
210  SmallVector<unsigned, 2> DstRegs;
211  for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
212  ++j, ++DefIdx)
213  DstRegs.push_back(MI.getOperand(DefIdx).getReg());
214 
215  Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg());
216  }
217 
218  } else if (NumMergeRegs > NumDefs) {
219  if (NumMergeRegs % NumDefs != 0)
220  return false;
221 
222  Builder.setInstr(MI);
223  // Transform to MERGEs
224  // %6 = G_MERGE_VALUES %17, %18, %19, %20
225  // %7, %8 = G_UNMERGE_VALUES %6
226  // to
227  // %7 = G_MERGE_VALUES %17, %18
228  // %8 = G_MERGE_VALUES %19, %20
229 
230  const unsigned NumRegs = NumMergeRegs / NumDefs;
231  for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
233  for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs;
234  ++j, ++Idx)
235  Regs.push_back(MergeI->getOperand(Idx).getReg());
236 
237  Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs);
238  }
239 
240  } else {
241  // FIXME: is a COPY appropriate if the types mismatch? We know both
242  // registers are allocatable by now.
243  if (MRI.getType(MI.getOperand(0).getReg()) !=
244  MRI.getType(MergeI->getOperand(1).getReg()))
245  return false;
246 
247  for (unsigned Idx = 0; Idx < NumDefs; ++Idx)
248  MRI.replaceRegWith(MI.getOperand(Idx).getReg(),
249  MergeI->getOperand(Idx + 1).getReg());
250  }
251 
252  markInstAndDefDead(MI, *MergeI, DeadInsts);
253  return true;
254  }
255 
256  static bool isMergeLikeOpcode(unsigned Opc) {
257  switch (Opc) {
258  case TargetOpcode::G_MERGE_VALUES:
259  case TargetOpcode::G_BUILD_VECTOR:
260  case TargetOpcode::G_CONCAT_VECTORS:
261  return true;
262  default:
263  return false;
264  }
265  }
266 
268  SmallVectorImpl<MachineInstr *> &DeadInsts) {
269  assert(MI.getOpcode() == TargetOpcode::G_EXTRACT);
270 
271  // Try to use the source registers from a G_MERGE_VALUES
272  //
273  // %2 = G_MERGE_VALUES %0, %1
274  // %3 = G_EXTRACT %2, N
275  // =>
276  //
277  // for N < %2.getSizeInBits() / 2
278  // %3 = G_EXTRACT %0, N
279  //
280  // for N >= %2.getSizeInBits() / 2
281  // %3 = G_EXTRACT %1, (N - %0.getSizeInBits()
282 
283  unsigned Src = lookThroughCopyInstrs(MI.getOperand(1).getReg());
284  MachineInstr *MergeI = MRI.getVRegDef(Src);
285  if (!MergeI || !isMergeLikeOpcode(MergeI->getOpcode()))
286  return false;
287 
288  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
289  LLT SrcTy = MRI.getType(Src);
290 
291  // TODO: Do we need to check if the resulting extract is supported?
292  unsigned ExtractDstSize = DstTy.getSizeInBits();
293  unsigned Offset = MI.getOperand(2).getImm();
294  unsigned NumMergeSrcs = MergeI->getNumOperands() - 1;
295  unsigned MergeSrcSize = SrcTy.getSizeInBits() / NumMergeSrcs;
296  unsigned MergeSrcIdx = Offset / MergeSrcSize;
297 
298  // Compute the offset of the last bit the extract needs.
299  unsigned EndMergeSrcIdx = (Offset + ExtractDstSize - 1) / MergeSrcSize;
300 
301  // Can't handle the case where the extract spans multiple inputs.
302  if (MergeSrcIdx != EndMergeSrcIdx)
303  return false;
304 
305  // TODO: We could modify MI in place in most cases.
306  Builder.setInstr(MI);
307  Builder.buildExtract(
308  MI.getOperand(0).getReg(),
309  MergeI->getOperand(MergeSrcIdx + 1).getReg(),
310  Offset - MergeSrcIdx * MergeSrcSize);
311  markInstAndDefDead(MI, *MergeI, DeadInsts);
312  return true;
313  }
314 
315  /// Try to combine away MI.
316  /// Returns true if it combined away the MI.
317  /// Adds instructions that are dead as a result of the combine
318  /// into DeadInsts, which can include MI.
321  GISelObserverWrapper &WrapperObserver) {
322  // This might be a recursive call, and we might have DeadInsts already
323  // populated. To avoid bad things happening later with multiple vreg defs
324  // etc, process the dead instructions now if any.
325  if (!DeadInsts.empty())
326  deleteMarkedDeadInsts(DeadInsts, WrapperObserver);
327  switch (MI.getOpcode()) {
328  default:
329  return false;
330  case TargetOpcode::G_ANYEXT:
331  return tryCombineAnyExt(MI, DeadInsts);
332  case TargetOpcode::G_ZEXT:
333  return tryCombineZExt(MI, DeadInsts);
334  case TargetOpcode::G_SEXT:
335  return tryCombineSExt(MI, DeadInsts);
336  case TargetOpcode::G_UNMERGE_VALUES:
337  return tryCombineMerges(MI, DeadInsts);
338  case TargetOpcode::G_EXTRACT:
339  return tryCombineExtract(MI, DeadInsts);
340  case TargetOpcode::G_TRUNC: {
341  bool Changed = false;
342  for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
343  Changed |= tryCombineInstruction(Use, DeadInsts, WrapperObserver);
344  return Changed;
345  }
346  }
347  }
348 
349 private:
350 
351  static unsigned getArtifactSrcReg(const MachineInstr &MI) {
352  switch (MI.getOpcode()) {
353  case TargetOpcode::COPY:
354  case TargetOpcode::G_TRUNC:
355  case TargetOpcode::G_ZEXT:
356  case TargetOpcode::G_ANYEXT:
357  case TargetOpcode::G_SEXT:
358  case TargetOpcode::G_UNMERGE_VALUES:
359  return MI.getOperand(MI.getNumOperands() - 1).getReg();
360  case TargetOpcode::G_EXTRACT:
361  return MI.getOperand(1).getReg();
362  default:
363  llvm_unreachable("Not a legalization artifact happen");
364  }
365  }
366 
367  /// Mark MI as dead. If a def of one of MI's operands, DefMI, would also be
368  /// dead due to MI being killed, then mark DefMI as dead too.
369  /// Some of the combines (extends(trunc)), try to walk through redundant
370  /// copies in between the extends and the truncs, and this attempts to collect
371  /// the in between copies if they're dead.
372  void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI,
373  SmallVectorImpl<MachineInstr *> &DeadInsts) {
374  DeadInsts.push_back(&MI);
375 
376  // Collect all the copy instructions that are made dead, due to deleting
377  // this instruction. Collect all of them until the Trunc(DefMI).
378  // Eg,
379  // %1(s1) = G_TRUNC %0(s32)
380  // %2(s1) = COPY %1(s1)
381  // %3(s1) = COPY %2(s1)
382  // %4(s32) = G_ANYEXT %3(s1)
383  // In this case, we would have replaced %4 with a copy of %0,
384  // and as a result, %3, %2, %1 are dead.
385  MachineInstr *PrevMI = &MI;
386  while (PrevMI != &DefMI) {
387  unsigned PrevRegSrc = getArtifactSrcReg(*PrevMI);
388 
389  MachineInstr *TmpDef = MRI.getVRegDef(PrevRegSrc);
390  if (MRI.hasOneUse(PrevRegSrc)) {
391  if (TmpDef != &DefMI) {
392  assert(TmpDef->getOpcode() == TargetOpcode::COPY &&
393  "Expecting copy here");
394  DeadInsts.push_back(TmpDef);
395  }
396  } else
397  break;
398  PrevMI = TmpDef;
399  }
400  if (PrevMI == &DefMI && MRI.hasOneUse(DefMI.getOperand(0).getReg()))
401  DeadInsts.push_back(&DefMI);
402  }
403 
404  /// Erase the dead instructions in the list and call the observer hooks.
405  /// Normally the Legalizer will deal with erasing instructions that have been
406  /// marked dead. However, for the trunc(ext(x)) cases we can end up trying to
407  /// process instructions which have been marked dead, but otherwise break the
408  /// MIR by introducing multiple vreg defs. For those cases, allow the combines
409  /// to explicitly delete the instructions before we run into trouble.
410  void deleteMarkedDeadInsts(SmallVectorImpl<MachineInstr *> &DeadInsts,
411  GISelObserverWrapper &WrapperObserver) {
412  for (auto *DeadMI : DeadInsts) {
413  LLVM_DEBUG(dbgs() << *DeadMI << "Is dead, eagerly deleting\n");
414  WrapperObserver.erasingInstr(*DeadMI);
415  DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
416  }
417  DeadInsts.clear();
418  }
419 
420  /// Checks if the target legalizer info has specified anything about the
421  /// instruction, or if unsupported.
422  bool isInstUnsupported(const LegalityQuery &Query) const {
423  using namespace LegalizeActions;
424  auto Step = LI.getAction(Query);
425  return Step.Action == Unsupported || Step.Action == NotFound;
426  }
427 
428  bool isConstantUnsupported(LLT Ty) const {
429  if (!Ty.isVector())
430  return isInstUnsupported({TargetOpcode::G_CONSTANT, {Ty}});
431 
432  LLT EltTy = Ty.getElementType();
433  return isInstUnsupported({TargetOpcode::G_CONSTANT, {EltTy}}) ||
434  isInstUnsupported({TargetOpcode::G_BUILD_VECTOR, {Ty, EltTy}});
435  }
436 
437  /// Looks through copy instructions and returns the actual
438  /// source register.
439  unsigned lookThroughCopyInstrs(unsigned Reg) {
440  unsigned TmpReg;
441  while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) {
442  if (MRI.getType(TmpReg).isValid())
443  Reg = TmpReg;
444  else
445  break;
446  }
447  return Reg;
448  }
449 };
450 
451 } // namespace llvm
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bind_ty< MachineInstr * > m_MInstr(MachineInstr *&MI)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
UnaryOp_match< SrcTy, TargetOpcode::G_ANYEXT > m_GAnyExt(const SrcTy &Src)
static unsigned getMergeOpcode(LLT OpTy, LLT DestTy)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getScalarSizeInBits() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
The LegalityQuery object bundles together all the information that&#39;s needed to decide whether a given...
bool tryCombineMerges(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
UnaryOp_match< SrcTy, TargetOpcode::G_ZEXT > m_GZExt(const SrcTy &Src)
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void erasingInstr(MachineInstr &MI) override
An instruction is about to be erased.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
bool tryCombineInstruction(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts, GISelObserverWrapper &WrapperObserver)
Try to combine away MI.
Or< Preds... > m_any_of(Preds &&... preds)
bool isVector() const
LegalizeActionStep getAction(const LegalityQuery &Query) const
Determine what action should be taken to legalize the described instruction.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
This operation is completely unsupported on the target.
Definition: LegalizerInfo.h:85
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
bool tryCombineAnyExt(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)
bool mi_match(Reg R, MachineRegisterInfo &MRI, Pattern &&P)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
UnaryOp_match< SrcTy, TargetOpcode::COPY > m_Copy(SrcTy &&Src)
And< Preds... > m_all_of(Preds &&... preds)
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:258
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
Sentinel value for when no action was found in the specified table.
Definition: LegalizerInfo.h:88
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, const LegalizerInfo &LI)
bool tryFoldImplicitDef(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)
Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
int64_t getImm() const
This file declares the MachineIRBuilder class.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
UnaryOp_match< SrcTy, TargetOpcode::G_SEXT > m_GSExt(const SrcTy &Src)
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
UnaryOp_match< SrcTy, TargetOpcode::G_TRUNC > m_GTrunc(const SrcTy &Src)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool tryCombineSExt(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)
LegalizeAction Action
The action to take or the final answer.
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool tryCombineZExt(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
operand_type_match m_Reg()
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
Simple wrapper observer that takes several observers, and calls each one for each event...
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
bool tryCombineExtract(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DeadInsts)