LLVM  9.0.0svn
LegalizeTypes.h
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1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the DAGTypeLegalizer class. This is a private interface
10 // shared between the code that implements the SelectionDAG::LegalizeTypes
11 // method.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
17 
18 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Debug.h"
23 
24 namespace llvm {
25 
26 //===----------------------------------------------------------------------===//
27 /// This takes an arbitrary SelectionDAG as input and hacks on it until only
28 /// value types the target machine can handle are left. This involves promoting
29 /// small sizes to large sizes or splitting up large values into small values.
30 ///
32  const TargetLowering &TLI;
33  SelectionDAG &DAG;
34 public:
35  /// This pass uses the NodeId on the SDNodes to hold information about the
36  /// state of the node. The enum has all the values.
37  enum NodeIdFlags {
38  /// All operands have been processed, so this node is ready to be handled.
39  ReadyToProcess = 0,
40 
41  /// This is a new node, not before seen, that was created in the process of
42  /// legalizing some other node.
43  NewNode = -1,
44 
45  /// This node's ID needs to be set to the number of its unprocessed
46  /// operands.
47  Unanalyzed = -2,
48 
49  /// This is a node that has already been processed.
50  Processed = -3
51 
52  // 1+ - This is a node which has this many unprocessed operands.
53  };
54 private:
55 
56  /// This is a bitvector that contains two bits for each simple value type,
57  /// where the two bits correspond to the LegalizeAction enum from
58  /// TargetLowering. This can be queried with "getTypeAction(VT)".
59  TargetLowering::ValueTypeActionImpl ValueTypeActions;
60 
61  /// Return how we should legalize values of this type.
62  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
63  return TLI.getTypeAction(*DAG.getContext(), VT);
64  }
65 
66  /// Return true if this type is legal on this target.
67  bool isTypeLegal(EVT VT) const {
68  return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
69  }
70 
71  /// Return true if this is a simple legal type.
72  bool isSimpleLegalType(EVT VT) const {
73  return VT.isSimple() && TLI.isTypeLegal(VT);
74  }
75 
76  /// Return true if this type can be passed in registers.
77  /// For example, x86_64's f128, should to be legally in registers
78  /// and only some operations converted to library calls or integer
79  /// bitwise operations.
80  bool isLegalInHWReg(EVT VT) const {
81  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
82  return VT == NVT && isSimpleLegalType(VT);
83  }
84 
85  EVT getSetCCResultType(EVT VT) const {
86  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
87  }
88 
89  /// Pretend all of this node's results are legal.
90  bool IgnoreNodeResults(SDNode *N) const {
91  return N->getOpcode() == ISD::TargetConstant ||
92  N->getOpcode() == ISD::Register;
93  }
94 
95  // Bijection from SDValue to unique id. As each created node gets a
96  // new id we do not need to worry about reuse expunging. Should we
97  // run out of ids, we can do a one time expensive compactifcation.
98  typedef unsigned TableId;
99 
100  TableId NextValueId = 1;
101 
104 
105  /// For integer nodes that are below legal width, this map indicates what
106  /// promoted value to use.
107  SmallDenseMap<TableId, TableId, 8> PromotedIntegers;
108 
109  /// For integer nodes that need to be expanded this map indicates which
110  /// operands are the expanded version of the input.
112 
113  /// For floating-point nodes converted to integers of the same size, this map
114  /// indicates the converted value to use.
115  SmallDenseMap<TableId, TableId, 8> SoftenedFloats;
116 
117  /// For floating-point nodes that have a smaller precision than the smallest
118  /// supported precision, this map indicates what promoted value to use.
119  SmallDenseMap<TableId, TableId, 8> PromotedFloats;
120 
121  /// For float nodes that need to be expanded this map indicates which operands
122  /// are the expanded version of the input.
124 
125  /// For nodes that are <1 x ty>, this map indicates the scalar value of type
126  /// 'ty' to use.
127  SmallDenseMap<TableId, TableId, 8> ScalarizedVectors;
128 
129  /// For nodes that need to be split this map indicates which operands are the
130  /// expanded version of the input.
132 
133  /// For vector nodes that need to be widened, indicates the widened value to
134  /// use.
135  SmallDenseMap<TableId, TableId, 8> WidenedVectors;
136 
137  /// For values that have been replaced with another, indicates the replacement
138  /// value to use.
139  SmallDenseMap<TableId, TableId, 8> ReplacedValues;
140 
141  /// This defines a worklist of nodes to process. In order to be pushed onto
142  /// this worklist, all operands of a node must have already been processed.
143  SmallVector<SDNode*, 128> Worklist;
144 
145  TableId getTableId(SDValue V) {
146  assert(V.getNode() && "Getting TableId on SDValue()");
147 
148  auto I = ValueToIdMap.find(V);
149  if (I != ValueToIdMap.end()) {
150  // replace if there's been a shift.
151  RemapId(I->second);
152  assert(I->second && "All Ids should be nonzero");
153  return I->second;
154  }
155  // Add if it's not there.
156  ValueToIdMap.insert(std::make_pair(V, NextValueId));
157  IdToValueMap.insert(std::make_pair(NextValueId, V));
158  ++NextValueId;
159  assert(NextValueId != 0 &&
160  "Ran out of Ids. Increase id type size or add compactification");
161  return NextValueId - 1;
162  }
163 
164  const SDValue &getSDValue(TableId &Id) {
165  RemapId(Id);
166  assert(Id && "TableId should be non-zero");
167  return IdToValueMap[Id];
168  }
169 
170 public:
172  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
173  ValueTypeActions(TLI.getValueTypeActions()) {
175  "Too many value types for ValueTypeActions to hold!");
176  }
177 
178  /// This is the main entry point for the type legalizer. This does a
179  /// top-down traversal of the dag, legalizing types as it goes. Returns
180  /// "true" if it made any changes.
181  bool run();
182 
183  void NoteDeletion(SDNode *Old, SDNode *New) {
184  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
185  TableId NewId = getTableId(SDValue(New, i));
186  TableId OldId = getTableId(SDValue(Old, i));
187 
188  if (OldId != NewId)
189  ReplacedValues[OldId] = NewId;
190 
191  // Delete Node from tables.
192  ValueToIdMap.erase(SDValue(Old, i));
193  IdToValueMap.erase(OldId);
194  PromotedIntegers.erase(OldId);
195  ExpandedIntegers.erase(OldId);
196  SoftenedFloats.erase(OldId);
197  PromotedFloats.erase(OldId);
198  ExpandedFloats.erase(OldId);
199  ScalarizedVectors.erase(OldId);
200  SplitVectors.erase(OldId);
201  WidenedVectors.erase(OldId);
202  }
203  }
204 
205  SelectionDAG &getDAG() const { return DAG; }
206 
207 private:
208  SDNode *AnalyzeNewNode(SDNode *N);
209  void AnalyzeNewValue(SDValue &Val);
210  void PerformExpensiveChecks();
211  void RemapId(TableId &Id);
212  void RemapValue(SDValue &V);
213 
214  // Common routines.
215  SDValue BitConvertToInteger(SDValue Op);
216  SDValue BitConvertVectorToIntegerVector(SDValue Op);
217  SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
218  bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
219  bool CustomWidenLowerNode(SDNode *N, EVT VT);
220 
221  /// Replace each result of the given MERGE_VALUES node with the corresponding
222  /// input operand, except for the result 'ResNo', for which the corresponding
223  /// input operand is returned.
224  SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
225 
226  SDValue JoinIntegers(SDValue Lo, SDValue Hi);
227  SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
228 
229  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
230  SDNode *Node, bool isSigned);
231  std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
232 
233  SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT);
234 
235  void ReplaceValueWith(SDValue From, SDValue To);
236  void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
237  void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
238  SDValue &Lo, SDValue &Hi);
239 
240  void AddToWorklist(SDNode *N) {
241  N->setNodeId(ReadyToProcess);
242  Worklist.push_back(N);
243  }
244 
245  //===--------------------------------------------------------------------===//
246  // Integer Promotion Support: LegalizeIntegerTypes.cpp
247  //===--------------------------------------------------------------------===//
248 
249  /// Given a processed operand Op which was promoted to a larger integer type,
250  /// this returns the promoted value. The low bits of the promoted value
251  /// corresponding to the original type are exactly equal to Op.
252  /// The extra bits contain rubbish, so the promoted value may need to be zero-
253  /// or sign-extended from the original type before it is usable (the helpers
254  /// SExtPromotedInteger and ZExtPromotedInteger can do this for you).
255  /// For example, if Op is an i16 and was promoted to an i32, then this method
256  /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
257  /// 16 bits of which contain rubbish.
258  SDValue GetPromotedInteger(SDValue Op) {
259  TableId &PromotedId = PromotedIntegers[getTableId(Op)];
260  SDValue PromotedOp = getSDValue(PromotedId);
261  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
262  return PromotedOp;
263  }
264  void SetPromotedInteger(SDValue Op, SDValue Result);
265 
266  /// Get a promoted operand and sign extend it to the final size.
267  SDValue SExtPromotedInteger(SDValue Op) {
268  EVT OldVT = Op.getValueType();
269  SDLoc dl(Op);
270  Op = GetPromotedInteger(Op);
271  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
272  DAG.getValueType(OldVT));
273  }
274 
275  /// Get a promoted operand and zero extend it to the final size.
276  SDValue ZExtPromotedInteger(SDValue Op) {
277  EVT OldVT = Op.getValueType();
278  SDLoc dl(Op);
279  Op = GetPromotedInteger(Op);
280  return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType());
281  }
282 
283  // Get a promoted operand and sign or zero extend it to the final size
284  // (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
285  // subtarget and type, the choice of sign or zero-extension will be
286  // consistent.
287  SDValue SExtOrZExtPromotedInteger(SDValue Op) {
288  EVT OldVT = Op.getValueType();
289  SDLoc DL(Op);
290  Op = GetPromotedInteger(Op);
291  if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
292  return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
293  DAG.getValueType(OldVT));
294  return DAG.getZeroExtendInReg(Op, DL, OldVT.getScalarType());
295  }
296 
297  // Integer Result Promotion.
298  void PromoteIntegerResult(SDNode *N, unsigned ResNo);
299  SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
300  SDValue PromoteIntRes_AssertSext(SDNode *N);
301  SDValue PromoteIntRes_AssertZext(SDNode *N);
302  SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
303  SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
304  SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
305  SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
306  SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
307  SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
308  SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
309  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
310  SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
311  SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
312  SDValue PromoteIntRes_BITCAST(SDNode *N);
313  SDValue PromoteIntRes_BSWAP(SDNode *N);
314  SDValue PromoteIntRes_BITREVERSE(SDNode *N);
315  SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
316  SDValue PromoteIntRes_Constant(SDNode *N);
317  SDValue PromoteIntRes_CTLZ(SDNode *N);
318  SDValue PromoteIntRes_CTPOP(SDNode *N);
319  SDValue PromoteIntRes_CTTZ(SDNode *N);
320  SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
321  SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
322  SDValue PromoteIntRes_FP_TO_FP16(SDNode *N);
323  SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
324  SDValue PromoteIntRes_LOAD(LoadSDNode *N);
325  SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
326  SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
327  SDValue PromoteIntRes_Overflow(SDNode *N);
328  SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
329  SDValue PromoteIntRes_SELECT(SDNode *N);
330  SDValue PromoteIntRes_VSELECT(SDNode *N);
331  SDValue PromoteIntRes_SELECT_CC(SDNode *N);
332  SDValue PromoteIntRes_SETCC(SDNode *N);
333  SDValue PromoteIntRes_SHL(SDNode *N);
334  SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
335  SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
336  SDValue PromoteIntRes_SExtIntBinOp(SDNode *N);
337  SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
338  SDValue PromoteIntRes_SRA(SDNode *N);
339  SDValue PromoteIntRes_SRL(SDNode *N);
340  SDValue PromoteIntRes_TRUNCATE(SDNode *N);
341  SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
342  SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo);
343  SDValue PromoteIntRes_UNDEF(SDNode *N);
344  SDValue PromoteIntRes_VAARG(SDNode *N);
345  SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
346  SDValue PromoteIntRes_ADDSUBSAT(SDNode *N);
347  SDValue PromoteIntRes_MULFIX(SDNode *N);
348  SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
349 
350  // Integer Operand Promotion.
351  bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
352  SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
353  SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
354  SDValue PromoteIntOp_BITCAST(SDNode *N);
355  SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
356  SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
357  SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
358  SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
359  SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
360  SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
361  SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
362  SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
363  SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
364  SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
365  SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
366  SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
367  SDValue PromoteIntOp_Shift(SDNode *N);
368  SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
369  SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
370  SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
371  SDValue PromoteIntOp_TRUNCATE(SDNode *N);
372  SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
373  SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
374  SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
375  SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
376  SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
377  SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
378  SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
379  SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
380  SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
381  SDValue PromoteIntOp_MULFIX(SDNode *N);
382  SDValue PromoteIntOp_FPOWI(SDNode *N);
383 
384  void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
385 
386  //===--------------------------------------------------------------------===//
387  // Integer Expansion Support: LegalizeIntegerTypes.cpp
388  //===--------------------------------------------------------------------===//
389 
390  /// Given a processed operand Op which was expanded into two integers of half
391  /// the size, this returns the two halves. The low bits of Op are exactly
392  /// equal to the bits of Lo; the high bits exactly equal Hi.
393  /// For example, if Op is an i64 which was expanded into two i32's, then this
394  /// method returns the two i32's, with Lo being equal to the lower 32 bits of
395  /// Op, and Hi being equal to the upper 32 bits.
396  void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
397  void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
398 
399  // Integer Result Expansion.
400  void ExpandIntegerResult(SDNode *N, unsigned ResNo);
401  void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
402  void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
403  void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
404  void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
405  void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
406  void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
407  void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
408  void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
409  void ExpandIntRes_READCYCLECOUNTER (SDNode *N, SDValue &Lo, SDValue &Hi);
410  void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
411  void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
412  void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
413  void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
414  void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
415  void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
416  void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
417 
418  void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
419  void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
420  void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
421  void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
422  void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
423  void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi);
424  void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
425  void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
426  void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
427  void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
428  void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
429  void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
430  void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
431 
432  void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
433 
434  void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
435  void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
436  void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
437  void ExpandIntRes_ADDSUBSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
438  void ExpandIntRes_MULFIX (SDNode *N, SDValue &Lo, SDValue &Hi);
439 
440  void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
441 
442  void ExpandShiftByConstant(SDNode *N, const APInt &Amt,
443  SDValue &Lo, SDValue &Hi);
444  bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
445  bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
446 
447  // Integer Operand Expansion.
448  bool ExpandIntegerOperand(SDNode *N, unsigned OpNo);
449  SDValue ExpandIntOp_BR_CC(SDNode *N);
450  SDValue ExpandIntOp_SELECT_CC(SDNode *N);
451  SDValue ExpandIntOp_SETCC(SDNode *N);
452  SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
453  SDValue ExpandIntOp_Shift(SDNode *N);
454  SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
455  SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
456  SDValue ExpandIntOp_TRUNCATE(SDNode *N);
457  SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
458  SDValue ExpandIntOp_RETURNADDR(SDNode *N);
459  SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
460 
461  void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
462  ISD::CondCode &CCCode, const SDLoc &dl);
463 
464  //===--------------------------------------------------------------------===//
465  // Float to Integer Conversion Support: LegalizeFloatTypes.cpp
466  //===--------------------------------------------------------------------===//
467 
468  /// Given an operand Op of Float type, returns the integer if the Op is not
469  /// supported in target HW and converted to the integer.
470  /// The integer contains exactly the same bits as Op - only the type changed.
471  /// For example, if Op is an f32 which was softened to an i32, then this
472  /// method returns an i32, the bits of which coincide with those of Op.
473  /// If the Op can be efficiently supported in target HW or the operand must
474  /// stay in a register, the Op is not converted to an integer.
475  /// In that case, the given op is returned.
476  SDValue GetSoftenedFloat(SDValue Op) {
477  TableId Id = getTableId(Op);
478  auto Iter = SoftenedFloats.find(Id);
479  if (Iter == SoftenedFloats.end()) {
480  assert(isSimpleLegalType(Op.getValueType()) &&
481  "Operand wasn't converted to integer?");
482  return Op;
483  }
484  SDValue SoftenedOp = getSDValue(Iter->second);
485  assert(SoftenedOp.getNode() && "Unconverted op in SoftenedFloats?");
486  return SoftenedOp;
487  }
488  void SetSoftenedFloat(SDValue Op, SDValue Result);
489 
490  // Convert Float Results to Integer for Non-HW-supported Operations.
491  bool SoftenFloatResult(SDNode *N, unsigned ResNo);
492  SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
493  SDValue SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo);
494  SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
495  SDValue SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo);
496  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
497  SDValue SoftenFloatRes_FABS(SDNode *N, unsigned ResNo);
498  SDValue SoftenFloatRes_FMINNUM(SDNode *N);
499  SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
500  SDValue SoftenFloatRes_FADD(SDNode *N);
501  SDValue SoftenFloatRes_FCEIL(SDNode *N);
502  SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo);
503  SDValue SoftenFloatRes_FCOS(SDNode *N);
504  SDValue SoftenFloatRes_FDIV(SDNode *N);
505  SDValue SoftenFloatRes_FEXP(SDNode *N);
506  SDValue SoftenFloatRes_FEXP2(SDNode *N);
507  SDValue SoftenFloatRes_FFLOOR(SDNode *N);
508  SDValue SoftenFloatRes_FLOG(SDNode *N);
509  SDValue SoftenFloatRes_FLOG2(SDNode *N);
510  SDValue SoftenFloatRes_FLOG10(SDNode *N);
511  SDValue SoftenFloatRes_FMA(SDNode *N);
512  SDValue SoftenFloatRes_FMUL(SDNode *N);
513  SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
514  SDValue SoftenFloatRes_FNEG(SDNode *N, unsigned ResNo);
515  SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
516  SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N);
517  SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
518  SDValue SoftenFloatRes_FPOW(SDNode *N);
519  SDValue SoftenFloatRes_FPOWI(SDNode *N);
520  SDValue SoftenFloatRes_FREM(SDNode *N);
521  SDValue SoftenFloatRes_FRINT(SDNode *N);
522  SDValue SoftenFloatRes_FROUND(SDNode *N);
523  SDValue SoftenFloatRes_FSIN(SDNode *N);
524  SDValue SoftenFloatRes_FSQRT(SDNode *N);
525  SDValue SoftenFloatRes_FSUB(SDNode *N);
526  SDValue SoftenFloatRes_FTRUNC(SDNode *N);
527  SDValue SoftenFloatRes_LOAD(SDNode *N, unsigned ResNo);
528  SDValue SoftenFloatRes_SELECT(SDNode *N, unsigned ResNo);
529  SDValue SoftenFloatRes_SELECT_CC(SDNode *N, unsigned ResNo);
530  SDValue SoftenFloatRes_UNDEF(SDNode *N);
531  SDValue SoftenFloatRes_VAARG(SDNode *N);
532  SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
533 
534  // Return true if we can skip softening the given operand or SDNode because
535  // either it was soften before by SoftenFloatResult and references to the
536  // operand were replaced by ReplaceValueWith or it's value type is legal in HW
537  // registers and the operand can be left unchanged.
538  bool CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo);
539 
540  // Convert Float Operand to Integer for Non-HW-supported Operations.
541  bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
542  SDValue SoftenFloatOp_BITCAST(SDNode *N);
543  SDValue SoftenFloatOp_COPY_TO_REG(SDNode *N);
544  SDValue SoftenFloatOp_BR_CC(SDNode *N);
545  SDValue SoftenFloatOp_FABS(SDNode *N);
546  SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
547  SDValue SoftenFloatOp_FNEG(SDNode *N);
548  SDValue SoftenFloatOp_FP_EXTEND(SDNode *N);
549  SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
550  SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
551  SDValue SoftenFloatOp_SELECT(SDNode *N);
552  SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
553  SDValue SoftenFloatOp_SETCC(SDNode *N);
554  SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
555 
556  //===--------------------------------------------------------------------===//
557  // Float Expansion Support: LegalizeFloatTypes.cpp
558  //===--------------------------------------------------------------------===//
559 
560  /// Given a processed operand Op which was expanded into two floating-point
561  /// values of half the size, this returns the two halves.
562  /// The low bits of Op are exactly equal to the bits of Lo; the high bits
563  /// exactly equal Hi. For example, if Op is a ppcf128 which was expanded
564  /// into two f64's, then this method returns the two f64's, with Lo being
565  /// equal to the lower 64 bits of Op, and Hi to the upper 64 bits.
566  void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
567  void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
568 
569  // Float Result Expansion.
570  void ExpandFloatResult(SDNode *N, unsigned ResNo);
571  void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
572  void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
573  void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
574  void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
575  void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
576  void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi);
577  void ExpandFloatRes_FCOPYSIGN (SDNode *N, SDValue &Lo, SDValue &Hi);
578  void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi);
579  void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
580  void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi);
581  void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi);
582  void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi);
583  void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
584  void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
585  void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
586  void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi);
587  void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
588  void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
589  void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
590  void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
591  void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
592  void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
593  void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi);
594  void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
595  void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi);
596  void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
597  void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
598  void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
599  void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
600  void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
601  void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
602 
603  // Float Operand Expansion.
604  bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
605  SDValue ExpandFloatOp_BR_CC(SDNode *N);
606  SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
607  SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
608  SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
609  SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
610  SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
611  SDValue ExpandFloatOp_SETCC(SDNode *N);
612  SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
613 
614  void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
615  ISD::CondCode &CCCode, const SDLoc &dl);
616 
617  //===--------------------------------------------------------------------===//
618  // Float promotion support: LegalizeFloatTypes.cpp
619  //===--------------------------------------------------------------------===//
620 
621  SDValue GetPromotedFloat(SDValue Op) {
622  TableId &PromotedId = PromotedFloats[getTableId(Op)];
623  SDValue PromotedOp = getSDValue(PromotedId);
624  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
625  return PromotedOp;
626  }
627  void SetPromotedFloat(SDValue Op, SDValue Result);
628 
629  void PromoteFloatResult(SDNode *N, unsigned ResNo);
630  SDValue PromoteFloatRes_BITCAST(SDNode *N);
631  SDValue PromoteFloatRes_BinOp(SDNode *N);
632  SDValue PromoteFloatRes_ConstantFP(SDNode *N);
633  SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
634  SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);
635  SDValue PromoteFloatRes_FMAD(SDNode *N);
636  SDValue PromoteFloatRes_FPOWI(SDNode *N);
637  SDValue PromoteFloatRes_FP_ROUND(SDNode *N);
638  SDValue PromoteFloatRes_LOAD(SDNode *N);
639  SDValue PromoteFloatRes_SELECT(SDNode *N);
640  SDValue PromoteFloatRes_SELECT_CC(SDNode *N);
641  SDValue PromoteFloatRes_UnaryOp(SDNode *N);
642  SDValue PromoteFloatRes_UNDEF(SDNode *N);
643  SDValue BitcastToInt_ATOMIC_SWAP(SDNode *N);
644  SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
645 
646  bool PromoteFloatOperand(SDNode *N, unsigned OpNo);
647  SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
648  SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
649  SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
650  SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo);
651  SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);
652  SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);
653  SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);
654 
655  //===--------------------------------------------------------------------===//
656  // Scalarization Support: LegalizeVectorTypes.cpp
657  //===--------------------------------------------------------------------===//
658 
659  /// Given a processed one-element vector Op which was scalarized to its
660  /// element type, this returns the element. For example, if Op is a v1i32,
661  /// Op = < i32 val >, this method returns val, an i32.
662  SDValue GetScalarizedVector(SDValue Op) {
663  TableId &ScalarizedId = ScalarizedVectors[getTableId(Op)];
664  SDValue ScalarizedOp = getSDValue(ScalarizedId);
665  assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
666  return ScalarizedOp;
667  }
668  void SetScalarizedVector(SDValue Op, SDValue Result);
669 
670  // Vector Result Scalarization: <1 x ty> -> ty.
671  void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
672  SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
673  SDValue ScalarizeVecRes_BinOp(SDNode *N);
674  SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
675  SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
676  SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
677  SDValue ScalarizeVecRes_OverflowOp(SDNode *N, unsigned ResNo);
678  SDValue ScalarizeVecRes_InregOp(SDNode *N);
679  SDValue ScalarizeVecRes_VecInregOp(SDNode *N);
680 
681  SDValue ScalarizeVecRes_BITCAST(SDNode *N);
682  SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N);
683  SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
684  SDValue ScalarizeVecRes_FP_ROUND(SDNode *N);
685  SDValue ScalarizeVecRes_FPOWI(SDNode *N);
686  SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
687  SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
688  SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
689  SDValue ScalarizeVecRes_VSELECT(SDNode *N);
690  SDValue ScalarizeVecRes_SELECT(SDNode *N);
691  SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
692  SDValue ScalarizeVecRes_SETCC(SDNode *N);
693  SDValue ScalarizeVecRes_UNDEF(SDNode *N);
694  SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
695 
696  SDValue ScalarizeVecRes_MULFIX(SDNode *N);
697 
698  // Vector Operand Scalarization: <1 x ty> -> ty.
699  bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
700  SDValue ScalarizeVecOp_BITCAST(SDNode *N);
701  SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
702  SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
703  SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
704  SDValue ScalarizeVecOp_VSELECT(SDNode *N);
705  SDValue ScalarizeVecOp_VSETCC(SDNode *N);
706  SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
707  SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
708 
709  //===--------------------------------------------------------------------===//
710  // Vector Splitting Support: LegalizeVectorTypes.cpp
711  //===--------------------------------------------------------------------===//
712 
713  /// Given a processed vector Op which was split into vectors of half the size,
714  /// this method returns the halves. The first elements of Op coincide with the
715  /// elements of Lo; the remaining elements of Op coincide with the elements of
716  /// Hi: Op is what you would get by concatenating Lo and Hi.
717  /// For example, if Op is a v8i32 that was split into two v4i32's, then this
718  /// method returns the two v4i32's, with Lo corresponding to the first 4
719  /// elements of Op, and Hi to the last 4 elements.
720  void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
721  void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
722 
723  // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
724  void SplitVectorResult(SDNode *N, unsigned ResNo);
725  void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
726  void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
727  void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
728  void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
729  void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
730  void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
731  void SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo, SDValue &Hi);
732  void SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
733  SDValue &Lo, SDValue &Hi);
734 
735  void SplitVecRes_MULFIX(SDNode *N, SDValue &Lo, SDValue &Hi);
736 
737  void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
738  void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
739  void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
740  void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
741  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
742  void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
743  void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
744  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
745  void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
746  void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
747  void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
748  void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
749  void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
750  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
751  SDValue &Hi);
752 
753  // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
754  bool SplitVectorOperand(SDNode *N, unsigned OpNo);
755  SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo);
756  SDValue SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo);
757  SDValue SplitVecOp_UnaryOp(SDNode *N);
758  SDValue SplitVecOp_TruncateHelper(SDNode *N);
759 
760  SDValue SplitVecOp_BITCAST(SDNode *N);
761  SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
762  SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
763  SDValue SplitVecOp_ExtVecInRegOp(SDNode *N);
764  SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
765  SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
766  SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
767  SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo);
768  SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
769  SDValue SplitVecOp_VSETCC(SDNode *N);
770  SDValue SplitVecOp_FP_ROUND(SDNode *N);
771  SDValue SplitVecOp_FCOPYSIGN(SDNode *N);
772 
773  //===--------------------------------------------------------------------===//
774  // Vector Widening Support: LegalizeVectorTypes.cpp
775  //===--------------------------------------------------------------------===//
776 
777  /// Given a processed vector Op which was widened into a larger vector, this
778  /// method returns the larger vector. The elements of the returned vector
779  /// consist of the elements of Op followed by elements containing rubbish.
780  /// For example, if Op is a v2i32 that was widened to a v4i32, then this
781  /// method returns a v4i32 for which the first two elements are the same as
782  /// those of Op, while the last two elements contain rubbish.
783  SDValue GetWidenedVector(SDValue Op) {
784  TableId &WidenedId = WidenedVectors[getTableId(Op)];
785  SDValue WidenedOp = getSDValue(WidenedId);
786  assert(WidenedOp.getNode() && "Operand wasn't widened?");
787  return WidenedOp;
788  }
789  void SetWidenedVector(SDValue Op, SDValue Result);
790 
791  // Widen Vector Result Promotion.
792  void WidenVectorResult(SDNode *N, unsigned ResNo);
793  SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo);
794  SDValue WidenVecRes_BITCAST(SDNode* N);
795  SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
796  SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
797  SDValue WidenVecRes_EXTEND_VECTOR_INREG(SDNode* N);
798  SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
799  SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
800  SDValue WidenVecRes_LOAD(SDNode* N);
801  SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N);
802  SDValue WidenVecRes_MGATHER(MaskedGatherSDNode* N);
803  SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
804  SDValue WidenVecRes_SELECT(SDNode* N);
805  SDValue WidenVSELECTAndMask(SDNode *N);
806  SDValue WidenVecRes_SELECT_CC(SDNode* N);
807  SDValue WidenVecRes_SETCC(SDNode* N);
808  SDValue WidenVecRes_UNDEF(SDNode *N);
809  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
810 
811  SDValue WidenVecRes_Ternary(SDNode *N);
812  SDValue WidenVecRes_Binary(SDNode *N);
813  SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
814  SDValue WidenVecRes_StrictFP(SDNode *N);
815  SDValue WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo);
816  SDValue WidenVecRes_Convert(SDNode *N);
817  SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
818  SDValue WidenVecRes_POWI(SDNode *N);
819  SDValue WidenVecRes_Shift(SDNode *N);
820  SDValue WidenVecRes_Unary(SDNode *N);
821  SDValue WidenVecRes_InregOp(SDNode *N);
822 
823  // Widen Vector Operand.
824  bool WidenVectorOperand(SDNode *N, unsigned OpNo);
825  SDValue WidenVecOp_BITCAST(SDNode *N);
826  SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
827  SDValue WidenVecOp_EXTEND(SDNode *N);
828  SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
829  SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
830  SDValue WidenVecOp_STORE(SDNode* N);
831  SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
832  SDValue WidenVecOp_MGATHER(SDNode* N, unsigned OpNo);
833  SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo);
834  SDValue WidenVecOp_SETCC(SDNode* N);
835 
836  SDValue WidenVecOp_Convert(SDNode *N);
837  SDValue WidenVecOp_FCOPYSIGN(SDNode *N);
838 
839  //===--------------------------------------------------------------------===//
840  // Vector Widening Utilities Support: LegalizeVectorTypes.cpp
841  //===--------------------------------------------------------------------===//
842 
843  /// Helper function to generate a set of loads to load a vector with a
844  /// resulting wider type. It takes:
845  /// LdChain: list of chains for the load to be generated.
846  /// Ld: load to widen
847  SDValue GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
848  LoadSDNode *LD);
849 
850  /// Helper function to generate a set of extension loads to load a vector with
851  /// a resulting wider type. It takes:
852  /// LdChain: list of chains for the load to be generated.
853  /// Ld: load to widen
854  /// ExtType: extension element type
855  SDValue GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
857 
858  /// Helper function to generate a set of stores to store a widen vector into
859  /// non-widen memory.
860  /// StChain: list of chains for the stores we have generated
861  /// ST: store of a widen value
862  void GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);
863 
864  /// Helper function to generate a set of stores to store a truncate widen
865  /// vector into non-widen memory.
866  /// StChain: list of chains for the stores we have generated
867  /// ST: store of a widen value
868  void GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
869  StoreSDNode *ST);
870 
871  /// Modifies a vector input (widen or narrows) to a vector of NVT. The
872  /// input vector must have the same element type as NVT.
873  /// When FillWithZeroes is "on" the vector will be widened with zeroes.
874  /// By default, the vector will be widened with undefined values.
875  SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
876 
877  /// Return a mask of vector type MaskVT to replace InMask. Also adjust
878  /// MaskVT to ToMaskVT if needed with vector extension or truncation.
879  SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT);
880 
881  //===--------------------------------------------------------------------===//
882  // Generic Splitting: LegalizeTypesGeneric.cpp
883  //===--------------------------------------------------------------------===//
884 
885  // Legalization methods which only use that the illegal type is split into two
886  // not necessarily identical types. As such they can be used for splitting
887  // vectors and expanding integers and floats.
888 
889  void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
890  if (Op.getValueType().isVector())
891  GetSplitVector(Op, Lo, Hi);
892  else if (Op.getValueType().isInteger())
893  GetExpandedInteger(Op, Lo, Hi);
894  else
895  GetExpandedFloat(Op, Lo, Hi);
896  }
897 
898  /// Use ISD::EXTRACT_ELEMENT nodes to extract the low and high parts of the
899  /// given value.
900  void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi);
901 
902  // Generic Result Splitting.
903  void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
904  SDValue &Lo, SDValue &Hi);
905  void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
906  void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
907  void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
908 
909  //===--------------------------------------------------------------------===//
910  // Generic Expansion: LegalizeTypesGeneric.cpp
911  //===--------------------------------------------------------------------===//
912 
913  // Legalization methods which only use that the illegal type is split into two
914  // identical types of half the size, and that the Lo/Hi part is stored first
915  // in memory on little/big-endian machines, followed by the Hi/Lo part. As
916  // such they can be used for expanding integers and floats.
917 
918  void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
919  if (Op.getValueType().isInteger())
920  GetExpandedInteger(Op, Lo, Hi);
921  else
922  GetExpandedFloat(Op, Lo, Hi);
923  }
924 
925 
926  /// This function will split the integer \p Op into \p NumElements
927  /// operations of type \p EltVT and store them in \p Ops.
928  void IntegerToVector(SDValue Op, unsigned NumElements,
929  SmallVectorImpl<SDValue> &Ops, EVT EltVT);
930 
931  // Generic Result Expansion.
932  void ExpandRes_MERGE_VALUES (SDNode *N, unsigned ResNo,
933  SDValue &Lo, SDValue &Hi);
934  void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi);
935  void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
936  void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
937  void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
938  void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
939  void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
940 
941  // Generic Operand Expansion.
942  SDValue ExpandOp_BITCAST (SDNode *N);
943  SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
944  SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
945  SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);
946  SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N);
947  SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
948 };
949 
950 } // end namespace llvm.
951 
952 #endif
EVT getValueType() const
Return the ValueType of the referenced return value.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
This takes an arbitrary SelectionDAG as input and hacks on it until only value types the target machi...
Definition: LegalizeTypes.h:31
void setNodeId(int Id)
Set unique node id.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
This is an SDNode representing atomic operations.
SelectionDAG & getDAG() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This class is used to represent an MSTORE node.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
This class is used to represent ISD::STORE nodes.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:940
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:107
Extended Value Type.
Definition: ValueTypes.h:33
NodeIdFlags
This pass uses the NodeId on the SDNodes to hold information about the state of the node...
Definition: LegalizeTypes.h:37
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
void NoteDeletion(SDNode *Old, SDNode *New)
BlockVerifier::State From
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:485
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
This class is used to represent an MSCATTER node.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This class is used to represent an MLOAD node.
This class is used to represent an MGATHER node.
SDValue getValueType(EVT)
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:406
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
DAGTypeLegalizer(SelectionDAG &dag)
This class is used to represent ISD::LOAD nodes.