LLVM  7.0.0svn
LegalizeTypes.h
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1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the DAGTypeLegalizer class. This is a private interface
11 // shared between the code that implements the SelectionDAG::LegalizeTypes
12 // method.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
17 #define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
18 
19 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/Debug.h"
24 
25 namespace llvm {
26 
27 //===----------------------------------------------------------------------===//
28 /// This takes an arbitrary SelectionDAG as input and hacks on it until only
29 /// value types the target machine can handle are left. This involves promoting
30 /// small sizes to large sizes or splitting up large values into small values.
31 ///
33  const TargetLowering &TLI;
34  SelectionDAG &DAG;
35 public:
36  /// This pass uses the NodeId on the SDNodes to hold information about the
37  /// state of the node. The enum has all the values.
38  enum NodeIdFlags {
39  /// All operands have been processed, so this node is ready to be handled.
40  ReadyToProcess = 0,
41 
42  /// This is a new node, not before seen, that was created in the process of
43  /// legalizing some other node.
44  NewNode = -1,
45 
46  /// This node's ID needs to be set to the number of its unprocessed
47  /// operands.
48  Unanalyzed = -2,
49 
50  /// This is a node that has already been processed.
51  Processed = -3
52 
53  // 1+ - This is a node which has this many unprocessed operands.
54  };
55 private:
56 
57  /// This is a bitvector that contains two bits for each simple value type,
58  /// where the two bits correspond to the LegalizeAction enum from
59  /// TargetLowering. This can be queried with "getTypeAction(VT)".
60  TargetLowering::ValueTypeActionImpl ValueTypeActions;
61 
62  /// Return how we should legalize values of this type.
63  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
64  return TLI.getTypeAction(*DAG.getContext(), VT);
65  }
66 
67  /// Return true if this type is legal on this target.
68  bool isTypeLegal(EVT VT) const {
69  return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
70  }
71 
72  /// Return true if this is a simple legal type.
73  bool isSimpleLegalType(EVT VT) const {
74  return VT.isSimple() && TLI.isTypeLegal(VT);
75  }
76 
77  /// Return true if this type can be passed in registers.
78  /// For example, x86_64's f128, should to be legally in registers
79  /// and only some operations converted to library calls or integer
80  /// bitwise operations.
81  bool isLegalInHWReg(EVT VT) const {
82  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
83  return VT == NVT && isSimpleLegalType(VT);
84  }
85 
86  EVT getSetCCResultType(EVT VT) const {
87  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
88  }
89 
90  /// Pretend all of this node's results are legal.
91  bool IgnoreNodeResults(SDNode *N) const {
92  return N->getOpcode() == ISD::TargetConstant ||
93  N->getOpcode() == ISD::Register;
94  }
95 
96  /// For integer nodes that are below legal width, this map indicates what
97  /// promoted value to use.
98  SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
99 
100  /// For integer nodes that need to be expanded this map indicates which
101  /// operands are the expanded version of the input.
103 
104  /// For floating-point nodes converted to integers of the same size, this map
105  /// indicates the converted value to use.
106  SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
107 
108  /// For floating-point nodes that have a smaller precision than the smallest
109  /// supported precision, this map indicates what promoted value to use.
110  SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;
111 
112  /// For float nodes that need to be expanded this map indicates which operands
113  /// are the expanded version of the input.
115 
116  /// For nodes that are <1 x ty>, this map indicates the scalar value of type
117  /// 'ty' to use.
118  SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
119 
120  /// For nodes that need to be split this map indicates which operands are the
121  /// expanded version of the input.
123 
124  /// For vector nodes that need to be widened, indicates the widened value to
125  /// use.
126  SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
127 
128  /// For values that have been replaced with another, indicates the replacement
129  /// value to use.
130  SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
131 
132  /// This defines a worklist of nodes to process. In order to be pushed onto
133  /// this worklist, all operands of a node must have already been processed.
134  SmallVector<SDNode*, 128> Worklist;
135 
136 public:
138  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
139  ValueTypeActions(TLI.getValueTypeActions()) {
141  "Too many value types for ValueTypeActions to hold!");
142  }
143 
144  /// This is the main entry point for the type legalizer. This does a
145  /// top-down traversal of the dag, legalizing types as it goes. Returns
146  /// "true" if it made any changes.
147  bool run();
148 
149  void NoteDeletion(SDNode *Old, SDNode *New) {
150  ExpungeNode(Old);
151  ExpungeNode(New);
152  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
153  ReplacedValues[SDValue(Old, i)] = SDValue(New, i);
154  }
155 
156  SelectionDAG &getDAG() const { return DAG; }
157 
158 private:
159  SDNode *AnalyzeNewNode(SDNode *N);
160  void AnalyzeNewValue(SDValue &Val);
161  void ExpungeNode(SDNode *N);
162  void PerformExpensiveChecks();
163  void RemapValue(SDValue &N);
164 
165  // Common routines.
166  SDValue BitConvertToInteger(SDValue Op);
167  SDValue BitConvertVectorToIntegerVector(SDValue Op);
168  SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
169  bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
170  bool CustomWidenLowerNode(SDNode *N, EVT VT);
171 
172  /// Replace each result of the given MERGE_VALUES node with the corresponding
173  /// input operand, except for the result 'ResNo', for which the corresponding
174  /// input operand is returned.
175  SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
176 
177  SDValue JoinIntegers(SDValue Lo, SDValue Hi);
178  SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
179 
180  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
181  SDNode *Node, bool isSigned);
182  std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
183 
184  SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT);
185 
186  void ReplaceValueWith(SDValue From, SDValue To);
187  void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
188  void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
189  SDValue &Lo, SDValue &Hi);
190 
191  void AddToWorklist(SDNode *N) {
192  N->setNodeId(ReadyToProcess);
193  Worklist.push_back(N);
194  }
195 
196  //===--------------------------------------------------------------------===//
197  // Integer Promotion Support: LegalizeIntegerTypes.cpp
198  //===--------------------------------------------------------------------===//
199 
200  /// Given a processed operand Op which was promoted to a larger integer type,
201  /// this returns the promoted value. The low bits of the promoted value
202  /// corresponding to the original type are exactly equal to Op.
203  /// The extra bits contain rubbish, so the promoted value may need to be zero-
204  /// or sign-extended from the original type before it is usable (the helpers
205  /// SExtPromotedInteger and ZExtPromotedInteger can do this for you).
206  /// For example, if Op is an i16 and was promoted to an i32, then this method
207  /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
208  /// 16 bits of which contain rubbish.
209  SDValue GetPromotedInteger(SDValue Op) {
210  SDValue &PromotedOp = PromotedIntegers[Op];
211  RemapValue(PromotedOp);
212  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
213  return PromotedOp;
214  }
215  void SetPromotedInteger(SDValue Op, SDValue Result);
216 
217  /// Get a promoted operand and sign extend it to the final size.
218  SDValue SExtPromotedInteger(SDValue Op) {
219  EVT OldVT = Op.getValueType();
220  SDLoc dl(Op);
221  Op = GetPromotedInteger(Op);
222  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
223  DAG.getValueType(OldVT));
224  }
225 
226  /// Get a promoted operand and zero extend it to the final size.
227  SDValue ZExtPromotedInteger(SDValue Op) {
228  EVT OldVT = Op.getValueType();
229  SDLoc dl(Op);
230  Op = GetPromotedInteger(Op);
231  return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType());
232  }
233 
234  // Integer Result Promotion.
235  void PromoteIntegerResult(SDNode *N, unsigned ResNo);
236  SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
237  SDValue PromoteIntRes_AssertSext(SDNode *N);
238  SDValue PromoteIntRes_AssertZext(SDNode *N);
239  SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
240  SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
241  SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
242  SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
243  SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
244  SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
245  SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
246  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
247  SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
248  SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
249  SDValue PromoteIntRes_BITCAST(SDNode *N);
250  SDValue PromoteIntRes_BSWAP(SDNode *N);
251  SDValue PromoteIntRes_BITREVERSE(SDNode *N);
252  SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
253  SDValue PromoteIntRes_Constant(SDNode *N);
254  SDValue PromoteIntRes_CTLZ(SDNode *N);
255  SDValue PromoteIntRes_CTPOP(SDNode *N);
256  SDValue PromoteIntRes_CTTZ(SDNode *N);
257  SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
258  SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
259  SDValue PromoteIntRes_FP_TO_FP16(SDNode *N);
260  SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
261  SDValue PromoteIntRes_LOAD(LoadSDNode *N);
262  SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
263  SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
264  SDValue PromoteIntRes_Overflow(SDNode *N);
265  SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
266  SDValue PromoteIntRes_SELECT(SDNode *N);
267  SDValue PromoteIntRes_VSELECT(SDNode *N);
268  SDValue PromoteIntRes_SELECT_CC(SDNode *N);
269  SDValue PromoteIntRes_SETCC(SDNode *N);
270  SDValue PromoteIntRes_SHL(SDNode *N);
271  SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
272  SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
273  SDValue PromoteIntRes_SExtIntBinOp(SDNode *N);
274  SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
275  SDValue PromoteIntRes_SRA(SDNode *N);
276  SDValue PromoteIntRes_SRL(SDNode *N);
277  SDValue PromoteIntRes_TRUNCATE(SDNode *N);
278  SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
279  SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo);
280  SDValue PromoteIntRes_UNDEF(SDNode *N);
281  SDValue PromoteIntRes_VAARG(SDNode *N);
282  SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
283 
284  // Integer Operand Promotion.
285  bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
286  SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
287  SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
288  SDValue PromoteIntOp_BITCAST(SDNode *N);
289  SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
290  SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
291  SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
292  SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
293  SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
294  SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
295  SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
296  SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
297  SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
298  SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
299  SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
300  SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
301  SDValue PromoteIntOp_Shift(SDNode *N);
302  SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
303  SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
304  SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
305  SDValue PromoteIntOp_TRUNCATE(SDNode *N);
306  SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
307  SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
308  SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
309  SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
310  SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
311  SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
312  SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
313 
314  void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
315 
316  //===--------------------------------------------------------------------===//
317  // Integer Expansion Support: LegalizeIntegerTypes.cpp
318  //===--------------------------------------------------------------------===//
319 
320  /// Given a processed operand Op which was expanded into two integers of half
321  /// the size, this returns the two halves. The low bits of Op are exactly
322  /// equal to the bits of Lo; the high bits exactly equal Hi.
323  /// For example, if Op is an i64 which was expanded into two i32's, then this
324  /// method returns the two i32's, with Lo being equal to the lower 32 bits of
325  /// Op, and Hi being equal to the upper 32 bits.
326  void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
327  void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
328 
329  // Integer Result Expansion.
330  void ExpandIntegerResult(SDNode *N, unsigned ResNo);
331  void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
332  void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
333  void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
334  void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
335  void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
336  void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
337  void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
338  void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
339  void ExpandIntRes_READCYCLECOUNTER (SDNode *N, SDValue &Lo, SDValue &Hi);
340  void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
341  void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
342  void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
343  void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
344  void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
345  void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
346  void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
347 
348  void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
349  void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
350  void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
351  void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
352  void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
353  void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi);
354  void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
355  void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
356  void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
357  void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
358  void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
359  void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
360  void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
361 
362  void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
363 
364  void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
365  void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
366  void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
367 
368  void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
369 
370  void ExpandShiftByConstant(SDNode *N, const APInt &Amt,
371  SDValue &Lo, SDValue &Hi);
372  bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
373  bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
374 
375  // Integer Operand Expansion.
376  bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
377  SDValue ExpandIntOp_BR_CC(SDNode *N);
378  SDValue ExpandIntOp_SELECT_CC(SDNode *N);
379  SDValue ExpandIntOp_SETCC(SDNode *N);
380  SDValue ExpandIntOp_SETCCE(SDNode *N);
381  SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
382  SDValue ExpandIntOp_Shift(SDNode *N);
383  SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
384  SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
385  SDValue ExpandIntOp_TRUNCATE(SDNode *N);
386  SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
387  SDValue ExpandIntOp_RETURNADDR(SDNode *N);
388  SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
389 
390  void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
391  ISD::CondCode &CCCode, const SDLoc &dl);
392 
393  //===--------------------------------------------------------------------===//
394  // Float to Integer Conversion Support: LegalizeFloatTypes.cpp
395  //===--------------------------------------------------------------------===//
396 
397  /// Given an operand Op of Float type, returns the integer if the Op is not
398  /// supported in target HW and converted to the integer.
399  /// The integer contains exactly the same bits as Op - only the type changed.
400  /// For example, if Op is an f32 which was softened to an i32, then this
401  /// method returns an i32, the bits of which coincide with those of Op.
402  /// If the Op can be efficiently supported in target HW or the operand must
403  /// stay in a register, the Op is not converted to an integer.
404  /// In that case, the given op is returned.
405  SDValue GetSoftenedFloat(SDValue Op) {
406  auto Iter = SoftenedFloats.find(Op);
407  if (Iter == SoftenedFloats.end()) {
408  assert(isSimpleLegalType(Op.getValueType()) &&
409  "Operand wasn't converted to integer?");
410  return Op;
411  }
412 
413  SDValue &SoftenedOp = Iter->second;
414  assert(SoftenedOp.getNode() && "Unconverted op in SoftenedFloats?");
415  RemapValue(SoftenedOp);
416  return SoftenedOp;
417  }
418  void SetSoftenedFloat(SDValue Op, SDValue Result);
419 
420  // Convert Float Results to Integer for Non-HW-supported Operations.
421  bool SoftenFloatResult(SDNode *N, unsigned ResNo);
422  SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
423  SDValue SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo);
424  SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
425  SDValue SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo);
426  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
427  SDValue SoftenFloatRes_FABS(SDNode *N, unsigned ResNo);
428  SDValue SoftenFloatRes_FMINNUM(SDNode *N);
429  SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
430  SDValue SoftenFloatRes_FADD(SDNode *N);
431  SDValue SoftenFloatRes_FCEIL(SDNode *N);
432  SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo);
433  SDValue SoftenFloatRes_FCOS(SDNode *N);
434  SDValue SoftenFloatRes_FDIV(SDNode *N);
435  SDValue SoftenFloatRes_FEXP(SDNode *N);
436  SDValue SoftenFloatRes_FEXP2(SDNode *N);
437  SDValue SoftenFloatRes_FFLOOR(SDNode *N);
438  SDValue SoftenFloatRes_FLOG(SDNode *N);
439  SDValue SoftenFloatRes_FLOG2(SDNode *N);
440  SDValue SoftenFloatRes_FLOG10(SDNode *N);
441  SDValue SoftenFloatRes_FMA(SDNode *N);
442  SDValue SoftenFloatRes_FMUL(SDNode *N);
443  SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
444  SDValue SoftenFloatRes_FNEG(SDNode *N, unsigned ResNo);
445  SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
446  SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N);
447  SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
448  SDValue SoftenFloatRes_FPOW(SDNode *N);
449  SDValue SoftenFloatRes_FPOWI(SDNode *N);
450  SDValue SoftenFloatRes_FREM(SDNode *N);
451  SDValue SoftenFloatRes_FRINT(SDNode *N);
452  SDValue SoftenFloatRes_FROUND(SDNode *N);
453  SDValue SoftenFloatRes_FSIN(SDNode *N);
454  SDValue SoftenFloatRes_FSQRT(SDNode *N);
455  SDValue SoftenFloatRes_FSUB(SDNode *N);
456  SDValue SoftenFloatRes_FTRUNC(SDNode *N);
457  SDValue SoftenFloatRes_LOAD(SDNode *N, unsigned ResNo);
458  SDValue SoftenFloatRes_SELECT(SDNode *N, unsigned ResNo);
459  SDValue SoftenFloatRes_SELECT_CC(SDNode *N, unsigned ResNo);
460  SDValue SoftenFloatRes_UNDEF(SDNode *N);
461  SDValue SoftenFloatRes_VAARG(SDNode *N);
462  SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
463 
464  // Return true if we can skip softening the given operand or SDNode because
465  // either it was soften before by SoftenFloatResult and references to the
466  // operand were replaced by ReplaceValueWith or it's value type is legal in HW
467  // registers and the operand can be left unchanged.
468  bool CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo);
469 
470  // Convert Float Operand to Integer for Non-HW-supported Operations.
471  bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
472  SDValue SoftenFloatOp_BITCAST(SDNode *N);
473  SDValue SoftenFloatOp_COPY_TO_REG(SDNode *N);
474  SDValue SoftenFloatOp_BR_CC(SDNode *N);
475  SDValue SoftenFloatOp_FABS(SDNode *N);
476  SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
477  SDValue SoftenFloatOp_FNEG(SDNode *N);
478  SDValue SoftenFloatOp_FP_EXTEND(SDNode *N);
479  SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
480  SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
481  SDValue SoftenFloatOp_SELECT(SDNode *N);
482  SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
483  SDValue SoftenFloatOp_SETCC(SDNode *N);
484  SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
485 
486  //===--------------------------------------------------------------------===//
487  // Float Expansion Support: LegalizeFloatTypes.cpp
488  //===--------------------------------------------------------------------===//
489 
490  /// Given a processed operand Op which was expanded into two floating-point
491  /// values of half the size, this returns the two halves.
492  /// The low bits of Op are exactly equal to the bits of Lo; the high bits
493  /// exactly equal Hi. For example, if Op is a ppcf128 which was expanded
494  /// into two f64's, then this method returns the two f64's, with Lo being
495  /// equal to the lower 64 bits of Op, and Hi to the upper 64 bits.
496  void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
497  void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
498 
499  // Float Result Expansion.
500  void ExpandFloatResult(SDNode *N, unsigned ResNo);
501  void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
502  void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
503  void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
504  void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
505  void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
506  void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi);
507  void ExpandFloatRes_FCOPYSIGN (SDNode *N, SDValue &Lo, SDValue &Hi);
508  void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi);
509  void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
510  void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi);
511  void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi);
512  void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi);
513  void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
514  void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
515  void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
516  void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi);
517  void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
518  void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
519  void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
520  void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
521  void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
522  void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
523  void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi);
524  void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
525  void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi);
526  void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
527  void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
528  void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
529  void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
530  void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
531  void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
532 
533  // Float Operand Expansion.
534  bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
535  SDValue ExpandFloatOp_BR_CC(SDNode *N);
536  SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
537  SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
538  SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
539  SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
540  SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
541  SDValue ExpandFloatOp_SETCC(SDNode *N);
542  SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
543 
544  void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
545  ISD::CondCode &CCCode, const SDLoc &dl);
546 
547  //===--------------------------------------------------------------------===//
548  // Float promotion support: LegalizeFloatTypes.cpp
549  //===--------------------------------------------------------------------===//
550 
551  SDValue GetPromotedFloat(SDValue Op) {
552  SDValue &PromotedOp = PromotedFloats[Op];
553  RemapValue(PromotedOp);
554  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
555  return PromotedOp;
556  }
557  void SetPromotedFloat(SDValue Op, SDValue Result);
558 
559  void PromoteFloatResult(SDNode *N, unsigned ResNo);
560  SDValue PromoteFloatRes_BITCAST(SDNode *N);
561  SDValue PromoteFloatRes_BinOp(SDNode *N);
562  SDValue PromoteFloatRes_ConstantFP(SDNode *N);
563  SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
564  SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);
565  SDValue PromoteFloatRes_FMAD(SDNode *N);
566  SDValue PromoteFloatRes_FPOWI(SDNode *N);
567  SDValue PromoteFloatRes_FP_ROUND(SDNode *N);
568  SDValue PromoteFloatRes_LOAD(SDNode *N);
569  SDValue PromoteFloatRes_SELECT(SDNode *N);
570  SDValue PromoteFloatRes_SELECT_CC(SDNode *N);
571  SDValue PromoteFloatRes_UnaryOp(SDNode *N);
572  SDValue PromoteFloatRes_UNDEF(SDNode *N);
573  SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
574 
575  bool PromoteFloatOperand(SDNode *N, unsigned ResNo);
576  SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
577  SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
578  SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
579  SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo);
580  SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);
581  SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);
582  SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);
583 
584  //===--------------------------------------------------------------------===//
585  // Scalarization Support: LegalizeVectorTypes.cpp
586  //===--------------------------------------------------------------------===//
587 
588  /// Given a processed one-element vector Op which was scalarized to its
589  /// element type, this returns the element. For example, if Op is a v1i32,
590  /// Op = < i32 val >, this method returns val, an i32.
591  SDValue GetScalarizedVector(SDValue Op) {
592  SDValue &ScalarizedOp = ScalarizedVectors[Op];
593  RemapValue(ScalarizedOp);
594  assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
595  return ScalarizedOp;
596  }
597  void SetScalarizedVector(SDValue Op, SDValue Result);
598 
599  // Vector Result Scalarization: <1 x ty> -> ty.
600  void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
601  SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
602  SDValue ScalarizeVecRes_BinOp(SDNode *N);
603  SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
604  SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
605  SDValue ScalarizeVecRes_InregOp(SDNode *N);
606  SDValue ScalarizeVecRes_VecInregOp(SDNode *N);
607 
608  SDValue ScalarizeVecRes_BITCAST(SDNode *N);
609  SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N);
610  SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
611  SDValue ScalarizeVecRes_FP_ROUND(SDNode *N);
612  SDValue ScalarizeVecRes_FPOWI(SDNode *N);
613  SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
614  SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
615  SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
616  SDValue ScalarizeVecRes_VSELECT(SDNode *N);
617  SDValue ScalarizeVecRes_SELECT(SDNode *N);
618  SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
619  SDValue ScalarizeVecRes_SETCC(SDNode *N);
620  SDValue ScalarizeVecRes_UNDEF(SDNode *N);
621  SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
622 
623  // Vector Operand Scalarization: <1 x ty> -> ty.
624  bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
625  SDValue ScalarizeVecOp_BITCAST(SDNode *N);
626  SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
627  SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
628  SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
629  SDValue ScalarizeVecOp_VSELECT(SDNode *N);
630  SDValue ScalarizeVecOp_VSETCC(SDNode *N);
631  SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
632  SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
633 
634  //===--------------------------------------------------------------------===//
635  // Vector Splitting Support: LegalizeVectorTypes.cpp
636  //===--------------------------------------------------------------------===//
637 
638  /// Given a processed vector Op which was split into vectors of half the size,
639  /// this method returns the halves. The first elements of Op coincide with the
640  /// elements of Lo; the remaining elements of Op coincide with the elements of
641  /// Hi: Op is what you would get by concatenating Lo and Hi.
642  /// For example, if Op is a v8i32 that was split into two v4i32's, then this
643  /// method returns the two v4i32's, with Lo corresponding to the first 4
644  /// elements of Op, and Hi to the last 4 elements.
645  void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
646  void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
647 
648  // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
649  void SplitVectorResult(SDNode *N, unsigned OpNo);
650  void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
651  void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
652  void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
653  void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
654  void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
655  void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
656 
657  void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
658  void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
659  void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
660  void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
661  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
662  void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
663  void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
664  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
665  void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
666  void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi);
667  void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi);
668  void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
669  void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
670  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
671  SDValue &Hi);
672 
673  // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
674  bool SplitVectorOperand(SDNode *N, unsigned OpNo);
675  SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo);
676  SDValue SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo);
677  SDValue SplitVecOp_UnaryOp(SDNode *N);
678  SDValue SplitVecOp_TruncateHelper(SDNode *N);
679 
680  SDValue SplitVecOp_BITCAST(SDNode *N);
681  SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
682  SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
683  SDValue SplitVecOp_ExtVecInRegOp(SDNode *N);
684  SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
685  SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
686  SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
687  SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
688  SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
689  SDValue SplitVecOp_VSETCC(SDNode *N);
690  SDValue SplitVecOp_FP_ROUND(SDNode *N);
691  SDValue SplitVecOp_FCOPYSIGN(SDNode *N);
692 
693  //===--------------------------------------------------------------------===//
694  // Vector Widening Support: LegalizeVectorTypes.cpp
695  //===--------------------------------------------------------------------===//
696 
697  /// Given a processed vector Op which was widened into a larger vector, this
698  /// method returns the larger vector. The elements of the returned vector
699  /// consist of the elements of Op followed by elements containing rubbish.
700  /// For example, if Op is a v2i32 that was widened to a v4i32, then this
701  /// method returns a v4i32 for which the first two elements are the same as
702  /// those of Op, while the last two elements contain rubbish.
703  SDValue GetWidenedVector(SDValue Op) {
704  SDValue &WidenedOp = WidenedVectors[Op];
705  RemapValue(WidenedOp);
706  assert(WidenedOp.getNode() && "Operand wasn't widened?");
707  return WidenedOp;
708  }
709  void SetWidenedVector(SDValue Op, SDValue Result);
710 
711  // Widen Vector Result Promotion.
712  void WidenVectorResult(SDNode *N, unsigned ResNo);
713  SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo);
714  SDValue WidenVecRes_BITCAST(SDNode* N);
715  SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
716  SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
717  SDValue WidenVecRes_EXTEND_VECTOR_INREG(SDNode* N);
718  SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
719  SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
720  SDValue WidenVecRes_LOAD(SDNode* N);
721  SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N);
722  SDValue WidenVecRes_MGATHER(MaskedGatherSDNode* N);
723  SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
724  SDValue WidenVecRes_SELECT(SDNode* N);
725  SDValue WidenVSELECTAndMask(SDNode *N);
726  SDValue WidenVecRes_SELECT_CC(SDNode* N);
727  SDValue WidenVecRes_SETCC(SDNode* N);
728  SDValue WidenVecRes_UNDEF(SDNode *N);
729  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
730 
731  SDValue WidenVecRes_Ternary(SDNode *N);
732  SDValue WidenVecRes_Binary(SDNode *N);
733  SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
734  SDValue WidenVecRes_Convert(SDNode *N);
735  SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
736  SDValue WidenVecRes_POWI(SDNode *N);
737  SDValue WidenVecRes_Shift(SDNode *N);
738  SDValue WidenVecRes_Unary(SDNode *N);
739  SDValue WidenVecRes_InregOp(SDNode *N);
740 
741  // Widen Vector Operand.
742  bool WidenVectorOperand(SDNode *N, unsigned OpNo);
743  SDValue WidenVecOp_BITCAST(SDNode *N);
744  SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
745  SDValue WidenVecOp_EXTEND(SDNode *N);
746  SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
747  SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
748  SDValue WidenVecOp_STORE(SDNode* N);
749  SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
750  SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo);
751  SDValue WidenVecOp_SETCC(SDNode* N);
752 
753  SDValue WidenVecOp_Convert(SDNode *N);
754  SDValue WidenVecOp_FCOPYSIGN(SDNode *N);
755 
756  //===--------------------------------------------------------------------===//
757  // Vector Widening Utilities Support: LegalizeVectorTypes.cpp
758  //===--------------------------------------------------------------------===//
759 
760  /// Helper function to generate a set of loads to load a vector with a
761  /// resulting wider type. It takes:
762  /// LdChain: list of chains for the load to be generated.
763  /// Ld: load to widen
764  SDValue GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
765  LoadSDNode *LD);
766 
767  /// Helper function to generate a set of extension loads to load a vector with
768  /// a resulting wider type. It takes:
769  /// LdChain: list of chains for the load to be generated.
770  /// Ld: load to widen
771  /// ExtType: extension element type
772  SDValue GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
773  LoadSDNode *LD, ISD::LoadExtType ExtType);
774 
775  /// Helper function to generate a set of stores to store a widen vector into
776  /// non-widen memory.
777  /// StChain: list of chains for the stores we have generated
778  /// ST: store of a widen value
779  void GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);
780 
781  /// Helper function to generate a set of stores to store a truncate widen
782  /// vector into non-widen memory.
783  /// StChain: list of chains for the stores we have generated
784  /// ST: store of a widen value
785  void GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
786  StoreSDNode *ST);
787 
788  /// Modifies a vector input (widen or narrows) to a vector of NVT. The
789  /// input vector must have the same element type as NVT.
790  /// When FillWithZeroes is "on" the vector will be widened with zeroes.
791  /// By default, the vector will be widened with undefined values.
792  SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
793 
794  /// Return a mask of vector type MaskVT to replace InMask. Also adjust
795  /// MaskVT to ToMaskVT if needed with vector extension or truncation.
796  SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT);
797 
798  /// Get the target mask VT, and widen if needed.
799  EVT getSETCCWidenedResultTy(SDValue SetCC);
800 
801  //===--------------------------------------------------------------------===//
802  // Generic Splitting: LegalizeTypesGeneric.cpp
803  //===--------------------------------------------------------------------===//
804 
805  // Legalization methods which only use that the illegal type is split into two
806  // not necessarily identical types. As such they can be used for splitting
807  // vectors and expanding integers and floats.
808 
809  void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
810  if (Op.getValueType().isVector())
811  GetSplitVector(Op, Lo, Hi);
812  else if (Op.getValueType().isInteger())
813  GetExpandedInteger(Op, Lo, Hi);
814  else
815  GetExpandedFloat(Op, Lo, Hi);
816  }
817 
818  /// Use ISD::EXTRACT_ELEMENT nodes to extract the low and high parts of the
819  /// given value.
820  void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi);
821 
822  // Generic Result Splitting.
823  void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
824  SDValue &Lo, SDValue &Hi);
825  void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
826  void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
827  void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
828 
829  //===--------------------------------------------------------------------===//
830  // Generic Expansion: LegalizeTypesGeneric.cpp
831  //===--------------------------------------------------------------------===//
832 
833  // Legalization methods which only use that the illegal type is split into two
834  // identical types of half the size, and that the Lo/Hi part is stored first
835  // in memory on little/big-endian machines, followed by the Hi/Lo part. As
836  // such they can be used for expanding integers and floats.
837 
838  void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
839  if (Op.getValueType().isInteger())
840  GetExpandedInteger(Op, Lo, Hi);
841  else
842  GetExpandedFloat(Op, Lo, Hi);
843  }
844 
845 
846  /// This function will split the integer \p Op into \p NumElements
847  /// operations of type \p EltVT and store them in \p Ops.
848  void IntegerToVector(SDValue Op, unsigned NumElements,
849  SmallVectorImpl<SDValue> &Ops, EVT EltVT);
850 
851  // Generic Result Expansion.
852  void ExpandRes_MERGE_VALUES (SDNode *N, unsigned ResNo,
853  SDValue &Lo, SDValue &Hi);
854  void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi);
855  void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
856  void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
857  void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
858  void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
859  void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
860 
861  // Generic Operand Expansion.
862  SDValue ExpandOp_BITCAST (SDNode *N);
863  SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
864  SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
865  SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);
866  SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N);
867  SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
868 };
869 
870 } // end namespace llvm.
871 
872 #endif
EVT getValueType() const
Return the ValueType of the referenced return value.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
This takes an arbitrary SelectionDAG as input and hacks on it until only value types the target machi...
Definition: LegalizeTypes.h:32
void setNodeId(int Id)
Set unique node id.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:390
This is an SDNode representing atomic operations.
SelectionDAG & getDAG() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This class is used to represent an MSTORE node.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:125
This class is used to represent ISD::STORE nodes.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:893
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:105
Extended Value Type.
Definition: ValueTypes.h:34
NodeIdFlags
This pass uses the NodeId on the SDNodes to hold information about the state of the node...
Definition: LegalizeTypes.h:38
void NoteDeletion(SDNode *Old, SDNode *New)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:464
#define N
This class is used to represent an MSCATTER node.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This class is used to represent an MLOAD node.
This class is used to represent an MGATHER node.
SDValue getValueType(EVT)
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:396
This file describes how to lower LLVM code to machine code.
DAGTypeLegalizer(SelectionDAG &dag)
This class is used to represent ISD::LOAD nodes.