LLVM  9.0.0svn
LegalizeVectorOps.cpp
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1 //===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::LegalizeVectors method.
10 //
11 // The vector legalizer looks for vector operations which might need to be
12 // scalarized and legalizes them. This is a separate step from Legalize because
13 // scalarizing can introduce illegal types. For example, suppose we have an
14 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
15 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
16 // operation, which introduces nodes with the illegal type i64 which must be
17 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
18 // the operation must be unrolled, which introduces nodes with the illegal
19 // type i8 which must be promoted.
20 //
21 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
22 // or operations that happen to take a vector which are custom-lowered;
23 // the legalization for such operations never produces nodes
24 // with illegal types, so it's okay to put off legalizing them until
25 // SelectionDAG::Legalize runs.
26 //
27 //===----------------------------------------------------------------------===//
28 
29 #include "llvm/ADT/APInt.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Compiler.h"
44 #include <cassert>
45 #include <cstdint>
46 #include <iterator>
47 #include <utility>
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "legalizevectorops"
52 
53 namespace {
54 
55 class VectorLegalizer {
56  SelectionDAG& DAG;
57  const TargetLowering &TLI;
58  bool Changed = false; // Keep track of whether anything changed
59 
60  /// For nodes that are of legal width, and that have more than one use, this
61  /// map indicates what regularized operand to use. This allows us to avoid
62  /// legalizing the same thing more than once.
64 
65  /// Adds a node to the translation cache.
66  void AddLegalizedOperand(SDValue From, SDValue To) {
67  LegalizedNodes.insert(std::make_pair(From, To));
68  // If someone requests legalization of the new node, return itself.
69  if (From != To)
70  LegalizedNodes.insert(std::make_pair(To, To));
71  }
72 
73  /// Legalizes the given node.
74  SDValue LegalizeOp(SDValue Op);
75 
76  /// Assuming the node is legal, "legalize" the results.
77  SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
78 
79  /// Implements unrolling a VSETCC.
80  SDValue UnrollVSETCC(SDValue Op);
81 
82  /// Implement expand-based legalization of vector operations.
83  ///
84  /// This is just a high-level routine to dispatch to specific code paths for
85  /// operations to legalize them.
86  SDValue Expand(SDValue Op);
87 
88  /// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
89  /// FP_TO_SINT isn't legal.
90  SDValue ExpandFP_TO_UINT(SDValue Op);
91 
92  /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
93  /// SINT_TO_FLOAT and SHR on vectors isn't legal.
94  SDValue ExpandUINT_TO_FLOAT(SDValue Op);
95 
96  /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
97  SDValue ExpandSEXTINREG(SDValue Op);
98 
99  /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
100  ///
101  /// Shuffles the low lanes of the operand into place and bitcasts to the proper
102  /// type. The contents of the bits in the extended part of each element are
103  /// undef.
104  SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
105 
106  /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
107  ///
108  /// Shuffles the low lanes of the operand into place, bitcasts to the proper
109  /// type, then shifts left and arithmetic shifts right to introduce a sign
110  /// extension.
111  SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
112 
113  /// Implement expansion for ZERO_EXTEND_VECTOR_INREG.
114  ///
115  /// Shuffles the low lanes of the operand into place and blends zeros into
116  /// the remaining lanes, finally bitcasting to the proper type.
117  SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
118 
119  /// Implement expand-based legalization of ABS vector operations.
120  /// If following expanding is legal/custom then do it:
121  /// (ABS x) --> (XOR (ADD x, (SRA x, sizeof(x)-1)), (SRA x, sizeof(x)-1))
122  /// else unroll the operation.
123  SDValue ExpandABS(SDValue Op);
124 
125  /// Expand bswap of vectors into a shuffle if legal.
126  SDValue ExpandBSWAP(SDValue Op);
127 
128  /// Implement vselect in terms of XOR, AND, OR when blend is not
129  /// supported by the target.
130  SDValue ExpandVSELECT(SDValue Op);
131  SDValue ExpandSELECT(SDValue Op);
132  SDValue ExpandLoad(SDValue Op);
133  SDValue ExpandStore(SDValue Op);
134  SDValue ExpandFNEG(SDValue Op);
135  SDValue ExpandFSUB(SDValue Op);
136  SDValue ExpandBITREVERSE(SDValue Op);
137  SDValue ExpandCTPOP(SDValue Op);
138  SDValue ExpandCTLZ(SDValue Op);
139  SDValue ExpandCTTZ(SDValue Op);
140  SDValue ExpandFunnelShift(SDValue Op);
141  SDValue ExpandROT(SDValue Op);
142  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
143  SDValue ExpandAddSubSat(SDValue Op);
144  SDValue ExpandFixedPointMul(SDValue Op);
145  SDValue ExpandStrictFPOp(SDValue Op);
146 
147  /// Implements vector promotion.
148  ///
149  /// This is essentially just bitcasting the operands to a different type and
150  /// bitcasting the result back to the original type.
151  SDValue Promote(SDValue Op);
152 
153  /// Implements [SU]INT_TO_FP vector promotion.
154  ///
155  /// This is a [zs]ext of the input operand to a larger integer type.
156  SDValue PromoteINT_TO_FP(SDValue Op);
157 
158  /// Implements FP_TO_[SU]INT vector promotion of the result type.
159  ///
160  /// It is promoted to a larger integer type. The result is then
161  /// truncated back to the original type.
162  SDValue PromoteFP_TO_INT(SDValue Op);
163 
164 public:
165  VectorLegalizer(SelectionDAG& dag) :
166  DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
167 
168  /// Begin legalizer the vector operations in the DAG.
169  bool Run();
170 };
171 
172 } // end anonymous namespace
173 
174 bool VectorLegalizer::Run() {
175  // Before we start legalizing vector nodes, check if there are any vectors.
176  bool HasVectors = false;
177  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
178  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
179  // Check if the values of the nodes contain vectors. We don't need to check
180  // the operands because we are going to check their values at some point.
181  for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
182  J != E; ++J)
183  HasVectors |= J->isVector();
184 
185  // If we found a vector node we can start the legalization.
186  if (HasVectors)
187  break;
188  }
189 
190  // If this basic block has no vectors then no need to legalize vectors.
191  if (!HasVectors)
192  return false;
193 
194  // The legalize process is inherently a bottom-up recursive process (users
195  // legalize their uses before themselves). Given infinite stack space, we
196  // could just start legalizing on the root and traverse the whole graph. In
197  // practice however, this causes us to run out of stack space on large basic
198  // blocks. To avoid this problem, compute an ordering of the nodes where each
199  // node is only legalized after all of its operands are legalized.
200  DAG.AssignTopologicalOrder();
201  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
202  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
203  LegalizeOp(SDValue(&*I, 0));
204 
205  // Finally, it's possible the root changed. Get the new root.
206  SDValue OldRoot = DAG.getRoot();
207  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
208  DAG.setRoot(LegalizedNodes[OldRoot]);
209 
210  LegalizedNodes.clear();
211 
212  // Remove dead nodes now.
213  DAG.RemoveDeadNodes();
214 
215  return Changed;
216 }
217 
218 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
219  // Generic legalization: just pass the operand through.
220  for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
221  AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
222  return Result.getValue(Op.getResNo());
223 }
224 
225 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
226  // Note that LegalizeOp may be reentered even from single-use nodes, which
227  // means that we always must cache transformed nodes.
228  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
229  if (I != LegalizedNodes.end()) return I->second;
230 
231  SDNode* Node = Op.getNode();
232 
233  // Legalize the operands
235  for (const SDValue &Op : Node->op_values())
236  Ops.push_back(LegalizeOp(Op));
237 
238  SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops),
239  Op.getResNo());
240 
241  if (Op.getOpcode() == ISD::LOAD) {
242  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
244  if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
245  LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: ";
246  Node->dump(&DAG));
247  switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
248  LD->getMemoryVT())) {
249  default: llvm_unreachable("This action is not supported yet!");
251  return TranslateLegalizeResults(Op, Result);
253  if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
254  assert(Lowered->getNumValues() == Op->getNumValues() &&
255  "Unexpected number of results");
256  if (Lowered != Result) {
257  // Make sure the new code is also legal.
258  Lowered = LegalizeOp(Lowered);
259  Changed = true;
260  }
261  return TranslateLegalizeResults(Op, Lowered);
262  }
265  Changed = true;
266  return LegalizeOp(ExpandLoad(Op));
267  }
268  }
269  } else if (Op.getOpcode() == ISD::STORE) {
270  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
271  EVT StVT = ST->getMemoryVT();
272  MVT ValVT = ST->getValue().getSimpleValueType();
273  if (StVT.isVector() && ST->isTruncatingStore()) {
274  LLVM_DEBUG(dbgs() << "\nLegalizing truncating vector store: ";
275  Node->dump(&DAG));
276  switch (TLI.getTruncStoreAction(ValVT, StVT)) {
277  default: llvm_unreachable("This action is not supported yet!");
279  return TranslateLegalizeResults(Op, Result);
280  case TargetLowering::Custom: {
281  SDValue Lowered = TLI.LowerOperation(Result, DAG);
282  if (Lowered != Result) {
283  // Make sure the new code is also legal.
284  Lowered = LegalizeOp(Lowered);
285  Changed = true;
286  }
287  return TranslateLegalizeResults(Op, Lowered);
288  }
290  Changed = true;
291  return LegalizeOp(ExpandStore(Op));
292  }
293  }
294  }
295 
296  bool HasVectorValue = false;
297  for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
298  J != E;
299  ++J)
300  HasVectorValue |= J->isVector();
301  if (!HasVectorValue)
302  return TranslateLegalizeResults(Op, Result);
303 
305  switch (Op.getOpcode()) {
306  default:
307  return TranslateLegalizeResults(Op, Result);
308  case ISD::STRICT_FADD:
309  case ISD::STRICT_FSUB:
310  case ISD::STRICT_FMUL:
311  case ISD::STRICT_FDIV:
312  case ISD::STRICT_FREM:
313  case ISD::STRICT_FSQRT:
314  case ISD::STRICT_FMA:
315  case ISD::STRICT_FPOW:
316  case ISD::STRICT_FPOWI:
317  case ISD::STRICT_FSIN:
318  case ISD::STRICT_FCOS:
319  case ISD::STRICT_FEXP:
320  case ISD::STRICT_FEXP2:
321  case ISD::STRICT_FLOG:
322  case ISD::STRICT_FLOG10:
323  case ISD::STRICT_FLOG2:
324  case ISD::STRICT_FRINT:
326  case ISD::STRICT_FMAXNUM:
327  case ISD::STRICT_FMINNUM:
328  case ISD::STRICT_FCEIL:
329  case ISD::STRICT_FFLOOR:
330  case ISD::STRICT_FROUND:
331  case ISD::STRICT_FTRUNC:
332  // These pseudo-ops get legalized as if they were their non-strict
333  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
334  // is also legal, but if ISD::FSQRT requires expansion then so does
335  // ISD::STRICT_FSQRT.
336  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
337  Node->getValueType(0));
338  break;
339  case ISD::ADD:
340  case ISD::SUB:
341  case ISD::MUL:
342  case ISD::MULHS:
343  case ISD::MULHU:
344  case ISD::SDIV:
345  case ISD::UDIV:
346  case ISD::SREM:
347  case ISD::UREM:
348  case ISD::SDIVREM:
349  case ISD::UDIVREM:
350  case ISD::FADD:
351  case ISD::FSUB:
352  case ISD::FMUL:
353  case ISD::FDIV:
354  case ISD::FREM:
355  case ISD::AND:
356  case ISD::OR:
357  case ISD::XOR:
358  case ISD::SHL:
359  case ISD::SRA:
360  case ISD::SRL:
361  case ISD::FSHL:
362  case ISD::FSHR:
363  case ISD::ROTL:
364  case ISD::ROTR:
365  case ISD::ABS:
366  case ISD::BSWAP:
367  case ISD::BITREVERSE:
368  case ISD::CTLZ:
369  case ISD::CTTZ:
372  case ISD::CTPOP:
373  case ISD::SELECT:
374  case ISD::VSELECT:
375  case ISD::SELECT_CC:
376  case ISD::SETCC:
377  case ISD::ZERO_EXTEND:
378  case ISD::ANY_EXTEND:
379  case ISD::TRUNCATE:
380  case ISD::SIGN_EXTEND:
381  case ISD::FP_TO_SINT:
382  case ISD::FP_TO_UINT:
383  case ISD::FNEG:
384  case ISD::FABS:
385  case ISD::FMINNUM:
386  case ISD::FMAXNUM:
387  case ISD::FMINNUM_IEEE:
388  case ISD::FMAXNUM_IEEE:
389  case ISD::FMINIMUM:
390  case ISD::FMAXIMUM:
391  case ISD::FCOPYSIGN:
392  case ISD::FSQRT:
393  case ISD::FSIN:
394  case ISD::FCOS:
395  case ISD::FPOWI:
396  case ISD::FPOW:
397  case ISD::FLOG:
398  case ISD::FLOG2:
399  case ISD::FLOG10:
400  case ISD::FEXP:
401  case ISD::FEXP2:
402  case ISD::FCEIL:
403  case ISD::FTRUNC:
404  case ISD::FRINT:
405  case ISD::FNEARBYINT:
406  case ISD::FROUND:
407  case ISD::FFLOOR:
408  case ISD::FP_ROUND:
409  case ISD::FP_EXTEND:
410  case ISD::FMA:
415  case ISD::SMIN:
416  case ISD::SMAX:
417  case ISD::UMIN:
418  case ISD::UMAX:
419  case ISD::SMUL_LOHI:
420  case ISD::UMUL_LOHI:
421  case ISD::FCANONICALIZE:
422  case ISD::SADDSAT:
423  case ISD::UADDSAT:
424  case ISD::SSUBSAT:
425  case ISD::USUBSAT:
426  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
427  break;
428  case ISD::SMULFIX:
429  case ISD::UMULFIX: {
430  unsigned Scale = Node->getConstantOperandVal(2);
431  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
432  Node->getValueType(0), Scale);
433  break;
434  }
435  case ISD::FP_ROUND_INREG:
436  Action = TLI.getOperationAction(Node->getOpcode(),
437  cast<VTSDNode>(Node->getOperand(1))->getVT());
438  break;
439  case ISD::SINT_TO_FP:
440  case ISD::UINT_TO_FP:
441  Action = TLI.getOperationAction(Node->getOpcode(),
442  Node->getOperand(0).getValueType());
443  break;
444  }
445 
446  LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
447 
448  switch (Action) {
449  default: llvm_unreachable("This action is not supported yet!");
451  Result = Promote(Op);
452  Changed = true;
453  break;
455  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
456  break;
457  case TargetLowering::Custom: {
458  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
459  if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
460  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
461  Result = Tmp1;
462  break;
463  }
464  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
466  }
468  Result = Expand(Op);
469  }
470 
471  // Make sure that the generated code is itself legal.
472  if (Result != Op) {
473  Result = LegalizeOp(Result);
474  Changed = true;
475  }
476 
477  // Note that LegalizeOp may be reentered even from single-use nodes, which
478  // means that we always must cache transformed nodes.
479  AddLegalizedOperand(Op, Result);
480  return Result;
481 }
482 
483 SDValue VectorLegalizer::Promote(SDValue Op) {
484  // For a few operations there is a specific concept for promotion based on
485  // the operand's type.
486  switch (Op.getOpcode()) {
487  case ISD::SINT_TO_FP:
488  case ISD::UINT_TO_FP:
489  // "Promote" the operation by extending the operand.
490  return PromoteINT_TO_FP(Op);
491  case ISD::FP_TO_UINT:
492  case ISD::FP_TO_SINT:
493  // Promote the operation by extending the operand.
494  return PromoteFP_TO_INT(Op);
495  }
496 
497  // There are currently two cases of vector promotion:
498  // 1) Bitcasting a vector of integers to a different type to a vector of the
499  // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
500  // 2) Extending a vector of floats to a vector of the same number of larger
501  // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
502  MVT VT = Op.getSimpleValueType();
503  assert(Op.getNode()->getNumValues() == 1 &&
504  "Can't promote a vector with multiple results!");
505  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
506  SDLoc dl(Op);
508 
509  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
510  if (Op.getOperand(j).getValueType().isVector())
511  if (Op.getOperand(j)
512  .getValueType()
514  .isFloatingPoint() &&
515  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
516  Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
517  else
518  Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
519  else
520  Operands[j] = Op.getOperand(j);
521  }
522 
523  Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
524  if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
526  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
527  return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
528  else
529  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
530 }
531 
532 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
533  // INT_TO_FP operations may require the input operand be promoted even
534  // when the type is otherwise legal.
535  MVT VT = Op.getOperand(0).getSimpleValueType();
536  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
538  "Vectors have different number of elements!");
539 
540  SDLoc dl(Op);
542 
543  unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
545  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
546  if (Op.getOperand(j).getValueType().isVector())
547  Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
548  else
549  Operands[j] = Op.getOperand(j);
550  }
551 
552  return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
553 }
554 
555 // For FP_TO_INT we promote the result type to a vector type with wider
556 // elements and then truncate the result. This is different from the default
557 // PromoteVector which uses bitcast to promote thus assumning that the
558 // promoted vector type has the same overall size.
559 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
560  MVT VT = Op.getSimpleValueType();
561  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
563  "Vectors have different number of elements!");
564 
565  unsigned NewOpc = Op->getOpcode();
566  // Change FP_TO_UINT to FP_TO_SINT if possible.
567  // TODO: Should we only do this if FP_TO_UINT itself isn't legal?
568  if (NewOpc == ISD::FP_TO_UINT &&
569  TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
570  NewOpc = ISD::FP_TO_SINT;
571 
572  SDLoc dl(Op);
573  SDValue Promoted = DAG.getNode(NewOpc, dl, NVT, Op.getOperand(0));
574 
575  // Assert that the converted value fits in the original type. If it doesn't
576  // (eg: because the value being converted is too big), then the result of the
577  // original operation was undefined anyway, so the assert is still correct.
578  Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
579  : ISD::AssertSext,
580  dl, NVT, Promoted,
581  DAG.getValueType(VT.getScalarType()));
582  return DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
583 }
584 
585 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
586  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
587 
588  EVT SrcVT = LD->getMemoryVT();
589  EVT SrcEltVT = SrcVT.getScalarType();
590  unsigned NumElem = SrcVT.getVectorNumElements();
591 
592  SDValue NewChain;
593  SDValue Value;
594  if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
595  SDLoc dl(Op);
596 
598  SmallVector<SDValue, 8> LoadChains;
599 
600  EVT DstEltVT = LD->getValueType(0).getScalarType();
601  SDValue Chain = LD->getChain();
602  SDValue BasePTR = LD->getBasePtr();
604 
605  // When elements in a vector is not byte-addressable, we cannot directly
606  // load each element by advancing pointer, which could only address bytes.
607  // Instead, we load all significant words, mask bits off, and concatenate
608  // them to form each element. Finally, they are extended to destination
609  // scalar type to build the destination vector.
610  EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
611 
612  assert(WideVT.isRound() &&
613  "Could not handle the sophisticated case when the widest integer is"
614  " not power of 2.");
615  assert(WideVT.bitsGE(SrcEltVT) &&
616  "Type is not legalized?");
617 
618  unsigned WideBytes = WideVT.getStoreSize();
619  unsigned Offset = 0;
620  unsigned RemainingBytes = SrcVT.getStoreSize();
621  SmallVector<SDValue, 8> LoadVals;
622  while (RemainingBytes > 0) {
623  SDValue ScalarLoad;
624  unsigned LoadBytes = WideBytes;
625 
626  if (RemainingBytes >= LoadBytes) {
627  ScalarLoad =
628  DAG.getLoad(WideVT, dl, Chain, BasePTR,
629  LD->getPointerInfo().getWithOffset(Offset),
630  MinAlign(LD->getAlignment(), Offset),
631  LD->getMemOperand()->getFlags(), LD->getAAInfo());
632  } else {
633  EVT LoadVT = WideVT;
634  while (RemainingBytes < LoadBytes) {
635  LoadBytes >>= 1; // Reduce the load size by half.
636  LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
637  }
638  ScalarLoad =
639  DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
640  LD->getPointerInfo().getWithOffset(Offset), LoadVT,
641  MinAlign(LD->getAlignment(), Offset),
642  LD->getMemOperand()->getFlags(), LD->getAAInfo());
643  }
644 
645  RemainingBytes -= LoadBytes;
646  Offset += LoadBytes;
647 
648  BasePTR = DAG.getObjectPtrOffset(dl, BasePTR, LoadBytes);
649 
650  LoadVals.push_back(ScalarLoad.getValue(0));
651  LoadChains.push_back(ScalarLoad.getValue(1));
652  }
653 
654  // Extract bits, pack and extend/trunc them into destination type.
655  unsigned SrcEltBits = SrcEltVT.getSizeInBits();
656  SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
657 
658  unsigned BitOffset = 0;
659  unsigned WideIdx = 0;
660  unsigned WideBits = WideVT.getSizeInBits();
661 
662  for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
663  SDValue Lo, Hi, ShAmt;
664 
665  if (BitOffset < WideBits) {
666  ShAmt = DAG.getConstant(
667  BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
668  Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
669  Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
670  }
671 
672  BitOffset += SrcEltBits;
673  if (BitOffset >= WideBits) {
674  WideIdx++;
675  BitOffset -= WideBits;
676  if (BitOffset > 0) {
677  ShAmt = DAG.getConstant(
678  SrcEltBits - BitOffset, dl,
679  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
680  Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
681  Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
682  }
683  }
684 
685  if (Hi.getNode())
686  Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
687 
688  switch (ExtType) {
689  default: llvm_unreachable("Unknown extended-load op!");
690  case ISD::EXTLOAD:
691  Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
692  break;
693  case ISD::ZEXTLOAD:
694  Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
695  break;
696  case ISD::SEXTLOAD:
697  ShAmt =
698  DAG.getConstant(WideBits - SrcEltBits, dl,
699  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
700  Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
701  Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
702  Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
703  break;
704  }
705  Vals.push_back(Lo);
706  }
707 
708  NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
709  Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
710  } else {
711  SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
712  // Skip past MERGE_VALUE node if known.
713  if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
714  NewChain = Scalarized.getOperand(1);
715  Value = Scalarized.getOperand(0);
716  } else {
717  NewChain = Scalarized.getValue(1);
718  Value = Scalarized.getValue(0);
719  }
720  }
721 
722  AddLegalizedOperand(Op.getValue(0), Value);
723  AddLegalizedOperand(Op.getValue(1), NewChain);
724 
725  return (Op.getResNo() ? NewChain : Value);
726 }
727 
728 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
729  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
730  SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
731  AddLegalizedOperand(Op, TF);
732  return TF;
733 }
734 
735 SDValue VectorLegalizer::Expand(SDValue Op) {
736  switch (Op->getOpcode()) {
738  return ExpandSEXTINREG(Op);
740  return ExpandANY_EXTEND_VECTOR_INREG(Op);
742  return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
744  return ExpandZERO_EXTEND_VECTOR_INREG(Op);
745  case ISD::BSWAP:
746  return ExpandBSWAP(Op);
747  case ISD::VSELECT:
748  return ExpandVSELECT(Op);
749  case ISD::SELECT:
750  return ExpandSELECT(Op);
751  case ISD::FP_TO_UINT:
752  return ExpandFP_TO_UINT(Op);
753  case ISD::UINT_TO_FP:
754  return ExpandUINT_TO_FLOAT(Op);
755  case ISD::FNEG:
756  return ExpandFNEG(Op);
757  case ISD::FSUB:
758  return ExpandFSUB(Op);
759  case ISD::SETCC:
760  return UnrollVSETCC(Op);
761  case ISD::ABS:
762  return ExpandABS(Op);
763  case ISD::BITREVERSE:
764  return ExpandBITREVERSE(Op);
765  case ISD::CTPOP:
766  return ExpandCTPOP(Op);
767  case ISD::CTLZ:
769  return ExpandCTLZ(Op);
770  case ISD::CTTZ:
772  return ExpandCTTZ(Op);
773  case ISD::FSHL:
774  case ISD::FSHR:
775  return ExpandFunnelShift(Op);
776  case ISD::ROTL:
777  case ISD::ROTR:
778  return ExpandROT(Op);
779  case ISD::FMINNUM:
780  case ISD::FMAXNUM:
781  return ExpandFMINNUM_FMAXNUM(Op);
782  case ISD::USUBSAT:
783  case ISD::SSUBSAT:
784  case ISD::UADDSAT:
785  case ISD::SADDSAT:
786  return ExpandAddSubSat(Op);
787  case ISD::SMULFIX:
788  case ISD::UMULFIX:
789  return ExpandFixedPointMul(Op);
790  case ISD::STRICT_FADD:
791  case ISD::STRICT_FSUB:
792  case ISD::STRICT_FMUL:
793  case ISD::STRICT_FDIV:
794  case ISD::STRICT_FREM:
795  case ISD::STRICT_FSQRT:
796  case ISD::STRICT_FMA:
797  case ISD::STRICT_FPOW:
798  case ISD::STRICT_FPOWI:
799  case ISD::STRICT_FSIN:
800  case ISD::STRICT_FCOS:
801  case ISD::STRICT_FEXP:
802  case ISD::STRICT_FEXP2:
803  case ISD::STRICT_FLOG:
804  case ISD::STRICT_FLOG10:
805  case ISD::STRICT_FLOG2:
806  case ISD::STRICT_FRINT:
808  case ISD::STRICT_FMAXNUM:
809  case ISD::STRICT_FMINNUM:
810  case ISD::STRICT_FCEIL:
811  case ISD::STRICT_FFLOOR:
812  case ISD::STRICT_FROUND:
813  case ISD::STRICT_FTRUNC:
814  return ExpandStrictFPOp(Op);
815  default:
816  return DAG.UnrollVectorOp(Op.getNode());
817  }
818 }
819 
820 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
821  // Lower a select instruction where the condition is a scalar and the
822  // operands are vectors. Lower this select to VSELECT and implement it
823  // using XOR AND OR. The selector bit is broadcasted.
824  EVT VT = Op.getValueType();
825  SDLoc DL(Op);
826 
827  SDValue Mask = Op.getOperand(0);
828  SDValue Op1 = Op.getOperand(1);
829  SDValue Op2 = Op.getOperand(2);
830 
831  assert(VT.isVector() && !Mask.getValueType().isVector()
832  && Op1.getValueType() == Op2.getValueType() && "Invalid type");
833 
834  // If we can't even use the basic vector operations of
835  // AND,OR,XOR, we will have to scalarize the op.
836  // Notice that the operation may be 'promoted' which means that it is
837  // 'bitcasted' to another type which is handled.
838  // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
839  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
840  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
841  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
842  TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
843  return DAG.UnrollVectorOp(Op.getNode());
844 
845  // Generate a mask operand.
847 
848  // What is the size of each element in the vector mask.
849  EVT BitTy = MaskTy.getScalarType();
850 
851  Mask = DAG.getSelect(DL, BitTy, Mask,
852  DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
853  BitTy),
854  DAG.getConstant(0, DL, BitTy));
855 
856  // Broadcast the mask so that the entire vector is all-one or all zero.
857  Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
858 
859  // Bitcast the operands to be the same type as the mask.
860  // This is needed when we select between FP types because
861  // the mask is a vector of integers.
862  Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
863  Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
864 
865  SDValue AllOnes = DAG.getConstant(
866  APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
867  SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
868 
869  Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
870  Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
871  SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
872  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
873 }
874 
875 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
876  EVT VT = Op.getValueType();
877 
878  // Make sure that the SRA and SHL instructions are available.
879  if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
880  TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
881  return DAG.UnrollVectorOp(Op.getNode());
882 
883  SDLoc DL(Op);
884  EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
885 
886  unsigned BW = VT.getScalarSizeInBits();
887  unsigned OrigBW = OrigTy.getScalarSizeInBits();
888  SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
889 
890  Op = Op.getOperand(0);
891  Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
892  return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
893 }
894 
895 // Generically expand a vector anyext in register to a shuffle of the relevant
896 // lanes into the appropriate locations, with other lanes left undef.
897 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
898  SDLoc DL(Op);
899  EVT VT = Op.getValueType();
900  int NumElements = VT.getVectorNumElements();
901  SDValue Src = Op.getOperand(0);
902  EVT SrcVT = Src.getValueType();
903  int NumSrcElements = SrcVT.getVectorNumElements();
904 
905  // Build a base mask of undef shuffles.
906  SmallVector<int, 16> ShuffleMask;
907  ShuffleMask.resize(NumSrcElements, -1);
908 
909  // Place the extended lanes into the correct locations.
910  int ExtLaneScale = NumSrcElements / NumElements;
911  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
912  for (int i = 0; i < NumElements; ++i)
913  ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
914 
915  return DAG.getNode(
916  ISD::BITCAST, DL, VT,
917  DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
918 }
919 
920 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
921  SDLoc DL(Op);
922  EVT VT = Op.getValueType();
923  SDValue Src = Op.getOperand(0);
924  EVT SrcVT = Src.getValueType();
925 
926  // First build an any-extend node which can be legalized above when we
927  // recurse through it.
928  Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
929 
930  // Now we need sign extend. Do this by shifting the elements. Even if these
931  // aren't legal operations, they have a better chance of being legalized
932  // without full scalarization than the sign extension does.
933  unsigned EltWidth = VT.getScalarSizeInBits();
934  unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
935  SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
936  return DAG.getNode(ISD::SRA, DL, VT,
937  DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
938  ShiftAmount);
939 }
940 
941 // Generically expand a vector zext in register to a shuffle of the relevant
942 // lanes into the appropriate locations, a blend of zero into the high bits,
943 // and a bitcast to the wider element type.
944 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
945  SDLoc DL(Op);
946  EVT VT = Op.getValueType();
947  int NumElements = VT.getVectorNumElements();
948  SDValue Src = Op.getOperand(0);
949  EVT SrcVT = Src.getValueType();
950  int NumSrcElements = SrcVT.getVectorNumElements();
951 
952  // Build up a zero vector to blend into this one.
953  SDValue Zero = DAG.getConstant(0, DL, SrcVT);
954 
955  // Shuffle the incoming lanes into the correct position, and pull all other
956  // lanes from the zero vector.
957  SmallVector<int, 16> ShuffleMask;
958  ShuffleMask.reserve(NumSrcElements);
959  for (int i = 0; i < NumSrcElements; ++i)
960  ShuffleMask.push_back(i);
961 
962  int ExtLaneScale = NumSrcElements / NumElements;
963  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
964  for (int i = 0; i < NumElements; ++i)
965  ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
966 
967  return DAG.getNode(ISD::BITCAST, DL, VT,
968  DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
969 }
970 
971 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
972  int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
973  for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
974  for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
975  ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
976 }
977 
978 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
979  EVT VT = Op.getValueType();
980 
981  // Generate a byte wise shuffle mask for the BSWAP.
982  SmallVector<int, 16> ShuffleMask;
983  createBSWAPShuffleMask(VT, ShuffleMask);
984  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
985 
986  // Only emit a shuffle if the mask is legal.
987  if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
988  return DAG.UnrollVectorOp(Op.getNode());
989 
990  SDLoc DL(Op);
991  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
992  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
993  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
994 }
995 
996 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
997  EVT VT = Op.getValueType();
998 
999  // If we have the scalar operation, it's probably cheaper to unroll it.
1000  if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
1001  return DAG.UnrollVectorOp(Op.getNode());
1002 
1003  // If the vector element width is a whole number of bytes, test if its legal
1004  // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
1005  // vector. This greatly reduces the number of bit shifts necessary.
1006  unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
1007  if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
1008  SmallVector<int, 16> BSWAPMask;
1009  createBSWAPShuffleMask(VT, BSWAPMask);
1010 
1011  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
1012  if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
1013  (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1014  (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
1015  TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
1016  TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
1017  TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
1018  SDLoc DL(Op);
1019  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
1020  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
1021  BSWAPMask);
1022  Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
1023  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1024  }
1025  }
1026 
1027  // If we have the appropriate vector bit operations, it is better to use them
1028  // than unrolling and expanding each component.
1029  if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
1030  !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
1031  !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
1032  !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1033  return DAG.UnrollVectorOp(Op.getNode());
1034 
1035  // Let LegalizeDAG handle this later.
1036  return Op;
1037 }
1038 
1039 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
1040  // Implement VSELECT in terms of XOR, AND, OR
1041  // on platforms which do not support blend natively.
1042  SDLoc DL(Op);
1043 
1044  SDValue Mask = Op.getOperand(0);
1045  SDValue Op1 = Op.getOperand(1);
1046  SDValue Op2 = Op.getOperand(2);
1047 
1048  EVT VT = Mask.getValueType();
1049 
1050  // If we can't even use the basic vector operations of
1051  // AND,OR,XOR, we will have to scalarize the op.
1052  // Notice that the operation may be 'promoted' which means that it is
1053  // 'bitcasted' to another type which is handled.
1054  // This operation also isn't safe with AND, OR, XOR when the boolean
1055  // type is 0/1 as we need an all ones vector constant to mask with.
1056  // FIXME: Sign extend 1 to all ones if thats legal on the target.
1057  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1058  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1059  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1060  TLI.getBooleanContents(Op1.getValueType()) !=
1062  return DAG.UnrollVectorOp(Op.getNode());
1063 
1064  // If the mask and the type are different sizes, unroll the vector op. This
1065  // can occur when getSetCCResultType returns something that is different in
1066  // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
1067  if (VT.getSizeInBits() != Op1.getValueSizeInBits())
1068  return DAG.UnrollVectorOp(Op.getNode());
1069 
1070  // Bitcast the operands to be the same type as the mask.
1071  // This is needed when we select between FP types because
1072  // the mask is a vector of integers.
1073  Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
1074  Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
1075 
1076  SDValue AllOnes = DAG.getConstant(
1078  SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
1079 
1080  Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1081  Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1082  SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
1083  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
1084 }
1085 
1086 SDValue VectorLegalizer::ExpandABS(SDValue Op) {
1087  // Attempt to expand using TargetLowering.
1088  SDValue Result;
1089  if (TLI.expandABS(Op.getNode(), Result, DAG))
1090  return Result;
1091 
1092  // Otherwise go ahead and unroll.
1093  return DAG.UnrollVectorOp(Op.getNode());
1094 }
1095 
1096 SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
1097  // Attempt to expand using TargetLowering.
1098  SDValue Result;
1099  if (TLI.expandFP_TO_UINT(Op.getNode(), Result, DAG))
1100  return Result;
1101 
1102  // Otherwise go ahead and unroll.
1103  return DAG.UnrollVectorOp(Op.getNode());
1104 }
1105 
1106 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
1107  EVT VT = Op.getOperand(0).getValueType();
1108  SDLoc DL(Op);
1109 
1110  // Attempt to expand using TargetLowering.
1111  SDValue Result;
1112  if (TLI.expandUINT_TO_FP(Op.getNode(), Result, DAG))
1113  return Result;
1114 
1115  // Make sure that the SINT_TO_FP and SRL instructions are available.
1116  if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
1117  TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
1118  return DAG.UnrollVectorOp(Op.getNode());
1119 
1120  unsigned BW = VT.getScalarSizeInBits();
1121  assert((BW == 64 || BW == 32) &&
1122  "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
1123 
1124  SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1125 
1126  // Constants to clear the upper part of the word.
1127  // Notice that we can also use SHL+SHR, but using a constant is slightly
1128  // faster on x86.
1129  uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1130  SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1131 
1132  // Two to the power of half-word-size.
1133  SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, Op.getValueType());
1134 
1135  // Clear upper part of LO, lower HI
1136  SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1137  SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1138 
1139  // Convert hi and lo to floats
1140  // Convert the hi part back to the upper values
1141  // TODO: Can any fast-math-flags be set on these nodes?
1142  SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1143  fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1144  SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1145 
1146  // Add the two halves
1147  return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1148 }
1149 
1150 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1151  if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1152  SDLoc DL(Op);
1153  SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1154  // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1155  return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1156  Zero, Op.getOperand(0));
1157  }
1158  return DAG.UnrollVectorOp(Op.getNode());
1159 }
1160 
1161 SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
1162  // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1163  // we can defer this to operation legalization where it will be lowered as
1164  // a+(-b).
1165  EVT VT = Op.getValueType();
1166  if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1167  TLI.isOperationLegalOrCustom(ISD::FADD, VT))
1168  return Op; // Defer to LegalizeDAG
1169 
1170  return DAG.UnrollVectorOp(Op.getNode());
1171 }
1172 
1173 SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {
1174  SDValue Result;
1175  if (TLI.expandCTPOP(Op.getNode(), Result, DAG))
1176  return Result;
1177 
1178  return DAG.UnrollVectorOp(Op.getNode());
1179 }
1180 
1181 SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
1182  SDValue Result;
1183  if (TLI.expandCTLZ(Op.getNode(), Result, DAG))
1184  return Result;
1185 
1186  return DAG.UnrollVectorOp(Op.getNode());
1187 }
1188 
1189 SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
1190  SDValue Result;
1191  if (TLI.expandCTTZ(Op.getNode(), Result, DAG))
1192  return Result;
1193 
1194  return DAG.UnrollVectorOp(Op.getNode());
1195 }
1196 
1197 SDValue VectorLegalizer::ExpandFunnelShift(SDValue Op) {
1198  SDValue Result;
1199  if (TLI.expandFunnelShift(Op.getNode(), Result, DAG))
1200  return Result;
1201 
1202  return DAG.UnrollVectorOp(Op.getNode());
1203 }
1204 
1205 SDValue VectorLegalizer::ExpandROT(SDValue Op) {
1206  SDValue Result;
1207  if (TLI.expandROT(Op.getNode(), Result, DAG))
1208  return Result;
1209 
1210  return DAG.UnrollVectorOp(Op.getNode());
1211 }
1212 
1213 SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
1214  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Op.getNode(), DAG))
1215  return Expanded;
1216  return DAG.UnrollVectorOp(Op.getNode());
1217 }
1218 
1219 SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
1220  if (SDValue Expanded = TLI.expandAddSubSat(Op.getNode(), DAG))
1221  return Expanded;
1222  return DAG.UnrollVectorOp(Op.getNode());
1223 }
1224 
1225 SDValue VectorLegalizer::ExpandFixedPointMul(SDValue Op) {
1226  if (SDValue Expanded = TLI.expandFixedPointMul(Op.getNode(), DAG))
1227  return Expanded;
1228  return DAG.UnrollVectorOp(Op.getNode());
1229 }
1230 
1231 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
1232  EVT VT = Op.getValueType();
1233  EVT EltVT = VT.getVectorElementType();
1234  unsigned NumElems = VT.getVectorNumElements();
1235  unsigned NumOpers = Op.getNumOperands();
1236  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1237  EVT ValueVTs[] = {EltVT, MVT::Other};
1238  SDValue Chain = Op.getOperand(0);
1239  SDLoc dl(Op);
1240 
1241  SmallVector<SDValue, 32> OpValues;
1242  SmallVector<SDValue, 32> OpChains;
1243  for (unsigned i = 0; i < NumElems; ++i) {
1245  SDValue Idx = DAG.getConstant(i, dl,
1246  TLI.getVectorIdxTy(DAG.getDataLayout()));
1247 
1248  // The Chain is the first operand.
1249  Opers.push_back(Chain);
1250 
1251  // Now process the remaining operands.
1252  for (unsigned j = 1; j < NumOpers; ++j) {
1253  SDValue Oper = Op.getOperand(j);
1254  EVT OperVT = Oper.getValueType();
1255 
1256  if (OperVT.isVector())
1257  Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1258  EltVT, Oper, Idx);
1259 
1260  Opers.push_back(Oper);
1261  }
1262 
1263  SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
1264 
1265  OpValues.push_back(ScalarOp.getValue(0));
1266  OpChains.push_back(ScalarOp.getValue(1));
1267  }
1268 
1269  SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
1270  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
1271 
1272  AddLegalizedOperand(Op.getValue(0), Result);
1273  AddLegalizedOperand(Op.getValue(1), NewChain);
1274 
1275  return Op.getResNo() ? NewChain : Result;
1276 }
1277 
1278 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1279  EVT VT = Op.getValueType();
1280  unsigned NumElems = VT.getVectorNumElements();
1281  EVT EltVT = VT.getVectorElementType();
1282  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1283  EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1284  SDLoc dl(Op);
1285  SmallVector<SDValue, 8> Ops(NumElems);
1286  for (unsigned i = 0; i < NumElems; ++i) {
1287  SDValue LHSElem = DAG.getNode(
1288  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1289  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1290  SDValue RHSElem = DAG.getNode(
1291  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1292  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1293  Ops[i] = DAG.getNode(ISD::SETCC, dl,
1294  TLI.getSetCCResultType(DAG.getDataLayout(),
1295  *DAG.getContext(), TmpEltVT),
1296  LHSElem, RHSElem, CC);
1297  Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1298  DAG.getConstant(APInt::getAllOnesValue
1299  (EltVT.getSizeInBits()), dl, EltVT),
1300  DAG.getConstant(0, dl, EltVT));
1301  }
1302  return DAG.getBuildVector(VT, dl, Ops);
1303 }
1304 
1306  return VectorLegalizer(*this).Run();
1307 }
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:537
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:606
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:518
bool isVector() const
Return true if this is a vector value type.
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
unsigned getVectorNumElements() const
const SDValue & getChain() const
unsigned getAlignment() const
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:507
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
void reserve(size_type N)
Definition: SmallVector.h:368
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
Shift and rotation operations.
Definition: ISDOpcodes.h:409
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:392
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:303
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:428
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:496
MVT getVectorElementType() const
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:234
Machine Value Type.
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isRound() const
Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:216
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:940
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:415
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:555
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:403
Iterator for intrusive lists based on ilist_node.
BlockVerifier::State From
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:318
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:338
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:552
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:601
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:412
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachinePointerInfo getWithOffset(int64_t O) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
EVT getMemoryVT() const
Return the type of the in-memory value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:311
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:485
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:615
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
unsigned getOpcode() const
SDValue getValue(unsigned R) const
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:301
unsigned getResNo() const
get the index which selects a specific result in the SDNode
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:442
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:464
const SDValue & getOperand(unsigned i) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:473
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:585
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl< int > &ShuffleMask)
This file describes how to lower LLVM code to machine code.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:379
void resize(size_type N)
Definition: SmallVector.h:343
This class is used to represent ISD::LOAD nodes.