LLVM  8.0.0svn
LegalizeVectorOps.cpp
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1 //===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::LegalizeVectors method.
11 //
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
21 //
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
27 //
28 //===----------------------------------------------------------------------===//
29 
30 #include "llvm/ADT/APInt.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Compiler.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "legalizevectorops"
53 
54 namespace {
55 
56 class VectorLegalizer {
57  SelectionDAG& DAG;
58  const TargetLowering &TLI;
59  bool Changed = false; // Keep track of whether anything changed
60 
61  /// For nodes that are of legal width, and that have more than one use, this
62  /// map indicates what regularized operand to use. This allows us to avoid
63  /// legalizing the same thing more than once.
65 
66  /// Adds a node to the translation cache.
67  void AddLegalizedOperand(SDValue From, SDValue To) {
68  LegalizedNodes.insert(std::make_pair(From, To));
69  // If someone requests legalization of the new node, return itself.
70  if (From != To)
71  LegalizedNodes.insert(std::make_pair(To, To));
72  }
73 
74  /// Legalizes the given node.
75  SDValue LegalizeOp(SDValue Op);
76 
77  /// Assuming the node is legal, "legalize" the results.
78  SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
79 
80  /// Implements unrolling a VSETCC.
81  SDValue UnrollVSETCC(SDValue Op);
82 
83  /// Implement expand-based legalization of vector operations.
84  ///
85  /// This is just a high-level routine to dispatch to specific code paths for
86  /// operations to legalize them.
87  SDValue Expand(SDValue Op);
88 
89  /// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
90  /// FP_TO_SINT isn't legal.
91  SDValue ExpandFP_TO_UINT(SDValue Op);
92 
93  /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
94  /// SINT_TO_FLOAT and SHR on vectors isn't legal.
95  SDValue ExpandUINT_TO_FLOAT(SDValue Op);
96 
97  /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
98  SDValue ExpandSEXTINREG(SDValue Op);
99 
100  /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
101  ///
102  /// Shuffles the low lanes of the operand into place and bitcasts to the proper
103  /// type. The contents of the bits in the extended part of each element are
104  /// undef.
105  SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
106 
107  /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
108  ///
109  /// Shuffles the low lanes of the operand into place, bitcasts to the proper
110  /// type, then shifts left and arithmetic shifts right to introduce a sign
111  /// extension.
112  SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
113 
114  /// Implement expansion for ZERO_EXTEND_VECTOR_INREG.
115  ///
116  /// Shuffles the low lanes of the operand into place and blends zeros into
117  /// the remaining lanes, finally bitcasting to the proper type.
118  SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
119 
120  /// Expand bswap of vectors into a shuffle if legal.
121  SDValue ExpandBSWAP(SDValue Op);
122 
123  /// Implement vselect in terms of XOR, AND, OR when blend is not
124  /// supported by the target.
125  SDValue ExpandVSELECT(SDValue Op);
126  SDValue ExpandSELECT(SDValue Op);
127  SDValue ExpandLoad(SDValue Op);
128  SDValue ExpandStore(SDValue Op);
129  SDValue ExpandFNEG(SDValue Op);
130  SDValue ExpandFSUB(SDValue Op);
131  SDValue ExpandBITREVERSE(SDValue Op);
132  SDValue ExpandCTPOP(SDValue Op);
133  SDValue ExpandCTLZ(SDValue Op);
134  SDValue ExpandCTTZ(SDValue Op);
135  SDValue ExpandFunnelShift(SDValue Op);
136  SDValue ExpandROT(SDValue Op);
137  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
138  SDValue ExpandStrictFPOp(SDValue Op);
139 
140  /// Implements vector promotion.
141  ///
142  /// This is essentially just bitcasting the operands to a different type and
143  /// bitcasting the result back to the original type.
144  SDValue Promote(SDValue Op);
145 
146  /// Implements [SU]INT_TO_FP vector promotion.
147  ///
148  /// This is a [zs]ext of the input operand to a larger integer type.
149  SDValue PromoteINT_TO_FP(SDValue Op);
150 
151  /// Implements FP_TO_[SU]INT vector promotion of the result type.
152  ///
153  /// It is promoted to a larger integer type. The result is then
154  /// truncated back to the original type.
155  SDValue PromoteFP_TO_INT(SDValue Op);
156 
157 public:
158  VectorLegalizer(SelectionDAG& dag) :
159  DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
160 
161  /// Begin legalizer the vector operations in the DAG.
162  bool Run();
163 };
164 
165 } // end anonymous namespace
166 
167 bool VectorLegalizer::Run() {
168  // Before we start legalizing vector nodes, check if there are any vectors.
169  bool HasVectors = false;
170  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
171  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
172  // Check if the values of the nodes contain vectors. We don't need to check
173  // the operands because we are going to check their values at some point.
174  for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
175  J != E; ++J)
176  HasVectors |= J->isVector();
177 
178  // If we found a vector node we can start the legalization.
179  if (HasVectors)
180  break;
181  }
182 
183  // If this basic block has no vectors then no need to legalize vectors.
184  if (!HasVectors)
185  return false;
186 
187  // The legalize process is inherently a bottom-up recursive process (users
188  // legalize their uses before themselves). Given infinite stack space, we
189  // could just start legalizing on the root and traverse the whole graph. In
190  // practice however, this causes us to run out of stack space on large basic
191  // blocks. To avoid this problem, compute an ordering of the nodes where each
192  // node is only legalized after all of its operands are legalized.
193  DAG.AssignTopologicalOrder();
194  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
195  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
196  LegalizeOp(SDValue(&*I, 0));
197 
198  // Finally, it's possible the root changed. Get the new root.
199  SDValue OldRoot = DAG.getRoot();
200  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
201  DAG.setRoot(LegalizedNodes[OldRoot]);
202 
203  LegalizedNodes.clear();
204 
205  // Remove dead nodes now.
206  DAG.RemoveDeadNodes();
207 
208  return Changed;
209 }
210 
211 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
212  // Generic legalization: just pass the operand through.
213  for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
214  AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
215  return Result.getValue(Op.getResNo());
216 }
217 
218 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
219  // Note that LegalizeOp may be reentered even from single-use nodes, which
220  // means that we always must cache transformed nodes.
221  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
222  if (I != LegalizedNodes.end()) return I->second;
223 
224  SDNode* Node = Op.getNode();
225 
226  // Legalize the operands
228  for (const SDValue &Op : Node->op_values())
229  Ops.push_back(LegalizeOp(Op));
230 
231  SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops),
232  Op.getResNo());
233 
234  if (Op.getOpcode() == ISD::LOAD) {
235  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
237  if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
238  LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: ";
239  Node->dump(&DAG));
240  switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
241  LD->getMemoryVT())) {
242  default: llvm_unreachable("This action is not supported yet!");
244  return TranslateLegalizeResults(Op, Result);
246  if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
247  assert(Lowered->getNumValues() == Op->getNumValues() &&
248  "Unexpected number of results");
249  if (Lowered != Result) {
250  // Make sure the new code is also legal.
251  Lowered = LegalizeOp(Lowered);
252  Changed = true;
253  }
254  return TranslateLegalizeResults(Op, Lowered);
255  }
258  Changed = true;
259  return LegalizeOp(ExpandLoad(Op));
260  }
261  }
262  } else if (Op.getOpcode() == ISD::STORE) {
263  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
264  EVT StVT = ST->getMemoryVT();
265  MVT ValVT = ST->getValue().getSimpleValueType();
266  if (StVT.isVector() && ST->isTruncatingStore()) {
267  LLVM_DEBUG(dbgs() << "\nLegalizing truncating vector store: ";
268  Node->dump(&DAG));
269  switch (TLI.getTruncStoreAction(ValVT, StVT)) {
270  default: llvm_unreachable("This action is not supported yet!");
272  return TranslateLegalizeResults(Op, Result);
273  case TargetLowering::Custom: {
274  SDValue Lowered = TLI.LowerOperation(Result, DAG);
275  if (Lowered != Result) {
276  // Make sure the new code is also legal.
277  Lowered = LegalizeOp(Lowered);
278  Changed = true;
279  }
280  return TranslateLegalizeResults(Op, Lowered);
281  }
283  Changed = true;
284  return LegalizeOp(ExpandStore(Op));
285  }
286  }
287  }
288 
289  bool HasVectorValue = false;
290  for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
291  J != E;
292  ++J)
293  HasVectorValue |= J->isVector();
294  if (!HasVectorValue)
295  return TranslateLegalizeResults(Op, Result);
296 
298  switch (Op.getOpcode()) {
299  default:
300  return TranslateLegalizeResults(Op, Result);
301  case ISD::STRICT_FADD:
302  case ISD::STRICT_FSUB:
303  case ISD::STRICT_FMUL:
304  case ISD::STRICT_FDIV:
305  case ISD::STRICT_FREM:
306  case ISD::STRICT_FSQRT:
307  case ISD::STRICT_FMA:
308  case ISD::STRICT_FPOW:
309  case ISD::STRICT_FPOWI:
310  case ISD::STRICT_FSIN:
311  case ISD::STRICT_FCOS:
312  case ISD::STRICT_FEXP:
313  case ISD::STRICT_FEXP2:
314  case ISD::STRICT_FLOG:
315  case ISD::STRICT_FLOG10:
316  case ISD::STRICT_FLOG2:
317  case ISD::STRICT_FRINT:
319  case ISD::STRICT_FMAXNUM:
320  case ISD::STRICT_FMINNUM:
321  case ISD::STRICT_FCEIL:
322  case ISD::STRICT_FFLOOR:
323  case ISD::STRICT_FROUND:
324  case ISD::STRICT_FTRUNC:
325  // These pseudo-ops get legalized as if they were their non-strict
326  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
327  // is also legal, but if ISD::FSQRT requires expansion then so does
328  // ISD::STRICT_FSQRT.
329  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
330  Node->getValueType(0));
331  break;
332  case ISD::ADD:
333  case ISD::SUB:
334  case ISD::MUL:
335  case ISD::MULHS:
336  case ISD::MULHU:
337  case ISD::SDIV:
338  case ISD::UDIV:
339  case ISD::SREM:
340  case ISD::UREM:
341  case ISD::SDIVREM:
342  case ISD::UDIVREM:
343  case ISD::FADD:
344  case ISD::FSUB:
345  case ISD::FMUL:
346  case ISD::FDIV:
347  case ISD::FREM:
348  case ISD::AND:
349  case ISD::OR:
350  case ISD::XOR:
351  case ISD::SHL:
352  case ISD::SRA:
353  case ISD::SRL:
354  case ISD::ROTL:
355  case ISD::ROTR:
356  case ISD::BSWAP:
357  case ISD::BITREVERSE:
358  case ISD::CTLZ:
359  case ISD::CTTZ:
362  case ISD::CTPOP:
363  case ISD::SELECT:
364  case ISD::VSELECT:
365  case ISD::SELECT_CC:
366  case ISD::SETCC:
367  case ISD::ZERO_EXTEND:
368  case ISD::ANY_EXTEND:
369  case ISD::TRUNCATE:
370  case ISD::SIGN_EXTEND:
371  case ISD::FP_TO_SINT:
372  case ISD::FP_TO_UINT:
373  case ISD::FNEG:
374  case ISD::FABS:
375  case ISD::FMINNUM:
376  case ISD::FMAXNUM:
377  case ISD::FMINNUM_IEEE:
378  case ISD::FMAXNUM_IEEE:
379  case ISD::FMINIMUM:
380  case ISD::FMAXIMUM:
381  case ISD::FCOPYSIGN:
382  case ISD::FSQRT:
383  case ISD::FSIN:
384  case ISD::FCOS:
385  case ISD::FPOWI:
386  case ISD::FPOW:
387  case ISD::FLOG:
388  case ISD::FLOG2:
389  case ISD::FLOG10:
390  case ISD::FEXP:
391  case ISD::FEXP2:
392  case ISD::FCEIL:
393  case ISD::FTRUNC:
394  case ISD::FRINT:
395  case ISD::FNEARBYINT:
396  case ISD::FROUND:
397  case ISD::FFLOOR:
398  case ISD::FP_ROUND:
399  case ISD::FP_EXTEND:
400  case ISD::FMA:
405  case ISD::SMIN:
406  case ISD::SMAX:
407  case ISD::UMIN:
408  case ISD::UMAX:
409  case ISD::SMUL_LOHI:
410  case ISD::UMUL_LOHI:
411  case ISD::FCANONICALIZE:
412  case ISD::SADDSAT:
413  case ISD::UADDSAT:
414  case ISD::SSUBSAT:
415  case ISD::USUBSAT:
416  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
417  break;
418  case ISD::SMULFIX: {
419  unsigned Scale = Node->getConstantOperandVal(2);
420  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
421  Node->getValueType(0), Scale);
422  break;
423  }
424  case ISD::FP_ROUND_INREG:
425  Action = TLI.getOperationAction(Node->getOpcode(),
426  cast<VTSDNode>(Node->getOperand(1))->getVT());
427  break;
428  case ISD::SINT_TO_FP:
429  case ISD::UINT_TO_FP:
430  Action = TLI.getOperationAction(Node->getOpcode(),
431  Node->getOperand(0).getValueType());
432  break;
433  }
434 
435  LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
436 
437  switch (Action) {
438  default: llvm_unreachable("This action is not supported yet!");
440  Result = Promote(Op);
441  Changed = true;
442  break;
444  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
445  break;
446  case TargetLowering::Custom: {
447  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
448  if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
449  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
450  Result = Tmp1;
451  break;
452  }
453  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
455  }
457  Result = Expand(Op);
458  }
459 
460  // Make sure that the generated code is itself legal.
461  if (Result != Op) {
462  Result = LegalizeOp(Result);
463  Changed = true;
464  }
465 
466  // Note that LegalizeOp may be reentered even from single-use nodes, which
467  // means that we always must cache transformed nodes.
468  AddLegalizedOperand(Op, Result);
469  return Result;
470 }
471 
472 SDValue VectorLegalizer::Promote(SDValue Op) {
473  // For a few operations there is a specific concept for promotion based on
474  // the operand's type.
475  switch (Op.getOpcode()) {
476  case ISD::SINT_TO_FP:
477  case ISD::UINT_TO_FP:
478  // "Promote" the operation by extending the operand.
479  return PromoteINT_TO_FP(Op);
480  case ISD::FP_TO_UINT:
481  case ISD::FP_TO_SINT:
482  // Promote the operation by extending the operand.
483  return PromoteFP_TO_INT(Op);
484  }
485 
486  // There are currently two cases of vector promotion:
487  // 1) Bitcasting a vector of integers to a different type to a vector of the
488  // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
489  // 2) Extending a vector of floats to a vector of the same number of larger
490  // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
491  MVT VT = Op.getSimpleValueType();
492  assert(Op.getNode()->getNumValues() == 1 &&
493  "Can't promote a vector with multiple results!");
494  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
495  SDLoc dl(Op);
497 
498  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
499  if (Op.getOperand(j).getValueType().isVector())
500  if (Op.getOperand(j)
501  .getValueType()
503  .isFloatingPoint() &&
504  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
505  Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
506  else
507  Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
508  else
509  Operands[j] = Op.getOperand(j);
510  }
511 
512  Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
513  if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
515  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
516  return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
517  else
518  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
519 }
520 
521 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
522  // INT_TO_FP operations may require the input operand be promoted even
523  // when the type is otherwise legal.
524  MVT VT = Op.getOperand(0).getSimpleValueType();
525  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
527  "Vectors have different number of elements!");
528 
529  SDLoc dl(Op);
531 
532  unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
534  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
535  if (Op.getOperand(j).getValueType().isVector())
536  Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
537  else
538  Operands[j] = Op.getOperand(j);
539  }
540 
541  return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
542 }
543 
544 // For FP_TO_INT we promote the result type to a vector type with wider
545 // elements and then truncate the result. This is different from the default
546 // PromoteVector which uses bitcast to promote thus assumning that the
547 // promoted vector type has the same overall size.
548 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
549  MVT VT = Op.getSimpleValueType();
550  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
552  "Vectors have different number of elements!");
553 
554  unsigned NewOpc = Op->getOpcode();
555  // Change FP_TO_UINT to FP_TO_SINT if possible.
556  // TODO: Should we only do this if FP_TO_UINT itself isn't legal?
557  if (NewOpc == ISD::FP_TO_UINT &&
558  TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
559  NewOpc = ISD::FP_TO_SINT;
560 
561  SDLoc dl(Op);
562  SDValue Promoted = DAG.getNode(NewOpc, dl, NVT, Op.getOperand(0));
563 
564  // Assert that the converted value fits in the original type. If it doesn't
565  // (eg: because the value being converted is too big), then the result of the
566  // original operation was undefined anyway, so the assert is still correct.
567  Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
568  : ISD::AssertSext,
569  dl, NVT, Promoted,
570  DAG.getValueType(VT.getScalarType()));
571  return DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
572 }
573 
574 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
575  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
576 
577  EVT SrcVT = LD->getMemoryVT();
578  EVT SrcEltVT = SrcVT.getScalarType();
579  unsigned NumElem = SrcVT.getVectorNumElements();
580 
581  SDValue NewChain;
582  SDValue Value;
583  if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
584  SDLoc dl(Op);
585 
587  SmallVector<SDValue, 8> LoadChains;
588 
589  EVT DstEltVT = LD->getValueType(0).getScalarType();
590  SDValue Chain = LD->getChain();
591  SDValue BasePTR = LD->getBasePtr();
593 
594  // When elements in a vector is not byte-addressable, we cannot directly
595  // load each element by advancing pointer, which could only address bytes.
596  // Instead, we load all significant words, mask bits off, and concatenate
597  // them to form each element. Finally, they are extended to destination
598  // scalar type to build the destination vector.
599  EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
600 
601  assert(WideVT.isRound() &&
602  "Could not handle the sophisticated case when the widest integer is"
603  " not power of 2.");
604  assert(WideVT.bitsGE(SrcEltVT) &&
605  "Type is not legalized?");
606 
607  unsigned WideBytes = WideVT.getStoreSize();
608  unsigned Offset = 0;
609  unsigned RemainingBytes = SrcVT.getStoreSize();
610  SmallVector<SDValue, 8> LoadVals;
611  while (RemainingBytes > 0) {
612  SDValue ScalarLoad;
613  unsigned LoadBytes = WideBytes;
614 
615  if (RemainingBytes >= LoadBytes) {
616  ScalarLoad =
617  DAG.getLoad(WideVT, dl, Chain, BasePTR,
618  LD->getPointerInfo().getWithOffset(Offset),
619  MinAlign(LD->getAlignment(), Offset),
620  LD->getMemOperand()->getFlags(), LD->getAAInfo());
621  } else {
622  EVT LoadVT = WideVT;
623  while (RemainingBytes < LoadBytes) {
624  LoadBytes >>= 1; // Reduce the load size by half.
625  LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
626  }
627  ScalarLoad =
628  DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
629  LD->getPointerInfo().getWithOffset(Offset), LoadVT,
630  MinAlign(LD->getAlignment(), Offset),
631  LD->getMemOperand()->getFlags(), LD->getAAInfo());
632  }
633 
634  RemainingBytes -= LoadBytes;
635  Offset += LoadBytes;
636 
637  BasePTR = DAG.getObjectPtrOffset(dl, BasePTR, LoadBytes);
638 
639  LoadVals.push_back(ScalarLoad.getValue(0));
640  LoadChains.push_back(ScalarLoad.getValue(1));
641  }
642 
643  // Extract bits, pack and extend/trunc them into destination type.
644  unsigned SrcEltBits = SrcEltVT.getSizeInBits();
645  SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
646 
647  unsigned BitOffset = 0;
648  unsigned WideIdx = 0;
649  unsigned WideBits = WideVT.getSizeInBits();
650 
651  for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
652  SDValue Lo, Hi, ShAmt;
653 
654  if (BitOffset < WideBits) {
655  ShAmt = DAG.getConstant(
656  BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
657  Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
658  Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
659  }
660 
661  BitOffset += SrcEltBits;
662  if (BitOffset >= WideBits) {
663  WideIdx++;
664  BitOffset -= WideBits;
665  if (BitOffset > 0) {
666  ShAmt = DAG.getConstant(
667  SrcEltBits - BitOffset, dl,
668  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
669  Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
670  Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
671  }
672  }
673 
674  if (Hi.getNode())
675  Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
676 
677  switch (ExtType) {
678  default: llvm_unreachable("Unknown extended-load op!");
679  case ISD::EXTLOAD:
680  Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
681  break;
682  case ISD::ZEXTLOAD:
683  Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
684  break;
685  case ISD::SEXTLOAD:
686  ShAmt =
687  DAG.getConstant(WideBits - SrcEltBits, dl,
688  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
689  Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
690  Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
691  Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
692  break;
693  }
694  Vals.push_back(Lo);
695  }
696 
697  NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
698  Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
699  } else {
700  SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
701  // Skip past MERGE_VALUE node if known.
702  if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
703  NewChain = Scalarized.getOperand(1);
704  Value = Scalarized.getOperand(0);
705  } else {
706  NewChain = Scalarized.getValue(1);
707  Value = Scalarized.getValue(0);
708  }
709  }
710 
711  AddLegalizedOperand(Op.getValue(0), Value);
712  AddLegalizedOperand(Op.getValue(1), NewChain);
713 
714  return (Op.getResNo() ? NewChain : Value);
715 }
716 
717 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
718  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
719  SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
720  AddLegalizedOperand(Op, TF);
721  return TF;
722 }
723 
724 SDValue VectorLegalizer::Expand(SDValue Op) {
725  switch (Op->getOpcode()) {
727  return ExpandSEXTINREG(Op);
729  return ExpandANY_EXTEND_VECTOR_INREG(Op);
731  return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
733  return ExpandZERO_EXTEND_VECTOR_INREG(Op);
734  case ISD::BSWAP:
735  return ExpandBSWAP(Op);
736  case ISD::VSELECT:
737  return ExpandVSELECT(Op);
738  case ISD::SELECT:
739  return ExpandSELECT(Op);
740  case ISD::FP_TO_UINT:
741  return ExpandFP_TO_UINT(Op);
742  case ISD::UINT_TO_FP:
743  return ExpandUINT_TO_FLOAT(Op);
744  case ISD::FNEG:
745  return ExpandFNEG(Op);
746  case ISD::FSUB:
747  return ExpandFSUB(Op);
748  case ISD::SETCC:
749  return UnrollVSETCC(Op);
750  case ISD::BITREVERSE:
751  return ExpandBITREVERSE(Op);
752  case ISD::CTPOP:
753  return ExpandCTPOP(Op);
754  case ISD::CTLZ:
756  return ExpandCTLZ(Op);
757  case ISD::CTTZ:
759  return ExpandCTTZ(Op);
760  case ISD::FSHL:
761  case ISD::FSHR:
762  return ExpandFunnelShift(Op);
763  case ISD::ROTL:
764  case ISD::ROTR:
765  return ExpandROT(Op);
766  case ISD::FMINNUM:
767  case ISD::FMAXNUM:
768  return ExpandFMINNUM_FMAXNUM(Op);
769  case ISD::STRICT_FADD:
770  case ISD::STRICT_FSUB:
771  case ISD::STRICT_FMUL:
772  case ISD::STRICT_FDIV:
773  case ISD::STRICT_FREM:
774  case ISD::STRICT_FSQRT:
775  case ISD::STRICT_FMA:
776  case ISD::STRICT_FPOW:
777  case ISD::STRICT_FPOWI:
778  case ISD::STRICT_FSIN:
779  case ISD::STRICT_FCOS:
780  case ISD::STRICT_FEXP:
781  case ISD::STRICT_FEXP2:
782  case ISD::STRICT_FLOG:
783  case ISD::STRICT_FLOG10:
784  case ISD::STRICT_FLOG2:
785  case ISD::STRICT_FRINT:
787  case ISD::STRICT_FMAXNUM:
788  case ISD::STRICT_FMINNUM:
789  case ISD::STRICT_FCEIL:
790  case ISD::STRICT_FFLOOR:
791  case ISD::STRICT_FROUND:
792  case ISD::STRICT_FTRUNC:
793  return ExpandStrictFPOp(Op);
794  default:
795  return DAG.UnrollVectorOp(Op.getNode());
796  }
797 }
798 
799 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
800  // Lower a select instruction where the condition is a scalar and the
801  // operands are vectors. Lower this select to VSELECT and implement it
802  // using XOR AND OR. The selector bit is broadcasted.
803  EVT VT = Op.getValueType();
804  SDLoc DL(Op);
805 
806  SDValue Mask = Op.getOperand(0);
807  SDValue Op1 = Op.getOperand(1);
808  SDValue Op2 = Op.getOperand(2);
809 
810  assert(VT.isVector() && !Mask.getValueType().isVector()
811  && Op1.getValueType() == Op2.getValueType() && "Invalid type");
812 
813  // If we can't even use the basic vector operations of
814  // AND,OR,XOR, we will have to scalarize the op.
815  // Notice that the operation may be 'promoted' which means that it is
816  // 'bitcasted' to another type which is handled.
817  // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
818  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
819  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
820  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
821  TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
822  return DAG.UnrollVectorOp(Op.getNode());
823 
824  // Generate a mask operand.
826 
827  // What is the size of each element in the vector mask.
828  EVT BitTy = MaskTy.getScalarType();
829 
830  Mask = DAG.getSelect(DL, BitTy, Mask,
831  DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
832  BitTy),
833  DAG.getConstant(0, DL, BitTy));
834 
835  // Broadcast the mask so that the entire vector is all-one or all zero.
836  Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
837 
838  // Bitcast the operands to be the same type as the mask.
839  // This is needed when we select between FP types because
840  // the mask is a vector of integers.
841  Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
842  Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
843 
844  SDValue AllOnes = DAG.getConstant(
845  APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
846  SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
847 
848  Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
849  Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
850  SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
851  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
852 }
853 
854 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
855  EVT VT = Op.getValueType();
856 
857  // Make sure that the SRA and SHL instructions are available.
858  if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
859  TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
860  return DAG.UnrollVectorOp(Op.getNode());
861 
862  SDLoc DL(Op);
863  EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
864 
865  unsigned BW = VT.getScalarSizeInBits();
866  unsigned OrigBW = OrigTy.getScalarSizeInBits();
867  SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
868 
869  Op = Op.getOperand(0);
870  Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
871  return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
872 }
873 
874 // Generically expand a vector anyext in register to a shuffle of the relevant
875 // lanes into the appropriate locations, with other lanes left undef.
876 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
877  SDLoc DL(Op);
878  EVT VT = Op.getValueType();
879  int NumElements = VT.getVectorNumElements();
880  SDValue Src = Op.getOperand(0);
881  EVT SrcVT = Src.getValueType();
882  int NumSrcElements = SrcVT.getVectorNumElements();
883 
884  // Build a base mask of undef shuffles.
885  SmallVector<int, 16> ShuffleMask;
886  ShuffleMask.resize(NumSrcElements, -1);
887 
888  // Place the extended lanes into the correct locations.
889  int ExtLaneScale = NumSrcElements / NumElements;
890  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
891  for (int i = 0; i < NumElements; ++i)
892  ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
893 
894  return DAG.getNode(
895  ISD::BITCAST, DL, VT,
896  DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
897 }
898 
899 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
900  SDLoc DL(Op);
901  EVT VT = Op.getValueType();
902  SDValue Src = Op.getOperand(0);
903  EVT SrcVT = Src.getValueType();
904 
905  // First build an any-extend node which can be legalized above when we
906  // recurse through it.
907  Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
908 
909  // Now we need sign extend. Do this by shifting the elements. Even if these
910  // aren't legal operations, they have a better chance of being legalized
911  // without full scalarization than the sign extension does.
912  unsigned EltWidth = VT.getScalarSizeInBits();
913  unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
914  SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
915  return DAG.getNode(ISD::SRA, DL, VT,
916  DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
917  ShiftAmount);
918 }
919 
920 // Generically expand a vector zext in register to a shuffle of the relevant
921 // lanes into the appropriate locations, a blend of zero into the high bits,
922 // and a bitcast to the wider element type.
923 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
924  SDLoc DL(Op);
925  EVT VT = Op.getValueType();
926  int NumElements = VT.getVectorNumElements();
927  SDValue Src = Op.getOperand(0);
928  EVT SrcVT = Src.getValueType();
929  int NumSrcElements = SrcVT.getVectorNumElements();
930 
931  // Build up a zero vector to blend into this one.
932  SDValue Zero = DAG.getConstant(0, DL, SrcVT);
933 
934  // Shuffle the incoming lanes into the correct position, and pull all other
935  // lanes from the zero vector.
936  SmallVector<int, 16> ShuffleMask;
937  ShuffleMask.reserve(NumSrcElements);
938  for (int i = 0; i < NumSrcElements; ++i)
939  ShuffleMask.push_back(i);
940 
941  int ExtLaneScale = NumSrcElements / NumElements;
942  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
943  for (int i = 0; i < NumElements; ++i)
944  ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
945 
946  return DAG.getNode(ISD::BITCAST, DL, VT,
947  DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
948 }
949 
950 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
951  int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
952  for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
953  for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
954  ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
955 }
956 
957 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
958  EVT VT = Op.getValueType();
959 
960  // Generate a byte wise shuffle mask for the BSWAP.
961  SmallVector<int, 16> ShuffleMask;
962  createBSWAPShuffleMask(VT, ShuffleMask);
963  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
964 
965  // Only emit a shuffle if the mask is legal.
966  if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
967  return DAG.UnrollVectorOp(Op.getNode());
968 
969  SDLoc DL(Op);
970  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
971  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
972  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
973 }
974 
975 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
976  EVT VT = Op.getValueType();
977 
978  // If we have the scalar operation, it's probably cheaper to unroll it.
979  if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
980  return DAG.UnrollVectorOp(Op.getNode());
981 
982  // If the vector element width is a whole number of bytes, test if its legal
983  // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
984  // vector. This greatly reduces the number of bit shifts necessary.
985  unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
986  if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
987  SmallVector<int, 16> BSWAPMask;
988  createBSWAPShuffleMask(VT, BSWAPMask);
989 
990  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
991  if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
992  (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
993  (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
994  TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
995  TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
996  TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
997  SDLoc DL(Op);
998  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
999  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
1000  BSWAPMask);
1001  Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
1002  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1003  }
1004  }
1005 
1006  // If we have the appropriate vector bit operations, it is better to use them
1007  // than unrolling and expanding each component.
1008  if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
1009  !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
1010  !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
1011  !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1012  return DAG.UnrollVectorOp(Op.getNode());
1013 
1014  // Let LegalizeDAG handle this later.
1015  return Op;
1016 }
1017 
1018 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
1019  // Implement VSELECT in terms of XOR, AND, OR
1020  // on platforms which do not support blend natively.
1021  SDLoc DL(Op);
1022 
1023  SDValue Mask = Op.getOperand(0);
1024  SDValue Op1 = Op.getOperand(1);
1025  SDValue Op2 = Op.getOperand(2);
1026 
1027  EVT VT = Mask.getValueType();
1028 
1029  // If we can't even use the basic vector operations of
1030  // AND,OR,XOR, we will have to scalarize the op.
1031  // Notice that the operation may be 'promoted' which means that it is
1032  // 'bitcasted' to another type which is handled.
1033  // This operation also isn't safe with AND, OR, XOR when the boolean
1034  // type is 0/1 as we need an all ones vector constant to mask with.
1035  // FIXME: Sign extend 1 to all ones if thats legal on the target.
1036  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1037  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1038  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1039  TLI.getBooleanContents(Op1.getValueType()) !=
1041  return DAG.UnrollVectorOp(Op.getNode());
1042 
1043  // If the mask and the type are different sizes, unroll the vector op. This
1044  // can occur when getSetCCResultType returns something that is different in
1045  // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
1046  if (VT.getSizeInBits() != Op1.getValueSizeInBits())
1047  return DAG.UnrollVectorOp(Op.getNode());
1048 
1049  // Bitcast the operands to be the same type as the mask.
1050  // This is needed when we select between FP types because
1051  // the mask is a vector of integers.
1052  Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
1053  Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
1054 
1055  SDValue AllOnes = DAG.getConstant(
1057  SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
1058 
1059  Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1060  Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1061  SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
1062  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
1063 }
1064 
1065 SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
1066  // Attempt to expand using TargetLowering.
1067  SDValue Result;
1068  if (TLI.expandFP_TO_UINT(Op.getNode(), Result, DAG))
1069  return Result;
1070 
1071  // Otherwise go ahead and unroll.
1072  return DAG.UnrollVectorOp(Op.getNode());
1073 }
1074 
1075 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
1076  EVT VT = Op.getOperand(0).getValueType();
1077  SDLoc DL(Op);
1078 
1079  // Attempt to expand using TargetLowering.
1080  SDValue Result;
1081  if (TLI.expandUINT_TO_FP(Op.getNode(), Result, DAG))
1082  return Result;
1083 
1084  // Make sure that the SINT_TO_FP and SRL instructions are available.
1085  if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
1086  TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
1087  return DAG.UnrollVectorOp(Op.getNode());
1088 
1089  unsigned BW = VT.getScalarSizeInBits();
1090  assert((BW == 64 || BW == 32) &&
1091  "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
1092 
1093  SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1094 
1095  // Constants to clear the upper part of the word.
1096  // Notice that we can also use SHL+SHR, but using a constant is slightly
1097  // faster on x86.
1098  uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1099  SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1100 
1101  // Two to the power of half-word-size.
1102  SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, Op.getValueType());
1103 
1104  // Clear upper part of LO, lower HI
1105  SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1106  SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1107 
1108  // Convert hi and lo to floats
1109  // Convert the hi part back to the upper values
1110  // TODO: Can any fast-math-flags be set on these nodes?
1111  SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1112  fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1113  SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1114 
1115  // Add the two halves
1116  return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1117 }
1118 
1119 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1120  if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1121  SDLoc DL(Op);
1122  SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1123  // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1124  return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1125  Zero, Op.getOperand(0));
1126  }
1127  return DAG.UnrollVectorOp(Op.getNode());
1128 }
1129 
1130 SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
1131  // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1132  // we can defer this to operation legalization where it will be lowered as
1133  // a+(-b).
1134  EVT VT = Op.getValueType();
1135  if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1136  TLI.isOperationLegalOrCustom(ISD::FADD, VT))
1137  return Op; // Defer to LegalizeDAG
1138 
1139  return DAG.UnrollVectorOp(Op.getNode());
1140 }
1141 
1142 SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {
1143  SDValue Result;
1144  if (TLI.expandCTPOP(Op.getNode(), Result, DAG))
1145  return Result;
1146 
1147  return DAG.UnrollVectorOp(Op.getNode());
1148 }
1149 
1150 SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
1151  SDValue Result;
1152  if (TLI.expandCTLZ(Op.getNode(), Result, DAG))
1153  return Result;
1154 
1155  return DAG.UnrollVectorOp(Op.getNode());
1156 }
1157 
1158 SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
1159  SDValue Result;
1160  if (TLI.expandCTTZ(Op.getNode(), Result, DAG))
1161  return Result;
1162 
1163  return DAG.UnrollVectorOp(Op.getNode());
1164 }
1165 
1166 SDValue VectorLegalizer::ExpandFunnelShift(SDValue Op) {
1167  SDValue Result;
1168  if (TLI.expandFunnelShift(Op.getNode(), Result, DAG))
1169  return Result;
1170 
1171  return DAG.UnrollVectorOp(Op.getNode());
1172 }
1173 
1174 SDValue VectorLegalizer::ExpandROT(SDValue Op) {
1175  SDValue Result;
1176  if (TLI.expandROT(Op.getNode(), Result, DAG))
1177  return Result;
1178 
1179  return DAG.UnrollVectorOp(Op.getNode());
1180 }
1181 
1182 SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
1183  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Op.getNode(), DAG))
1184  return Expanded;
1185  return DAG.UnrollVectorOp(Op.getNode());
1186 }
1187 
1188 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
1189  EVT VT = Op.getValueType();
1190  EVT EltVT = VT.getVectorElementType();
1191  unsigned NumElems = VT.getVectorNumElements();
1192  unsigned NumOpers = Op.getNumOperands();
1193  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1194  EVT ValueVTs[] = {EltVT, MVT::Other};
1195  SDValue Chain = Op.getOperand(0);
1196  SDLoc dl(Op);
1197 
1198  SmallVector<SDValue, 32> OpValues;
1199  SmallVector<SDValue, 32> OpChains;
1200  for (unsigned i = 0; i < NumElems; ++i) {
1202  SDValue Idx = DAG.getConstant(i, dl,
1203  TLI.getVectorIdxTy(DAG.getDataLayout()));
1204 
1205  // The Chain is the first operand.
1206  Opers.push_back(Chain);
1207 
1208  // Now process the remaining operands.
1209  for (unsigned j = 1; j < NumOpers; ++j) {
1210  SDValue Oper = Op.getOperand(j);
1211  EVT OperVT = Oper.getValueType();
1212 
1213  if (OperVT.isVector())
1214  Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1215  EltVT, Oper, Idx);
1216 
1217  Opers.push_back(Oper);
1218  }
1219 
1220  SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
1221 
1222  OpValues.push_back(ScalarOp.getValue(0));
1223  OpChains.push_back(ScalarOp.getValue(1));
1224  }
1225 
1226  SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
1227  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
1228 
1229  AddLegalizedOperand(Op.getValue(0), Result);
1230  AddLegalizedOperand(Op.getValue(1), NewChain);
1231 
1232  return Op.getResNo() ? NewChain : Result;
1233 }
1234 
1235 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1236  EVT VT = Op.getValueType();
1237  unsigned NumElems = VT.getVectorNumElements();
1238  EVT EltVT = VT.getVectorElementType();
1239  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1240  EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1241  SDLoc dl(Op);
1242  SmallVector<SDValue, 8> Ops(NumElems);
1243  for (unsigned i = 0; i < NumElems; ++i) {
1244  SDValue LHSElem = DAG.getNode(
1245  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1246  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1247  SDValue RHSElem = DAG.getNode(
1248  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1249  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1250  Ops[i] = DAG.getNode(ISD::SETCC, dl,
1251  TLI.getSetCCResultType(DAG.getDataLayout(),
1252  *DAG.getContext(), TmpEltVT),
1253  LHSElem, RHSElem, CC);
1254  Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1255  DAG.getConstant(APInt::getAllOnesValue
1256  (EltVT.getSizeInBits()), dl, EltVT),
1257  DAG.getConstant(0, dl, EltVT));
1258  }
1259  return DAG.getBuildVector(VT, dl, Ops);
1260 }
1261 
1263  return VectorLegalizer(*this).Run();
1264 }
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:571
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:538
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:594
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:296
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:562
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:605
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:519
bool isVector() const
Return true if this is a vector value type.
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
unsigned getVectorNumElements() const
const SDValue & getChain() const
unsigned getAlignment() const
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:289
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:508
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:384
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
void reserve(size_type N)
Definition: SmallVector.h:376
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:212
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:435
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
Shift and rotation operations.
Definition: ISDOpcodes.h:410
RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same wi...
Definition: ISDOpcodes.h:280
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:304
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:478
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:429
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:497
MVT getVectorElementType() const
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:524
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:327
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:610
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:235
Machine Value Type.
Simple binary floating point operators.
Definition: ISDOpcodes.h:283
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isRound() const
Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:217
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:934
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:416
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:556
Extended Value Type.
Definition: ValueTypes.h:34
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:265
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:401
Iterator for intrusive lists based on ilist_node.
BlockVerifier::State From
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:319
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:339
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:553
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:96
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:600
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:413
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
MachinePointerInfo getWithOffset(int64_t O) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
EVT getMemoryVT() const
Return the type of the in-memory value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:420
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:468
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:471
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:312
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:486
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:614
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:273
unsigned getOpcode() const
SDValue getValue(unsigned R) const
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:302
unsigned getResNo() const
get the index which selects a specific result in the SDNode
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:443
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:198
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:465
const SDValue & getOperand(unsigned i) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:474
#define LLVM_DEBUG(X)
Definition: Debug.h:123
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:584
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl< int > &ShuffleMask)
This file describes how to lower LLVM code to machine code.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:380
void resize(size_type N)
Definition: SmallVector.h:351
This class is used to represent ISD::LOAD nodes.