LLVM  7.0.0svn
Legalizer.cpp
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1 //===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize individual
11 /// instructions and the LegalizePass wrapper pass for the primary
12 /// legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
18 #include "llvm/ADT/SetVector.h"
27 #include "llvm/Support/Debug.h"
28 
29 #include <iterator>
30 
31 #define DEBUG_TYPE "legalizer"
32 
33 using namespace llvm;
34 
35 char Legalizer::ID = 0;
37  "Legalize the Machine IR a function's Machine IR", false,
38  false)
41  "Legalize the Machine IR a function's Machine IR", false,
42  false)
43 
44 Legalizer::Legalizer() : MachineFunctionPass(ID) {
46 }
47 
51 }
52 
53 void Legalizer::init(MachineFunction &MF) {
54 }
55 
56 static bool isArtifact(const MachineInstr &MI) {
57  switch (MI.getOpcode()) {
58  default:
59  return false;
60  case TargetOpcode::G_TRUNC:
61  case TargetOpcode::G_ZEXT:
62  case TargetOpcode::G_ANYEXT:
63  case TargetOpcode::G_SEXT:
64  case TargetOpcode::G_MERGE_VALUES:
65  case TargetOpcode::G_UNMERGE_VALUES:
66  return true;
67  }
68 }
69 
71  // If the ISel pipeline failed, do not bother running that pass.
72  if (MF.getProperties().hasProperty(
74  return false;
75  DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
76  init(MF);
77  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
78  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
79  LegalizerHelper Helper(MF);
80 
81  const size_t NumBlocks = MF.size();
83 
84  // Populate Insts
85  GISelWorkList<256> InstList;
86  GISelWorkList<128> ArtifactList;
88  // Perform legalization bottom up so we can DCE as we legalize.
89  // Traverse BB in RPOT and within each basic block, add insts top down,
90  // so when we pop_back_val in the legalization process, we traverse bottom-up.
91  for (auto *MBB : RPOT) {
92  if (MBB->empty())
93  continue;
94  for (MachineInstr &MI : *MBB) {
95  // Only legalize pre-isel generic instructions: others don't have types
96  // and are assumed to be legal.
97  if (!isPreISelGenericOpcode(MI.getOpcode()))
98  continue;
99  if (isArtifact(MI))
100  ArtifactList.insert(&MI);
101  else
102  InstList.insert(&MI);
103  }
104  }
106  // Only legalize pre-isel generic instructions.
107  // Legalization process could generate Target specific pseudo
108  // instructions with generic types. Don't record them
109  if (isPreISelGenericOpcode(MI->getOpcode())) {
110  if (isArtifact(*MI))
111  ArtifactList.insert(MI);
112  else
113  InstList.insert(MI);
114  }
115  DEBUG(dbgs() << ".. .. New MI: " << *MI;);
116  });
117  const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
118  LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo);
119  auto RemoveDeadInstFromLists = [&InstList,
120  &ArtifactList](MachineInstr *DeadMI) {
121  InstList.remove(DeadMI);
122  ArtifactList.remove(DeadMI);
123  };
124  bool Changed = false;
125  do {
126  while (!InstList.empty()) {
127  MachineInstr &MI = *InstList.pop_back_val();
128  assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
129  if (isTriviallyDead(MI, MRI)) {
130  DEBUG(dbgs() << MI << "Is dead; erasing.\n");
132  continue;
133  }
134 
135  // Do the legalization for this instruction.
136  auto Res = Helper.legalizeInstrStep(MI);
137  // Error out if we couldn't legalize this instruction. We may want to
138  // fall back to DAG ISel instead in the future.
141  reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
142  "unable to legalize instruction", MI);
143  return false;
144  }
145  Changed |= Res == LegalizerHelper::Legalized;
146  }
147  while (!ArtifactList.empty()) {
148  MachineInstr &MI = *ArtifactList.pop_back_val();
149  assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
150  if (isTriviallyDead(MI, MRI)) {
151  DEBUG(dbgs() << MI << "Is dead; erasing.\n");
152  RemoveDeadInstFromLists(&MI);
154  continue;
155  }
156  SmallVector<MachineInstr *, 4> DeadInstructions;
157  if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions)) {
158  for (auto *DeadMI : DeadInstructions) {
159  DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
160  RemoveDeadInstFromLists(DeadMI);
161  DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
162  }
163  Changed = true;
164  continue;
165  }
166  // If this was not an artifact (that could be combined away), this might
167  // need special handling. Add it to InstList, so when it's processed
168  // there, it has to be legal or specially handled.
169  else
170  InstList.insert(&MI);
171  }
172  } while (!InstList.empty());
173 
174  // For now don't support if new blocks are inserted - we would need to fix the
175  // outerloop for that.
176  if (MF.size() != NumBlocks) {
177  MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
178  MF.getFunction().getSubprogram(),
179  /*MBB=*/nullptr);
180  R << "inserting blocks is not supported yet";
181  reportGISelFailure(MF, TPC, MORE, R);
182  return false;
183  }
184 
185  return Changed;
186 }
const LegalizerInfo & getLegalizerInfo() const
Expose LegalizerInfo so the clients can re-use.
MachineIRBuilder MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions. ...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MachineFunctionProperties & getProperties() const
Get the function properties.
unsigned size() const
bool empty() const
Definition: GISelWorkList.h:33
void remove(MachineInstr *I)
Remove - remove I from the worklist if it exists.
Definition: GISelWorkList.h:46
INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE, "Legalize the Machine IR a function's Machine IR", false, false) INITIALIZE_PASS_END(Legalizer
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
Target-Independent Code Generator Pass Configuration Options.
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
void recordInsertions(std::function< void(MachineInstr *)> InsertedInstr)
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:363
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
unsigned const MachineRegisterInfo * MRI
LegalizeResult legalizeInstrStep(MachineInstr &MI)
Replace MI by a sequence of legal instructions that can implement the same operation.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1497
Represent the analysis usage information of a pass.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: Legalizer.cpp:70
Some kind of error has occurred and we could not legalize this instruction.
Legalize the Machine IR a function s Machine IR
Definition: Legalizer.cpp:40
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
The optimization diagnostic interface.
#define MORE()
Definition: regcomp.c:256
MachineInstr * pop_back_val()
Definition: GISelWorkList.h:56
void insert(MachineInstr *I)
Add - Add the specified instruction to the worklist if it isn&#39;t already in it.
Definition: GISelWorkList.h:39
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static char ID
Definition: Legalizer.h:33
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:59
Representation of each machine instruction.
Definition: MachineInstr.h:60
Instruction has been legalized and the MachineFunction changed.
#define DEBUG_TYPE
Definition: Legalizer.cpp:31
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool isArtifact(const MachineInstr &MI)
Definition: Legalizer.cpp:56
void initializeLegalizerPass(PassRegistry &)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: Legalizer.cpp:48
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
#define DEBUG(X)
Definition: Debug.h:118
print Print MemDeps of function
IRTranslator LLVM IR MI
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:80