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LiveIntervalAnalysis.h
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1 //===- LiveIntervalAnalysis.h - Live Interval Analysis ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LiveInterval analysis pass. Given some
11 /// numbering of each the machine instructions (in this implemention depth-first
12 /// order) an interval [i, j) is said to be a live interval for register v if
13 /// there is no instruction with number j' > j such that v is live at j' and
14 /// there is no instruction with number i' < i such that v is live at i'. In
15 /// this implementation intervals can have holes, i.e. an interval might look
16 /// like [1,20), [50,65), [1000,1001).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
22 
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/IndexedMap.h"
25 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/MC/LaneBitmask.h"
34 #include "llvm/Support/Compiler.h"
36 #include <cassert>
37 #include <cstdint>
38 #include <utility>
39 
40 namespace llvm {
41 
42 extern cl::opt<bool> UseSegmentSetForPhysRegs;
43 
44 class BitVector;
45 class LiveRangeCalc;
46 class MachineBlockFrequencyInfo;
47 class MachineDominatorTree;
48 class MachineFunction;
49 class MachineInstr;
50 class MachineRegisterInfo;
51 class raw_ostream;
52 class TargetInstrInfo;
53 class VirtRegMap;
54 
56  MachineFunction* MF;
58  const TargetRegisterInfo* TRI;
59  const TargetInstrInfo* TII;
60  AliasAnalysis *AA;
61  SlotIndexes* Indexes;
62  MachineDominatorTree *DomTree = nullptr;
63  LiveRangeCalc *LRCalc = nullptr;
64 
65  /// Special pool allocator for VNInfo's (LiveInterval val#).
66  VNInfo::Allocator VNInfoAllocator;
67 
68  /// Live interval pointers for all the virtual registers.
70 
71  /// Sorted list of instructions with register mask operands. Always use the
72  /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
73  SmallVector<SlotIndex, 8> RegMaskSlots;
74 
75  /// This vector is parallel to RegMaskSlots, it holds a pointer to the
76  /// corresponding register mask. This pointer can be recomputed as:
77  ///
78  /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
79  /// unsigned OpNum = findRegMaskOperand(MI);
80  /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
81  ///
82  /// This is kept in a separate vector partly because some standard
83  /// libraries don't support lower_bound() with mixed objects, partly to
84  /// improve locality when searching in RegMaskSlots.
85  /// Also see the comment in LiveInterval::find().
87 
88  /// For each basic block number, keep (begin, size) pairs indexing into the
89  /// RegMaskSlots and RegMaskBits arrays.
90  /// Note that basic block numbers may not be layout contiguous, that's why
91  /// we can't just keep track of the first register mask in each basic
92  /// block.
94 
95  /// Keeps a live range set for each register unit to track fixed physreg
96  /// interference.
97  SmallVector<LiveRange*, 0> RegUnitRanges;
98 
99  public:
100  static char ID;
101 
102  LiveIntervals();
103  ~LiveIntervals() override;
104 
105  /// Calculate the spill weight to assign to a single instruction.
106  static float getSpillWeight(bool isDef, bool isUse,
107  const MachineBlockFrequencyInfo *MBFI,
108  const MachineInstr &Instr);
109 
110  /// Calculate the spill weight to assign to a single instruction.
111  static float getSpillWeight(bool isDef, bool isUse,
112  const MachineBlockFrequencyInfo *MBFI,
113  const MachineBasicBlock *MBB);
114 
116  if (hasInterval(Reg))
117  return *VirtRegIntervals[Reg];
118  else
120  }
121 
122  const LiveInterval &getInterval(unsigned Reg) const {
123  return const_cast<LiveIntervals*>(this)->getInterval(Reg);
124  }
125 
126  bool hasInterval(unsigned Reg) const {
127  return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
128  }
129 
130  /// Interval creation.
132  assert(!hasInterval(Reg) && "Interval already exists!");
133  VirtRegIntervals.grow(Reg);
134  VirtRegIntervals[Reg] = createInterval(Reg);
135  return *VirtRegIntervals[Reg];
136  }
137 
140  computeVirtRegInterval(LI);
141  return LI;
142  }
143 
144  /// Interval removal.
145  void removeInterval(unsigned Reg) {
146  delete VirtRegIntervals[Reg];
147  VirtRegIntervals[Reg] = nullptr;
148  }
149 
150  /// Given a register and an instruction, adds a live segment from that
151  /// instruction to the end of its MBB.
153  MachineInstr &startInst);
154 
155  /// After removing some uses of a register, shrink its live range to just
156  /// the remaining uses. This method does not compute reaching defs for new
157  /// uses, and it doesn't remove dead defs.
158  /// Dead PHIDef values are marked as unused. New dead machine instructions
159  /// are added to the dead vector. Returns true if the interval may have been
160  /// separated into multiple connected components.
161  bool shrinkToUses(LiveInterval *li,
162  SmallVectorImpl<MachineInstr*> *dead = nullptr);
163 
164  /// Specialized version of
165  /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
166  /// that works on a subregister live range and only looks at uses matching
167  /// the lane mask of the subregister range.
168  /// This may leave the subrange empty which needs to be cleaned up with
169  /// LiveInterval::removeEmptySubranges() afterwards.
170  void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
171 
172  /// Extend the live range \p LR to reach all points in \p Indices. The
173  /// points in the \p Indices array must be jointly dominated by the union
174  /// of the existing defs in \p LR and points in \p Undefs.
175  ///
176  /// PHI-defs are added as needed to maintain SSA form.
177  ///
178  /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
179  /// will be extended to be live out of the basic block.
180  /// If a SlotIndex in \p Indices is jointy dominated only by points in
181  /// \p Undefs, the live range will not be extended to that point.
182  ///
183  /// See also LiveRangeCalc::extend().
185  ArrayRef<SlotIndex> Undefs);
186 
188  extendToIndices(LR, Indices, /*Undefs=*/{});
189  }
190 
191  /// If \p LR has a live value at \p Kill, prune its live range by removing
192  /// any liveness reachable from Kill. Add live range end points to
193  /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
194  /// value's live range.
195  ///
196  /// Calling pruneValue() and extendToIndices() can be used to reconstruct
197  /// SSA form after adding defs to a virtual register.
199  SmallVectorImpl<SlotIndex> *EndPoints);
200 
201  /// This function should not be used. Its intend is to tell you that
202  /// you are doing something wrong if you call pruveValue directly on a
203  /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
204  /// LiveRange and all the LiveRange of the subranges if any.
208  "Use pruneValue on the main LiveRange and on each subrange");
209  }
210 
212  return Indexes;
213  }
214 
216  return AA;
217  }
218 
219  /// Returns true if the specified machine instr has been removed or was
220  /// never entered in the map.
221  bool isNotInMIMap(const MachineInstr &Instr) const {
222  return !Indexes->hasIndex(Instr);
223  }
224 
225  /// Returns the base index of the given instruction.
227  return Indexes->getInstructionIndex(Instr);
228  }
229 
230  /// Returns the instruction associated with the given index.
232  return Indexes->getInstructionFromIndex(index);
233  }
234 
235  /// Return the first index in the given basic block.
237  return Indexes->getMBBStartIdx(mbb);
238  }
239 
240  /// Return the last index in the given basic block.
242  return Indexes->getMBBEndIdx(mbb);
243  }
244 
245  bool isLiveInToMBB(const LiveRange &LR,
246  const MachineBasicBlock *mbb) const {
247  return LR.liveAt(getMBBStartIdx(mbb));
248  }
249 
250  bool isLiveOutOfMBB(const LiveRange &LR,
251  const MachineBasicBlock *mbb) const {
252  return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
253  }
254 
256  return Indexes->getMBBFromIndex(index);
257  }
258 
260  Indexes->insertMBBInMaps(MBB);
261  assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
262  "Blocks must be added in order.");
263  RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
264  }
265 
267  return Indexes->insertMachineInstrInMaps(MI);
268  }
269 
272  for (MachineBasicBlock::iterator I = B; I != E; ++I)
273  Indexes->insertMachineInstrInMaps(*I);
274  }
275 
277  Indexes->removeMachineInstrFromMaps(MI);
278  }
279 
281  return Indexes->replaceMachineInstrInMaps(MI, NewMI);
282  }
283 
284  VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
285 
286  void getAnalysisUsage(AnalysisUsage &AU) const override;
287  void releaseMemory() override;
288 
289  /// Pass entry point; Calculates LiveIntervals.
290  bool runOnMachineFunction(MachineFunction&) override;
291 
292  /// Implement the dump method.
293  void print(raw_ostream &O, const Module* = nullptr) const override;
294 
295  /// If LI is confined to a single basic block, return a pointer to that
296  /// block. If LI is live in to or out of any block, return NULL.
298 
299  /// Returns true if VNI is killed by any PHI-def values in LI.
300  /// This may conservatively return true to avoid expensive computations.
301  bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
302 
303  /// Add kill flags to any instruction that kills a virtual register.
304  void addKillFlags(const VirtRegMap*);
305 
306  /// Call this method to notify LiveIntervals that instruction \p MI has been
307  /// moved within a basic block. This will update the live intervals for all
308  /// operands of \p MI. Moves between basic blocks are not supported.
309  ///
310  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
311  void handleMove(MachineInstr &MI, bool UpdateFlags = false);
312 
313  /// Update intervals for operands of \p MI so that they begin/end on the
314  /// SlotIndex for \p BundleStart.
315  ///
316  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
317  ///
318  /// Requires MI and BundleStart to have SlotIndexes, and assumes
319  /// existing liveness is accurate. BundleStart should be the first
320  /// instruction in the Bundle.
321  void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
322  bool UpdateFlags = false);
323 
324  /// Update live intervals for instructions in a range of iterators. It is
325  /// intended for use after target hooks that may insert or remove
326  /// instructions, and is only efficient for a small number of instructions.
327  ///
328  /// OrigRegs is a vector of registers that were originally used by the
329  /// instructions in the range between the two iterators.
330  ///
331  /// Currently, the only only changes that are supported are simple removal
332  /// and addition of uses.
336  ArrayRef<unsigned> OrigRegs);
337 
338  // Register mask functions.
339  //
340  // Machine instructions may use a register mask operand to indicate that a
341  // large number of registers are clobbered by the instruction. This is
342  // typically used for calls.
343  //
344  // For compile time performance reasons, these clobbers are not recorded in
345  // the live intervals for individual physical registers. Instead,
346  // LiveIntervalAnalysis maintains a sorted list of instructions with
347  // register mask operands.
348 
349  /// Returns a sorted array of slot indices of all instructions with
350  /// register mask operands.
351  ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
352 
353  /// Returns a sorted array of slot indices of all instructions with register
354  /// mask operands in the basic block numbered \p MBBNum.
356  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
357  return getRegMaskSlots().slice(P.first, P.second);
358  }
359 
360  /// Returns an array of register mask pointers corresponding to
361  /// getRegMaskSlots().
362  ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
363 
364  /// Returns an array of mask pointers corresponding to
365  /// getRegMaskSlotsInBlock(MBBNum).
367  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
368  return getRegMaskBits().slice(P.first, P.second);
369  }
370 
371  /// Test if \p LI is live across any register mask instructions, and
372  /// compute a bit mask of physical registers that are not clobbered by any
373  /// of them.
374  ///
375  /// Returns false if \p LI doesn't cross any register mask instructions. In
376  /// that case, the bit vector is not filled in.
378  BitVector &UsableRegs);
379 
380  // Register unit functions.
381  //
382  // Fixed interference occurs when MachineInstrs use physregs directly
383  // instead of virtual registers. This typically happens when passing
384  // arguments to a function call, or when instructions require operands in
385  // fixed registers.
386  //
387  // Each physreg has one or more register units, see MCRegisterInfo. We
388  // track liveness per register unit to handle aliasing registers more
389  // efficiently.
390 
391  /// Return the live range for register unit \p Unit. It will be computed if
392  /// it doesn't exist.
393  LiveRange &getRegUnit(unsigned Unit) {
394  LiveRange *LR = RegUnitRanges[Unit];
395  if (!LR) {
396  // Compute missing ranges on demand.
397  // Use segment set to speed-up initial computation of the live range.
398  RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
399  computeRegUnitRange(*LR, Unit);
400  }
401  return *LR;
402  }
403 
404  /// Return the live range for register unit \p Unit if it has already been
405  /// computed, or nullptr if it hasn't been computed yet.
406  LiveRange *getCachedRegUnit(unsigned Unit) {
407  return RegUnitRanges[Unit];
408  }
409 
410  const LiveRange *getCachedRegUnit(unsigned Unit) const {
411  return RegUnitRanges[Unit];
412  }
413 
414  /// Remove computed live range for register unit \p Unit. Subsequent uses
415  /// should rely on on-demand recomputation.
416  void removeRegUnit(unsigned Unit) {
417  delete RegUnitRanges[Unit];
418  RegUnitRanges[Unit] = nullptr;
419  }
420 
421  /// Remove value numbers and related live segments starting at position
422  /// \p Pos that are part of any liverange of physical register \p Reg or one
423  /// of its subregisters.
424  void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
425 
426  /// Remove value number and related live segments of \p LI and its subranges
427  /// that start at position \p Pos.
428  void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
429 
430  /// Split separate components in LiveInterval \p LI into separate intervals.
433 
434  /// For live interval \p LI with correct SubRanges construct matching
435  /// information for the main live range. Expects the main live range to not
436  /// have any segments or value numbers.
438 
439  private:
440  /// Compute live intervals for all virtual registers.
441  void computeVirtRegs();
442 
443  /// Compute RegMaskSlots and RegMaskBits.
444  void computeRegMasks();
445 
446  /// Walk the values in \p LI and check for dead values:
447  /// - Dead PHIDef values are marked as unused.
448  /// - Dead operands are marked as such.
449  /// - Completely dead machine instructions are added to the \p dead vector
450  /// if it is not nullptr.
451  /// Returns true if any PHI value numbers have been removed which may
452  /// have separated the interval into multiple connected components.
453  bool computeDeadValues(LiveInterval &LI,
455 
456  static LiveInterval* createInterval(unsigned Reg);
457 
458  void printInstrs(raw_ostream &O) const;
459  void dumpInstrs() const;
460 
461  void computeLiveInRegUnits();
462  void computeRegUnitRange(LiveRange&, unsigned Unit);
463  void computeVirtRegInterval(LiveInterval&);
464 
465 
466  /// Helper function for repairIntervalsInRange(), walks backwards and
467  /// creates/modifies live segments in \p LR to match the operands found.
468  /// Only full operands or operands with subregisters matching \p LaneMask
469  /// are considered.
470  void repairOldRegInRange(MachineBasicBlock::iterator Begin,
472  const SlotIndex endIdx, LiveRange &LR,
473  unsigned Reg,
474  LaneBitmask LaneMask = LaneBitmask::getAll());
475 
476  class HMEditor;
477  };
478 
479 } // end namespace llvm
480 
481 #endif // LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
A common definition of LaneBitmask for use in TableGen and CodeGen.
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
bool runOnMachineFunction(MachineFunction &) override
Pass entry point; Calculates LiveIntervals.
static LaneBitmask getAll()
Definition: LaneBitmask.h:84
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
ArrayRef< const uint32_t * > getRegMaskBits() const
Returns an array of register mask pointers corresponding to getRegMaskSlots().
void removeMachineInstrFromMaps(MachineInstr &MI)
Removes machine instruction (bundle) MI from the mapping.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
A live range for subregisters.
Definition: LiveInterval.h:645
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex, SmallVectorImpl< SlotIndex > *)
This function should not be used.
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map...
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
VNInfo::Allocator & getVNInfoAllocator()
const LiveInterval & getInterval(unsigned Reg) const
Reg
All possible values of the reg field in the ModR/M byte.
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:414
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
void insertMBBInMaps(MachineBasicBlock *MBB)
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:533
SlotIndexes pass.
Definition: SlotIndexes.h:331
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
AliasAnalysis * getAliasAnalysis() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
bool inBounds(IndexT n) const
Definition: IndexedMap.h:74
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn&#39;t...
TargetInstrInfo - Interface to description of machine instruction set.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:577
#define P(N)
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:424
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
bool hasInterval(unsigned Reg) const
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:645
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:138
void removeInterval(unsigned Reg)
Interval removal.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:389
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval *> &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:409
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:487
Represent the analysis usage information of a pass.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr *> *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:144
static const unsigned End
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:497
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
Update live intervals for instructions in a range of iterators.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void removeRegUnit(unsigned Unit)
Remove computed live range for register unit Unit.
Toolkit used by handleMove to trim or extend live intervals.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
LiveInterval & getInterval(unsigned Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &Instr)
Calculate the spill weight to assign to a single instruction.
cl::opt< bool > UseSegmentSetForPhysRegs
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveInterval & createEmptyInterval(unsigned Reg)
Interval creation.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
void addKillFlags(const VirtRegMap *)
Add kill flags to any instruction that kills a virtual register.
#define I(x, y, z)
Definition: MD5.cpp:58
SlotIndexes * getSlotIndexes() const
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
void grow(IndexT n)
Definition: IndexedMap.h:68
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart, bool UpdateFlags=false)
Update intervals for operands of MI so that they begin/end on the SlotIndex for BundleStart.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
const LiveRange * getCachedRegUnit(unsigned Unit) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block...
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
Definition: SlotIndexes.h:630