LLVM  8.0.0svn
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
29 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
30 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
31 
32 void LiveRangeEdit::Delegate::anchor() { }
33 
34 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg,
35  bool createSubRanges) {
36  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37  if (VRM)
38  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 
40  LiveInterval &LI = LIS.createEmptyInterval(VReg);
41  if (Parent && !Parent->isSpillable())
42  LI.markNotSpillable();
43  if (createSubRanges) {
44  // Create empty subranges if the OldReg's interval has them. Do not create
45  // the main range here---it will be constructed later after the subranges
46  // have been finalized.
47  LiveInterval &OldLI = LIS.getInterval(OldReg);
48  VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
49  for (LiveInterval::SubRange &S : OldLI.subranges())
50  LI.createSubRange(Alloc, S.LaneMask);
51  }
52  return LI;
53 }
54 
55 unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
56  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
57  if (VRM) {
58  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
59  }
60  // FIXME: Getting the interval here actually computes it.
61  // In theory, this may not be what we want, but in practice
62  // the createEmptyIntervalFrom API is used when this is not
63  // the case. Generally speaking we just want to annotate the
64  // LiveInterval when it gets created but we cannot do that at
65  // the moment.
66  if (Parent && !Parent->isSpillable())
67  LIS.getInterval(VReg).markNotSpillable();
68  return VReg;
69 }
70 
72  const MachineInstr *DefMI,
73  AliasAnalysis *aa) {
74  assert(DefMI && "Missing instruction");
75  ScannedRemattable = true;
76  if (!TII.isTriviallyReMaterializable(*DefMI, aa))
77  return false;
78  Remattable.insert(VNI);
79  return true;
80 }
81 
82 void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
83  for (VNInfo *VNI : getParent().valnos) {
84  if (VNI->isUnused())
85  continue;
86  unsigned Original = VRM->getOriginal(getReg());
87  LiveInterval &OrigLI = LIS.getInterval(Original);
88  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
89  if (!OrigVNI)
90  continue;
91  MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
92  if (!DefMI)
93  continue;
94  checkRematerializable(OrigVNI, DefMI, aa);
95  }
96  ScannedRemattable = true;
97 }
98 
100  if (!ScannedRemattable)
101  scanRemattable(aa);
102  return !Remattable.empty();
103 }
104 
105 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
106 /// OrigIdx are also available with the same value at UseIdx.
107 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
108  SlotIndex OrigIdx,
109  SlotIndex UseIdx) const {
110  OrigIdx = OrigIdx.getRegSlot(true);
111  UseIdx = UseIdx.getRegSlot(true);
112  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
113  const MachineOperand &MO = OrigMI->getOperand(i);
114  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
115  continue;
116 
117  // We can't remat physreg uses, unless it is a constant.
119  if (MRI.isConstantPhysReg(MO.getReg()))
120  continue;
121  return false;
122  }
123 
124  LiveInterval &li = LIS.getInterval(MO.getReg());
125  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
126  if (!OVNI)
127  continue;
128 
129  // Don't allow rematerialization immediately after the original def.
130  // It would be incorrect if OrigMI redefines the register.
131  // See PR14098.
132  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
133  return false;
134 
135  if (OVNI != li.getVNInfoAt(UseIdx))
136  return false;
137  }
138  return true;
139 }
140 
142  SlotIndex UseIdx, bool cheapAsAMove) {
143  assert(ScannedRemattable && "Call anyRematerializable first");
144 
145  // Use scanRemattable info.
146  if (!Remattable.count(OrigVNI))
147  return false;
148 
149  // No defining instruction provided.
150  SlotIndex DefIdx;
151  assert(RM.OrigMI && "No defining instruction for remattable value");
152  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
153 
154  // If only cheap remats were requested, bail out early.
155  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
156  return false;
157 
158  // Verify that all used registers are available with the same values.
159  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
160  return false;
161 
162  return true;
163 }
164 
167  unsigned DestReg,
168  const Remat &RM,
169  const TargetRegisterInfo &tri,
170  bool Late) {
171  assert(RM.OrigMI && "Invalid remat");
172  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
173  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
174  // to false anyway in case the isDead flag of RM.OrigMI's dest register
175  // is true.
176  (*--MI).getOperand(0).setIsDead(false);
177  Rematted.insert(RM.ParentVNI);
178  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
179 }
180 
182  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
183  LIS.removeInterval(Reg);
184 }
185 
186 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
188  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
189 
190  // Check that there is a single def and a single use.
191  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
192  MachineInstr *MI = MO.getParent();
193  if (MO.isDef()) {
194  if (DefMI && DefMI != MI)
195  return false;
196  if (!MI->canFoldAsLoad())
197  return false;
198  DefMI = MI;
199  } else if (!MO.isUndef()) {
200  if (UseMI && UseMI != MI)
201  return false;
202  // FIXME: Targets don't know how to fold subreg uses.
203  if (MO.getSubReg())
204  return false;
205  UseMI = MI;
206  }
207  }
208  if (!DefMI || !UseMI)
209  return false;
210 
211  // Since we're moving the DefMI load, make sure we're not extending any live
212  // ranges.
213  if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
214  LIS.getInstructionIndex(*UseMI)))
215  return false;
216 
217  // We also need to make sure it is safe to move the load.
218  // Assume there are stores between DefMI and UseMI.
219  bool SawStore = true;
220  if (!DefMI->isSafeToMove(nullptr, SawStore))
221  return false;
222 
223  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
224  << " into single use: " << *UseMI);
225 
227  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
228  return false;
229 
230  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
231  if (!FoldMI)
232  return false;
233  LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
234  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
236  DefMI->addRegisterDead(LI->reg, nullptr);
237  Dead.push_back(DefMI);
238  ++NumDCEFoldedLoads;
239  return true;
240 }
241 
242 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
243  const MachineOperand &MO) const {
244  const MachineInstr &MI = *MO.getParent();
245  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
246  if (LI.Query(Idx).isKill())
247  return true;
248  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
249  unsigned SubReg = MO.getSubReg();
250  LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
251  for (const LiveInterval::SubRange &S : LI.subranges()) {
252  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
253  return true;
254  }
255  return false;
256 }
257 
258 /// Find all live intervals that need to shrink, then remove the instruction.
259 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
260  AliasAnalysis *AA) {
261  assert(MI->allDefsAreDead() && "Def isn't really dead");
262  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
263 
264  // Never delete a bundled instruction.
265  if (MI->isBundled()) {
266  return;
267  }
268  // Never delete inline asm.
269  if (MI->isInlineAsm()) {
270  LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
271  return;
272  }
273 
274  // Use the same criteria as DeadMachineInstructionElim.
275  bool SawStore = false;
276  if (!MI->isSafeToMove(nullptr, SawStore)) {
277  LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
278  return;
279  }
280 
281  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
282 
283  // Collect virtual registers to be erased after MI is gone.
284  SmallVector<unsigned, 8> RegsToErase;
285  bool ReadsPhysRegs = false;
286  bool isOrigDef = false;
287  unsigned Dest;
288  // Only optimize rematerialize case when the instruction has one def, since
289  // otherwise we could leave some dead defs in the code. This case is
290  // extremely rare.
291  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
292  MI->getDesc().getNumDefs() == 1) {
293  Dest = MI->getOperand(0).getReg();
294  unsigned Original = VRM->getOriginal(Dest);
295  LiveInterval &OrigLI = LIS.getInterval(Original);
296  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
297  // The original live-range may have been shrunk to
298  // an empty live-range. It happens when it is dead, but
299  // we still keep it around to be able to rematerialize
300  // other values that depend on it.
301  if (OrigVNI)
302  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
303  }
304 
305  // Check for live intervals that may shrink
307  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
308  if (!MOI->isReg())
309  continue;
310  unsigned Reg = MOI->getReg();
312  // Check if MI reads any unreserved physregs.
313  if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
314  ReadsPhysRegs = true;
315  else if (MOI->isDef())
316  LIS.removePhysRegDefAt(Reg, Idx);
317  continue;
318  }
319  LiveInterval &LI = LIS.getInterval(Reg);
320 
321  // Shrink read registers, unless it is likely to be expensive and
322  // unlikely to change anything. We typically don't want to shrink the
323  // PIC base register that has lots of uses everywhere.
324  // Always shrink COPY uses that probably come from live range splitting.
325  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
326  (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
327  ToShrink.insert(&LI);
328 
329  // Remove defined value.
330  if (MOI->isDef()) {
331  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
332  TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
333  LIS.removeVRegDefAt(LI, Idx);
334  if (LI.empty())
335  RegsToErase.push_back(Reg);
336  }
337  }
338 
339  // Currently, we don't support DCE of physreg live ranges. If MI reads
340  // any unreserved physregs, don't erase the instruction, but turn it into
341  // a KILL instead. This way, the physreg live ranges don't end up
342  // dangling.
343  // FIXME: It would be better to have something like shrinkToUses() for
344  // physregs. That could potentially enable more DCE and it would free up
345  // the physreg. It would not happen often, though.
346  if (ReadsPhysRegs) {
347  MI->setDesc(TII.get(TargetOpcode::KILL));
348  // Remove all operands that aren't physregs.
349  for (unsigned i = MI->getNumOperands(); i; --i) {
350  const MachineOperand &MO = MI->getOperand(i-1);
352  continue;
353  MI->RemoveOperand(i-1);
354  }
355  LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
356  } else {
357  // If the dest of MI is an original reg and MI is reMaterializable,
358  // don't delete the inst. Replace the dest with a new reg, and keep
359  // the inst for remat of other siblings. The inst is saved in
360  // LiveRangeEdit::DeadRemats and will be deleted after all the
361  // allocations of the func are done.
362  if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
363  LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
364  VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
365  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
366  pop_back();
367  DeadRemats->insert(MI);
368  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
369  MI->substituteRegister(Dest, NewLI.reg, 0, TRI);
370  MI->getOperand(0).setIsDead(true);
371  } else {
372  if (TheDelegate)
373  TheDelegate->LRE_WillEraseInstruction(MI);
374  LIS.RemoveMachineInstrFromMaps(*MI);
375  MI->eraseFromParent();
376  ++NumDCEDeleted;
377  }
378  }
379 
380  // Erase any virtregs that are now empty and unused. There may be <undef>
381  // uses around. Keep the empty live range in that case.
382  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
383  unsigned Reg = RegsToErase[i];
384  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
385  ToShrink.remove(&LIS.getInterval(Reg));
386  eraseVirtReg(Reg);
387  }
388  }
389 }
390 
392  ArrayRef<unsigned> RegsBeingSpilled,
393  AliasAnalysis *AA) {
394  ToShrinkSet ToShrink;
395 
396  for (;;) {
397  // Erase all dead defs.
398  while (!Dead.empty())
399  eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
400 
401  if (ToShrink.empty())
402  break;
403 
404  // Shrink just one live interval. Then delete new dead defs.
405  LiveInterval *LI = ToShrink.back();
406  ToShrink.pop_back();
407  if (foldAsLoad(LI, Dead))
408  continue;
409  unsigned VReg = LI->reg;
410  if (TheDelegate)
411  TheDelegate->LRE_WillShrinkVirtReg(VReg);
412  if (!LIS.shrinkToUses(LI, &Dead))
413  continue;
414 
415  // Don't create new intervals for a register being spilled.
416  // The new intervals would have to be spilled anyway so its not worth it.
417  // Also they currently aren't spilled so creating them and not spilling
418  // them results in incorrect code.
419  bool BeingSpilled = false;
420  for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
421  if (VReg == RegsBeingSpilled[i]) {
422  BeingSpilled = true;
423  break;
424  }
425  }
426 
427  if (BeingSpilled) continue;
428 
429  // LI may have been separated, create new intervals.
430  LI->RenumberValues();
432  LIS.splitSeparateComponents(*LI, SplitLIs);
433  if (!SplitLIs.empty())
434  ++NumFracRanges;
435 
436  unsigned Original = VRM ? VRM->getOriginal(VReg) : 0;
437  for (const LiveInterval *SplitLI : SplitLIs) {
438  // If LI is an original interval that hasn't been split yet, make the new
439  // intervals their own originals instead of referring to LI. The original
440  // interval must contain all the split products, and LI doesn't.
441  if (Original != VReg && Original != 0)
442  VRM->setIsSplitFromReg(SplitLI->reg, Original);
443  if (TheDelegate)
444  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg);
445  }
446  }
447 }
448 
449 // Keep track of new virtual registers created via
450 // MachineRegisterInfo::createVirtualRegister.
451 void
452 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
453 {
454  if (VRM)
455  VRM->grow();
456 
457  NewRegs.push_back(VReg);
458 }
459 
460 void
462  const MachineLoopInfo &Loops,
463  const MachineBlockFrequencyInfo &MBFI) {
464  VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
465  for (unsigned I = 0, Size = size(); I < Size; ++I) {
466  LiveInterval &LI = LIS.getInterval(get(I));
467  if (MRI.recomputeRegClass(LI.reg))
468  LLVM_DEBUG({
470  dbgs() << "Inflated " << printReg(LI.reg) << " to "
471  << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
472  });
474  }
475 }
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
bool empty() const
Definition: LiveInterval.h:370
void push_back(const T &Elt)
Definition: SmallVector.h:218
mop_iterator operands_end()
Definition: MachineInstr.h:356
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const unsigned reg
Definition: LiveInterval.h:667
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
unsigned getReg() const
getReg - Returns the register number.
void eliminateDeadDefs(SmallVectorImpl< MachineInstr *> &Dead, ArrayRef< unsigned > RegsBeingSpilled=None, AliasAnalysis *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool isInlineAsm() const
Definition: MachineInstr.h:867
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
A live range for subregisters.
Definition: LiveInterval.h:645
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
const T & back() const
Return the last element of the SetVector.
Definition: SetVector.h:129
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Hexagon Hardware Loops
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:723
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned SubReg
bool remove(const value_type &X)
Remove an item from the set vector.
Definition: SetVector.h:158
void pop_back()
Remove the last element of the SetVector.
Definition: SetVector.h:222
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:255
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
unsigned getReg() const
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:529
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:409
unsigned createFrom(unsigned OldReg)
createFrom - Create a new virtual register based on OldReg.
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:733
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:140
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:973
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:258
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
void grow(size_t MinSize=0)
Grow the allocated memory (without initializing new elements), doubling the size of the allocated mem...
Definition: SmallVector.h:240
unsigned size() const
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isCopy() const
Definition: MachineInstr.h:892
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
LiveInterval & getParent() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:198
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li&#39;s spill weight and allocation hint.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:381
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:772
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:224
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:605
#define I(x, y, z)
Definition: MD5.cpp:58
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:73
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Remat - Information needed to rematerialize at a specific location.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:319
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
mop_iterator operands_begin()
Definition: MachineInstr.h:355
A vector that has set insertion semantics.
Definition: SetVector.h:41
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eraseVirtReg(unsigned Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS...
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.