LLVM  9.0.0svn
Instruction.h
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1 //===--------------------- Instruction.h ------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines abstractions used by the Pipeline to model register reads,
11 /// register writes and instructions.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MCA_INSTRUCTION_H
16 #define LLVM_MCA_INSTRUCTION_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
22 
23 #ifndef NDEBUG
25 #endif
26 
27 #include <memory>
28 
29 namespace llvm {
30 
31 namespace mca {
32 
33 constexpr int UNKNOWN_CYCLES = -512;
34 
35 /// A register write descriptor.
37  // Operand index. The index is negative for implicit writes only.
38  // For implicit writes, the actual operand index is computed performing
39  // a bitwise not of the OpIndex.
40  int OpIndex;
41  // Write latency. Number of cycles before write-back stage.
42  unsigned Latency;
43  // This field is set to a value different than zero only if this
44  // is an implicit definition.
45  unsigned RegisterID;
46  // Instruction itineraries would set this field to the SchedClass ID.
47  // Otherwise, it defaults to the WriteResourceID from the MCWriteLatencyEntry
48  // element associated to this write.
49  // When computing read latencies, this value is matched against the
50  // "ReadAdvance" information. The hardware backend may implement
51  // dedicated forwarding paths to quickly propagate write results to dependent
52  // instructions waiting in the reservation station (effectively bypassing the
53  // write-back stage).
55  // True only if this is a write obtained from an optional definition.
56  // Optional definitions are allowed to reference regID zero (i.e. "no
57  // register").
59 
60  bool isImplicitWrite() const { return OpIndex < 0; };
61 };
62 
63 /// A register read descriptor.
65  // A MCOperand index. This is used by the Dispatch logic to identify register
66  // reads. Implicit reads have negative indices. The actual operand index of an
67  // implicit read is the bitwise not of field OpIndex.
68  int OpIndex;
69  // The actual "UseIdx". This is used to query the ReadAdvance table. Explicit
70  // uses always come first in the sequence of uses.
71  unsigned UseIndex;
72  // This field is only set if this is an implicit read.
73  unsigned RegisterID;
74  // Scheduling Class Index. It is used to query the scheduling model for the
75  // MCSchedClassDesc object.
76  unsigned SchedClassID;
77 
78  bool isImplicitRead() const { return OpIndex < 0; };
79 };
80 
81 class ReadState;
82 
83 /// Tracks uses of a register definition (e.g. register write).
84 ///
85 /// Each implicit/explicit register write is associated with an instance of
86 /// this class. A WriteState object tracks the dependent users of a
87 /// register write. It also tracks how many cycles are left before the write
88 /// back stage.
89 class WriteState {
90  const WriteDescriptor *WD;
91  // On instruction issue, this field is set equal to the write latency.
92  // Before instruction issue, this field defaults to -512, a special
93  // value that represents an "unknown" number of cycles.
94  int CyclesLeft;
95 
96  // Actual register defined by this write. This field is only used
97  // to speedup queries on the register file.
98  // For implicit writes, this field always matches the value of
99  // field RegisterID from WD.
100  unsigned RegisterID;
101 
102  // Physical register file that serves register RegisterID.
103  unsigned PRFID;
104 
105  // True if this write implicitly clears the upper portion of RegisterID's
106  // super-registers.
107  bool ClearsSuperRegs;
108 
109  // True if this write is from a dependency breaking zero-idiom instruction.
110  bool WritesZero;
111 
112  // True if this write has been eliminated at register renaming stage.
113  // Example: a register move doesn't consume scheduler/pipleline resources if
114  // it is eliminated at register renaming stage. It still consumes
115  // decode bandwidth, and ROB entries.
116  bool IsEliminated;
117 
118  // This field is set if this is a partial register write, and it has a false
119  // dependency on any previous write of the same register (or a portion of it).
120  // DependentWrite must be able to complete before this write completes, so
121  // that we don't break the WAW, and the two writes can be merged together.
122  const WriteState *DependentWrite;
123 
124  // A partial write that is in a false dependency with this write.
125  WriteState *PartialWrite;
126 
127  unsigned DependentWriteCyclesLeft;
128 
129  // A list of dependent reads. Users is a set of dependent
130  // reads. A dependent read is added to the set only if CyclesLeft
131  // is "unknown". As soon as CyclesLeft is 'known', each user in the set
132  // gets notified with the actual CyclesLeft.
133 
134  // The 'second' element of a pair is a "ReadAdvance" number of cycles.
136 
137 public:
138  WriteState(const WriteDescriptor &Desc, unsigned RegID,
139  bool clearsSuperRegs = false, bool writesZero = false)
140  : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
141  ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero),
142  IsEliminated(false), DependentWrite(nullptr), PartialWrite(nullptr),
143  DependentWriteCyclesLeft(0) {}
144 
145  WriteState(const WriteState &Other) = default;
146  WriteState &operator=(const WriteState &Other) = default;
147 
148  int getCyclesLeft() const { return CyclesLeft; }
149  unsigned getWriteResourceID() const { return WD->SClassOrWriteResourceID; }
150  unsigned getRegisterID() const { return RegisterID; }
151  unsigned getRegisterFileID() const { return PRFID; }
152  unsigned getLatency() const { return WD->Latency; }
153  const WriteState *getDependentWrite() const { return DependentWrite; }
154 
155  // This method adds Use to the set of data dependent reads. IID is the
156  // instruction identifier associated with this write. ReadAdvance is the
157  // number of cycles to subtract from the latency of this data dependency.
158  // Use is in a RAW dependency with this write.
159  void addUser(unsigned IID, ReadState *Use, int ReadAdvance);
160 
161  // Use is a younger register write that is in a false dependency with this
162  // write. IID is the instruction identifier associated with this write.
163  void addUser(unsigned IID, WriteState *Use);
164 
165  unsigned getDependentWriteCyclesLeft() const {
166  return DependentWriteCyclesLeft;
167  }
168 
169  unsigned getNumUsers() const {
170  unsigned NumUsers = Users.size();
171  if (PartialWrite)
172  ++NumUsers;
173  return NumUsers;
174  }
175 
176  bool clearsSuperRegisters() const { return ClearsSuperRegs; }
177  bool isWriteZero() const { return WritesZero; }
178  bool isEliminated() const { return IsEliminated; }
179 
180  bool isReady() const {
181  if (DependentWrite)
182  return false;
183  unsigned CyclesLeft = getDependentWriteCyclesLeft();
184  return !CyclesLeft || CyclesLeft < getLatency();
185  }
186 
187  bool isExecuted() const {
188  return CyclesLeft != UNKNOWN_CYCLES && CyclesLeft <= 0;
189  }
190 
191  void setDependentWrite(const WriteState *Other) { DependentWrite = Other; }
192  void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) {
193  DependentWriteCyclesLeft = Cycles;
194  DependentWrite = nullptr;
195  }
196 
197  void setWriteZero() { WritesZero = true; }
198  void setEliminated() {
199  assert(Users.empty() && "Write is in an inconsistent state.");
200  CyclesLeft = 0;
201  IsEliminated = true;
202  }
203 
204  void setPRF(unsigned PRF) { PRFID = PRF; }
205 
206  // On every cycle, update CyclesLeft and notify dependent users.
207  void cycleEvent();
208  void onInstructionIssued(unsigned IID);
209 
210 #ifndef NDEBUG
211  void dump() const;
212 #endif
213 };
214 
215 /// Tracks register operand latency in cycles.
216 ///
217 /// A read may be dependent on more than one write. This occurs when some
218 /// writes only partially update the register associated to this read.
219 class ReadState {
220  const ReadDescriptor *RD;
221  // Physical register identified associated to this read.
222  unsigned RegisterID;
223  // Physical register file that serves register RegisterID.
224  unsigned PRFID;
225  // Number of writes that contribute to the definition of RegisterID.
226  // In the absence of partial register updates, the number of DependentWrites
227  // cannot be more than one.
228  unsigned DependentWrites;
229  // Number of cycles left before RegisterID can be read. This value depends on
230  // the latency of all the dependent writes. It defaults to UNKNOWN_CYCLES.
231  // It gets set to the value of field TotalCycles only when the 'CyclesLeft' of
232  // every dependent write is known.
233  int CyclesLeft;
234  // This field is updated on every writeStartEvent(). When the number of
235  // dependent writes (i.e. field DependentWrite) is zero, this value is
236  // propagated to field CyclesLeft.
237  unsigned TotalCycles;
238  // This field is set to true only if there are no dependent writes, and
239  // there are no `CyclesLeft' to wait.
240  bool IsReady;
241  // True if this is a read from a known zero register.
242  bool IsZero;
243  // True if this register read is from a dependency-breaking instruction.
244  bool IndependentFromDef;
245 
246 public:
247  ReadState(const ReadDescriptor &Desc, unsigned RegID)
248  : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0),
249  CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0), IsReady(true),
250  IsZero(false), IndependentFromDef(false) {}
251 
252  const ReadDescriptor &getDescriptor() const { return *RD; }
253  unsigned getSchedClass() const { return RD->SchedClassID; }
254  unsigned getRegisterID() const { return RegisterID; }
255  unsigned getRegisterFileID() const { return PRFID; }
256 
257  bool isPending() const { return !IndependentFromDef && CyclesLeft > 0; }
258  bool isReady() const { return IsReady; }
259  bool isImplicitRead() const { return RD->isImplicitRead(); }
260 
261  bool isIndependentFromDef() const { return IndependentFromDef; }
262  void setIndependentFromDef() { IndependentFromDef = true; }
263 
264  void cycleEvent();
265  void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles);
266  void setDependentWrites(unsigned Writes) {
267  DependentWrites = Writes;
268  IsReady = !Writes;
269  }
270 
271  bool isReadZero() const { return IsZero; }
272  void setReadZero() { IsZero = true; }
273  void setPRF(unsigned ID) { PRFID = ID; }
274 };
275 
276 /// A sequence of cycles.
277 ///
278 /// This class can be used as a building block to construct ranges of cycles.
280  unsigned Begin; // Inclusive.
281  unsigned End; // Exclusive.
282  bool Reserved; // Resources associated to this segment must be reserved.
283 
284 public:
285  CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved = false)
286  : Begin(StartCycle), End(EndCycle), Reserved(IsReserved) {}
287 
288  bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; }
289  bool startsAfter(const CycleSegment &CS) const { return End <= CS.Begin; }
290  bool endsBefore(const CycleSegment &CS) const { return Begin >= CS.End; }
291  bool overlaps(const CycleSegment &CS) const {
292  return !startsAfter(CS) && !endsBefore(CS);
293  }
294  bool isExecuting() const { return Begin == 0 && End != 0; }
295  bool isExecuted() const { return End == 0; }
296  bool operator<(const CycleSegment &Other) const {
297  return Begin < Other.Begin;
298  }
300  if (Begin)
301  Begin--;
302  if (End)
303  End--;
304  return *this;
305  }
306 
307  bool isValid() const { return Begin <= End; }
308  unsigned size() const { return End - Begin; };
309  void subtract(unsigned Cycles) {
310  assert(End >= Cycles);
311  End -= Cycles;
312  }
313 
314  unsigned begin() const { return Begin; }
315  unsigned end() const { return End; }
316  void setEnd(unsigned NewEnd) { End = NewEnd; }
317  bool isReserved() const { return Reserved; }
318  void setReserved() { Reserved = true; }
319 };
320 
321 /// Helper used by class InstrDesc to describe how hardware resources
322 /// are used.
323 ///
324 /// This class describes how many resource units of a specific resource kind
325 /// (and how many cycles) are "used" by an instruction.
328  unsigned NumUnits;
329  ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
330  : CS(Cycles), NumUnits(Units) {}
331  unsigned size() const { return CS.size(); }
332  bool isReserved() const { return CS.isReserved(); }
333  void setReserved() { CS.setReserved(); }
334 };
335 
336 /// An instruction descriptor
337 struct InstrDesc {
338  SmallVector<WriteDescriptor, 4> Writes; // Implicit writes are at the end.
339  SmallVector<ReadDescriptor, 4> Reads; // Implicit reads are at the end.
340 
341  // For every resource used by an instruction of this kind, this vector
342  // reports the number of "consumed cycles".
344 
345  // A list of buffered resources consumed by this instruction.
347 
350 
351  unsigned MaxLatency;
352  // Number of MicroOps for this instruction.
353  unsigned NumMicroOps;
354  // SchedClassID used to construct this InstrDesc.
355  // This information is currently used by views to do fast queries on the
356  // subtarget when computing the reciprocal throughput.
357  unsigned SchedClassID;
358 
359  bool MayLoad;
360  bool MayStore;
363  bool EndGroup;
364 
365  // True if all buffered resources are in-order, and there is at least one
366  // buffer which is a dispatch hazard (BufferSize = 0).
368 
369  // A zero latency instruction doesn't consume any scheduler resources.
370  bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
371 
372  InstrDesc() = default;
373  InstrDesc(const InstrDesc &Other) = delete;
374  InstrDesc &operator=(const InstrDesc &Other) = delete;
375 };
376 
377 /// Base class for instructions consumed by the simulation pipeline.
378 ///
379 /// This class tracks data dependencies as well as generic properties
380 /// of the instruction.
382  const InstrDesc &Desc;
383 
384  // This field is set for instructions that are candidates for move
385  // elimination. For more information about move elimination, see the
386  // definition of RegisterMappingTracker in RegisterFile.h
387  bool IsOptimizableMove;
388 
389  // Output dependencies.
390  // One entry per each implicit and explicit register definition.
392 
393  // Input dependencies.
394  // One entry per each implicit and explicit register use.
396 
397 public:
398  InstructionBase(const InstrDesc &D) : Desc(D), IsOptimizableMove(false) {}
399 
401  const ArrayRef<WriteState> getDefs() const { return Defs; }
403  const ArrayRef<ReadState> getUses() const { return Uses; }
404  const InstrDesc &getDesc() const { return Desc; }
405 
406  unsigned getLatency() const { return Desc.MaxLatency; }
407 
408  bool hasDependentUsers() const {
409  return any_of(Defs,
410  [](const WriteState &Def) { return Def.getNumUsers() > 0; });
411  }
412 
413  unsigned getNumUsers() const {
414  unsigned NumUsers = 0;
415  for (const WriteState &Def : Defs)
416  NumUsers += Def.getNumUsers();
417  return NumUsers;
418  }
419 
420  // Returns true if this instruction is a candidate for move elimination.
421  bool isOptimizableMove() const { return IsOptimizableMove; }
422  void setOptimizableMove() { IsOptimizableMove = true; }
423  bool isMemOp() const { return Desc.MayLoad || Desc.MayStore; }
424 };
425 
426 /// An instruction propagated through the simulated instruction pipeline.
427 ///
428 /// This class is used to monitor changes to the internal state of instructions
429 /// that are sent to the various components of the simulated hardware pipeline.
430 class Instruction : public InstructionBase {
431  enum InstrStage {
432  IS_INVALID, // Instruction in an invalid state.
433  IS_DISPATCHED, // Instruction dispatched but operands are not ready.
434  IS_PENDING, // Instruction is not ready, but operand latency is known.
435  IS_READY, // Instruction dispatched and operands ready.
436  IS_EXECUTING, // Instruction issued.
437  IS_EXECUTED, // Instruction executed. Values are written back.
438  IS_RETIRED // Instruction retired.
439  };
440 
441  // The current instruction stage.
442  enum InstrStage Stage;
443 
444  // This value defaults to the instruction latency. This instruction is
445  // considered executed when field CyclesLeft goes to zero.
446  int CyclesLeft;
447 
448  // Retire Unit token ID for this instruction.
449  unsigned RCUTokenID;
450 
451  // A bitmask of busy processor resource units.
452  // This field is set to zero only if execution is not delayed during this
453  // cycle because of unavailable pipeline resources.
454  uint64_t CriticalResourceMask;
455 
456  // An instruction identifier. This field is only set if execution is delayed
457  // by a memory dependency.
458  unsigned CriticalMemDep;
459 
460 public:
462  : InstructionBase(D), Stage(IS_INVALID), CyclesLeft(UNKNOWN_CYCLES),
463  RCUTokenID(0), CriticalResourceMask(0), CriticalMemDep(0) {}
464 
465  unsigned getRCUTokenID() const { return RCUTokenID; }
466  int getCyclesLeft() const { return CyclesLeft; }
467 
468  // Transition to the dispatch stage, and assign a RCUToken to this
469  // instruction. The RCUToken is used to track the completion of every
470  // register write performed by this instruction.
471  void dispatch(unsigned RCUTokenID);
472 
473  // Instruction issued. Transition to the IS_EXECUTING state, and update
474  // all the register definitions.
475  void execute(unsigned IID);
476 
477  // Force a transition from the IS_DISPATCHED state to the IS_READY or
478  // IS_PENDING state. State transitions normally occur either at the beginning
479  // of a new cycle (see method cycleEvent()), or as a result of another issue
480  // event. This method is called every time the instruction might have changed
481  // in state. It internally delegates to method updateDispatched() and
482  // updateWaiting().
483  void update();
484  bool updateDispatched();
485  bool updatePending();
486 
487  bool isDispatched() const { return Stage == IS_DISPATCHED; }
488  bool isPending() const { return Stage == IS_PENDING; }
489  bool isReady() const { return Stage == IS_READY; }
490  bool isExecuting() const { return Stage == IS_EXECUTING; }
491  bool isExecuted() const { return Stage == IS_EXECUTED; }
492  bool isRetired() const { return Stage == IS_RETIRED; }
493 
494  bool isEliminated() const {
495  return isReady() && getDefs().size() &&
496  all_of(getDefs(),
497  [](const WriteState &W) { return W.isEliminated(); });
498  }
499 
500  // Forces a transition from state IS_DISPATCHED to state IS_EXECUTED.
501  void forceExecuted();
502 
503  void retire() {
504  assert(isExecuted() && "Instruction is in an invalid state!");
505  Stage = IS_RETIRED;
506  }
507 
508  uint64_t getCriticalResourceMask() const { return CriticalResourceMask; }
509  unsigned getCriticalMemDep() const { return CriticalMemDep; }
510  void setCriticalResourceMask(uint64_t ResourceMask) {
511  CriticalResourceMask = ResourceMask;
512  }
513  void setCriticalMemDep(unsigned IID) { CriticalMemDep = IID; }
514 
515  void cycleEvent();
516 };
517 
518 /// An InstRef contains both a SourceMgr index and Instruction pair. The index
519 /// is used as a unique identifier for the instruction. MCA will make use of
520 /// this index as a key throughout MCA.
521 class InstRef {
522  std::pair<unsigned, Instruction *> Data;
523 
524 public:
525  InstRef() : Data(std::make_pair(0, nullptr)) {}
526  InstRef(unsigned Index, Instruction *I) : Data(std::make_pair(Index, I)) {}
527 
528  bool operator==(const InstRef &Other) const { return Data == Other.Data; }
529 
530  unsigned getSourceIndex() const { return Data.first; }
531  Instruction *getInstruction() { return Data.second; }
532  const Instruction *getInstruction() const { return Data.second; }
533 
534  /// Returns true if this references a valid instruction.
535  operator bool() const { return Data.second != nullptr; }
536 
537  /// Invalidate this reference.
538  void invalidate() { Data.second = nullptr; }
539 
540 #ifndef NDEBUG
541  void print(raw_ostream &OS) const { OS << getSourceIndex(); }
542 #endif
543 };
544 
545 #ifndef NDEBUG
547  IR.print(OS);
548  return OS;
549 }
550 #endif
551 
552 /// A reference to a register write.
553 ///
554 /// This class is mainly used by the register file to describe register
555 /// mappings. It correlates a register write to the source index of the
556 /// defining instruction.
557 class WriteRef {
558  std::pair<unsigned, WriteState *> Data;
559  static const unsigned INVALID_IID;
560 
561 public:
562  WriteRef() : Data(INVALID_IID, nullptr) {}
563  WriteRef(unsigned SourceIndex, WriteState *WS) : Data(SourceIndex, WS) {}
564 
565  unsigned getSourceIndex() const { return Data.first; }
566  const WriteState *getWriteState() const { return Data.second; }
567  WriteState *getWriteState() { return Data.second; }
568  void invalidate() { Data.second = nullptr; }
569  bool isWriteZero() const {
570  assert(isValid() && "Invalid null WriteState found!");
571  return getWriteState()->isWriteZero();
572  }
573 
574  /// Returns true if this register write has been executed, and the new
575  /// register value is therefore available to users.
576  bool isAvailable() const {
577  if (getSourceIndex() == INVALID_IID)
578  return false;
579  const WriteState *WS = getWriteState();
580  return !WS || WS->isExecuted();
581  }
582 
583  bool isValid() const { return Data.second && Data.first != INVALID_IID; }
584  bool operator==(const WriteRef &Other) const { return Data == Other.Data; }
585 
586 #ifndef NDEBUG
587  void dump() const;
588 #endif
589 };
590 
591 } // namespace mca
592 } // namespace llvm
593 
594 #endif // LLVM_MCA_INSTRUCTION_H
const WriteState * getWriteState() const
Definition: Instruction.h:566
Instruction * getInstruction()
Definition: Instruction.h:531
unsigned getRegisterFileID() const
Definition: Instruction.h:255
bool isEliminated() const
Definition: Instruction.h:178
unsigned end() const
Definition: Instruction.h:315
An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:430
bool hasDependentUsers() const
Definition: Instruction.h:408
unsigned size() const
Definition: Instruction.h:331
A sequence of cycles.
Definition: Instruction.h:279
unsigned getLatency() const
Definition: Instruction.h:152
WriteState(const WriteDescriptor &Desc, unsigned RegID, bool clearsSuperRegs=false, bool writesZero=false)
Definition: Instruction.h:138
bool isWriteZero() const
Definition: Instruction.h:177
InstructionBase(const InstrDesc &D)
Definition: Instruction.h:398
This class represents lattice values for constants.
Definition: AllocatorList.h:23
constexpr int UNKNOWN_CYCLES
Definition: Instruction.h:33
unsigned getCriticalMemDep() const
Definition: Instruction.h:509
int getCyclesLeft() const
Definition: Instruction.h:466
bool isAvailable() const
Returns true if this register write has been executed, and the new register value is therefore availa...
Definition: Instruction.h:576
InstRef(unsigned Index, Instruction *I)
Definition: Instruction.h:526
bool operator==(const WriteRef &Other) const
Definition: Instruction.h:584
SmallVector< uint64_t, 4 > Buffers
Definition: Instruction.h:346
bool isDispatched() const
Definition: Instruction.h:487
unsigned UsedProcResGroups
Definition: Instruction.h:349
bool isImplicitRead() const
Definition: Instruction.h:78
A register read descriptor.
Definition: Instruction.h:64
Instruction(const InstrDesc &D)
Definition: Instruction.h:461
bool isExecuted() const
Definition: Instruction.h:187
bool isReadZero() const
Definition: Instruction.h:271
WriteState * getWriteState()
Definition: Instruction.h:567
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
unsigned UsedProcResUnits
Definition: Instruction.h:348
block Block Frequency true
iv Induction Variable Users
Definition: IVUsers.cpp:51
bool isValid() const
Definition: Instruction.h:583
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:521
bool isRetired() const
Definition: Instruction.h:492
WriteRef(unsigned SourceIndex, WriteState *WS)
Definition: Instruction.h:563
const ReadDescriptor & getDescriptor() const
Definition: Instruction.h:252
unsigned getSourceIndex() const
Definition: Instruction.h:530
Definition: BitVector.h:937
SmallVectorImpl< WriteState > & getDefs()
Definition: Instruction.h:400
bool isWriteZero() const
Definition: Instruction.h:569
Tracks register operand latency in cycles.
Definition: Instruction.h:219
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isEliminated() const
Definition: Instruction.h:494
SmallVector< ReadDescriptor, 4 > Reads
Definition: Instruction.h:339
unsigned getRegisterID() const
Definition: Instruction.h:150
void subtract(unsigned Cycles)
Definition: Instruction.h:309
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:849
void setIndependentFromDef()
Definition: Instruction.h:262
unsigned getNumUsers() const
Definition: Instruction.h:169
Helper used by class InstrDesc to describe how hardware resources are used.
Definition: Instruction.h:326
unsigned getLatency() const
Definition: Instruction.h:406
uint64_t getCriticalResourceMask() const
Definition: Instruction.h:508
A register write descriptor.
Definition: Instruction.h:36
bool isImplicitRead() const
Definition: Instruction.h:259
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isReserved() const
Definition: Instruction.h:317
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
const InstrDesc & getDesc() const
Definition: Instruction.h:404
ResourceUsage(CycleSegment Cycles, unsigned Units=1)
Definition: Instruction.h:329
int getCyclesLeft() const
Definition: Instruction.h:148
void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles)
Definition: Instruction.h:192
bool isReady() const
Definition: Instruction.h:180
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
const ArrayRef< ReadState > getUses() const
Definition: Instruction.h:403
bool operator==(const InstRef &Other) const
Definition: Instruction.h:528
ReadState(const ReadDescriptor &Desc, unsigned RegID)
Definition: Instruction.h:247
CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved=false)
Definition: Instruction.h:285
void invalidate()
Invalidate this reference.
Definition: Instruction.h:538
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
bool isReady() const
Definition: Instruction.h:258
SmallVectorImpl< ReadState > & getUses()
Definition: Instruction.h:402
unsigned getRCUTokenID() const
Definition: Instruction.h:465
void setCriticalMemDep(unsigned IID)
Definition: Instruction.h:513
CycleSegment & operator--(void)
Definition: Instruction.h:299
const ArrayRef< WriteState > getDefs() const
Definition: Instruction.h:401
SmallVector< std::pair< uint64_t, ResourceUsage >, 4 > Resources
Definition: Instruction.h:343
size_t size() const
Definition: SmallVector.h:52
bool isExecuted() const
Definition: Instruction.h:295
void setDependentWrites(unsigned Writes)
Definition: Instruction.h:266
void setCriticalResourceMask(uint64_t ResourceMask)
Definition: Instruction.h:510
unsigned getRegisterFileID() const
Definition: Instruction.h:151
Base class for instructions consumed by the simulation pipeline.
Definition: Instruction.h:381
bool startsAfter(const CycleSegment &CS) const
Definition: Instruction.h:289
bool isImplicitWrite() const
Definition: Instruction.h:60
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
Tracks uses of a register definition (e.g.
Definition: Instruction.h:89
bool endsBefore(const CycleSegment &CS) const
Definition: Instruction.h:290
const WriteState * getDependentWrite() const
Definition: Instruction.h:153
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
A reference to a register write.
Definition: Instruction.h:557
void setEnd(unsigned NewEnd)
Definition: Instruction.h:316
bool isOptimizableMove() const
Definition: Instruction.h:421
unsigned begin() const
Definition: Instruction.h:314
bool isIndependentFromDef() const
Definition: Instruction.h:261
bool isReady() const
Definition: Instruction.h:489
raw_ostream & operator<<(raw_ostream &OS, const InstRef &IR)
Definition: Instruction.h:546
void setPRF(unsigned PRF)
Definition: Instruction.h:204
An instruction descriptor.
Definition: Instruction.h:337
unsigned getSourceIndex() const
Definition: Instruction.h:565
bool overlaps(const CycleSegment &CS) const
Definition: Instruction.h:291
bool isExecuting() const
Definition: Instruction.h:490
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
bool isZeroLatency() const
Definition: Instruction.h:370
unsigned getDependentWriteCyclesLeft() const
Definition: Instruction.h:165
bool isPending() const
Definition: Instruction.h:488
unsigned getNumUsers() const
Definition: Instruction.h:413
unsigned getRegisterID() const
Definition: Instruction.h:254
void setPRF(unsigned ID)
Definition: Instruction.h:273
bool operator<(const CycleSegment &Other) const
Definition: Instruction.h:296
unsigned getWriteResourceID() const
Definition: Instruction.h:149
bool isExecuting() const
Definition: Instruction.h:294
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPending() const
Definition: Instruction.h:257
void setDependentWrite(const WriteState *Other)
Definition: Instruction.h:191
const Instruction * getInstruction() const
Definition: Instruction.h:532
void print(raw_ostream &OS) const
Definition: Instruction.h:541
bool isExecuted() const
Definition: Instruction.h:491
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool clearsSuperRegisters() const
Definition: Instruction.h:176
bool contains(unsigned Cycle) const
Definition: Instruction.h:288
Statically lint checks LLVM IR
Definition: Lint.cpp:192
unsigned size() const
Definition: Instruction.h:308
SmallVector< WriteDescriptor, 4 > Writes
Definition: Instruction.h:338
unsigned getSchedClass() const
Definition: Instruction.h:253