LLVM  9.0.0svn
MCSubtargetInfo.cpp
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1 //===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/ArrayRef.h"
11 #include "llvm/ADT/StringRef.h"
13 #include "llvm/MC/MCSchedule.h"
16 #include <algorithm>
17 #include <cassert>
18 #include <cstring>
19 
20 using namespace llvm;
21 
24  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
26  return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
27 }
28 
30  FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
31  if (!CPU.empty())
32  CPUSchedModel = &getSchedModelForCPU(CPU);
33  else
34  CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
35 }
36 
38  FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
39 }
40 
42  const Triple &TT, StringRef C, StringRef FS,
44  const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
45  const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
46  const InstrStage *IS, const unsigned *OC, const unsigned *FP)
47  : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
48  ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
49  ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
50  InitMCProcessorInfo(CPU, FS);
51 }
52 
54  FeatureBits.flip(FB);
55  return FeatureBits;
56 }
57 
59  FeatureBits ^= FB;
60  return FeatureBits;
61 }
62 
64  SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
65  return FeatureBits;
66 }
67 
69  SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
70  return FeatureBits;
71 }
72 
74  SubtargetFeatures T(FS);
75  FeatureBitset Set, All;
76  for (std::string F : T.getFeatures()) {
77  SubtargetFeatures::ApplyFeatureFlag(Set, F, ProcFeatures);
78  if (F[0] == '-')
79  F[0] = '+';
80  SubtargetFeatures::ApplyFeatureFlag(All, F, ProcFeatures);
81  }
82  return (FeatureBits & All) == Set;
83 }
84 
86  assert(ProcSchedModels && "Processor machine model not available!");
87 
88  ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
89 
90  assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
91  [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
92  return strcmp(LHS.Key, RHS.Key) < 0;
93  }) &&
94  "Processor machine model table is not sorted");
95 
96  // Find entry
97  auto Found =
98  std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
99  if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
100  if (CPU != "help") // Don't error if the user asked for help.
101  errs() << "'" << CPU
102  << "' is not a recognized processor for this target"
103  << " (ignoring processor)\n";
105  }
106  assert(Found->Value && "Missing processor SchedModel value");
107  return *(const MCSchedModel *)Found->Value;
108 }
109 
112  const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
113  return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
114 }
115 
117  InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
118  ForwardingPaths);
119 }
uint64_t CallInst * C
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const FeatureBitset Features
F(f)
const char * Key
K-V key string.
Used to provide key value pairs for CPU and arbitrary pointers.
SI optimize exec mask operations pre RA
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
#define T
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1281
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
static const MCSchedModel & GetDefaultSchedModel()
Returns the default initialized model.
Definition: MCSchedule.h:373
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Container class for subtarget features.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
static void ToggleFeature(FeatureBitset &Bits, StringRef String, ArrayRef< SubtargetFeatureKV > FeatureTable)
Toggles a feature and update the feature bits.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
Manages the enabling and disabling of subtarget specific features.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
These values represent a non-pipelined step in the execution of an instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature, ArrayRef< SubtargetFeatureKV > FeatureTable)
Applies the feature flag and update the feature bits.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static FeatureBitset getFeatures(StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > ProcDesc, ArrayRef< SubtargetFeatureKV > ProcFeatures)
FeatureBitset getFeatureBits(StringRef CPU, ArrayRef< SubtargetFeatureKV > CPUTable, ArrayRef< SubtargetFeatureKV > FeatureTable)
Returns feature bits of a CPU.
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:243
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.