LLVM  12.0.0git
MSP430ISelLowering.h
Go to the documentation of this file.
1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16 
17 #include "MSP430.h"
20 
21 namespace llvm {
22  namespace MSP430ISD {
23  enum NodeType : unsigned {
25 
26  /// Return with a flag operand. Operand 0 is the chain operand.
28 
29  /// Same as RET_FLAG, but used for returning from ISRs.
31 
32  /// Y = R{R,L}A X, rotate right (left) arithmetically
33  RRA, RLA,
34 
35  /// Y = RRC X, rotate right via carry
36  RRC,
37 
38  /// Rotate right via carry, carry gets cleared beforehand by clrc
40 
41  /// CALL - These operations represent an abstract call
42  /// instruction, which includes a bunch of information.
44 
45  /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
46  /// and TargetGlobalAddress.
48 
49  /// CMP - Compare instruction.
50  CMP,
51 
52  /// SetCC - Operand 0 is condition code, and operand 1 is the flag
53  /// operand produced by a CMP instruction.
55 
56  /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
57  /// is the block to branch if condition is true, operand 2 is the
58  /// condition code, and operand 3 is the flag operand produced by a CMP
59  /// instruction.
61 
62  /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
63  /// is condition code and operand 4 is flag operand.
65 
66  /// DADD - Decimal addition with carry
67  /// TODO Nothing generates a node of this type yet.
69  };
70  }
71 
72  class MSP430Subtarget;
74  public:
75  explicit MSP430TargetLowering(const TargetMachine &TM,
76  const MSP430Subtarget &STI);
77 
78  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
79  return MVT::i8;
80  }
81 
83  return MVT::i16;
84  }
85 
86  /// LowerOperation - Provide custom lowering hooks for some operations.
87  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
88 
89  /// getTargetNodeName - This method returns the name of a target specific
90  /// DAG node.
91  const char *getTargetNodeName(unsigned Opcode) const override;
92 
93  SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
95  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
96  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
97  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
102  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
104  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
105  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
106 
108  getConstraintType(StringRef Constraint) const override;
109  std::pair<unsigned, const TargetRegisterClass *>
110  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
111  StringRef Constraint, MVT VT) const override;
112 
113  /// isTruncateFree - Return true if it's free to truncate a value of type
114  /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
115  /// register R15W to i8 by referencing its sub-register R15B.
116  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
117  bool isTruncateFree(EVT VT1, EVT VT2) const override;
118 
119  /// isZExtFree - Return true if any actual instruction that defines a value
120  /// of type Ty1 implicit zero-extends the value to Ty2 in the result
121  /// register. This does not necessarily include registers defined in unknown
122  /// ways, such as incoming arguments, or copies from unknown virtual
123  /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
124  /// necessarily apply to truncate instructions. e.g. on msp430, all
125  /// instructions that define 8-bit values implicit zero-extend the result
126  /// out to 16 bits.
127  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
128  bool isZExtFree(EVT VT1, EVT VT2) const override;
129  bool isZExtFree(SDValue Val, EVT VT2) const override;
130 
131  bool isLegalICmpImmediate(int64_t) const override;
132  bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
133 
135  EmitInstrWithCustomInserter(MachineInstr &MI,
136  MachineBasicBlock *BB) const override;
137  MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
138  MachineBasicBlock *BB) const;
139 
140  private:
141  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
142  CallingConv::ID CallConv, bool isVarArg,
143  bool isTailCall,
145  const SmallVectorImpl<SDValue> &OutVals,
147  const SDLoc &dl, SelectionDAG &DAG,
148  SmallVectorImpl<SDValue> &InVals) const;
149 
150  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
151  bool isVarArg,
153  const SDLoc &dl, SelectionDAG &DAG,
154  SmallVectorImpl<SDValue> &InVals) const;
155 
156  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
157  CallingConv::ID CallConv, bool isVarArg,
159  const SDLoc &dl, SelectionDAG &DAG,
160  SmallVectorImpl<SDValue> &InVals) const;
161 
162  SDValue
163  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
165  const SDLoc &dl, SelectionDAG &DAG,
166  SmallVectorImpl<SDValue> &InVals) const override;
167  SDValue
168  LowerCall(TargetLowering::CallLoweringInfo &CLI,
169  SmallVectorImpl<SDValue> &InVals) const override;
170 
171  bool CanLowerReturn(CallingConv::ID CallConv,
172  MachineFunction &MF,
173  bool IsVarArg,
175  LLVMContext &Context) const override;
176 
177  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
179  const SmallVectorImpl<SDValue> &OutVals,
180  const SDLoc &dl, SelectionDAG &DAG) const override;
181 
182  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
183  SDValue &Base,
184  SDValue &Offset,
186  SelectionDAG &DAG) const override;
187  };
188 } // namespace llvm
189 
190 #endif
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1111
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
Return with a flag operand. Operand 0 is the chain operand.
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MSP430 conditional branches.
static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
Y = RRC X, rotate right via carry.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
unsigned const TargetRegisterInfo * TRI
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
Rotate right via carry, carry gets cleared beforehand by clrc.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Same as RET_FLAG, but used for returning from ISRs.
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
Extended Value Type.
Definition: ValueTypes.h:35
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:223
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:62
#define N
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Y = R{R,L}A X, rotate right (left) arithmetically.
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1153