LLVM  6.0.0svn
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MachineCombinerPattern.h File Reference
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 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Enumerations

enum  llvm::MachineCombinerPattern {
  llvm::MachineCombinerPattern::REASSOC_AX_BY, llvm::MachineCombinerPattern::REASSOC_AX_YB, llvm::MachineCombinerPattern::REASSOC_XA_BY, llvm::MachineCombinerPattern::REASSOC_XA_YB,
  llvm::MachineCombinerPattern::MULADDW_OP1, llvm::MachineCombinerPattern::MULADDW_OP2, llvm::MachineCombinerPattern::MULSUBW_OP1, llvm::MachineCombinerPattern::MULSUBW_OP2,
  llvm::MachineCombinerPattern::MULADDWI_OP1, llvm::MachineCombinerPattern::MULSUBWI_OP1, llvm::MachineCombinerPattern::MULADDX_OP1, llvm::MachineCombinerPattern::MULADDX_OP2,
  llvm::MachineCombinerPattern::MULSUBX_OP1, llvm::MachineCombinerPattern::MULSUBX_OP2, llvm::MachineCombinerPattern::MULADDXI_OP1, llvm::MachineCombinerPattern::MULSUBXI_OP1,
  llvm::MachineCombinerPattern::FMULADDS_OP1, llvm::MachineCombinerPattern::FMULADDS_OP2, llvm::MachineCombinerPattern::FMULSUBS_OP1, llvm::MachineCombinerPattern::FMULSUBS_OP2,
  llvm::MachineCombinerPattern::FMULADDD_OP1, llvm::MachineCombinerPattern::FMULADDD_OP2, llvm::MachineCombinerPattern::FMULSUBD_OP1, llvm::MachineCombinerPattern::FMULSUBD_OP2,
  llvm::MachineCombinerPattern::FNMULSUBS_OP1, llvm::MachineCombinerPattern::FNMULSUBD_OP1, llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP1, llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP2,
  llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP1, llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP2, llvm::MachineCombinerPattern::FMLAv2f32_OP2, llvm::MachineCombinerPattern::FMLAv2f32_OP1,
  llvm::MachineCombinerPattern::FMLAv2f64_OP1, llvm::MachineCombinerPattern::FMLAv2f64_OP2, llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP1, llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP2,
  llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP1, llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP2, llvm::MachineCombinerPattern::FMLAv4f32_OP1, llvm::MachineCombinerPattern::FMLAv4f32_OP2,
  llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP1, llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP2, llvm::MachineCombinerPattern::FMLSv1i32_indexed_OP2, llvm::MachineCombinerPattern::FMLSv1i64_indexed_OP2,
  llvm::MachineCombinerPattern::FMLSv2f32_OP1, llvm::MachineCombinerPattern::FMLSv2f32_OP2, llvm::MachineCombinerPattern::FMLSv2f64_OP1, llvm::MachineCombinerPattern::FMLSv2f64_OP2,
  llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP1, llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP2, llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP1, llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP2,
  llvm::MachineCombinerPattern::FMLSv4f32_OP1, llvm::MachineCombinerPattern::FMLSv4f32_OP2, llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP1, llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP2
}
 These are instruction patterns matched by the machine combiner pass. More...