LLVM 19.0.0git
MachineIRBuilder.h
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1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
21#include "llvm/IR/DebugLoc.h"
22#include "llvm/IR/Module.h"
23
24namespace llvm {
25
26// Forward declarations.
27class APInt;
28class BlockAddress;
29class Constant;
30class ConstantFP;
31class ConstantInt;
32class DataLayout;
33class GISelCSEInfo;
34class GlobalValue;
35class TargetRegisterClass;
36class MachineFunction;
37class MachineInstr;
38class TargetInstrInfo;
39class GISelChangeObserver;
40
41/// Class which stores all the state required in a MachineIRBuilder.
42/// Since MachineIRBuilders will only store state in this object, it allows
43/// to transfer BuilderState between different kinds of MachineIRBuilders.
45 /// MachineFunction under construction.
46 MachineFunction *MF = nullptr;
47 /// Information used to access the description of the opcodes.
48 const TargetInstrInfo *TII = nullptr;
49 /// Information used to verify types are consistent and to create virtual registers.
51 /// Debug location to be set to any instruction we create.
53 /// PC sections metadata to be set to any instruction we create.
54 MDNode *PCSections = nullptr;
55
56 /// \name Fields describing the insertion point.
57 /// @{
60 /// @}
61
63
65};
66
67class DstOp {
68 union {
72 };
73
74public:
75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81
83 switch (Ty) {
84 case DstType::Ty_Reg:
85 MIB.addDef(Reg);
86 break;
87 case DstType::Ty_LLT:
88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89 break;
90 case DstType::Ty_RC:
91 MIB.addDef(MRI.createVirtualRegister(RC));
92 break;
93 }
94 }
95
97 switch (Ty) {
98 case DstType::Ty_RC:
99 return LLT{};
100 case DstType::Ty_LLT:
101 return LLTTy;
102 case DstType::Ty_Reg:
103 return MRI.getType(Reg);
104 }
105 llvm_unreachable("Unrecognised DstOp::DstType enum");
106 }
107
108 Register getReg() const {
109 assert(Ty == DstType::Ty_Reg && "Not a register");
110 return Reg;
111 }
112
114 switch (Ty) {
115 case DstType::Ty_RC:
116 return RC;
117 default:
118 llvm_unreachable("Not a RC Operand");
119 }
120 }
121
122 DstType getDstOpKind() const { return Ty; }
123
124private:
125 DstType Ty;
126};
127
128class SrcOp {
129 union {
133 int64_t Imm;
134 };
135
136public:
138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 /// Use of registers held in unsigned integer variables (or more rarely signed
143 /// integers) is no longer permitted to avoid ambiguity with upcoming support
144 /// for immediates.
145 SrcOp(unsigned) = delete;
146 SrcOp(int) = delete;
147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149
151 switch (Ty) {
153 MIB.addPredicate(Pred);
154 break;
155 case SrcType::Ty_Reg:
156 MIB.addUse(Reg);
157 break;
158 case SrcType::Ty_MIB:
159 MIB.addUse(SrcMIB->getOperand(0).getReg());
160 break;
161 case SrcType::Ty_Imm:
162 MIB.addImm(Imm);
163 break;
164 }
165 }
166
168 switch (Ty) {
170 case SrcType::Ty_Imm:
171 llvm_unreachable("Not a register operand");
172 case SrcType::Ty_Reg:
173 return MRI.getType(Reg);
174 case SrcType::Ty_MIB:
175 return MRI.getType(SrcMIB->getOperand(0).getReg());
176 }
177 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178 }
179
180 Register getReg() const {
181 switch (Ty) {
183 case SrcType::Ty_Imm:
184 llvm_unreachable("Not a register operand");
185 case SrcType::Ty_Reg:
186 return Reg;
187 case SrcType::Ty_MIB:
188 return SrcMIB->getOperand(0).getReg();
189 }
190 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191 }
192
194 switch (Ty) {
196 return Pred;
197 default:
198 llvm_unreachable("Not a register operand");
199 }
200 }
201
202 int64_t getImm() const {
203 switch (Ty) {
204 case SrcType::Ty_Imm:
205 return Imm;
206 default:
207 llvm_unreachable("Not an immediate");
208 }
209 }
210
211 SrcType getSrcOpKind() const { return Ty; }
212
213private:
214 SrcType Ty;
215};
216
217/// Helper class to build MachineInstr.
218/// It keeps internally the insertion point and debug location for all
219/// the new instructions we want to create.
220/// This information can be modified via the related setters.
222
224
225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
226
227protected:
228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
229
230 void validateUnaryOp(const LLT Res, const LLT Op0);
231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
233
234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
235 const LLT Op1Ty);
236
237 void recordInsertion(MachineInstr *InsertedInstr) const {
238 if (State.Observer)
239 State.Observer->createdInstr(*InsertedInstr);
240 }
241
242public:
243 /// Some constructors for easy use.
244 MachineIRBuilder() = default;
246
248 setMF(*MBB.getParent());
249 setInsertPt(MBB, InsPt);
250 }
251
253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
254 setInstr(MI);
255 setDebugLoc(MI.getDebugLoc());
256 }
257
260 setChangeObserver(Observer);
261 }
262
263 virtual ~MachineIRBuilder() = default;
264
265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
266
268 assert(State.TII && "TargetInstrInfo is not set");
269 return *State.TII;
270 }
271
272 /// Getter for the function we currently build.
274 assert(State.MF && "MachineFunction is not set");
275 return *State.MF;
276 }
277
278 const MachineFunction &getMF() const {
279 assert(State.MF && "MachineFunction is not set");
280 return *State.MF;
281 }
282
283 const DataLayout &getDataLayout() const {
285 }
286
288 return getMF().getFunction().getContext();
289 }
290
291 /// Getter for DebugLoc
292 const DebugLoc &getDL() { return State.DL; }
293
294 /// Getter for MRI
295 MachineRegisterInfo *getMRI() { return State.MRI; }
296 const MachineRegisterInfo *getMRI() const { return State.MRI; }
297
298 /// Getter for the State
299 MachineIRBuilderState &getState() { return State; }
300
301 /// Setter for the State
302 void setState(const MachineIRBuilderState &NewState) { State = NewState; }
303
304 /// Getter for the basic block we currently build.
305 const MachineBasicBlock &getMBB() const {
306 assert(State.MBB && "MachineBasicBlock is not set");
307 return *State.MBB;
308 }
309
311 return const_cast<MachineBasicBlock &>(
312 const_cast<const MachineIRBuilder *>(this)->getMBB());
313 }
314
315 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
316 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
317
318 /// Current insertion point for new instructions.
320
321 /// Set the insertion point before the specified position.
322 /// \pre MBB must be in getMF().
323 /// \pre II must be a valid iterator in MBB.
325 assert(MBB.getParent() == &getMF() &&
326 "Basic block is in a different function");
327 State.MBB = &MBB;
328 State.II = II;
329 }
330
331 /// @}
332
334
335 /// \name Setters for the insertion point.
336 /// @{
337 /// Set the MachineFunction where to build instructions.
338 void setMF(MachineFunction &MF);
339
340 /// Set the insertion point to the end of \p MBB.
341 /// \pre \p MBB must be contained by getMF().
343 State.MBB = &MBB;
344 State.II = MBB.end();
345 assert(&getMF() == MBB.getParent() &&
346 "Basic block is in a different function");
347 }
348
349 /// Set the insertion point to before MI.
350 /// \pre MI must be in getMF().
352 assert(MI.getParent() && "Instruction is not part of a basic block");
353 setMBB(*MI.getParent());
354 State.II = MI.getIterator();
355 setPCSections(MI.getPCSections());
356 }
357 /// @}
358
359 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
360 /// \pre MI must be in getMF().
362 setInstr(MI);
363 setDebugLoc(MI.getDebugLoc());
364 }
365
367 State.Observer = &Observer;
368 }
369
371
372 void stopObservingChanges() { State.Observer = nullptr; }
373
374 bool isObservingChanges() const { return State.Observer != nullptr; }
375 /// @}
376
377 /// Set the debug location to \p DL for all the next build instructions.
378 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
379
380 /// Get the current instruction's debug location.
381 const DebugLoc &getDebugLoc() { return State.DL; }
382
383 /// Set the PC sections metadata to \p MD for all the next build instructions.
384 void setPCSections(MDNode *MD) { State.PCSections = MD; }
385
386 /// Get the current instruction's PC sections metadata.
387 MDNode *getPCSections() { return State.PCSections; }
388
389 /// Build and insert <empty> = \p Opcode <empty>.
390 /// The insertion point is the one set by the last call of either
391 /// setBasicBlock or setMI.
392 ///
393 /// \pre setBasicBlock or setMI must have been called.
394 ///
395 /// \return a MachineInstrBuilder for the newly created instruction.
397 return insertInstr(buildInstrNoInsert(Opcode));
398 }
399
400 /// Build but don't insert <empty> = \p Opcode <empty>.
401 ///
402 /// \pre setMF, setBasicBlock or setMI must have been called.
403 ///
404 /// \return a MachineInstrBuilder for the newly created instruction.
406
407 /// Insert an existing instruction at the insertion point.
409
410 /// Build and insert a DBG_VALUE instruction expressing the fact that the
411 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
413 const MDNode *Expr);
414
415 /// Build and insert a DBG_VALUE instruction expressing the fact that the
416 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
417 /// Expr).
419 const MDNode *Variable,
420 const MDNode *Expr);
421
422 /// Build and insert a DBG_VALUE instruction expressing the fact that the
423 /// associated \p Variable lives in the stack slot specified by \p FI
424 /// (suitably modified by \p Expr).
425 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
426 const MDNode *Expr);
427
428 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
429 /// given by \p C (suitably modified by \p Expr).
431 const MDNode *Variable,
432 const MDNode *Expr);
433
434 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
435 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
437
438 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
439 ///
440 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
441 /// the allocated memory into \p Res.
442 /// \pre setBasicBlock or setMI must have been called.
443 /// \pre \p Res must be a generic virtual register with pointer type.
444 ///
445 /// \return a MachineInstrBuilder for the newly created instruction.
447 Align Alignment);
448
449 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
450 ///
451 /// G_FRAME_INDEX materializes the address of an alloca value or other
452 /// stack-based object.
453 ///
454 /// \pre setBasicBlock or setMI must have been called.
455 /// \pre \p Res must be a generic virtual register with pointer type.
456 ///
457 /// \return a MachineInstrBuilder for the newly created instruction.
459
460 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
461 ///
462 /// G_GLOBAL_VALUE materializes the address of the specified global
463 /// into \p Res.
464 ///
465 /// \pre setBasicBlock or setMI must have been called.
466 /// \pre \p Res must be a generic virtual register with pointer type
467 /// in the same address space as \p GV.
468 ///
469 /// \return a MachineInstrBuilder for the newly created instruction.
471
472 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
473 ///
474 /// G_CONSTANT_POOL materializes the address of an object in the constant
475 /// pool.
476 ///
477 /// \pre setBasicBlock or setMI must have been called.
478 /// \pre \p Res must be a generic virtual register with pointer type.
479 ///
480 /// \return a MachineInstrBuilder for the newly created instruction.
481 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
482
483 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
484 ///
485 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
486 /// storing the resulting pointer in \p Res. Addressible units are typically
487 /// bytes but this can vary between targets.
488 ///
489 /// \pre setBasicBlock or setMI must have been called.
490 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
491 /// type.
492 /// \pre \p Op1 must be a generic virtual register with scalar type.
493 ///
494 /// \return a MachineInstrBuilder for the newly created instruction.
495 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
496 const SrcOp &Op1,
497 std::optional<unsigned> Flags = std::nullopt);
498
499 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
500 ///
501 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
502 /// storing the resulting pointer in \p Res. If \p Value is zero then no
503 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
504 /// \p Res.
505 ///
506 /// \pre setBasicBlock or setMI must have been called.
507 /// \pre \p Op0 must be a generic virtual register with pointer type.
508 /// \pre \p ValueTy must be a scalar type.
509 /// \pre \p Res must be 0. This is to detect confusion between
510 /// materializePtrAdd() and buildPtrAdd().
511 /// \post \p Res will either be a new generic virtual register of the same
512 /// type as \p Op0 or \p Op0 itself.
513 ///
514 /// \return a MachineInstrBuilder for the newly created instruction.
515 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
516 Register Op0,
517 const LLT ValueTy,
519
520 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
522 const SrcOp &Op1) {
523 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
524 }
525
526 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
527 ///
528 /// This clears the low bits of a pointer operand without destroying its
529 /// pointer properties. This has the effect of rounding the address *down* to
530 /// a specified alignment in bits.
531 ///
532 /// \pre setBasicBlock or setMI must have been called.
533 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
534 /// type.
535 /// \pre \p NumBits must be an integer representing the number of low bits to
536 /// be cleared in \p Op0.
537 ///
538 /// \return a MachineInstrBuilder for the newly created instruction.
539 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
540 uint32_t NumBits);
541
542 /// Build and insert
543 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
544 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
545 ///
546 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
547 ///
548 /// \pre setBasicBlock or setMI must have been called.
549 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
550 /// same vector element type and Op0 must have fewer elements then Res.
551 ///
552 /// \return a MachineInstrBuilder for the newly created build vector instr.
554 const SrcOp &Op0);
555
556 /// Build and insert
557 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
558 /// \p Res = G_BUILD_VECTOR a, b, ..., x
559 ///
560 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
561 ///
562 /// \pre setBasicBlock or setMI must have been called.
563 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
564 /// same vector element type and Op0 must have more elements then Res.
565 ///
566 /// \return a MachineInstrBuilder for the newly created build vector instr.
568 const SrcOp &Op0);
569
570 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
571 ///
572 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
573 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
574 ///
575 /// \pre setBasicBlock or setMI must have been called.
576 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
577 /// same scalar type.
578 ////\pre \p CarryOut must be generic virtual register with scalar type
579 ///(typically s1)
580 ///
581 /// \return The newly created instruction.
582 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
583 const SrcOp &Op0, const SrcOp &Op1) {
584 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
585 }
586
587 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
588 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
589 const SrcOp &Op0, const SrcOp &Op1) {
590 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
591 }
592
593 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
594 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
595 const SrcOp &Op0, const SrcOp &Op1) {
596 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
597 }
598
599 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
600 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
601 const SrcOp &Op0, const SrcOp &Op1) {
602 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
603 }
604
605 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
606 /// \p Op1, \p CarryIn
607 ///
608 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
609 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
610 /// arithmetic.
611 ///
612 /// \pre setBasicBlock or setMI must have been called.
613 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
614 /// with the same scalar type.
615 /// \pre \p CarryOut and \p CarryIn must be generic virtual
616 /// registers with the same scalar type (typically s1)
617 ///
618 /// \return The newly created instruction.
619 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
620 const SrcOp &Op0, const SrcOp &Op1,
621 const SrcOp &CarryIn) {
622 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
623 {Op0, Op1, CarryIn});
624 }
625
626 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
627 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
628 const SrcOp &Op0, const SrcOp &Op1,
629 const SrcOp &CarryIn) {
630 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
631 {Op0, Op1, CarryIn});
632 }
633
634 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
635 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
636 const SrcOp &Op0, const SrcOp &Op1,
637 const SrcOp &CarryIn) {
638 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
639 {Op0, Op1, CarryIn});
640 }
641
642 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
643 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
644 const SrcOp &Op0, const SrcOp &Op1,
645 const SrcOp &CarryIn) {
646 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
647 {Op0, Op1, CarryIn});
648 }
649
650 /// Build and insert \p Res = G_ANYEXT \p Op0
651 ///
652 /// G_ANYEXT produces a register of the specified width, with bits 0 to
653 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
654 /// (i.e. this is neither zero nor sign-extension). For a vector register,
655 /// each element is extended individually.
656 ///
657 /// \pre setBasicBlock or setMI must have been called.
658 /// \pre \p Res must be a generic virtual register with scalar or vector type.
659 /// \pre \p Op must be a generic virtual register with scalar or vector type.
660 /// \pre \p Op must be smaller than \p Res
661 ///
662 /// \return The newly created instruction.
663
664 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
665
666 /// Build and insert \p Res = G_SEXT \p Op
667 ///
668 /// G_SEXT produces a register of the specified width, with bits 0 to
669 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
670 /// high bit of \p Op (i.e. 2s-complement sign extended).
671 ///
672 /// \pre setBasicBlock or setMI must have been called.
673 /// \pre \p Res must be a generic virtual register with scalar or vector type.
674 /// \pre \p Op must be a generic virtual register with scalar or vector type.
675 /// \pre \p Op must be smaller than \p Res
676 ///
677 /// \return The newly created instruction.
678 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
679
680 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
681 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
682 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
683 }
684
685 /// Build and insert \p Res = G_FPEXT \p Op
687 std::optional<unsigned> Flags = std::nullopt) {
688 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
689 }
690
691 /// Build and insert a G_PTRTOINT instruction.
693 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
694 }
695
696 /// Build and insert a G_INTTOPTR instruction.
698 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
699 }
700
701 /// Build and insert \p Dst = G_BITCAST \p Src
702 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
703 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
704 }
705
706 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
708 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
709 }
710
711 /// \return The opcode of the extension the target wants to use for boolean
712 /// values.
713 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
714
715 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
716 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
717 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
718 bool IsFP);
719
720 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
721 // or COPY depending on how the target wants to extend boolean values, using
722 // the original register size.
724 bool IsVector,
725 bool IsFP);
726
727 /// Build and insert \p Res = G_ZEXT \p Op
728 ///
729 /// G_ZEXT produces a register of the specified width, with bits 0 to
730 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
731 /// register, each element is extended individually.
732 ///
733 /// \pre setBasicBlock or setMI must have been called.
734 /// \pre \p Res must be a generic virtual register with scalar or vector type.
735 /// \pre \p Op must be a generic virtual register with scalar or vector type.
736 /// \pre \p Op must be smaller than \p Res
737 ///
738 /// \return The newly created instruction.
739 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
740
741 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
742 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
743 /// ///
744 /// \pre setBasicBlock or setMI must have been called.
745 /// \pre \p Res must be a generic virtual register with scalar or vector type.
746 /// \pre \p Op must be a generic virtual register with scalar or vector type.
747 ///
748 /// \return The newly created instruction.
750
751 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
752 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
753 /// ///
754 /// \pre setBasicBlock or setMI must have been called.
755 /// \pre \p Res must be a generic virtual register with scalar or vector type.
756 /// \pre \p Op must be a generic virtual register with scalar or vector type.
757 ///
758 /// \return The newly created instruction.
760
761 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
762 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
763 /// ///
764 /// \pre setBasicBlock or setMI must have been called.
765 /// \pre \p Res must be a generic virtual register with scalar or vector type.
766 /// \pre \p Op must be a generic virtual register with scalar or vector type.
767 ///
768 /// \return The newly created instruction.
770
771 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
772 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
773 /// \p Op.
774 /// ///
775 /// \pre setBasicBlock or setMI must have been called.
776 /// \pre \p Res must be a generic virtual register with scalar or vector type.
777 /// \pre \p Op must be a generic virtual register with scalar or vector type.
778 ///
779 /// \return The newly created instruction.
780 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
781 const SrcOp &Op);
782
783 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
784 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
785 /// emulated using G_AND.
787 int64_t ImmOp);
788
789 /// Build and insert an appropriate cast between two registers of equal size.
790 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
791
792 /// Build and insert G_BR \p Dest
793 ///
794 /// G_BR is an unconditional branch to \p Dest.
795 ///
796 /// \pre setBasicBlock or setMI must have been called.
797 ///
798 /// \return a MachineInstrBuilder for the newly created instruction.
800
801 /// Build and insert G_BRCOND \p Tst, \p Dest
802 ///
803 /// G_BRCOND is a conditional branch to \p Dest.
804 ///
805 /// \pre setBasicBlock or setMI must have been called.
806 /// \pre \p Tst must be a generic virtual register with scalar
807 /// type. At the beginning of legalization, this will be a single
808 /// bit (s1). Targets with interesting flags registers may change
809 /// this. For a wider type, whether the branch is taken must only
810 /// depend on bit 0 (for now).
811 ///
812 /// \return The newly created instruction.
814
815 /// Build and insert G_BRINDIRECT \p Tgt
816 ///
817 /// G_BRINDIRECT is an indirect branch to \p Tgt.
818 ///
819 /// \pre setBasicBlock or setMI must have been called.
820 /// \pre \p Tgt must be a generic virtual register with pointer type.
821 ///
822 /// \return a MachineInstrBuilder for the newly created instruction.
824
825 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
826 ///
827 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
828 /// jump table index \p JTI and index \p IndexReg
829 ///
830 /// \pre setBasicBlock or setMI must have been called.
831 /// \pre \p TablePtr must be a generic virtual register with pointer type.
832 /// \pre \p JTI must be a jump table index.
833 /// \pre \p IndexReg must be a generic virtual register with pointer type.
834 ///
835 /// \return a MachineInstrBuilder for the newly created instruction.
836 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
837 Register IndexReg);
838
839 /// Build and insert \p Res = G_CONSTANT \p Val
840 ///
841 /// G_CONSTANT is an integer constant with the specified size and value. \p
842 /// Val will be extended or truncated to the size of \p Reg.
843 ///
844 /// \pre setBasicBlock or setMI must have been called.
845 /// \pre \p Res must be a generic virtual register with scalar or pointer
846 /// type.
847 ///
848 /// \return The newly created instruction.
849 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
850 const ConstantInt &Val);
851
852 /// Build and insert \p Res = G_CONSTANT \p Val
853 ///
854 /// G_CONSTANT is an integer constant with the specified size and value.
855 ///
856 /// \pre setBasicBlock or setMI must have been called.
857 /// \pre \p Res must be a generic virtual register with scalar type.
858 ///
859 /// \return The newly created instruction.
860 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
861 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
862
863 /// Build and insert \p Res = G_FCONSTANT \p Val
864 ///
865 /// G_FCONSTANT is a floating-point constant with the specified size and
866 /// value.
867 ///
868 /// \pre setBasicBlock or setMI must have been called.
869 /// \pre \p Res must be a generic virtual register with scalar type.
870 ///
871 /// \return The newly created instruction.
872 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
873 const ConstantFP &Val);
874
875 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
876 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
877
878 /// Build and insert \p Res = COPY Op
879 ///
880 /// Register-to-register COPY sets \p Res to \p Op.
881 ///
882 /// \pre setBasicBlock or setMI must have been called.
883 ///
884 /// \return a MachineInstrBuilder for the newly created instruction.
885 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
886
887
888 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
889 ///
890 /// \return a MachineInstrBuilder for the newly created instruction.
892 const SrcOp &Op, unsigned Val) {
893 return buildInstr(Opc, Res, Op).addImm(Val);
894 }
895
896 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
897 ///
898 /// \return a MachineInstrBuilder for the newly created instruction.
900 unsigned Size) {
901 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
902 }
903
904 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
905 ///
906 /// \return a MachineInstrBuilder for the newly created instruction.
908 unsigned Size) {
909 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
910 }
911
912 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
913 ///
914 /// \return a MachineInstrBuilder for the newly created instruction.
916 Align AlignVal) {
917 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
918 AlignVal.value());
919 }
920
921 /// Build and insert `Res = G_LOAD Addr, MMO`.
922 ///
923 /// Loads the value stored at \p Addr. Puts the result in \p Res.
924 ///
925 /// \pre setBasicBlock or setMI must have been called.
926 /// \pre \p Res must be a generic virtual register.
927 /// \pre \p Addr must be a generic virtual register with pointer type.
928 ///
929 /// \return a MachineInstrBuilder for the newly created instruction.
931 MachineMemOperand &MMO) {
932 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
933 }
934
935 /// Build and insert a G_LOAD instruction, while constructing the
936 /// MachineMemOperand.
938 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
939 Align Alignment,
941 const AAMDNodes &AAInfo = AAMDNodes());
942
943 /// Build and insert `Res = <opcode> Addr, MMO`.
944 ///
945 /// Loads the value stored at \p Addr. Puts the result in \p Res.
946 ///
947 /// \pre setBasicBlock or setMI must have been called.
948 /// \pre \p Res must be a generic virtual register.
949 /// \pre \p Addr must be a generic virtual register with pointer type.
950 ///
951 /// \return a MachineInstrBuilder for the newly created instruction.
952 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
953 const SrcOp &Addr, MachineMemOperand &MMO);
954
955 /// Helper to create a load from a constant offset given a base address. Load
956 /// the type of \p Dst from \p Offset from the given base address and memory
957 /// operand.
959 const SrcOp &BasePtr,
960 MachineMemOperand &BaseMMO,
961 int64_t Offset);
962
963 /// Build and insert `G_STORE Val, Addr, MMO`.
964 ///
965 /// Stores the value \p Val to \p Addr.
966 ///
967 /// \pre setBasicBlock or setMI must have been called.
968 /// \pre \p Val must be a generic virtual register.
969 /// \pre \p Addr must be a generic virtual register with pointer type.
970 ///
971 /// \return a MachineInstrBuilder for the newly created instruction.
972 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
973 MachineMemOperand &MMO);
974
975 /// Build and insert a G_STORE instruction, while constructing the
976 /// MachineMemOperand.
978 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
979 Align Alignment,
981 const AAMDNodes &AAInfo = AAMDNodes());
982
983 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
984 ///
985 /// \pre setBasicBlock or setMI must have been called.
986 /// \pre \p Res and \p Src must be generic virtual registers.
987 ///
988 /// \return a MachineInstrBuilder for the newly created instruction.
989 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
990
991 /// Build and insert \p Res = IMPLICIT_DEF.
993
994 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
995 ///
996 /// G_MERGE_VALUES combines the input elements contiguously into a larger
997 /// register. It should only be used when the destination register is not a
998 /// vector.
999 ///
1000 /// \pre setBasicBlock or setMI must have been called.
1001 /// \pre The entire register \p Res (and no more) must be covered by the input
1002 /// registers.
1003 /// \pre The type of all \p Ops registers must be identical.
1004 ///
1005 /// \return a MachineInstrBuilder for the newly created instruction.
1007 ArrayRef<Register> Ops);
1008
1009 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1010 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1011 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1012 ///
1013 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1014 /// register. It is used when the destination register is not a vector.
1015 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1016 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1017 ///
1018 /// \pre setBasicBlock or setMI must have been called.
1019 /// \pre The entire register \p Res (and no more) must be covered by the input
1020 /// registers.
1021 /// \pre The type of all \p Ops registers must be identical.
1022 ///
1023 /// \return a MachineInstrBuilder for the newly created instruction. The
1024 /// opcode of the new instruction will depend on the types of both
1025 /// the destination and the sources.
1027 ArrayRef<Register> Ops);
1029 std::initializer_list<SrcOp> Ops);
1030
1031 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1032 ///
1033 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1034 ///
1035 /// \pre setBasicBlock or setMI must have been called.
1036 /// \pre The entire register \p Res (and no more) must be covered by the input
1037 /// registers.
1038 /// \pre The type of all \p Res registers must be identical.
1039 ///
1040 /// \return a MachineInstrBuilder for the newly created instruction.
1043
1044 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1046
1047 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1048 ///
1049 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1050 /// \pre setBasicBlock or setMI must have been called.
1051 /// \pre The entire register \p Res (and no more) must be covered by the
1052 /// input scalar registers.
1053 /// \pre The type of all \p Ops registers must be identical.
1054 ///
1055 /// \return a MachineInstrBuilder for the newly created instruction.
1057 ArrayRef<Register> Ops);
1058
1059 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1060 /// built with G_CONSTANT.
1062 ArrayRef<APInt> Ops);
1063
1064 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1065 /// the number of elements
1066 MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src);
1067
1068 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1069 ///
1070 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1071 /// which have types larger than the destination vector element type, and
1072 /// truncates the values to fit.
1073 ///
1074 /// If the operands given are already the same size as the vector elt type,
1075 /// then this method will instead create a G_BUILD_VECTOR instruction.
1076 ///
1077 /// \pre setBasicBlock or setMI must have been called.
1078 /// \pre The type of all \p Ops registers must be identical.
1079 ///
1080 /// \return a MachineInstrBuilder for the newly created instruction.
1082 ArrayRef<Register> Ops);
1083
1084 /// Build and insert a vector splat of a scalar \p Src using a
1085 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1086 ///
1087 /// \pre setBasicBlock or setMI must have been called.
1088 /// \pre \p Src must have the same type as the element type of \p Dst
1089 ///
1090 /// \return a MachineInstrBuilder for the newly created instruction.
1091 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1092
1093 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1094 ///
1095 /// \pre setBasicBlock or setMI must have been called.
1096 ///
1097 /// \return a MachineInstrBuilder for the newly created instruction.
1098 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1099 const SrcOp &Src2, ArrayRef<int> Mask);
1100
1101 /// Build and insert \p Res = G_SPLAT_VECTOR \p Val
1102 ///
1103 /// \pre setBasicBlock or setMI must have been called.
1104 /// \pre \p Res must be a generic virtual register with vector type.
1105 /// \pre \p Val must be a generic virtual register with scalar type.
1106 ///
1107 /// \return a MachineInstrBuilder for the newly created instruction.
1108 MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val);
1109
1110 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1111 ///
1112 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1113 /// vectors.
1114 ///
1115 /// \pre setBasicBlock or setMI must have been called.
1116 /// \pre The entire register \p Res (and no more) must be covered by the input
1117 /// registers.
1118 /// \pre The type of all source operands must be identical.
1119 ///
1120 /// \return a MachineInstrBuilder for the newly created instruction.
1122 ArrayRef<Register> Ops);
1123
1124 /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
1125 ///
1126 /// \pre setBasicBlock or setMI must have been called.
1127 /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
1128 /// vector type.
1129 ///
1130 /// \return a MachineInstrBuilder for the newly created instruction.
1131 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1132 const SrcOp &Src1, unsigned Index);
1133
1134 /// Build and insert `Res = G_EXTRACT_SUBVECTOR Src, Idx0`.
1135 ///
1136 /// \pre setBasicBlock or setMI must have been called.
1137 /// \pre \p Res and \p Src must be generic virtual registers with vector type.
1138 ///
1139 /// \return a MachineInstrBuilder for the newly created instruction.
1141 unsigned Index);
1142
1143 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1144 const SrcOp &Op, unsigned Index);
1145
1146 /// Build and insert \p Res = G_VSCALE \p MinElts
1147 ///
1148 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1149 /// into \p Res.
1150 ///
1151 /// \pre setBasicBlock or setMI must have been called.
1152 /// \pre \p Res must be a generic virtual register with scalar type.
1153 ///
1154 /// \return a MachineInstrBuilder for the newly created instruction.
1155 MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts);
1156
1157 /// Build and insert \p Res = G_VSCALE \p MinElts
1158 ///
1159 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1160 /// into \p Res.
1161 ///
1162 /// \pre setBasicBlock or setMI must have been called.
1163 /// \pre \p Res must be a generic virtual register with scalar type.
1164 ///
1165 /// \return a MachineInstrBuilder for the newly created instruction.
1166 MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
1167
1168 /// Build and insert \p Res = G_VSCALE \p MinElts
1169 ///
1170 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1171 /// into \p Res.
1172 ///
1173 /// \pre setBasicBlock or setMI must have been called.
1174 /// \pre \p Res must be a generic virtual register with scalar type.
1175 ///
1176 /// \return a MachineInstrBuilder for the newly created instruction.
1177 MachineInstrBuilder buildVScale(const DstOp &Res, const APInt &MinElts);
1178
1179 /// Build and insert a G_INTRINSIC instruction.
1180 ///
1181 /// There are four different opcodes based on combinations of whether the
1182 /// intrinsic has side effects and whether it is convergent. These properties
1183 /// can be specified as explicit parameters, or else they are retrieved from
1184 /// the MCID for the intrinsic.
1185 ///
1186 /// The parameter \p Res provides the Registers or MOs that will be defined by
1187 /// this instruction.
1188 ///
1189 /// \pre setBasicBlock or setMI must have been called.
1190 ///
1191 /// \return a MachineInstrBuilder for the newly created instruction.
1193 bool HasSideEffects, bool isConvergent);
1196 bool HasSideEffects, bool isConvergent);
1198
1199 /// Build and insert \p Res = G_FPTRUNC \p Op
1200 ///
1201 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1202 ///
1203 /// \pre setBasicBlock or setMI must have been called.
1204 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1205 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1206 /// \pre \p Res must be smaller than \p Op
1207 ///
1208 /// \return The newly created instruction.
1210 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1211 std::optional<unsigned> Flags = std::nullopt);
1212
1213 /// Build and insert \p Res = G_TRUNC \p Op
1214 ///
1215 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1216 /// truncated independently before being packed into the destination.
1217 ///
1218 /// \pre setBasicBlock or setMI must have been called.
1219 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1220 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1221 /// \pre \p Res must be smaller than \p Op
1222 ///
1223 /// \return The newly created instruction.
1224 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1225
1226 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1227 ///
1228 /// \pre setBasicBlock or setMI must have been called.
1229
1230 /// \pre \p Res must be a generic virtual register with scalar or
1231 /// vector type. Typically this starts as s1 or <N x s1>.
1232 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1233 /// same number of elements as \p Res. If \p Res is a scalar,
1234 /// \p Op0 must be either a scalar or pointer.
1235 /// \pre \p Pred must be an integer predicate.
1236 ///
1237 /// \return a MachineInstrBuilder for the newly created instruction.
1239 const SrcOp &Op0, const SrcOp &Op1);
1240
1241 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1242 ///
1243 /// \pre setBasicBlock or setMI must have been called.
1244
1245 /// \pre \p Res must be a generic virtual register with scalar or
1246 /// vector type. Typically this starts as s1 or <N x s1>.
1247 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1248 /// same number of elements as \p Res (or scalar, if \p Res is
1249 /// scalar).
1250 /// \pre \p Pred must be a floating-point predicate.
1251 ///
1252 /// \return a MachineInstrBuilder for the newly created instruction.
1254 const SrcOp &Op0, const SrcOp &Op1,
1255 std::optional<unsigned> Flags = std::nullopt);
1256
1257 /// Build and insert a \p Res = G_IS_FPCLASS \p Src, \p Mask
1259 unsigned Mask) {
1260 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res},
1261 {Src, SrcOp(static_cast<int64_t>(Mask))});
1262 }
1263
1264 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1265 ///
1266 /// \pre setBasicBlock or setMI must have been called.
1267 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1268 /// with the same type.
1269 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1270 /// vector type. If vector then it must have the same number of
1271 /// elements as the other parameters.
1272 ///
1273 /// \return a MachineInstrBuilder for the newly created instruction.
1274 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1275 const SrcOp &Op0, const SrcOp &Op1,
1276 std::optional<unsigned> Flags = std::nullopt);
1277
1278 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1279 /// \p Elt, \p Idx
1280 ///
1281 /// \pre setBasicBlock or setMI must have been called.
1282 /// \pre \p Res and \p Val must be a generic virtual register
1283 // with the same vector type.
1284 /// \pre \p Elt and \p Idx must be a generic virtual register
1285 /// with scalar type.
1286 ///
1287 /// \return The newly created instruction.
1289 const SrcOp &Val,
1290 const SrcOp &Elt,
1291 const SrcOp &Idx);
1292
1293 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1294 ///
1295 /// \pre setBasicBlock or setMI must have been called.
1296 /// \pre \p Res must be a generic virtual register with scalar type.
1297 /// \pre \p Val must be a generic virtual register with vector type.
1298 ///
1299 /// \return The newly created instruction.
1301 const SrcOp &Val,
1302 const int Idx) {
1303 return buildExtractVectorElement(Res, Val,
1305 }
1306
1307 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1308 ///
1309 /// \pre setBasicBlock or setMI must have been called.
1310 /// \pre \p Res must be a generic virtual register with scalar type.
1311 /// \pre \p Val must be a generic virtual register with vector type.
1312 /// \pre \p Idx must be a generic virtual register with scalar type.
1313 ///
1314 /// \return The newly created instruction.
1316 const SrcOp &Val,
1317 const SrcOp &Idx);
1318
1319 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1320 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1321 ///
1322 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1323 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1324 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1325 ///
1326 /// \pre setBasicBlock or setMI must have been called.
1327 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1328 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1329 /// will be assigned 0 on failure and 1 on success.
1330 /// \pre \p Addr must be a generic virtual register with pointer type.
1331 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1332 /// registers of the same type.
1333 ///
1334 /// \return a MachineInstrBuilder for the newly created instruction.
1336 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1337 Register Addr, Register CmpVal, Register NewVal,
1338 MachineMemOperand &MMO);
1339
1340 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1341 /// MMO`.
1342 ///
1343 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1344 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1345 /// Addr in \p Res.
1346 ///
1347 /// \pre setBasicBlock or setMI must have been called.
1348 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1349 /// \pre \p Addr must be a generic virtual register with pointer type.
1350 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1351 /// registers of the same type.
1352 ///
1353 /// \return a MachineInstrBuilder for the newly created instruction.
1355 Register CmpVal, Register NewVal,
1356 MachineMemOperand &MMO);
1357
1358 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1359 ///
1360 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1361 /// original value from \p Addr in \p OldValRes. The modification is
1362 /// determined by the opcode.
1363 ///
1364 /// \pre setBasicBlock or setMI must have been called.
1365 /// \pre \p OldValRes must be a generic virtual register.
1366 /// \pre \p Addr must be a generic virtual register with pointer type.
1367 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1368 /// same type.
1369 ///
1370 /// \return a MachineInstrBuilder for the newly created instruction.
1371 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1372 const SrcOp &Addr, const SrcOp &Val,
1373 MachineMemOperand &MMO);
1374
1375 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1376 ///
1377 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1378 /// value from \p Addr in \p OldValRes.
1379 ///
1380 /// \pre setBasicBlock or setMI must have been called.
1381 /// \pre \p OldValRes must be a generic virtual register.
1382 /// \pre \p Addr must be a generic virtual register with pointer type.
1383 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1384 /// same type.
1385 ///
1386 /// \return a MachineInstrBuilder for the newly created instruction.
1388 Register Val, MachineMemOperand &MMO);
1389
1390 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1391 ///
1392 /// Atomically replace the value at \p Addr with the addition of \p Val and
1393 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1394 ///
1395 /// \pre setBasicBlock or setMI must have been called.
1396 /// \pre \p OldValRes must be a generic virtual register.
1397 /// \pre \p Addr must be a generic virtual register with pointer type.
1398 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1399 /// same type.
1400 ///
1401 /// \return a MachineInstrBuilder for the newly created instruction.
1403 Register Val, MachineMemOperand &MMO);
1404
1405 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1406 ///
1407 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1408 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1409 ///
1410 /// \pre setBasicBlock or setMI must have been called.
1411 /// \pre \p OldValRes must be a generic virtual register.
1412 /// \pre \p Addr must be a generic virtual register with pointer type.
1413 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1414 /// same type.
1415 ///
1416 /// \return a MachineInstrBuilder for the newly created instruction.
1418 Register Val, MachineMemOperand &MMO);
1419
1420 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1421 ///
1422 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1423 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1424 ///
1425 /// \pre setBasicBlock or setMI must have been called.
1426 /// \pre \p OldValRes must be a generic virtual register.
1427 /// \pre \p Addr must be a generic virtual register with pointer type.
1428 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1429 /// same type.
1430 ///
1431 /// \return a MachineInstrBuilder for the newly created instruction.
1433 Register Val, MachineMemOperand &MMO);
1434
1435 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1436 ///
1437 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1438 /// and the original value. Puts the original value from \p Addr in \p
1439 /// OldValRes.
1440 ///
1441 /// \pre setBasicBlock or setMI must have been called.
1442 /// \pre \p OldValRes must be a generic virtual register.
1443 /// \pre \p Addr must be a generic virtual register with pointer type.
1444 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1445 /// same type.
1446 ///
1447 /// \return a MachineInstrBuilder for the newly created instruction.
1449 Register Val, MachineMemOperand &MMO);
1450
1451 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1452 ///
1453 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1454 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1455 ///
1456 /// \pre setBasicBlock or setMI must have been called.
1457 /// \pre \p OldValRes must be a generic virtual register.
1458 /// \pre \p Addr must be a generic virtual register with pointer type.
1459 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1460 /// same type.
1461 ///
1462 /// \return a MachineInstrBuilder for the newly created instruction.
1464 Register Val, MachineMemOperand &MMO);
1465
1466 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1467 ///
1468 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1469 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1470 ///
1471 /// \pre setBasicBlock or setMI must have been called.
1472 /// \pre \p OldValRes must be a generic virtual register.
1473 /// \pre \p Addr must be a generic virtual register with pointer type.
1474 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1475 /// same type.
1476 ///
1477 /// \return a MachineInstrBuilder for the newly created instruction.
1479 Register Val, MachineMemOperand &MMO);
1480
1481 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1482 ///
1483 /// Atomically replace the value at \p Addr with the signed maximum of \p
1484 /// Val and the original value. Puts the original value from \p Addr in \p
1485 /// OldValRes.
1486 ///
1487 /// \pre setBasicBlock or setMI must have been called.
1488 /// \pre \p OldValRes must be a generic virtual register.
1489 /// \pre \p Addr must be a generic virtual register with pointer type.
1490 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1491 /// same type.
1492 ///
1493 /// \return a MachineInstrBuilder for the newly created instruction.
1495 Register Val, MachineMemOperand &MMO);
1496
1497 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1498 ///
1499 /// Atomically replace the value at \p Addr with the signed minimum of \p
1500 /// Val and the original value. Puts the original value from \p Addr in \p
1501 /// OldValRes.
1502 ///
1503 /// \pre setBasicBlock or setMI must have been called.
1504 /// \pre \p OldValRes must be a generic virtual register.
1505 /// \pre \p Addr must be a generic virtual register with pointer type.
1506 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1507 /// same type.
1508 ///
1509 /// \return a MachineInstrBuilder for the newly created instruction.
1511 Register Val, MachineMemOperand &MMO);
1512
1513 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1514 ///
1515 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1516 /// Val and the original value. Puts the original value from \p Addr in \p
1517 /// OldValRes.
1518 ///
1519 /// \pre setBasicBlock or setMI must have been called.
1520 /// \pre \p OldValRes must be a generic virtual register.
1521 /// \pre \p Addr must be a generic virtual register with pointer type.
1522 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1523 /// same type.
1524 ///
1525 /// \return a MachineInstrBuilder for the newly created instruction.
1527 Register Val, MachineMemOperand &MMO);
1528
1529 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1530 ///
1531 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1532 /// Val and the original value. Puts the original value from \p Addr in \p
1533 /// OldValRes.
1534 ///
1535 /// \pre setBasicBlock or setMI must have been called.
1536 /// \pre \p OldValRes must be a generic virtual register.
1537 /// \pre \p Addr must be a generic virtual register with pointer type.
1538 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1539 /// same type.
1540 ///
1541 /// \return a MachineInstrBuilder for the newly created instruction.
1543 Register Val, MachineMemOperand &MMO);
1544
1545 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1547 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1548 MachineMemOperand &MMO);
1549
1550 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1552 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1553 MachineMemOperand &MMO);
1554
1555 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1556 ///
1557 /// Atomically replace the value at \p Addr with the floating point maximum of
1558 /// \p Val and the original value. Puts the original value from \p Addr in \p
1559 /// OldValRes.
1560 ///
1561 /// \pre setBasicBlock or setMI must have been called.
1562 /// \pre \p OldValRes must be a generic virtual register.
1563 /// \pre \p Addr must be a generic virtual register with pointer type.
1564 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1565 /// same type.
1566 ///
1567 /// \return a MachineInstrBuilder for the newly created instruction.
1569 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1570 MachineMemOperand &MMO);
1571
1572 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1573 ///
1574 /// Atomically replace the value at \p Addr with the floating point minimum of
1575 /// \p Val and the original value. Puts the original value from \p Addr in \p
1576 /// OldValRes.
1577 ///
1578 /// \pre setBasicBlock or setMI must have been called.
1579 /// \pre \p OldValRes must be a generic virtual register.
1580 /// \pre \p Addr must be a generic virtual register with pointer type.
1581 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1582 /// same type.
1583 ///
1584 /// \return a MachineInstrBuilder for the newly created instruction.
1586 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1587 MachineMemOperand &MMO);
1588
1589 /// Build and insert `G_FENCE Ordering, Scope`.
1590 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1591
1592 /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType
1593 MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW,
1594 unsigned Locality, unsigned CacheType,
1595 MachineMemOperand &MMO);
1596
1597 /// Build and insert \p Dst = G_FREEZE \p Src
1598 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1599 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1600 }
1601
1602 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1603 ///
1604 /// G_BLOCK_ADDR computes the address of a basic block.
1605 ///
1606 /// \pre setBasicBlock or setMI must have been called.
1607 /// \pre \p Res must be a generic virtual register of a pointer type.
1608 ///
1609 /// \return The newly created instruction.
1611
1612 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1613 ///
1614 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1615 /// truncated to their width.
1616 ///
1617 /// \pre setBasicBlock or setMI must have been called.
1618 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1619 /// with the same (scalar or vector) type).
1620 ///
1621 /// \return a MachineInstrBuilder for the newly created instruction.
1622
1623 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1624 const SrcOp &Src1,
1625 std::optional<unsigned> Flags = std::nullopt) {
1626 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1627 }
1628
1629 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1630 ///
1631 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1632 /// \p Op1, truncated to their width.
1633 ///
1634 /// \pre setBasicBlock or setMI must have been called.
1635 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1636 /// with the same (scalar or vector) type).
1637 ///
1638 /// \return a MachineInstrBuilder for the newly created instruction.
1639
1640 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1641 const SrcOp &Src1,
1642 std::optional<unsigned> Flags = std::nullopt) {
1643 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1644 }
1645
1646 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1647 ///
1648 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1649 /// truncated to their width.
1650 ///
1651 /// \pre setBasicBlock or setMI must have been called.
1652 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1653 /// with the same (scalar or vector) type).
1654 ///
1655 /// \return a MachineInstrBuilder for the newly created instruction.
1656 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1657 const SrcOp &Src1,
1658 std::optional<unsigned> Flags = std::nullopt) {
1659 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1660 }
1661
1663 const SrcOp &Src1,
1664 std::optional<unsigned> Flags = std::nullopt) {
1665 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1666 }
1667
1669 const SrcOp &Src1,
1670 std::optional<unsigned> Flags = std::nullopt) {
1671 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1672 }
1673
1674 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1675 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1676 const SrcOp &Src1,
1677 std::optional<unsigned> Flags = std::nullopt) {
1678 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1679 }
1680
1681 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1682 const SrcOp &Src1,
1683 std::optional<unsigned> Flags = std::nullopt) {
1684 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1685 }
1686
1688 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1689 std::optional<unsigned> Flags = std::nullopt) {
1690 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1691 }
1692
1694 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1695 std::optional<unsigned> Flags = std::nullopt) {
1696 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1697 }
1698
1700 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1701 std::optional<unsigned> Flags = std::nullopt) {
1702 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1703 }
1704
1706 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1707 std::optional<unsigned> Flags = std::nullopt) {
1708 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1709 }
1710
1711 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1712 const SrcOp &Src1,
1713 std::optional<unsigned> Flags = std::nullopt) {
1714 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1715 }
1716
1717 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1718 const SrcOp &Src1,
1719 std::optional<unsigned> Flags = std::nullopt) {
1720 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1721 }
1722
1723 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1724 const SrcOp &Src1,
1725 std::optional<unsigned> Flags = std::nullopt) {
1726 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1727 }
1728
1729 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1730 ///
1731 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1732 /// Op1.
1733 ///
1734 /// \pre setBasicBlock or setMI must have been called.
1735 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1736 /// with the same (scalar or vector) type).
1737 ///
1738 /// \return a MachineInstrBuilder for the newly created instruction.
1739
1740 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1741 const SrcOp &Src1) {
1742 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1743 }
1744
1745 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1746 ///
1747 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1748 /// Op1.
1749 ///
1750 /// \pre setBasicBlock or setMI must have been called.
1751 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1752 /// with the same (scalar or vector) type).
1753 ///
1754 /// \return a MachineInstrBuilder for the newly created instruction.
1755 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1756 const SrcOp &Src1,
1757 std::optional<unsigned> Flags = std::nullopt) {
1758 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1759 }
1760
1761 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1762 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1763 const SrcOp &Src1) {
1764 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1765 }
1766
1767 /// Build and insert a bitwise not,
1768 /// \p NegOne = G_CONSTANT -1
1769 /// \p Res = G_OR \p Op0, NegOne
1770 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1771 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1772 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1773 }
1774
1775 /// Build and insert integer negation
1776 /// \p Zero = G_CONSTANT 0
1777 /// \p Res = G_SUB Zero, \p Op0
1778 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1779 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1780 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1781 }
1782
1783 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1784 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1785 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1786 }
1787
1788 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1789 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1790 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1791 }
1792
1793 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1795 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1796 }
1797
1798 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1799 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1800 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1801 }
1802
1803 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1805 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1806 }
1807
1808 /// Build and insert \p Dst = G_BSWAP \p Src0
1809 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1810 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1811 }
1812
1813 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1814 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1815 const SrcOp &Src1,
1816 std::optional<unsigned> Flags = std::nullopt) {
1817 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1818 }
1819
1820 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1822 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1823 std::optional<unsigned> Flags = std::nullopt) {
1824 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1825 }
1826
1827 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1828 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1829 const SrcOp &Src1,
1830 std::optional<unsigned> Flags = std::nullopt) {
1831 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1832 }
1833
1834 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1835 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1836 const SrcOp &Src1,
1837 std::optional<unsigned> Flags = std::nullopt) {
1838 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1839 }
1840
1841 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1842 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1843 const SrcOp &Src1, const SrcOp &Src2,
1844 std::optional<unsigned> Flags = std::nullopt) {
1845 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1846 }
1847
1848 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1849 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1850 const SrcOp &Src1, const SrcOp &Src2,
1851 std::optional<unsigned> Flags = std::nullopt) {
1852 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1853 }
1854
1855 /// Build and insert \p Res = G_FNEG \p Op0
1856 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1857 std::optional<unsigned> Flags = std::nullopt) {
1858 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1859 }
1860
1861 /// Build and insert \p Res = G_FABS \p Op0
1862 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1863 std::optional<unsigned> Flags = std::nullopt) {
1864 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1865 }
1866
1867 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1869 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1870 std::optional<unsigned> Flags = std::nullopt) {
1871 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1872 }
1873
1874 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1876 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1877 std::optional<unsigned> Flags = std::nullopt) {
1878 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1879 }
1880
1881 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1883 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1884 std::optional<unsigned> Flags = std::nullopt) {
1885 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1886 }
1887
1888 /// Build and insert \p Dst = G_FLOG \p Src
1890 std::optional<unsigned> Flags = std::nullopt) {
1891 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1892 }
1893
1894 /// Build and insert \p Dst = G_FLOG2 \p Src
1896 std::optional<unsigned> Flags = std::nullopt) {
1897 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1898 }
1899
1900 /// Build and insert \p Dst = G_FEXP2 \p Src
1902 std::optional<unsigned> Flags = std::nullopt) {
1903 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1904 }
1905
1906 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1907 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1908 const SrcOp &Src1,
1909 std::optional<unsigned> Flags = std::nullopt) {
1910 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1911 }
1912
1913 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
1915 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1916 std::optional<unsigned> Flags = std::nullopt) {
1917 return buildInstr(TargetOpcode::G_FLDEXP, {Dst}, {Src0, Src1}, Flags);
1918 }
1919
1920 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src
1922 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src,
1923 std::optional<unsigned> Flags = std::nullopt) {
1924 return buildInstr(TargetOpcode::G_FFREXP, {Fract, Exp}, {Src}, Flags);
1925 }
1926
1927 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1929 const SrcOp &Src1) {
1930 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1931 }
1932
1933 /// Build and insert \p Res = G_UITOFP \p Src0
1934 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1935 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1936 }
1937
1938 /// Build and insert \p Res = G_SITOFP \p Src0
1939 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1940 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1941 }
1942
1943 /// Build and insert \p Res = G_FPTOUI \p Src0
1944 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1945 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1946 }
1947
1948 /// Build and insert \p Res = G_FPTOSI \p Src0
1949 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1950 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1951 }
1952
1953 /// Build and insert \p Dst = G_INTRINSIC_ROUNDEVEN \p Src0, \p Src1
1955 buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0,
1956 std::optional<unsigned> Flags = std::nullopt) {
1957 return buildInstr(TargetOpcode::G_INTRINSIC_ROUNDEVEN, {Dst}, {Src0},
1958 Flags);
1959 }
1960
1961 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1962 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1963 const SrcOp &Src1) {
1964 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1965 }
1966
1967 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1968 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1969 const SrcOp &Src1) {
1970 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1971 }
1972
1973 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1974 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1975 const SrcOp &Src1) {
1976 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1977 }
1978
1979 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1980 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1981 const SrcOp &Src1) {
1982 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1983 }
1984
1985 /// Build and insert \p Dst = G_ABS \p Src
1986 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1987 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1988 }
1989
1990 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1991 ///
1992 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1993 /// the jump table index \p JTI.
1994 ///
1995 /// \return a MachineInstrBuilder for the newly created instruction.
1996 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1997
1998 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1999 ///
2000 /// \p ScalarIn is the scalar accumulator input to start the sequential
2001 /// reduction operation of \p VecIn.
2003 const SrcOp &ScalarIn,
2004 const SrcOp &VecIn) {
2005 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
2006 {ScalarIn, {VecIn}});
2007 }
2008
2009 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
2010 ///
2011 /// \p ScalarIn is the scalar accumulator input to start the sequential
2012 /// reduction operation of \p VecIn.
2014 const SrcOp &ScalarIn,
2015 const SrcOp &VecIn) {
2016 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
2017 {ScalarIn, {VecIn}});
2018 }
2019
2020 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
2021 ///
2022 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2023 /// \p VecIn.
2025 const SrcOp &ScalarIn,
2026 const SrcOp &VecIn) {
2027 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
2028 }
2029
2030 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
2031 ///
2032 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2033 /// \p VecIn.
2035 const SrcOp &ScalarIn,
2036 const SrcOp &VecIn) {
2037 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
2038 }
2039
2040 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
2042 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
2043 }
2044
2045 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
2047 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
2048 }
2049
2050 /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
2052 const SrcOp &Src) {
2053 return buildInstr(TargetOpcode::G_VECREDUCE_FMAXIMUM, {Dst}, {Src});
2054 }
2055
2056 /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
2058 const SrcOp &Src) {
2059 return buildInstr(TargetOpcode::G_VECREDUCE_FMINIMUM, {Dst}, {Src});
2060 }
2061
2062 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
2064 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
2065 }
2066
2067 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
2069 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
2070 }
2071
2072 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
2074 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
2075 }
2076
2077 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
2079 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
2080 }
2081
2082 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
2084 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
2085 }
2086
2087 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
2089 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
2090 }
2091
2092 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
2094 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
2095 }
2096
2097 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
2099 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
2100 }
2101
2102 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
2104 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
2105 }
2106
2107 /// Build and insert G_MEMCPY or G_MEMMOVE
2108 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
2109 const SrcOp &SrcPtr,
2110 const SrcOp &Size,
2111 MachineMemOperand &DstMMO,
2112 MachineMemOperand &SrcMMO) {
2113 auto MIB = buildInstr(
2114 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2115 MIB.addMemOperand(&DstMMO);
2116 MIB.addMemOperand(&SrcMMO);
2117 return MIB;
2118 }
2119
2120 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2121 const SrcOp &Size, MachineMemOperand &DstMMO,
2122 MachineMemOperand &SrcMMO) {
2123 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2124 DstMMO, SrcMMO);
2125 }
2126
2127 /// Build and insert G_TRAP or G_DEBUGTRAP
2129 return buildInstr(Debug ? TargetOpcode::G_DEBUGTRAP : TargetOpcode::G_TRAP);
2130 }
2131
2132 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2134 const SrcOp &LSB, const SrcOp &Width) {
2135 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
2136 }
2137
2138 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2140 const SrcOp &LSB, const SrcOp &Width) {
2141 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2142 }
2143
2144 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2146 const SrcOp &Amt) {
2147 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2148 }
2149
2150 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2152 const SrcOp &Amt) {
2153 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2154 }
2155
2156 /// Build and insert \p Dst = G_BITREVERSE \p Src
2158 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2159 }
2160
2161 virtual MachineInstrBuilder
2162 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2163 std::optional<unsigned> Flags = std::nullopt);
2164};
2165
2166} // End namespace llvm.
2167#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
unsigned Reg
Module.h This file contains the declarations for the Module class.
#define P(N)
bool Debug
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:889
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:960
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:268
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
DstOp(const MachineOperand &Op)
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
Register getReg() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:350
The CSE Analysis object.
Definition: CSEInfo.h:69
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Metadata node.
Definition: Metadata.h:1067
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
GISelChangeObserver * getObserver()
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLDEXP Src0, Src1.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)
Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)
Build and insert Res = G_VSCALE MinElts.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMINIMUM Src.
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAXIMUM Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
MachineInstrBuilder buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_ROUNDEVEN Src0, Src1.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src, unsigned Mask)
Build and insert a Res = G_IS_FPCLASS Src, Mask.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
bool isObservingChanges() const
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrap(bool Debug=false)
Build and insert G_TRAP or G_DEBUGTRAP.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineInstrBuilder buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Fract, Exp = G_FFREXP Src.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)
Build and insert G_PREFETCH Addr, RW, Locality, CacheType.
MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)
Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)
Build and insert Res = G_SPLAT_VECTOR Val.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setState(const MachineIRBuilderState &NewState)
Setter for the State.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.h:287
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
DWARFExpression::Operation Op
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...