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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the MachineIRBuilder class.
11 /// This is a helper class to build MachineInstr.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
16 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 
34 /// Class which stores all the state required in a MachineIRBuilder.
35 /// Since MachineIRBuilders will only store state in this object, it allows
36 /// to transfer BuilderState between different kinds of MachineIRBuilders.
38  /// MachineFunction under construction.
40  /// Information used to access the description of the opcodes.
42  /// Information used to verify types are consistent and to create virtual registers.
44  /// Debug location to be set to any instruction we create.
46 
47  /// \name Fields describing the insertion point.
48  /// @{
51  /// @}
52 
53  std::function<void(MachineInstr *)> InsertedInstr;
54 };
55 
56 /// Helper class to build MachineInstr.
57 /// It keeps internally the insertion point and debug location for all
58 /// the new instructions we want to create.
59 /// This information can be modify via the related setters.
61 
63  void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
64 
65 protected:
66  unsigned getDestFromArg(unsigned Reg) { return Reg; }
67  unsigned getDestFromArg(LLT Ty) {
68  return getMF().getRegInfo().createGenericVirtualRegister(Ty);
69  }
70  unsigned getDestFromArg(const TargetRegisterClass *RC) {
71  return getMF().getRegInfo().createVirtualRegister(RC);
72  }
73 
74  void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg) {
75  MIB.addUse(Reg);
76  }
77 
79  MIB.addUse(UseMIB->getOperand(0).getReg());
80  }
81 
83  template<typename UseArgTy, typename ... UseArgsTy>
84  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
85  addUseFromArg(MIB, Arg1);
86  addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
87  }
88  unsigned getRegFromArg(unsigned Reg) { return Reg; }
89  unsigned getRegFromArg(const MachineInstrBuilder &MIB) {
90  return MIB->getOperand(0).getReg();
91  }
92 
93  void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
94 
95 public:
96  /// Some constructors for easy use.
97  MachineIRBuilderBase() = default;
100  setInstr(MI);
101  }
102 
103  MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
104 
106  assert(State.TII && "TargetInstrInfo is not set");
107  return *State.TII;
108  }
109 
110  /// Getter for the function we currently build.
112  assert(State.MF && "MachineFunction is not set");
113  return *State.MF;
114  }
115 
116  /// Getter for DebugLoc
117  const DebugLoc &getDL() { return State.DL; }
118 
119  /// Getter for MRI
120  MachineRegisterInfo *getMRI() { return State.MRI; }
121 
122  /// Getter for the State
123  MachineIRBuilderState &getState() { return State; }
124 
125  /// Getter for the basic block we currently build.
127  assert(State.MBB && "MachineBasicBlock is not set");
128  return *State.MBB;
129  }
130 
131  /// Current insertion point for new instructions.
133 
134  /// Set the insertion point before the specified position.
135  /// \pre MBB must be in getMF().
136  /// \pre II must be a valid iterator in MBB.
138  /// @}
139 
140  /// \name Setters for the insertion point.
141  /// @{
142  /// Set the MachineFunction where to build instructions.
143  void setMF(MachineFunction &);
144 
145  /// Set the insertion point to the end of \p MBB.
146  /// \pre \p MBB must be contained by getMF().
147  void setMBB(MachineBasicBlock &MBB);
148 
149  /// Set the insertion point to before MI.
150  /// \pre MI must be in getMF().
151  void setInstr(MachineInstr &MI);
152  /// @}
153 
154  /// \name Control where instructions we create are recorded (typically for
155  /// visiting again later during legalization).
156  /// @{
157  void recordInsertion(MachineInstr *InsertedInstr) const;
158  void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
159  void stopRecordingInsertions();
160  /// @}
161 
162  /// Set the debug location to \p DL for all the next build instructions.
163  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
164 
165  /// Get the current instruction's debug location.
166  DebugLoc getDebugLoc() { return State.DL; }
167 
168  /// Build and insert <empty> = \p Opcode <empty>.
169  /// The insertion point is the one set by the last call of either
170  /// setBasicBlock or setMI.
171  ///
172  /// \pre setBasicBlock or setMI must have been called.
173  ///
174  /// \return a MachineInstrBuilder for the newly created instruction.
175  MachineInstrBuilder buildInstr(unsigned Opcode);
176 
177  /// Build but don't insert <empty> = \p Opcode <empty>.
178  ///
179  /// \pre setMF, setBasicBlock or setMI must have been called.
180  ///
181  /// \return a MachineInstrBuilder for the newly created instruction.
182  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
183 
184  /// Insert an existing instruction at the insertion point.
185  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
186 
187  /// Build and insert a DBG_VALUE instruction expressing the fact that the
188  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
189  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
190  const MDNode *Expr);
191 
192  /// Build and insert a DBG_VALUE instruction expressing the fact that the
193  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
194  /// Expr).
195  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
196  const MDNode *Variable,
197  const MDNode *Expr);
198 
199  /// Build and insert a DBG_VALUE instruction expressing the fact that the
200  /// associated \p Variable lives in the stack slot specified by \p FI
201  /// (suitably modified by \p Expr).
202  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
203  const MDNode *Expr);
204 
205  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
206  /// given by \p C (suitably modified by \p Expr).
207  MachineInstrBuilder buildConstDbgValue(const Constant &C,
208  const MDNode *Variable,
209  const MDNode *Expr);
210 
211  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
212  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
213  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
214 
215  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
216  ///
217  /// G_FRAME_INDEX materializes the address of an alloca value or other
218  /// stack-based object.
219  ///
220  /// \pre setBasicBlock or setMI must have been called.
221  /// \pre \p Res must be a generic virtual register with pointer type.
222  ///
223  /// \return a MachineInstrBuilder for the newly created instruction.
224  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
225 
226  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
227  ///
228  /// G_GLOBAL_VALUE materializes the address of the specified global
229  /// into \p Res.
230  ///
231  /// \pre setBasicBlock or setMI must have been called.
232  /// \pre \p Res must be a generic virtual register with pointer type
233  /// in the same address space as \p GV.
234  ///
235  /// \return a MachineInstrBuilder for the newly created instruction.
236  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
237 
238 
239  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
240  ///
241  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
242  /// storing the resulting pointer in \p Res.
243  ///
244  /// \pre setBasicBlock or setMI must have been called.
245  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
246  /// type.
247  /// \pre \p Op1 must be a generic virtual register with scalar type.
248  ///
249  /// \return a MachineInstrBuilder for the newly created instruction.
250  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
251  unsigned Op1);
252 
253  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
254  ///
255  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
256  /// storing the resulting pointer in \p Res. If \p Value is zero then no
257  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
258  /// \p Res.
259  ///
260  /// \pre setBasicBlock or setMI must have been called.
261  /// \pre \p Op0 must be a generic virtual register with pointer type.
262  /// \pre \p ValueTy must be a scalar type.
263  /// \pre \p Res must be 0. This is to detect confusion between
264  /// materializeGEP() and buildGEP().
265  /// \post \p Res will either be a new generic virtual register of the same
266  /// type as \p Op0 or \p Op0 itself.
267  ///
268  /// \return a MachineInstrBuilder for the newly created instruction.
269  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
270  const LLT &ValueTy,
271  uint64_t Value);
272 
273  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
274  ///
275  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
276  /// pointer properties. This has the effect of rounding the address *down* to
277  /// a specified alignment in bits.
278  ///
279  /// \pre setBasicBlock or setMI must have been called.
280  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
281  /// type.
282  /// \pre \p NumBits must be an integer representing the number of low bits to
283  /// be cleared in \p Op0.
284  ///
285  /// \return a MachineInstrBuilder for the newly created instruction.
286  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
287  uint32_t NumBits);
288 
289  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
290  /// \p Op1, \p CarryIn
291  ///
292  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
293  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
294  /// arithmetic.
295  ///
296  /// \pre setBasicBlock or setMI must have been called.
297  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
298  /// with the same scalar type.
299  /// \pre \p CarryOut and \p CarryIn must be generic virtual
300  /// registers with the same scalar type (typically s1)
301  ///
302  /// \return The newly created instruction.
303  MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0,
304  unsigned Op1, unsigned CarryIn);
305 
306 
307  /// Build and insert \p Res = G_ANYEXT \p Op0
308  ///
309  /// G_ANYEXT produces a register of the specified width, with bits 0 to
310  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
311  /// (i.e. this is neither zero nor sign-extension). For a vector register,
312  /// each element is extended individually.
313  ///
314  /// \pre setBasicBlock or setMI must have been called.
315  /// \pre \p Res must be a generic virtual register with scalar or vector type.
316  /// \pre \p Op must be a generic virtual register with scalar or vector type.
317  /// \pre \p Op must be smaller than \p Res
318  ///
319  /// \return The newly created instruction.
320 
321  MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op);
322  template <typename DstType, typename ArgType>
323  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
324  return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
325  }
326 
327  /// Build and insert \p Res = G_SEXT \p Op
328  ///
329  /// G_SEXT produces a register of the specified width, with bits 0 to
330  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
331  /// high bit of \p Op (i.e. 2s-complement sign extended).
332  ///
333  /// \pre setBasicBlock or setMI must have been called.
334  /// \pre \p Res must be a generic virtual register with scalar or vector type.
335  /// \pre \p Op must be a generic virtual register with scalar or vector type.
336  /// \pre \p Op must be smaller than \p Res
337  ///
338  /// \return The newly created instruction.
339  template <typename DstType, typename ArgType>
340  MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) {
341  return buildSExt(getDestFromArg(Res), getRegFromArg(Arg));
342  }
343  MachineInstrBuilder buildSExt(unsigned Res, unsigned Op);
344 
345  /// Build and insert \p Res = G_ZEXT \p Op
346  ///
347  /// G_ZEXT produces a register of the specified width, with bits 0 to
348  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
349  /// register, each element is extended individually.
350  ///
351  /// \pre setBasicBlock or setMI must have been called.
352  /// \pre \p Res must be a generic virtual register with scalar or vector type.
353  /// \pre \p Op must be a generic virtual register with scalar or vector type.
354  /// \pre \p Op must be smaller than \p Res
355  ///
356  /// \return The newly created instruction.
357  template <typename DstType, typename ArgType>
358  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
359  return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
360  }
361  MachineInstrBuilder buildZExt(unsigned Res, unsigned Op);
362 
363  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
364  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
365  /// ///
366  /// \pre setBasicBlock or setMI must have been called.
367  /// \pre \p Res must be a generic virtual register with scalar or vector type.
368  /// \pre \p Op must be a generic virtual register with scalar or vector type.
369  ///
370  /// \return The newly created instruction.
371  template <typename DstTy, typename UseArgTy>
372  MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
373  return buildSExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
374  }
375  MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op);
376 
377  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
378  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
379  /// ///
380  /// \pre setBasicBlock or setMI must have been called.
381  /// \pre \p Res must be a generic virtual register with scalar or vector type.
382  /// \pre \p Op must be a generic virtual register with scalar or vector type.
383  ///
384  /// \return The newly created instruction.
385  template <typename DstTy, typename UseArgTy>
386  MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
387  return buildZExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
388  }
389  MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op);
390 
391  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
392  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
393  /// ///
394  /// \pre setBasicBlock or setMI must have been called.
395  /// \pre \p Res must be a generic virtual register with scalar or vector type.
396  /// \pre \p Op must be a generic virtual register with scalar or vector type.
397  ///
398  /// \return The newly created instruction.
399  template <typename DstTy, typename UseArgTy>
400  MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
401  return buildAnyExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
402  }
403  MachineInstrBuilder buildAnyExtOrTrunc(unsigned Res, unsigned Op);
404 
405  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
406  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
407  /// \p Op.
408  /// ///
409  /// \pre setBasicBlock or setMI must have been called.
410  /// \pre \p Res must be a generic virtual register with scalar or vector type.
411  /// \pre \p Op must be a generic virtual register with scalar or vector type.
412  ///
413  /// \return The newly created instruction.
414  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res,
415  unsigned Op);
416 
417  /// Build and insert an appropriate cast between two registers of equal size.
418  template <typename DstType, typename ArgType>
419  MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg) {
420  return buildCast(getDestFromArg(Res), getRegFromArg(Arg));
421  }
422  MachineInstrBuilder buildCast(unsigned Dst, unsigned Src);
423 
424  /// Build and insert G_BR \p Dest
425  ///
426  /// G_BR is an unconditional branch to \p Dest.
427  ///
428  /// \pre setBasicBlock or setMI must have been called.
429  ///
430  /// \return a MachineInstrBuilder for the newly created instruction.
431  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
432 
433  /// Build and insert G_BRCOND \p Tst, \p Dest
434  ///
435  /// G_BRCOND is a conditional branch to \p Dest.
436  ///
437  /// \pre setBasicBlock or setMI must have been called.
438  /// \pre \p Tst must be a generic virtual register with scalar
439  /// type. At the beginning of legalization, this will be a single
440  /// bit (s1). Targets with interesting flags registers may change
441  /// this. For a wider type, whether the branch is taken must only
442  /// depend on bit 0 (for now).
443  ///
444  /// \return The newly created instruction.
445  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
446 
447  /// Build and insert G_BRINDIRECT \p Tgt
448  ///
449  /// G_BRINDIRECT is an indirect branch to \p Tgt.
450  ///
451  /// \pre setBasicBlock or setMI must have been called.
452  /// \pre \p Tgt must be a generic virtual register with pointer type.
453  ///
454  /// \return a MachineInstrBuilder for the newly created instruction.
455  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
456 
457  /// Build and insert \p Res = G_CONSTANT \p Val
458  ///
459  /// G_CONSTANT is an integer constant with the specified size and value. \p
460  /// Val will be extended or truncated to the size of \p Reg.
461  ///
462  /// \pre setBasicBlock or setMI must have been called.
463  /// \pre \p Res must be a generic virtual register with scalar or pointer
464  /// type.
465  ///
466  /// \return The newly created instruction.
467  MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val);
468 
469  /// Build and insert \p Res = G_CONSTANT \p Val
470  ///
471  /// G_CONSTANT is an integer constant with the specified size and value.
472  ///
473  /// \pre setBasicBlock or setMI must have been called.
474  /// \pre \p Res must be a generic virtual register with scalar type.
475  ///
476  /// \return The newly created instruction.
477  MachineInstrBuilder buildConstant(unsigned Res, int64_t Val);
478 
479  template <typename DstType>
480  MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val) {
481  return buildConstant(getDestFromArg(Res), Val);
482  }
483  /// Build and insert \p Res = G_FCONSTANT \p Val
484  ///
485  /// G_FCONSTANT is a floating-point constant with the specified size and
486  /// value.
487  ///
488  /// \pre setBasicBlock or setMI must have been called.
489  /// \pre \p Res must be a generic virtual register with scalar type.
490  ///
491  /// \return The newly created instruction.
492  template <typename DstType>
493  MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val) {
494  return buildFConstant(getDestFromArg(Res), Val);
495  }
496  MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val);
497 
498  template <typename DstType>
499  MachineInstrBuilder buildFConstant(DstType &&Res, double Val) {
500  return buildFConstant(getDestFromArg(Res), Val);
501  }
502  MachineInstrBuilder buildFConstant(unsigned Res, double Val);
503 
504  /// Build and insert \p Res = COPY Op
505  ///
506  /// Register-to-register COPY sets \p Res to \p Op.
507  ///
508  /// \pre setBasicBlock or setMI must have been called.
509  ///
510  /// \return a MachineInstrBuilder for the newly created instruction.
511  MachineInstrBuilder buildCopy(unsigned Res, unsigned Op);
512  template <typename DstType, typename SrcType>
513  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514  return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515  }
516 
517  /// Build and insert `Res = G_LOAD Addr, MMO`.
518  ///
519  /// Loads the value stored at \p Addr. Puts the result in \p Res.
520  ///
521  /// \pre setBasicBlock or setMI must have been called.
522  /// \pre \p Res must be a generic virtual register.
523  /// \pre \p Addr must be a generic virtual register with pointer type.
524  ///
525  /// \return a MachineInstrBuilder for the newly created instruction.
526  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
527  MachineMemOperand &MMO);
528 
529  /// Build and insert `Res = <opcode> Addr, MMO`.
530  ///
531  /// Loads the value stored at \p Addr. Puts the result in \p Res.
532  ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res must be a generic virtual register.
535  /// \pre \p Addr must be a generic virtual register with pointer type.
536  ///
537  /// \return a MachineInstrBuilder for the newly created instruction.
538  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
539  unsigned Addr, MachineMemOperand &MMO);
540 
541  /// Build and insert `G_STORE Val, Addr, MMO`.
542  ///
543  /// Stores the value \p Val to \p Addr.
544  ///
545  /// \pre setBasicBlock or setMI must have been called.
546  /// \pre \p Val must be a generic virtual register.
547  /// \pre \p Addr must be a generic virtual register with pointer type.
548  ///
549  /// \return a MachineInstrBuilder for the newly created instruction.
550  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
551  MachineMemOperand &MMO);
552 
553  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
554  ///
555  /// \pre setBasicBlock or setMI must have been called.
556  /// \pre \p Res and \p Src must be generic virtual registers.
557  ///
558  /// \return a MachineInstrBuilder for the newly created instruction.
559  MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
560 
561  /// Build and insert \p Res = IMPLICIT_DEF.
562  template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
563  return buildUndef(getDestFromArg(Res));
564  }
565  MachineInstrBuilder buildUndef(unsigned Res);
566 
567  /// Build and insert instructions to put \p Ops together at the specified p
568  /// Indices to form a larger register.
569  ///
570  /// If the types of the input registers are uniform and cover the entirity of
571  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
572  /// followed by a sequence of G_INSERT instructions.
573  ///
574  /// \pre setBasicBlock or setMI must have been called.
575  /// \pre The final element of the sequence must not extend past the end of the
576  /// destination register.
577  /// \pre The bits defined by each Op (derived from index and scalar size) must
578  /// not overlap.
579  /// \pre \p Indices must be in ascending order of bit position.
580  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
581  ArrayRef<uint64_t> Indices);
582 
583  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
584  ///
585  /// G_MERGE_VALUES combines the input elements contiguously into a larger
586  /// register.
587  ///
588  /// \pre setBasicBlock or setMI must have been called.
589  /// \pre The entire register \p Res (and no more) must be covered by the input
590  /// registers.
591  /// \pre The type of all \p Ops registers must be identical.
592  ///
593  /// \return a MachineInstrBuilder for the newly created instruction.
594  MachineInstrBuilder buildMerge(unsigned Res, ArrayRef<unsigned> Ops);
595 
596  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
597  ///
598  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
599  ///
600  /// \pre setBasicBlock or setMI must have been called.
601  /// \pre The entire register \p Res (and no more) must be covered by the input
602  /// registers.
603  /// \pre The type of all \p Res registers must be identical.
604  ///
605  /// \return a MachineInstrBuilder for the newly created instruction.
606  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op);
607 
608  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
609  unsigned Op, unsigned Index);
610 
611  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
612  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
613  /// result register definition unless \p Reg is NoReg (== 0). The second
614  /// operand will be the intrinsic's ID.
615  ///
616  /// Callers are expected to add the required definitions and uses afterwards.
617  ///
618  /// \pre setBasicBlock or setMI must have been called.
619  ///
620  /// \return a MachineInstrBuilder for the newly created instruction.
621  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
622  bool HasSideEffects);
623 
624  /// Build and insert \p Res = G_FPTRUNC \p Op
625  ///
626  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
627  ///
628  /// \pre setBasicBlock or setMI must have been called.
629  /// \pre \p Res must be a generic virtual register with scalar or vector type.
630  /// \pre \p Op must be a generic virtual register with scalar or vector type.
631  /// \pre \p Res must be smaller than \p Op
632  ///
633  /// \return The newly created instruction.
634  template <typename DstType, typename SrcType>
635  MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src) {
636  return buildFPTrunc(getDestFromArg(Res), getRegFromArg(Src));
637  }
638  MachineInstrBuilder buildFPTrunc(unsigned Res, unsigned Op);
639 
640  /// Build and insert \p Res = G_TRUNC \p Op
641  ///
642  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
643  /// truncated independently before being packed into the destination.
644  ///
645  /// \pre setBasicBlock or setMI must have been called.
646  /// \pre \p Res must be a generic virtual register with scalar or vector type.
647  /// \pre \p Op must be a generic virtual register with scalar or vector type.
648  /// \pre \p Res must be smaller than \p Op
649  ///
650  /// \return The newly created instruction.
651  MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op);
652  template <typename DstType, typename SrcType>
653  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
654  return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
655  }
656 
657  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
658  ///
659  /// \pre setBasicBlock or setMI must have been called.
660 
661  /// \pre \p Res must be a generic virtual register with scalar or
662  /// vector type. Typically this starts as s1 or <N x s1>.
663  /// \pre \p Op0 and Op1 must be generic virtual registers with the
664  /// same number of elements as \p Res. If \p Res is a scalar,
665  /// \p Op0 must be either a scalar or pointer.
666  /// \pre \p Pred must be an integer predicate.
667  ///
668  /// \return a MachineInstrBuilder for the newly created instruction.
670  unsigned Res, unsigned Op0, unsigned Op1);
671  template <typename DstTy, typename... UseArgsTy>
673  UseArgsTy &&... UseArgs) {
674  return buildICmp(Pred, getDestFromArg(Dst), getRegFromArg(UseArgs)...);
675  }
676 
677  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
678  ///
679  /// \pre setBasicBlock or setMI must have been called.
680 
681  /// \pre \p Res must be a generic virtual register with scalar or
682  /// vector type. Typically this starts as s1 or <N x s1>.
683  /// \pre \p Op0 and Op1 must be generic virtual registers with the
684  /// same number of elements as \p Res (or scalar, if \p Res is
685  /// scalar).
686  /// \pre \p Pred must be a floating-point predicate.
687  ///
688  /// \return a MachineInstrBuilder for the newly created instruction.
690  unsigned Res, unsigned Op0, unsigned Op1);
691 
692  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
693  ///
694  /// \pre setBasicBlock or setMI must have been called.
695  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
696  /// with the same type.
697  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
698  /// vector type. If vector then it must have the same number of
699  /// elements as the other parameters.
700  ///
701  /// \return a MachineInstrBuilder for the newly created instruction.
702  MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst,
703  unsigned Op0, unsigned Op1);
704  template <typename DstTy, typename... UseArgsTy>
705  MachineInstrBuilder buildSelect(DstTy &&Dst, UseArgsTy &&... UseArgs) {
706  return buildSelect(getDestFromArg(Dst), getRegFromArg(UseArgs)...);
707  }
708 
709  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
710  /// \p Elt, \p Idx
711  ///
712  /// \pre setBasicBlock or setMI must have been called.
713  /// \pre \p Res and \p Val must be a generic virtual register
714  // with the same vector type.
715  /// \pre \p Elt and \p Idx must be a generic virtual register
716  /// with scalar type.
717  ///
718  /// \return The newly created instruction.
719  MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val,
720  unsigned Elt, unsigned Idx);
721 
722  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
723  ///
724  /// \pre setBasicBlock or setMI must have been called.
725  /// \pre \p Res must be a generic virtual register with scalar type.
726  /// \pre \p Val must be a generic virtual register with vector type.
727  /// \pre \p Idx must be a generic virtual register with scalar type.
728  ///
729  /// \return The newly created instruction.
730  MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val,
731  unsigned Idx);
732 
733  /// Build and insert `OldValRes<def>, SuccessRes<def> =
734  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
735  ///
736  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
737  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
738  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
739  ///
740  /// \pre setBasicBlock or setMI must have been called.
741  /// \pre \p OldValRes must be a generic virtual register of scalar type.
742  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
743  /// will be assigned 0 on failure and 1 on success.
744  /// \pre \p Addr must be a generic virtual register with pointer type.
745  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
746  /// registers of the same type.
747  ///
748  /// \return a MachineInstrBuilder for the newly created instruction.
750  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
751  unsigned Addr, unsigned CmpVal, unsigned NewVal,
752  MachineMemOperand &MMO);
753 
754  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
755  /// MMO`.
756  ///
757  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
758  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
759  /// Addr in \p Res.
760  ///
761  /// \pre setBasicBlock or setMI must have been called.
762  /// \pre \p OldValRes must be a generic virtual register of scalar type.
763  /// \pre \p Addr must be a generic virtual register with pointer type.
764  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
765  /// registers of the same type.
766  ///
767  /// \return a MachineInstrBuilder for the newly created instruction.
768  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
769  unsigned CmpVal, unsigned NewVal,
770  MachineMemOperand &MMO);
771 
772  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
773  ///
774  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
775  /// original value from \p Addr in \p OldValRes. The modification is
776  /// determined by the opcode.
777  ///
778  /// \pre setBasicBlock or setMI must have been called.
779  /// \pre \p OldValRes must be a generic virtual register.
780  /// \pre \p Addr must be a generic virtual register with pointer type.
781  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
782  /// same type.
783  ///
784  /// \return a MachineInstrBuilder for the newly created instruction.
785  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
786  unsigned Addr, unsigned Val,
787  MachineMemOperand &MMO);
788 
789  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
790  ///
791  /// Atomically replace the value at \p Addr with \p Val. Puts the original
792  /// value from \p Addr in \p OldValRes.
793  ///
794  /// \pre setBasicBlock or setMI must have been called.
795  /// \pre \p OldValRes must be a generic virtual register.
796  /// \pre \p Addr must be a generic virtual register with pointer type.
797  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
798  /// same type.
799  ///
800  /// \return a MachineInstrBuilder for the newly created instruction.
801  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
802  unsigned Val, MachineMemOperand &MMO);
803 
804  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
805  ///
806  /// Atomically replace the value at \p Addr with the addition of \p Val and
807  /// the original value. Puts the original value from \p Addr in \p OldValRes.
808  ///
809  /// \pre setBasicBlock or setMI must have been called.
810  /// \pre \p OldValRes must be a generic virtual register.
811  /// \pre \p Addr must be a generic virtual register with pointer type.
812  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
813  /// same type.
814  ///
815  /// \return a MachineInstrBuilder for the newly created instruction.
816  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
817  unsigned Val, MachineMemOperand &MMO);
818 
819  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
820  ///
821  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
822  /// the original value. Puts the original value from \p Addr in \p OldValRes.
823  ///
824  /// \pre setBasicBlock or setMI must have been called.
825  /// \pre \p OldValRes must be a generic virtual register.
826  /// \pre \p Addr must be a generic virtual register with pointer type.
827  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
828  /// same type.
829  ///
830  /// \return a MachineInstrBuilder for the newly created instruction.
831  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
832  unsigned Val, MachineMemOperand &MMO);
833 
834  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
835  ///
836  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
837  /// the original value. Puts the original value from \p Addr in \p OldValRes.
838  ///
839  /// \pre setBasicBlock or setMI must have been called.
840  /// \pre \p OldValRes must be a generic virtual register.
841  /// \pre \p Addr must be a generic virtual register with pointer type.
842  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
843  /// same type.
844  ///
845  /// \return a MachineInstrBuilder for the newly created instruction.
846  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
847  unsigned Val, MachineMemOperand &MMO);
848 
849  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
850  ///
851  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
852  /// and the original value. Puts the original value from \p Addr in \p
853  /// OldValRes.
854  ///
855  /// \pre setBasicBlock or setMI must have been called.
856  /// \pre \p OldValRes must be a generic virtual register.
857  /// \pre \p Addr must be a generic virtual register with pointer type.
858  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
859  /// same type.
860  ///
861  /// \return a MachineInstrBuilder for the newly created instruction.
862  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
863  unsigned Val, MachineMemOperand &MMO);
864 
865  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
866  ///
867  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
868  /// the original value. Puts the original value from \p Addr in \p OldValRes.
869  ///
870  /// \pre setBasicBlock or setMI must have been called.
871  /// \pre \p OldValRes must be a generic virtual register.
872  /// \pre \p Addr must be a generic virtual register with pointer type.
873  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
874  /// same type.
875  ///
876  /// \return a MachineInstrBuilder for the newly created instruction.
877  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
878  unsigned Val, MachineMemOperand &MMO);
879 
880  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
881  ///
882  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
883  /// the original value. Puts the original value from \p Addr in \p OldValRes.
884  ///
885  /// \pre setBasicBlock or setMI must have been called.
886  /// \pre \p OldValRes must be a generic virtual register.
887  /// \pre \p Addr must be a generic virtual register with pointer type.
888  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
889  /// same type.
890  ///
891  /// \return a MachineInstrBuilder for the newly created instruction.
892  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
893  unsigned Val, MachineMemOperand &MMO);
894 
895  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
896  ///
897  /// Atomically replace the value at \p Addr with the signed maximum of \p
898  /// Val and the original value. Puts the original value from \p Addr in \p
899  /// OldValRes.
900  ///
901  /// \pre setBasicBlock or setMI must have been called.
902  /// \pre \p OldValRes must be a generic virtual register.
903  /// \pre \p Addr must be a generic virtual register with pointer type.
904  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
905  /// same type.
906  ///
907  /// \return a MachineInstrBuilder for the newly created instruction.
908  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
909  unsigned Val, MachineMemOperand &MMO);
910 
911  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
912  ///
913  /// Atomically replace the value at \p Addr with the signed minimum of \p
914  /// Val and the original value. Puts the original value from \p Addr in \p
915  /// OldValRes.
916  ///
917  /// \pre setBasicBlock or setMI must have been called.
918  /// \pre \p OldValRes must be a generic virtual register.
919  /// \pre \p Addr must be a generic virtual register with pointer type.
920  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
921  /// same type.
922  ///
923  /// \return a MachineInstrBuilder for the newly created instruction.
924  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
925  unsigned Val, MachineMemOperand &MMO);
926 
927  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
928  ///
929  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
930  /// Val and the original value. Puts the original value from \p Addr in \p
931  /// OldValRes.
932  ///
933  /// \pre setBasicBlock or setMI must have been called.
934  /// \pre \p OldValRes must be a generic virtual register.
935  /// \pre \p Addr must be a generic virtual register with pointer type.
936  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
937  /// same type.
938  ///
939  /// \return a MachineInstrBuilder for the newly created instruction.
940  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
941  unsigned Val, MachineMemOperand &MMO);
942 
943  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
944  ///
945  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
946  /// Val and the original value. Puts the original value from \p Addr in \p
947  /// OldValRes.
948  ///
949  /// \pre setBasicBlock or setMI must have been called.
950  /// \pre \p OldValRes must be a generic virtual register.
951  /// \pre \p Addr must be a generic virtual register with pointer type.
952  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
953  /// same type.
954  ///
955  /// \return a MachineInstrBuilder for the newly created instruction.
956  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
957  unsigned Val, MachineMemOperand &MMO);
958 
959  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
960  ///
961  /// G_BLOCK_ADDR computes the address of a basic block.
962  ///
963  /// \pre setBasicBlock or setMI must have been called.
964  /// \pre \p Res must be a generic virtual register of a pointer type.
965  ///
966  /// \return The newly created instruction.
967  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
968 };
969 
970 /// A CRTP class that contains methods for building instructions that can
971 /// be constant folded. MachineIRBuilders that want to inherit from this will
972 /// need to implement buildBinaryOp (for constant folding binary ops).
973 /// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform
974 /// additional folding for Opc.
975 template <typename Base>
977  Base &base() { return static_cast<Base &>(*this); }
978 
979 public:
981  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
982  ///
983  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
984  /// truncated to their width.
985  ///
986  /// \pre setBasicBlock or setMI must have been called.
987  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
988  /// with the same (scalar or vector) type).
989  ///
990  /// \return a MachineInstrBuilder for the newly created instruction.
991 
992  MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) {
993  return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1);
994  }
995  template <typename DstTy, typename... UseArgsTy>
996  MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
997  unsigned Res = base().getDestFromArg(Ty);
998  return base().buildAdd(Res, (base().getRegFromArg(UseArgs))...);
999  }
1000 
1001  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1002  ///
1003  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1004  /// truncated to their width.
1005  ///
1006  /// \pre setBasicBlock or setMI must have been called.
1007  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1008  /// with the same (scalar or vector) type).
1009  ///
1010  /// \return a MachineInstrBuilder for the newly created instruction.
1011 
1012  MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) {
1013  return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1);
1014  }
1015  template <typename DstTy, typename... UseArgsTy>
1016  MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1017  unsigned Res = base().getDestFromArg(Ty);
1018  return base().buildSub(Res, (base().getRegFromArg(UseArgs))...);
1019  }
1020 
1021  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1022  ///
1023  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1024  /// truncated to their width.
1025  ///
1026  /// \pre setBasicBlock or setMI must have been called.
1027  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1028  /// with the same (scalar or vector) type).
1029  ///
1030  /// \return a MachineInstrBuilder for the newly created instruction.
1031  MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) {
1032  return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1);
1033  }
1034  template <typename DstTy, typename... UseArgsTy>
1035  MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1036  unsigned Res = base().getDestFromArg(Ty);
1037  return base().buildMul(Res, (base().getRegFromArg(UseArgs))...);
1038  }
1039 
1040  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1041  ///
1042  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1043  /// Op1.
1044  ///
1045  /// \pre setBasicBlock or setMI must have been called.
1046  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1047  /// with the same (scalar or vector) type).
1048  ///
1049  /// \return a MachineInstrBuilder for the newly created instruction.
1050 
1051  MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) {
1052  return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1);
1053  }
1054  template <typename DstTy, typename... UseArgsTy>
1055  MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1056  unsigned Res = base().getDestFromArg(Ty);
1057  return base().buildAnd(Res, (base().getRegFromArg(UseArgs))...);
1058  }
1059 
1060  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1061  ///
1062  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1063  /// Op1.
1064  ///
1065  /// \pre setBasicBlock or setMI must have been called.
1066  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1067  /// with the same (scalar or vector) type).
1068  ///
1069  /// \return a MachineInstrBuilder for the newly created instruction.
1070  MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) {
1071  return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1);
1072  }
1073  template <typename DstTy, typename... UseArgsTy>
1074  MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1075  unsigned Res = base().getDestFromArg(Ty);
1076  return base().buildOr(Res, (base().getRegFromArg(UseArgs))...);
1077  }
1078 };
1079 
1080 class MachineIRBuilder : public FoldableInstructionsBuilder<MachineIRBuilder> {
1081 public:
1084  MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst,
1085  unsigned Src0, unsigned Src1) {
1086  validateBinaryOp(Dst, Src0, Src1);
1087  return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1);
1088  }
1090  /// DAG like Generic method for building arbitrary instructions as above.
1091  /// \Opc opcode for the instruction.
1092  /// \Ty Either LLT/TargetRegisterClass/unsigned types for Dst
1093  /// \Args Variadic list of uses of types(unsigned/MachineInstrBuilder)
1094  /// Uses of type MachineInstrBuilder will perform
1095  /// getOperand(0).getReg() to convert to register.
1096  template <typename DstTy, typename... UseArgsTy>
1097  MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty,
1098  UseArgsTy &&... Args) {
1099  auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100  addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101  return MIB;
1102  }
1103 };
1104 
1105 } // End namespace llvm.
1106 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_OR Op0, Op1.
uint64_t CallInst * C
MachineIRBuilderBase()=default
Some constructors for easy use.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildUndef(DstType &&Res)
Build and insert Res = IMPLICIT_DEF.
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_SEXT Op.
A CRTP class that contains methods for building instructions that can be constant folded...
unsigned Reg
void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args)
MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src)
Build and insert Res = G_FPTRUNC Op.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:864
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs)
The address of a basic block.
Definition: Constants.h:836
A description of a memory reference used in the backend.
std::function< void(MachineInstr *)> InsertedInstr
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineIRBuilderBase(MachineInstr &MI)
MachineBasicBlock::iterator II
MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src)
MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg)
MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_ZEXT Op.
unsigned getRegFromArg(unsigned Reg)
TargetInstrInfo - Interface to description of machine instruction set.
MachineIRBuilderBase(MachineFunction &MF)
MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs)
const TargetInstrInfo & getTII()
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
unsigned getDestFromArg(const TargetRegisterClass *RC)
MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs)
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg)
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:657
DebugLoc DL
Debug location to be set to any instruction we create.
const DebugLoc & getDL()
Getter for DebugLoc.
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, DstTy &&Dst, UseArgsTy &&... UseArgs)
void addUsesFromArgs(MachineInstrBuilder &MIB)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
unsigned getDestFromArg(unsigned Reg)
MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
MachineIRBuilderBase(const MachineIRBuilderState &BState)
MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst, unsigned Src0, unsigned Src1)
MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_ADD Op0, Op1.
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
unsigned getDestFromArg(LLT Ty)
MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineInstrBuilder buildFConstant(DstType &&Res, double Val)
MachineInstrBuilder buildSelect(DstTy &&Dst, UseArgsTy &&... UseArgs)
MachineRegisterInfo * getMRI()
Getter for MRI.
unsigned getRegFromArg(const MachineInstrBuilder &MIB)
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg)
Build and insert an appropriate cast between two registers of equal size.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs)
LLVM Value Representation.
Definition: Value.h:73
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1373
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
print Print MemDeps of function
IRTranslator LLVM IR MI
MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_MUL Op0, Op1.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs)
void addUseFromArg(MachineInstrBuilder &MIB, const MachineInstrBuilder &UseMIB)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val)
Helper class to build MachineInstr.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.