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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
70  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
71  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
72  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
73 
75  switch (Ty) {
76  case DstType::Ty_Reg:
77  MIB.addDef(Reg);
78  break;
79  case DstType::Ty_LLT:
80  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
81  break;
82  case DstType::Ty_RC:
83  MIB.addDef(MRI.createVirtualRegister(RC));
84  break;
85  }
86  }
87 
89  switch (Ty) {
90  case DstType::Ty_RC:
91  return LLT{};
92  case DstType::Ty_LLT:
93  return LLTTy;
94  case DstType::Ty_Reg:
95  return MRI.getType(Reg);
96  }
97  llvm_unreachable("Unrecognised DstOp::DstType enum");
98  }
99 
100  Register getReg() const {
101  assert(Ty == DstType::Ty_Reg && "Not a register");
102  return Reg;
103  }
104 
106  switch (Ty) {
107  case DstType::Ty_RC:
108  return RC;
109  default:
110  llvm_unreachable("Not a RC Operand");
111  }
112  }
113 
114  DstType getDstOpKind() const { return Ty; }
115 
116 private:
117  DstType Ty;
118 };
119 
120 class SrcOp {
121  union {
125  int64_t Imm;
126  };
127 
128 public:
129  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
130  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
132  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
133  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
134  /// Use of registers held in unsigned integer variables (or more rarely signed
135  /// integers) is no longer permitted to avoid ambiguity with upcoming support
136  /// for immediates.
137  SrcOp(unsigned) = delete;
138  SrcOp(int) = delete;
139  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
141 
142  void addSrcToMIB(MachineInstrBuilder &MIB) const {
143  switch (Ty) {
144  case SrcType::Ty_Predicate:
145  MIB.addPredicate(Pred);
146  break;
147  case SrcType::Ty_Reg:
148  MIB.addUse(Reg);
149  break;
150  case SrcType::Ty_MIB:
151  MIB.addUse(SrcMIB->getOperand(0).getReg());
152  break;
153  case SrcType::Ty_Imm:
154  MIB.addImm(Imm);
155  break;
156  }
157  }
158 
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  case SrcType::Ty_Imm:
163  llvm_unreachable("Not a register operand");
164  case SrcType::Ty_Reg:
165  return MRI.getType(Reg);
166  case SrcType::Ty_MIB:
167  return MRI.getType(SrcMIB->getOperand(0).getReg());
168  }
169  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
170  }
171 
172  Register getReg() const {
173  switch (Ty) {
174  case SrcType::Ty_Predicate:
175  case SrcType::Ty_Imm:
176  llvm_unreachable("Not a register operand");
177  case SrcType::Ty_Reg:
178  return Reg;
179  case SrcType::Ty_MIB:
180  return SrcMIB->getOperand(0).getReg();
181  }
182  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
183  }
184 
186  switch (Ty) {
187  case SrcType::Ty_Predicate:
188  return Pred;
189  default:
190  llvm_unreachable("Not a register operand");
191  }
192  }
193 
194  int64_t getImm() const {
195  switch (Ty) {
196  case SrcType::Ty_Imm:
197  return Imm;
198  default:
199  llvm_unreachable("Not an immediate");
200  }
201  }
202 
203  SrcType getSrcOpKind() const { return Ty; }
204 
205 private:
206  SrcType Ty;
207 };
208 
209 class FlagsOp {
210  Optional<unsigned> Flags;
211 
212 public:
213  explicit FlagsOp(unsigned F) : Flags(F) {}
214  FlagsOp() : Flags(None) {}
215  Optional<unsigned> getFlags() const { return Flags; }
216 };
217 /// Helper class to build MachineInstr.
218 /// It keeps internally the insertion point and debug location for all
219 /// the new instructions we want to create.
220 /// This information can be modify via the related setters.
222 
223  MachineIRBuilderState State;
224 
225 protected:
226  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
227 
228  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
229  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
230 
231  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
232  const LLT &Op1Ty);
233  void recordInsertion(MachineInstr *MI) const;
234 
235 public:
236  /// Some constructors for easy use.
237  MachineIRBuilder() = default;
240  setInstr(MI);
241  }
242 
243  virtual ~MachineIRBuilder() = default;
244 
245  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
246 
248  assert(State.TII && "TargetInstrInfo is not set");
249  return *State.TII;
250  }
251 
252  /// Getter for the function we currently build.
254  assert(State.MF && "MachineFunction is not set");
255  return *State.MF;
256  }
257 
258  const MachineFunction &getMF() const {
259  assert(State.MF && "MachineFunction is not set");
260  return *State.MF;
261  }
262 
263  const DataLayout &getDataLayout() const {
264  return getMF().getFunction().getParent()->getDataLayout();
265  }
266 
267  /// Getter for DebugLoc
268  const DebugLoc &getDL() { return State.DL; }
269 
270  /// Getter for MRI
271  MachineRegisterInfo *getMRI() { return State.MRI; }
272  const MachineRegisterInfo *getMRI() const { return State.MRI; }
273 
274  /// Getter for the State
275  MachineIRBuilderState &getState() { return State; }
276 
277  /// Getter for the basic block we currently build.
278  const MachineBasicBlock &getMBB() const {
279  assert(State.MBB && "MachineBasicBlock is not set");
280  return *State.MBB;
281  }
282 
284  return const_cast<MachineBasicBlock &>(
285  const_cast<const MachineIRBuilder *>(this)->getMBB());
286  }
287 
288  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
289  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
290 
291  /// Current insertion point for new instructions.
293 
294  /// Set the insertion point before the specified position.
295  /// \pre MBB must be in getMF().
296  /// \pre II must be a valid iterator in MBB.
298  /// @}
299 
300  void setCSEInfo(GISelCSEInfo *Info);
301 
302  /// \name Setters for the insertion point.
303  /// @{
304  /// Set the MachineFunction where to build instructions.
305  void setMF(MachineFunction &MF);
306 
307  /// Set the insertion point to the end of \p MBB.
308  /// \pre \p MBB must be contained by getMF().
309  void setMBB(MachineBasicBlock &MBB);
310 
311  /// Set the insertion point to before MI.
312  /// \pre MI must be in getMF().
313  void setInstr(MachineInstr &MI);
314  /// @}
315 
316  void setChangeObserver(GISelChangeObserver &Observer);
317  void stopObservingChanges();
318  /// @}
319 
320  /// Set the debug location to \p DL for all the next build instructions.
321  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
322 
323  /// Get the current instruction's debug location.
324  DebugLoc getDebugLoc() { return State.DL; }
325 
326  /// Build and insert <empty> = \p Opcode <empty>.
327  /// The insertion point is the one set by the last call of either
328  /// setBasicBlock or setMI.
329  ///
330  /// \pre setBasicBlock or setMI must have been called.
331  ///
332  /// \return a MachineInstrBuilder for the newly created instruction.
333  MachineInstrBuilder buildInstr(unsigned Opcode);
334 
335  /// Build but don't insert <empty> = \p Opcode <empty>.
336  ///
337  /// \pre setMF, setBasicBlock or setMI must have been called.
338  ///
339  /// \return a MachineInstrBuilder for the newly created instruction.
340  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
341 
342  /// Insert an existing instruction at the insertion point.
343  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
344 
345  /// Build and insert a DBG_VALUE instruction expressing the fact that the
346  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
347  MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
348  const MDNode *Expr);
349 
350  /// Build and insert a DBG_VALUE instruction expressing the fact that the
351  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
352  /// Expr).
353  MachineInstrBuilder buildIndirectDbgValue(Register Reg,
354  const MDNode *Variable,
355  const MDNode *Expr);
356 
357  /// Build and insert a DBG_VALUE instruction expressing the fact that the
358  /// associated \p Variable lives in the stack slot specified by \p FI
359  /// (suitably modified by \p Expr).
360  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
361  const MDNode *Expr);
362 
363  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
364  /// given by \p C (suitably modified by \p Expr).
365  MachineInstrBuilder buildConstDbgValue(const Constant &C,
366  const MDNode *Variable,
367  const MDNode *Expr);
368 
369  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
370  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
371  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
372 
373  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
374  ///
375  /// G_FRAME_INDEX materializes the address of an alloca value or other
376  /// stack-based object.
377  ///
378  /// \pre setBasicBlock or setMI must have been called.
379  /// \pre \p Res must be a generic virtual register with pointer type.
380  ///
381  /// \return a MachineInstrBuilder for the newly created instruction.
382  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
383 
384  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
385  ///
386  /// G_GLOBAL_VALUE materializes the address of the specified global
387  /// into \p Res.
388  ///
389  /// \pre setBasicBlock or setMI must have been called.
390  /// \pre \p Res must be a generic virtual register with pointer type
391  /// in the same address space as \p GV.
392  ///
393  /// \return a MachineInstrBuilder for the newly created instruction.
394  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
395 
396  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
397  ///
398  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
399  /// storing the resulting pointer in \p Res.
400  ///
401  /// \pre setBasicBlock or setMI must have been called.
402  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
403  /// type.
404  /// \pre \p Op1 must be a generic virtual register with scalar type.
405  ///
406  /// \return a MachineInstrBuilder for the newly created instruction.
407  MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0,
408  const SrcOp &Op1);
409 
410  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
411  ///
412  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
413  /// storing the resulting pointer in \p Res. If \p Value is zero then no
414  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
415  /// \p Res.
416  ///
417  /// \pre setBasicBlock or setMI must have been called.
418  /// \pre \p Op0 must be a generic virtual register with pointer type.
419  /// \pre \p ValueTy must be a scalar type.
420  /// \pre \p Res must be 0. This is to detect confusion between
421  /// materializeGEP() and buildGEP().
422  /// \post \p Res will either be a new generic virtual register of the same
423  /// type as \p Op0 or \p Op0 itself.
424  ///
425  /// \return a MachineInstrBuilder for the newly created instruction.
426  Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
427  const LLT &ValueTy,
428  uint64_t Value);
429 
430  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
431  ///
432  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
433  /// pointer properties. This has the effect of rounding the address *down* to
434  /// a specified alignment in bits.
435  ///
436  /// \pre setBasicBlock or setMI must have been called.
437  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
438  /// type.
439  /// \pre \p NumBits must be an integer representing the number of low bits to
440  /// be cleared in \p Op0.
441  ///
442  /// \return a MachineInstrBuilder for the newly created instruction.
443  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
444  uint32_t NumBits);
445 
446  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
447  ///
448  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
449  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
450  ///
451  /// \pre setBasicBlock or setMI must have been called.
452  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
453  /// same scalar type.
454  ////\pre \p CarryOut must be generic virtual register with scalar type
455  ///(typically s1)
456  ///
457  /// \return The newly created instruction.
458  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
459  const SrcOp &Op0, const SrcOp &Op1);
460 
461  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
462  /// \p Op1, \p CarryIn
463  ///
464  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
465  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
466  /// arithmetic.
467  ///
468  /// \pre setBasicBlock or setMI must have been called.
469  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
470  /// with the same scalar type.
471  /// \pre \p CarryOut and \p CarryIn must be generic virtual
472  /// registers with the same scalar type (typically s1)
473  ///
474  /// \return The newly created instruction.
475  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
476  const SrcOp &Op0, const SrcOp &Op1,
477  const SrcOp &CarryIn);
478 
479  /// Build and insert \p Res = G_ANYEXT \p Op0
480  ///
481  /// G_ANYEXT produces a register of the specified width, with bits 0 to
482  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
483  /// (i.e. this is neither zero nor sign-extension). For a vector register,
484  /// each element is extended individually.
485  ///
486  /// \pre setBasicBlock or setMI must have been called.
487  /// \pre \p Res must be a generic virtual register with scalar or vector type.
488  /// \pre \p Op must be a generic virtual register with scalar or vector type.
489  /// \pre \p Op must be smaller than \p Res
490  ///
491  /// \return The newly created instruction.
492 
493  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
494 
495  /// Build and insert \p Res = G_SEXT \p Op
496  ///
497  /// G_SEXT produces a register of the specified width, with bits 0 to
498  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
499  /// high bit of \p Op (i.e. 2s-complement sign extended).
500  ///
501  /// \pre setBasicBlock or setMI must have been called.
502  /// \pre \p Res must be a generic virtual register with scalar or vector type.
503  /// \pre \p Op must be a generic virtual register with scalar or vector type.
504  /// \pre \p Op must be smaller than \p Res
505  ///
506  /// \return The newly created instruction.
507  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
508 
509  /// Build and insert a G_PTRTOINT instruction.
510  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
511  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
512  }
513 
514  /// Build and insert a G_INTTOPTR instruction.
515  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
516  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
517  }
518 
519  /// Build and insert \p Dst = G_BITCAST \p Src
520  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
521  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
522  }
523 
524  /// \return The opcode of the extension the target wants to use for boolean
525  /// values.
526  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
527 
528  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
529  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
530  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
531  bool IsFP);
532 
533  /// Build and insert \p Res = G_ZEXT \p Op
534  ///
535  /// G_ZEXT produces a register of the specified width, with bits 0 to
536  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
537  /// register, each element is extended individually.
538  ///
539  /// \pre setBasicBlock or setMI must have been called.
540  /// \pre \p Res must be a generic virtual register with scalar or vector type.
541  /// \pre \p Op must be a generic virtual register with scalar or vector type.
542  /// \pre \p Op must be smaller than \p Res
543  ///
544  /// \return The newly created instruction.
545  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
546 
547  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
548  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
549  /// ///
550  /// \pre setBasicBlock or setMI must have been called.
551  /// \pre \p Res must be a generic virtual register with scalar or vector type.
552  /// \pre \p Op must be a generic virtual register with scalar or vector type.
553  ///
554  /// \return The newly created instruction.
555  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
556 
557  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
558  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
559  /// ///
560  /// \pre setBasicBlock or setMI must have been called.
561  /// \pre \p Res must be a generic virtual register with scalar or vector type.
562  /// \pre \p Op must be a generic virtual register with scalar or vector type.
563  ///
564  /// \return The newly created instruction.
565  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
566 
567  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
568  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
569  /// ///
570  /// \pre setBasicBlock or setMI must have been called.
571  /// \pre \p Res must be a generic virtual register with scalar or vector type.
572  /// \pre \p Op must be a generic virtual register with scalar or vector type.
573  ///
574  /// \return The newly created instruction.
575  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
576 
577  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
578  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
579  /// \p Op.
580  /// ///
581  /// \pre setBasicBlock or setMI must have been called.
582  /// \pre \p Res must be a generic virtual register with scalar or vector type.
583  /// \pre \p Op must be a generic virtual register with scalar or vector type.
584  ///
585  /// \return The newly created instruction.
586  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
587  const SrcOp &Op);
588 
589  /// Build and insert an appropriate cast between two registers of equal size.
590  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
591 
592  /// Build and insert G_BR \p Dest
593  ///
594  /// G_BR is an unconditional branch to \p Dest.
595  ///
596  /// \pre setBasicBlock or setMI must have been called.
597  ///
598  /// \return a MachineInstrBuilder for the newly created instruction.
599  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
600 
601  /// Build and insert G_BRCOND \p Tst, \p Dest
602  ///
603  /// G_BRCOND is a conditional branch to \p Dest.
604  ///
605  /// \pre setBasicBlock or setMI must have been called.
606  /// \pre \p Tst must be a generic virtual register with scalar
607  /// type. At the beginning of legalization, this will be a single
608  /// bit (s1). Targets with interesting flags registers may change
609  /// this. For a wider type, whether the branch is taken must only
610  /// depend on bit 0 (for now).
611  ///
612  /// \return The newly created instruction.
613  MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
614 
615  /// Build and insert G_BRINDIRECT \p Tgt
616  ///
617  /// G_BRINDIRECT is an indirect branch to \p Tgt.
618  ///
619  /// \pre setBasicBlock or setMI must have been called.
620  /// \pre \p Tgt must be a generic virtual register with pointer type.
621  ///
622  /// \return a MachineInstrBuilder for the newly created instruction.
623  MachineInstrBuilder buildBrIndirect(Register Tgt);
624 
625  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
626  ///
627  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
628  /// jump table index \p JTI and index \p IndexReg
629  ///
630  /// \pre setBasicBlock or setMI must have been called.
631  /// \pre \p TablePtr must be a generic virtual register with pointer type.
632  /// \pre \p JTI must be be a jump table index.
633  /// \pre \p IndexReg must be a generic virtual register with pointer type.
634  ///
635  /// \return a MachineInstrBuilder for the newly created instruction.
636  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
637  Register IndexReg);
638 
639  /// Build and insert \p Res = G_CONSTANT \p Val
640  ///
641  /// G_CONSTANT is an integer constant with the specified size and value. \p
642  /// Val will be extended or truncated to the size of \p Reg.
643  ///
644  /// \pre setBasicBlock or setMI must have been called.
645  /// \pre \p Res must be a generic virtual register with scalar or pointer
646  /// type.
647  ///
648  /// \return The newly created instruction.
649  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
650  const ConstantInt &Val);
651 
652  /// Build and insert \p Res = G_CONSTANT \p Val
653  ///
654  /// G_CONSTANT is an integer constant with the specified size and value.
655  ///
656  /// \pre setBasicBlock or setMI must have been called.
657  /// \pre \p Res must be a generic virtual register with scalar type.
658  ///
659  /// \return The newly created instruction.
660  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
661  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
662 
663  /// Build and insert \p Res = G_FCONSTANT \p Val
664  ///
665  /// G_FCONSTANT is a floating-point constant with the specified size and
666  /// value.
667  ///
668  /// \pre setBasicBlock or setMI must have been called.
669  /// \pre \p Res must be a generic virtual register with scalar type.
670  ///
671  /// \return The newly created instruction.
672  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
673  const ConstantFP &Val);
674 
675  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
676  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
677 
678  /// Build and insert \p Res = COPY Op
679  ///
680  /// Register-to-register COPY sets \p Res to \p Op.
681  ///
682  /// \pre setBasicBlock or setMI must have been called.
683  ///
684  /// \return a MachineInstrBuilder for the newly created instruction.
685  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
686 
687  /// Build and insert `Res = G_LOAD Addr, MMO`.
688  ///
689  /// Loads the value stored at \p Addr. Puts the result in \p Res.
690  ///
691  /// \pre setBasicBlock or setMI must have been called.
692  /// \pre \p Res must be a generic virtual register.
693  /// \pre \p Addr must be a generic virtual register with pointer type.
694  ///
695  /// \return a MachineInstrBuilder for the newly created instruction.
696  MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
697  MachineMemOperand &MMO);
698 
699  /// Build and insert `Res = <opcode> Addr, MMO`.
700  ///
701  /// Loads the value stored at \p Addr. Puts the result in \p Res.
702  ///
703  /// \pre setBasicBlock or setMI must have been called.
704  /// \pre \p Res must be a generic virtual register.
705  /// \pre \p Addr must be a generic virtual register with pointer type.
706  ///
707  /// \return a MachineInstrBuilder for the newly created instruction.
708  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
709  const SrcOp &Addr, MachineMemOperand &MMO);
710 
711  /// Build and insert `G_STORE Val, Addr, MMO`.
712  ///
713  /// Stores the value \p Val to \p Addr.
714  ///
715  /// \pre setBasicBlock or setMI must have been called.
716  /// \pre \p Val must be a generic virtual register.
717  /// \pre \p Addr must be a generic virtual register with pointer type.
718  ///
719  /// \return a MachineInstrBuilder for the newly created instruction.
720  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
721  MachineMemOperand &MMO);
722 
723  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
724  ///
725  /// \pre setBasicBlock or setMI must have been called.
726  /// \pre \p Res and \p Src must be generic virtual registers.
727  ///
728  /// \return a MachineInstrBuilder for the newly created instruction.
729  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
730 
731  /// Build and insert \p Res = IMPLICIT_DEF.
732  MachineInstrBuilder buildUndef(const DstOp &Res);
733 
734  /// Build and insert instructions to put \p Ops together at the specified p
735  /// Indices to form a larger register.
736  ///
737  /// If the types of the input registers are uniform and cover the entirity of
738  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
739  /// followed by a sequence of G_INSERT instructions.
740  ///
741  /// \pre setBasicBlock or setMI must have been called.
742  /// \pre The final element of the sequence must not extend past the end of the
743  /// destination register.
744  /// \pre The bits defined by each Op (derived from index and scalar size) must
745  /// not overlap.
746  /// \pre \p Indices must be in ascending order of bit position.
747  void buildSequence(Register Res, ArrayRef<Register> Ops,
748  ArrayRef<uint64_t> Indices);
749 
750  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
751  ///
752  /// G_MERGE_VALUES combines the input elements contiguously into a larger
753  /// register.
754  ///
755  /// \pre setBasicBlock or setMI must have been called.
756  /// \pre The entire register \p Res (and no more) must be covered by the input
757  /// registers.
758  /// \pre The type of all \p Ops registers must be identical.
759  ///
760  /// \return a MachineInstrBuilder for the newly created instruction.
761  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
762 
763  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
764  ///
765  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
766  ///
767  /// \pre setBasicBlock or setMI must have been called.
768  /// \pre The entire register \p Res (and no more) must be covered by the input
769  /// registers.
770  /// \pre The type of all \p Res registers must be identical.
771  ///
772  /// \return a MachineInstrBuilder for the newly created instruction.
773  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
774  MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
775 
776  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
777  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
778 
779  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
780  ///
781  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
782  /// \pre setBasicBlock or setMI must have been called.
783  /// \pre The entire register \p Res (and no more) must be covered by the
784  /// input scalar registers.
785  /// \pre The type of all \p Ops registers must be identical.
786  ///
787  /// \return a MachineInstrBuilder for the newly created instruction.
788  MachineInstrBuilder buildBuildVector(const DstOp &Res,
789  ArrayRef<Register> Ops);
790 
791  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
792  /// the number of elements
793  MachineInstrBuilder buildSplatVector(const DstOp &Res,
794  const SrcOp &Src);
795 
796  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
797  ///
798  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
799  /// which have types larger than the destination vector element type, and
800  /// truncates the values to fit.
801  ///
802  /// If the operands given are already the same size as the vector elt type,
803  /// then this method will instead create a G_BUILD_VECTOR instruction.
804  ///
805  /// \pre setBasicBlock or setMI must have been called.
806  /// \pre The type of all \p Ops registers must be identical.
807  ///
808  /// \return a MachineInstrBuilder for the newly created instruction.
809  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
810  ArrayRef<Register> Ops);
811 
812  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
813  ///
814  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
815  /// vectors.
816  ///
817  /// \pre setBasicBlock or setMI must have been called.
818  /// \pre The entire register \p Res (and no more) must be covered by the input
819  /// registers.
820  /// \pre The type of all source operands must be identical.
821  ///
822  /// \return a MachineInstrBuilder for the newly created instruction.
823  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
824  ArrayRef<Register> Ops);
825 
826  MachineInstrBuilder buildInsert(Register Res, Register Src,
827  Register Op, unsigned Index);
828 
829  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
830  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
831  /// result register definition unless \p Reg is NoReg (== 0). The second
832  /// operand will be the intrinsic's ID.
833  ///
834  /// Callers are expected to add the required definitions and uses afterwards.
835  ///
836  /// \pre setBasicBlock or setMI must have been called.
837  ///
838  /// \return a MachineInstrBuilder for the newly created instruction.
840  bool HasSideEffects);
841  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
842  bool HasSideEffects);
843 
844  /// Build and insert \p Res = G_FPTRUNC \p Op
845  ///
846  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
847  ///
848  /// \pre setBasicBlock or setMI must have been called.
849  /// \pre \p Res must be a generic virtual register with scalar or vector type.
850  /// \pre \p Op must be a generic virtual register with scalar or vector type.
851  /// \pre \p Res must be smaller than \p Op
852  ///
853  /// \return The newly created instruction.
854  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
855 
856  /// Build and insert \p Res = G_TRUNC \p Op
857  ///
858  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
859  /// truncated independently before being packed into the destination.
860  ///
861  /// \pre setBasicBlock or setMI must have been called.
862  /// \pre \p Res must be a generic virtual register with scalar or vector type.
863  /// \pre \p Op must be a generic virtual register with scalar or vector type.
864  /// \pre \p Res must be smaller than \p Op
865  ///
866  /// \return The newly created instruction.
867  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
868 
869  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
870  ///
871  /// \pre setBasicBlock or setMI must have been called.
872 
873  /// \pre \p Res must be a generic virtual register with scalar or
874  /// vector type. Typically this starts as s1 or <N x s1>.
875  /// \pre \p Op0 and Op1 must be generic virtual registers with the
876  /// same number of elements as \p Res. If \p Res is a scalar,
877  /// \p Op0 must be either a scalar or pointer.
878  /// \pre \p Pred must be an integer predicate.
879  ///
880  /// \return a MachineInstrBuilder for the newly created instruction.
881  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
882  const SrcOp &Op0, const SrcOp &Op1);
883 
884  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
885  ///
886  /// \pre setBasicBlock or setMI must have been called.
887 
888  /// \pre \p Res must be a generic virtual register with scalar or
889  /// vector type. Typically this starts as s1 or <N x s1>.
890  /// \pre \p Op0 and Op1 must be generic virtual registers with the
891  /// same number of elements as \p Res (or scalar, if \p Res is
892  /// scalar).
893  /// \pre \p Pred must be a floating-point predicate.
894  ///
895  /// \return a MachineInstrBuilder for the newly created instruction.
896  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
897  const SrcOp &Op0, const SrcOp &Op1,
898  Optional<unsigned> Flags = None);
899 
900  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
901  ///
902  /// \pre setBasicBlock or setMI must have been called.
903  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
904  /// with the same type.
905  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
906  /// vector type. If vector then it must have the same number of
907  /// elements as the other parameters.
908  ///
909  /// \return a MachineInstrBuilder for the newly created instruction.
910  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
911  const SrcOp &Op0, const SrcOp &Op1,
912  Optional<unsigned> Flags = None);
913 
914  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
915  /// \p Elt, \p Idx
916  ///
917  /// \pre setBasicBlock or setMI must have been called.
918  /// \pre \p Res and \p Val must be a generic virtual register
919  // with the same vector type.
920  /// \pre \p Elt and \p Idx must be a generic virtual register
921  /// with scalar type.
922  ///
923  /// \return The newly created instruction.
924  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
925  const SrcOp &Val,
926  const SrcOp &Elt,
927  const SrcOp &Idx);
928 
929  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
930  ///
931  /// \pre setBasicBlock or setMI must have been called.
932  /// \pre \p Res must be a generic virtual register with scalar type.
933  /// \pre \p Val must be a generic virtual register with vector type.
934  /// \pre \p Idx must be a generic virtual register with scalar type.
935  ///
936  /// \return The newly created instruction.
937  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
938  const SrcOp &Val,
939  const SrcOp &Idx);
940 
941  /// Build and insert `OldValRes<def>, SuccessRes<def> =
942  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
943  ///
944  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
945  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
946  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
947  ///
948  /// \pre setBasicBlock or setMI must have been called.
949  /// \pre \p OldValRes must be a generic virtual register of scalar type.
950  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
951  /// will be assigned 0 on failure and 1 on success.
952  /// \pre \p Addr must be a generic virtual register with pointer type.
953  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
954  /// registers of the same type.
955  ///
956  /// \return a MachineInstrBuilder for the newly created instruction.
958  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
959  Register Addr, Register CmpVal, Register NewVal,
960  MachineMemOperand &MMO);
961 
962  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
963  /// MMO`.
964  ///
965  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
966  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
967  /// Addr in \p Res.
968  ///
969  /// \pre setBasicBlock or setMI must have been called.
970  /// \pre \p OldValRes must be a generic virtual register of scalar type.
971  /// \pre \p Addr must be a generic virtual register with pointer type.
972  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
973  /// registers of the same type.
974  ///
975  /// \return a MachineInstrBuilder for the newly created instruction.
976  MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
977  Register CmpVal, Register NewVal,
978  MachineMemOperand &MMO);
979 
980  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
981  ///
982  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
983  /// original value from \p Addr in \p OldValRes. The modification is
984  /// determined by the opcode.
985  ///
986  /// \pre setBasicBlock or setMI must have been called.
987  /// \pre \p OldValRes must be a generic virtual register.
988  /// \pre \p Addr must be a generic virtual register with pointer type.
989  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
990  /// same type.
991  ///
992  /// \return a MachineInstrBuilder for the newly created instruction.
993  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
994  const SrcOp &Addr, const SrcOp &Val,
995  MachineMemOperand &MMO);
996 
997  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
998  ///
999  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1000  /// value from \p Addr in \p OldValRes.
1001  ///
1002  /// \pre setBasicBlock or setMI must have been called.
1003  /// \pre \p OldValRes must be a generic virtual register.
1004  /// \pre \p Addr must be a generic virtual register with pointer type.
1005  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1006  /// same type.
1007  ///
1008  /// \return a MachineInstrBuilder for the newly created instruction.
1009  MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1010  Register Val, MachineMemOperand &MMO);
1011 
1012  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1013  ///
1014  /// Atomically replace the value at \p Addr with the addition of \p Val and
1015  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1016  ///
1017  /// \pre setBasicBlock or setMI must have been called.
1018  /// \pre \p OldValRes must be a generic virtual register.
1019  /// \pre \p Addr must be a generic virtual register with pointer type.
1020  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1021  /// same type.
1022  ///
1023  /// \return a MachineInstrBuilder for the newly created instruction.
1024  MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1025  Register Val, MachineMemOperand &MMO);
1026 
1027  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1028  ///
1029  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1030  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1031  ///
1032  /// \pre setBasicBlock or setMI must have been called.
1033  /// \pre \p OldValRes must be a generic virtual register.
1034  /// \pre \p Addr must be a generic virtual register with pointer type.
1035  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1036  /// same type.
1037  ///
1038  /// \return a MachineInstrBuilder for the newly created instruction.
1039  MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1040  Register Val, MachineMemOperand &MMO);
1041 
1042  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1043  ///
1044  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1045  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1046  ///
1047  /// \pre setBasicBlock or setMI must have been called.
1048  /// \pre \p OldValRes must be a generic virtual register.
1049  /// \pre \p Addr must be a generic virtual register with pointer type.
1050  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1051  /// same type.
1052  ///
1053  /// \return a MachineInstrBuilder for the newly created instruction.
1054  MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1055  Register Val, MachineMemOperand &MMO);
1056 
1057  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1058  ///
1059  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1060  /// and the original value. Puts the original value from \p Addr in \p
1061  /// OldValRes.
1062  ///
1063  /// \pre setBasicBlock or setMI must have been called.
1064  /// \pre \p OldValRes must be a generic virtual register.
1065  /// \pre \p Addr must be a generic virtual register with pointer type.
1066  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1067  /// same type.
1068  ///
1069  /// \return a MachineInstrBuilder for the newly created instruction.
1070  MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1071  Register Val, MachineMemOperand &MMO);
1072 
1073  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1074  ///
1075  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1076  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1077  ///
1078  /// \pre setBasicBlock or setMI must have been called.
1079  /// \pre \p OldValRes must be a generic virtual register.
1080  /// \pre \p Addr must be a generic virtual register with pointer type.
1081  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1082  /// same type.
1083  ///
1084  /// \return a MachineInstrBuilder for the newly created instruction.
1085  MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1086  Register Val, MachineMemOperand &MMO);
1087 
1088  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1089  ///
1090  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1091  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1092  ///
1093  /// \pre setBasicBlock or setMI must have been called.
1094  /// \pre \p OldValRes must be a generic virtual register.
1095  /// \pre \p Addr must be a generic virtual register with pointer type.
1096  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1097  /// same type.
1098  ///
1099  /// \return a MachineInstrBuilder for the newly created instruction.
1100  MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1101  Register Val, MachineMemOperand &MMO);
1102 
1103  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1104  ///
1105  /// Atomically replace the value at \p Addr with the signed maximum of \p
1106  /// Val and the original value. Puts the original value from \p Addr in \p
1107  /// OldValRes.
1108  ///
1109  /// \pre setBasicBlock or setMI must have been called.
1110  /// \pre \p OldValRes must be a generic virtual register.
1111  /// \pre \p Addr must be a generic virtual register with pointer type.
1112  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1113  /// same type.
1114  ///
1115  /// \return a MachineInstrBuilder for the newly created instruction.
1116  MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1117  Register Val, MachineMemOperand &MMO);
1118 
1119  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1120  ///
1121  /// Atomically replace the value at \p Addr with the signed minimum of \p
1122  /// Val and the original value. Puts the original value from \p Addr in \p
1123  /// OldValRes.
1124  ///
1125  /// \pre setBasicBlock or setMI must have been called.
1126  /// \pre \p OldValRes must be a generic virtual register.
1127  /// \pre \p Addr must be a generic virtual register with pointer type.
1128  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1129  /// same type.
1130  ///
1131  /// \return a MachineInstrBuilder for the newly created instruction.
1132  MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1133  Register Val, MachineMemOperand &MMO);
1134 
1135  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1136  ///
1137  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1138  /// Val and the original value. Puts the original value from \p Addr in \p
1139  /// OldValRes.
1140  ///
1141  /// \pre setBasicBlock or setMI must have been called.
1142  /// \pre \p OldValRes must be a generic virtual register.
1143  /// \pre \p Addr must be a generic virtual register with pointer type.
1144  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1145  /// same type.
1146  ///
1147  /// \return a MachineInstrBuilder for the newly created instruction.
1148  MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1149  Register Val, MachineMemOperand &MMO);
1150 
1151  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1152  ///
1153  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1154  /// Val and the original value. Puts the original value from \p Addr in \p
1155  /// OldValRes.
1156  ///
1157  /// \pre setBasicBlock or setMI must have been called.
1158  /// \pre \p OldValRes must be a generic virtual register.
1159  /// \pre \p Addr must be a generic virtual register with pointer type.
1160  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1161  /// same type.
1162  ///
1163  /// \return a MachineInstrBuilder for the newly created instruction.
1164  MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1165  Register Val, MachineMemOperand &MMO);
1166 
1167  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1168  MachineInstrBuilder buildAtomicRMWFAdd(
1169  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1170  MachineMemOperand &MMO);
1171 
1172  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1173  MachineInstrBuilder buildAtomicRMWFSub(
1174  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1175  MachineMemOperand &MMO);
1176 
1177  /// Build and insert `G_FENCE Ordering, Scope`.
1178  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1179 
1180  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1181  ///
1182  /// G_BLOCK_ADDR computes the address of a basic block.
1183  ///
1184  /// \pre setBasicBlock or setMI must have been called.
1185  /// \pre \p Res must be a generic virtual register of a pointer type.
1186  ///
1187  /// \return The newly created instruction.
1188  MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1189 
1190  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1191  ///
1192  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1193  /// truncated to their width.
1194  ///
1195  /// \pre setBasicBlock or setMI must have been called.
1196  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1197  /// with the same (scalar or vector) type).
1198  ///
1199  /// \return a MachineInstrBuilder for the newly created instruction.
1200 
1201  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1202  const SrcOp &Src1,
1203  Optional<unsigned> Flags = None) {
1204  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1205  }
1206 
1207  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1208  ///
1209  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1210  /// truncated to their width.
1211  ///
1212  /// \pre setBasicBlock or setMI must have been called.
1213  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1214  /// with the same (scalar or vector) type).
1215  ///
1216  /// \return a MachineInstrBuilder for the newly created instruction.
1217 
1218  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1219  const SrcOp &Src1,
1220  Optional<unsigned> Flags = None) {
1221  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1222  }
1223 
1224  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1225  ///
1226  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1227  /// truncated to their width.
1228  ///
1229  /// \pre setBasicBlock or setMI must have been called.
1230  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1231  /// with the same (scalar or vector) type).
1232  ///
1233  /// \return a MachineInstrBuilder for the newly created instruction.
1234  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1235  const SrcOp &Src1,
1236  Optional<unsigned> Flags = None) {
1237  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1238  }
1239 
1240  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1241  const SrcOp &Src1,
1242  Optional<unsigned> Flags = None) {
1243  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1244  }
1245 
1246  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1247  const SrcOp &Src1,
1248  Optional<unsigned> Flags = None) {
1249  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1250  }
1251 
1252  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1253  const SrcOp &Src1,
1254  Optional<unsigned> Flags = None) {
1255  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1256  }
1257 
1258  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1259  const SrcOp &Src1,
1260  Optional<unsigned> Flags = None) {
1261  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1262  }
1263 
1264  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1265  const SrcOp &Src1,
1266  Optional<unsigned> Flags = None) {
1267  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1268  }
1269 
1270  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1271  const SrcOp &Src1,
1272  Optional<unsigned> Flags = None) {
1273  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1274  }
1275 
1276  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1277  ///
1278  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1279  /// Op1.
1280  ///
1281  /// \pre setBasicBlock or setMI must have been called.
1282  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1283  /// with the same (scalar or vector) type).
1284  ///
1285  /// \return a MachineInstrBuilder for the newly created instruction.
1286 
1287  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1288  const SrcOp &Src1) {
1289  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1290  }
1291 
1292  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1293  ///
1294  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1295  /// Op1.
1296  ///
1297  /// \pre setBasicBlock or setMI must have been called.
1298  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1299  /// with the same (scalar or vector) type).
1300  ///
1301  /// \return a MachineInstrBuilder for the newly created instruction.
1302  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1303  const SrcOp &Src1) {
1304  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1305  }
1306 
1307  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1308  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1309  const SrcOp &Src1) {
1310  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1311  }
1312 
1313  /// Build and insert a bitwise not,
1314  /// \p NegOne = G_CONSTANT -1
1315  /// \p Res = G_OR \p Op0, NegOne
1316  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1317  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1318  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1319  }
1320 
1321  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1322  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1323  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1324  }
1325 
1326  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1327  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1328  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1329  }
1330 
1331  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1333  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1334  }
1335 
1336  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1337  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1338  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1339  }
1340 
1341  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1343  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1344  }
1345 
1346  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1347  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1348  const SrcOp &Src1) {
1349  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1});
1350  }
1351 
1352  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1353  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1354  const SrcOp &Src1) {
1355  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1356  }
1357 
1358  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1359  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1360  const SrcOp &Src1, const SrcOp &Src2) {
1361  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1362  }
1363 
1364  /// Build and insert \p Res = G_FNEG \p Op0
1365  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
1366  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
1367  }
1368 
1369  /// Build and insert \p Res = G_FABS \p Op0
1370  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1371  Optional<unsigned> Flags = None) {
1372  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1373  }
1374 
1375  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1377  Optional<unsigned> Flags = None) {
1378  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1379  }
1380 
1381  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1383  const SrcOp &Src1) {
1384  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1385  }
1386 
1387  /// Build and insert \p Res = G_UITOFP \p Src0
1388  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1389  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1390  }
1391 
1392  /// Build and insert \p Res = G_SITOFP \p Src0
1393  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1394  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1395  }
1396 
1397  /// Build and insert \p Res = G_FPTOUI \p Src0
1398  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1399  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1400  }
1401 
1402  /// Build and insert \p Res = G_FPTOSI \p Src0
1403  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1404  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1405  }
1406 
1407  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1408  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1409  const SrcOp &Src1) {
1410  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1411  }
1412 
1413  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1414  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1415  const SrcOp &Src1) {
1416  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1417  }
1418 
1419  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1420  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1421  const SrcOp &Src1) {
1422  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1423  }
1424 
1425  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1426  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1427  const SrcOp &Src1) {
1428  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1429  }
1430 
1431  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1432  ///
1433  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1434  /// the jump table index \p JTI.
1435  ///
1436  /// \return a MachineInstrBuilder for the newly created instruction.
1437  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1438 
1439  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1440  ArrayRef<SrcOp> SrcOps,
1441  Optional<unsigned> Flags = None);
1442 };
1443 
1444 } // End namespace llvm.
1445 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
CmpInst::Predicate Pred
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DstType getDstOpKind() const
DstOp(Register R)
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
SrcOp(Register R)
int64_t getImm() const
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
MachineBasicBlock::iterator II
SrcOp(int64_t V)
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
DstOp(unsigned R)
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FNEG Op0.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FADD Op0, Op1.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
DstOp(const MachineOperand &Op)
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Register getReg() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineIRBuilderState & getState()
Getter for the State.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1395
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(uint64_t V)
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.