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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
62  unsigned Reg;
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  unsigned getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
122  unsigned Reg;
124  };
125 
126 public:
127  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128  SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
131  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 
133  void addSrcToMIB(MachineInstrBuilder &MIB) const {
134  switch (Ty) {
135  case SrcType::Ty_Predicate:
136  MIB.addPredicate(Pred);
137  break;
138  case SrcType::Ty_Reg:
139  MIB.addUse(Reg);
140  break;
141  case SrcType::Ty_MIB:
142  MIB.addUse(SrcMIB->getOperand(0).getReg());
143  break;
144  }
145  }
146 
148  switch (Ty) {
149  case SrcType::Ty_Predicate:
150  llvm_unreachable("Not a register operand");
151  case SrcType::Ty_Reg:
152  return MRI.getType(Reg);
153  case SrcType::Ty_MIB:
154  return MRI.getType(SrcMIB->getOperand(0).getReg());
155  }
156  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
157  }
158 
159  unsigned getReg() const {
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return Reg;
165  case SrcType::Ty_MIB:
166  return SrcMIB->getOperand(0).getReg();
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
172  switch (Ty) {
173  case SrcType::Ty_Predicate:
174  return Pred;
175  default:
176  llvm_unreachable("Not a register operand");
177  }
178  }
179 
180  SrcType getSrcOpKind() const { return Ty; }
181 
182 private:
183  SrcType Ty;
184 };
185 
186 class FlagsOp {
187  Optional<unsigned> Flags;
188 
189 public:
190  explicit FlagsOp(unsigned F) : Flags(F) {}
191  FlagsOp() : Flags(None) {}
192  Optional<unsigned> getFlags() const { return Flags; }
193 };
194 /// Helper class to build MachineInstr.
195 /// It keeps internally the insertion point and debug location for all
196 /// the new instructions we want to create.
197 /// This information can be modify via the related setters.
199 
200  MachineIRBuilderState State;
201 
202 protected:
203  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
204 
205  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
206  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
207 
208  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
209  const LLT &Op1Ty);
210  void recordInsertion(MachineInstr *MI) const;
211 
212 public:
213  /// Some constructors for easy use.
214  MachineIRBuilder() = default;
217  setInstr(MI);
218  }
219 
220  virtual ~MachineIRBuilder() = default;
221 
222  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
223 
225  assert(State.TII && "TargetInstrInfo is not set");
226  return *State.TII;
227  }
228 
229  /// Getter for the function we currently build.
231  assert(State.MF && "MachineFunction is not set");
232  return *State.MF;
233  }
234 
235  const MachineFunction &getMF() const {
236  assert(State.MF && "MachineFunction is not set");
237  return *State.MF;
238  }
239 
240  const DataLayout &getDataLayout() const {
241  return getMF().getFunction().getParent()->getDataLayout();
242  }
243 
244  /// Getter for DebugLoc
245  const DebugLoc &getDL() { return State.DL; }
246 
247  /// Getter for MRI
248  MachineRegisterInfo *getMRI() { return State.MRI; }
249  const MachineRegisterInfo *getMRI() const { return State.MRI; }
250 
251  /// Getter for the State
252  MachineIRBuilderState &getState() { return State; }
253 
254  /// Getter for the basic block we currently build.
255  const MachineBasicBlock &getMBB() const {
256  assert(State.MBB && "MachineBasicBlock is not set");
257  return *State.MBB;
258  }
259 
261  return const_cast<MachineBasicBlock &>(
262  const_cast<const MachineIRBuilder *>(this)->getMBB());
263  }
264 
265  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
266  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
267 
268  /// Current insertion point for new instructions.
270 
271  /// Set the insertion point before the specified position.
272  /// \pre MBB must be in getMF().
273  /// \pre II must be a valid iterator in MBB.
275  /// @}
276 
277  void setCSEInfo(GISelCSEInfo *Info);
278 
279  /// \name Setters for the insertion point.
280  /// @{
281  /// Set the MachineFunction where to build instructions.
282  void setMF(MachineFunction &MF);
283 
284  /// Set the insertion point to the end of \p MBB.
285  /// \pre \p MBB must be contained by getMF().
286  void setMBB(MachineBasicBlock &MBB);
287 
288  /// Set the insertion point to before MI.
289  /// \pre MI must be in getMF().
290  void setInstr(MachineInstr &MI);
291  /// @}
292 
293  void setChangeObserver(GISelChangeObserver &Observer);
294  void stopObservingChanges();
295  /// @}
296 
297  /// Set the debug location to \p DL for all the next build instructions.
298  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
299 
300  /// Get the current instruction's debug location.
301  DebugLoc getDebugLoc() { return State.DL; }
302 
303  /// Build and insert <empty> = \p Opcode <empty>.
304  /// The insertion point is the one set by the last call of either
305  /// setBasicBlock or setMI.
306  ///
307  /// \pre setBasicBlock or setMI must have been called.
308  ///
309  /// \return a MachineInstrBuilder for the newly created instruction.
310  MachineInstrBuilder buildInstr(unsigned Opcode);
311 
312  /// Build but don't insert <empty> = \p Opcode <empty>.
313  ///
314  /// \pre setMF, setBasicBlock or setMI must have been called.
315  ///
316  /// \return a MachineInstrBuilder for the newly created instruction.
317  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
318 
319  /// Insert an existing instruction at the insertion point.
320  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
321 
322  /// Build and insert a DBG_VALUE instruction expressing the fact that the
323  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
324  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
325  const MDNode *Expr);
326 
327  /// Build and insert a DBG_VALUE instruction expressing the fact that the
328  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
329  /// Expr).
330  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
331  const MDNode *Variable,
332  const MDNode *Expr);
333 
334  /// Build and insert a DBG_VALUE instruction expressing the fact that the
335  /// associated \p Variable lives in the stack slot specified by \p FI
336  /// (suitably modified by \p Expr).
337  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
338  const MDNode *Expr);
339 
340  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
341  /// given by \p C (suitably modified by \p Expr).
342  MachineInstrBuilder buildConstDbgValue(const Constant &C,
343  const MDNode *Variable,
344  const MDNode *Expr);
345 
346  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
347  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
348  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
349 
350  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
351  ///
352  /// G_FRAME_INDEX materializes the address of an alloca value or other
353  /// stack-based object.
354  ///
355  /// \pre setBasicBlock or setMI must have been called.
356  /// \pre \p Res must be a generic virtual register with pointer type.
357  ///
358  /// \return a MachineInstrBuilder for the newly created instruction.
359  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
360 
361  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
362  ///
363  /// G_GLOBAL_VALUE materializes the address of the specified global
364  /// into \p Res.
365  ///
366  /// \pre setBasicBlock or setMI must have been called.
367  /// \pre \p Res must be a generic virtual register with pointer type
368  /// in the same address space as \p GV.
369  ///
370  /// \return a MachineInstrBuilder for the newly created instruction.
371  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
372 
373 
374  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
375  ///
376  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
377  /// storing the resulting pointer in \p Res.
378  ///
379  /// \pre setBasicBlock or setMI must have been called.
380  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
381  /// type.
382  /// \pre \p Op1 must be a generic virtual register with scalar type.
383  ///
384  /// \return a MachineInstrBuilder for the newly created instruction.
385  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
386  unsigned Op1);
387 
388  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
389  ///
390  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
391  /// storing the resulting pointer in \p Res. If \p Value is zero then no
392  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
393  /// \p Res.
394  ///
395  /// \pre setBasicBlock or setMI must have been called.
396  /// \pre \p Op0 must be a generic virtual register with pointer type.
397  /// \pre \p ValueTy must be a scalar type.
398  /// \pre \p Res must be 0. This is to detect confusion between
399  /// materializeGEP() and buildGEP().
400  /// \post \p Res will either be a new generic virtual register of the same
401  /// type as \p Op0 or \p Op0 itself.
402  ///
403  /// \return a MachineInstrBuilder for the newly created instruction.
404  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
405  const LLT &ValueTy,
406  uint64_t Value);
407 
408  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
409  ///
410  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
411  /// pointer properties. This has the effect of rounding the address *down* to
412  /// a specified alignment in bits.
413  ///
414  /// \pre setBasicBlock or setMI must have been called.
415  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
416  /// type.
417  /// \pre \p NumBits must be an integer representing the number of low bits to
418  /// be cleared in \p Op0.
419  ///
420  /// \return a MachineInstrBuilder for the newly created instruction.
421  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
422  uint32_t NumBits);
423 
424  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
425  ///
426  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
427  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
428  ///
429  /// \pre setBasicBlock or setMI must have been called.
430  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
431  /// same scalar type.
432  ////\pre \p CarryOut must be generic virtual register with scalar type
433  ///(typically s1)
434  ///
435  /// \return The newly created instruction.
436  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
437  const SrcOp &Op0, const SrcOp &Op1);
438 
439  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
440  /// \p Op1, \p CarryIn
441  ///
442  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
443  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
444  /// arithmetic.
445  ///
446  /// \pre setBasicBlock or setMI must have been called.
447  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
448  /// with the same scalar type.
449  /// \pre \p CarryOut and \p CarryIn must be generic virtual
450  /// registers with the same scalar type (typically s1)
451  ///
452  /// \return The newly created instruction.
453  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
454  const SrcOp &Op0, const SrcOp &Op1,
455  const SrcOp &CarryIn);
456 
457  /// Build and insert \p Res = G_ANYEXT \p Op0
458  ///
459  /// G_ANYEXT produces a register of the specified width, with bits 0 to
460  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
461  /// (i.e. this is neither zero nor sign-extension). For a vector register,
462  /// each element is extended individually.
463  ///
464  /// \pre setBasicBlock or setMI must have been called.
465  /// \pre \p Res must be a generic virtual register with scalar or vector type.
466  /// \pre \p Op must be a generic virtual register with scalar or vector type.
467  /// \pre \p Op must be smaller than \p Res
468  ///
469  /// \return The newly created instruction.
470 
471  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
472 
473  /// Build and insert \p Res = G_SEXT \p Op
474  ///
475  /// G_SEXT produces a register of the specified width, with bits 0 to
476  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
477  /// high bit of \p Op (i.e. 2s-complement sign extended).
478  ///
479  /// \pre setBasicBlock or setMI must have been called.
480  /// \pre \p Res must be a generic virtual register with scalar or vector type.
481  /// \pre \p Op must be a generic virtual register with scalar or vector type.
482  /// \pre \p Op must be smaller than \p Res
483  ///
484  /// \return The newly created instruction.
485  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
486 
487  /// Build and insert a G_PTRTOINT instruction.
488  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
489  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
490  }
491 
492  /// Build and insert \p Dst = G_BITCAST \p Src
493  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
494  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
495  }
496 
497  /// \return The opcode of the extension the target wants to use for boolean
498  /// values.
499  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
500 
501  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
502  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
503  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
504  bool IsFP);
505 
506  /// Build and insert \p Res = G_ZEXT \p Op
507  ///
508  /// G_ZEXT produces a register of the specified width, with bits 0 to
509  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
510  /// register, each element is extended individually.
511  ///
512  /// \pre setBasicBlock or setMI must have been called.
513  /// \pre \p Res must be a generic virtual register with scalar or vector type.
514  /// \pre \p Op must be a generic virtual register with scalar or vector type.
515  /// \pre \p Op must be smaller than \p Res
516  ///
517  /// \return The newly created instruction.
518  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
519 
520  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
521  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
522  /// ///
523  /// \pre setBasicBlock or setMI must have been called.
524  /// \pre \p Res must be a generic virtual register with scalar or vector type.
525  /// \pre \p Op must be a generic virtual register with scalar or vector type.
526  ///
527  /// \return The newly created instruction.
528  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
529 
530  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
531  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
532  /// ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res must be a generic virtual register with scalar or vector type.
535  /// \pre \p Op must be a generic virtual register with scalar or vector type.
536  ///
537  /// \return The newly created instruction.
538  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
539 
540  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
541  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
542  /// ///
543  /// \pre setBasicBlock or setMI must have been called.
544  /// \pre \p Res must be a generic virtual register with scalar or vector type.
545  /// \pre \p Op must be a generic virtual register with scalar or vector type.
546  ///
547  /// \return The newly created instruction.
548  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
549 
550  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
551  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
552  /// \p Op.
553  /// ///
554  /// \pre setBasicBlock or setMI must have been called.
555  /// \pre \p Res must be a generic virtual register with scalar or vector type.
556  /// \pre \p Op must be a generic virtual register with scalar or vector type.
557  ///
558  /// \return The newly created instruction.
559  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
560  const SrcOp &Op);
561 
562  /// Build and insert an appropriate cast between two registers of equal size.
563  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
564 
565  /// Build and insert G_BR \p Dest
566  ///
567  /// G_BR is an unconditional branch to \p Dest.
568  ///
569  /// \pre setBasicBlock or setMI must have been called.
570  ///
571  /// \return a MachineInstrBuilder for the newly created instruction.
572  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
573 
574  /// Build and insert G_BRCOND \p Tst, \p Dest
575  ///
576  /// G_BRCOND is a conditional branch to \p Dest.
577  ///
578  /// \pre setBasicBlock or setMI must have been called.
579  /// \pre \p Tst must be a generic virtual register with scalar
580  /// type. At the beginning of legalization, this will be a single
581  /// bit (s1). Targets with interesting flags registers may change
582  /// this. For a wider type, whether the branch is taken must only
583  /// depend on bit 0 (for now).
584  ///
585  /// \return The newly created instruction.
586  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
587 
588  /// Build and insert G_BRINDIRECT \p Tgt
589  ///
590  /// G_BRINDIRECT is an indirect branch to \p Tgt.
591  ///
592  /// \pre setBasicBlock or setMI must have been called.
593  /// \pre \p Tgt must be a generic virtual register with pointer type.
594  ///
595  /// \return a MachineInstrBuilder for the newly created instruction.
596  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
597 
598  /// Build and insert \p Res = G_CONSTANT \p Val
599  ///
600  /// G_CONSTANT is an integer constant with the specified size and value. \p
601  /// Val will be extended or truncated to the size of \p Reg.
602  ///
603  /// \pre setBasicBlock or setMI must have been called.
604  /// \pre \p Res must be a generic virtual register with scalar or pointer
605  /// type.
606  ///
607  /// \return The newly created instruction.
608  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
609  const ConstantInt &Val);
610 
611  /// Build and insert \p Res = G_CONSTANT \p Val
612  ///
613  /// G_CONSTANT is an integer constant with the specified size and value.
614  ///
615  /// \pre setBasicBlock or setMI must have been called.
616  /// \pre \p Res must be a generic virtual register with scalar type.
617  ///
618  /// \return The newly created instruction.
619  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
620  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
621 
622  /// Build and insert \p Res = G_FCONSTANT \p Val
623  ///
624  /// G_FCONSTANT is a floating-point constant with the specified size and
625  /// value.
626  ///
627  /// \pre setBasicBlock or setMI must have been called.
628  /// \pre \p Res must be a generic virtual register with scalar type.
629  ///
630  /// \return The newly created instruction.
631  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
632  const ConstantFP &Val);
633 
634  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
635 
636  /// Build and insert \p Res = COPY Op
637  ///
638  /// Register-to-register COPY sets \p Res to \p Op.
639  ///
640  /// \pre setBasicBlock or setMI must have been called.
641  ///
642  /// \return a MachineInstrBuilder for the newly created instruction.
643  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
644 
645  /// Build and insert `Res = G_LOAD Addr, MMO`.
646  ///
647  /// Loads the value stored at \p Addr. Puts the result in \p Res.
648  ///
649  /// \pre setBasicBlock or setMI must have been called.
650  /// \pre \p Res must be a generic virtual register.
651  /// \pre \p Addr must be a generic virtual register with pointer type.
652  ///
653  /// \return a MachineInstrBuilder for the newly created instruction.
654  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
655  MachineMemOperand &MMO);
656 
657  /// Build and insert `Res = <opcode> Addr, MMO`.
658  ///
659  /// Loads the value stored at \p Addr. Puts the result in \p Res.
660  ///
661  /// \pre setBasicBlock or setMI must have been called.
662  /// \pre \p Res must be a generic virtual register.
663  /// \pre \p Addr must be a generic virtual register with pointer type.
664  ///
665  /// \return a MachineInstrBuilder for the newly created instruction.
666  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
667  unsigned Addr, MachineMemOperand &MMO);
668 
669  /// Build and insert `G_STORE Val, Addr, MMO`.
670  ///
671  /// Stores the value \p Val to \p Addr.
672  ///
673  /// \pre setBasicBlock or setMI must have been called.
674  /// \pre \p Val must be a generic virtual register.
675  /// \pre \p Addr must be a generic virtual register with pointer type.
676  ///
677  /// \return a MachineInstrBuilder for the newly created instruction.
678  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
679  MachineMemOperand &MMO);
680 
681  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
682  ///
683  /// \pre setBasicBlock or setMI must have been called.
684  /// \pre \p Res and \p Src must be generic virtual registers.
685  ///
686  /// \return a MachineInstrBuilder for the newly created instruction.
687  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
688 
689  /// Build and insert \p Res = IMPLICIT_DEF.
690  MachineInstrBuilder buildUndef(const DstOp &Res);
691 
692  /// Build and insert instructions to put \p Ops together at the specified p
693  /// Indices to form a larger register.
694  ///
695  /// If the types of the input registers are uniform and cover the entirity of
696  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
697  /// followed by a sequence of G_INSERT instructions.
698  ///
699  /// \pre setBasicBlock or setMI must have been called.
700  /// \pre The final element of the sequence must not extend past the end of the
701  /// destination register.
702  /// \pre The bits defined by each Op (derived from index and scalar size) must
703  /// not overlap.
704  /// \pre \p Indices must be in ascending order of bit position.
705  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
706  ArrayRef<uint64_t> Indices);
707 
708  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
709  ///
710  /// G_MERGE_VALUES combines the input elements contiguously into a larger
711  /// register.
712  ///
713  /// \pre setBasicBlock or setMI must have been called.
714  /// \pre The entire register \p Res (and no more) must be covered by the input
715  /// registers.
716  /// \pre The type of all \p Ops registers must be identical.
717  ///
718  /// \return a MachineInstrBuilder for the newly created instruction.
719  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
720 
721  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
722  ///
723  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
724  ///
725  /// \pre setBasicBlock or setMI must have been called.
726  /// \pre The entire register \p Res (and no more) must be covered by the input
727  /// registers.
728  /// \pre The type of all \p Res registers must be identical.
729  ///
730  /// \return a MachineInstrBuilder for the newly created instruction.
731  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
732  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
733 
734  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
735  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
736 
737  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
738  ///
739  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
740  /// \pre setBasicBlock or setMI must have been called.
741  /// \pre The entire register \p Res (and no more) must be covered by the
742  /// input scalar registers.
743  /// \pre The type of all \p Ops registers must be identical.
744  ///
745  /// \return a MachineInstrBuilder for the newly created instruction.
746  MachineInstrBuilder buildBuildVector(const DstOp &Res,
747  ArrayRef<unsigned> Ops);
748 
749  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
750  /// the number of elements
751  MachineInstrBuilder buildSplatVector(const DstOp &Res,
752  const SrcOp &Src);
753 
754  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
755  ///
756  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
757  /// which have types larger than the destination vector element type, and
758  /// truncates the values to fit.
759  ///
760  /// If the operands given are already the same size as the vector elt type,
761  /// then this method will instead create a G_BUILD_VECTOR instruction.
762  ///
763  /// \pre setBasicBlock or setMI must have been called.
764  /// \pre The type of all \p Ops registers must be identical.
765  ///
766  /// \return a MachineInstrBuilder for the newly created instruction.
767  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
768  ArrayRef<unsigned> Ops);
769 
770  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
771  ///
772  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
773  /// vectors.
774  ///
775  /// \pre setBasicBlock or setMI must have been called.
776  /// \pre The entire register \p Res (and no more) must be covered by the input
777  /// registers.
778  /// \pre The type of all source operands must be identical.
779  ///
780  /// \return a MachineInstrBuilder for the newly created instruction.
781  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
782  ArrayRef<unsigned> Ops);
783 
784  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
785  unsigned Op, unsigned Index);
786 
787  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
788  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
789  /// result register definition unless \p Reg is NoReg (== 0). The second
790  /// operand will be the intrinsic's ID.
791  ///
792  /// Callers are expected to add the required definitions and uses afterwards.
793  ///
794  /// \pre setBasicBlock or setMI must have been called.
795  ///
796  /// \return a MachineInstrBuilder for the newly created instruction.
798  bool HasSideEffects);
799 
800  /// Build and insert \p Res = G_FPTRUNC \p Op
801  ///
802  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
803  ///
804  /// \pre setBasicBlock or setMI must have been called.
805  /// \pre \p Res must be a generic virtual register with scalar or vector type.
806  /// \pre \p Op must be a generic virtual register with scalar or vector type.
807  /// \pre \p Res must be smaller than \p Op
808  ///
809  /// \return The newly created instruction.
810  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
811 
812  /// Build and insert \p Res = G_TRUNC \p Op
813  ///
814  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
815  /// truncated independently before being packed into the destination.
816  ///
817  /// \pre setBasicBlock or setMI must have been called.
818  /// \pre \p Res must be a generic virtual register with scalar or vector type.
819  /// \pre \p Op must be a generic virtual register with scalar or vector type.
820  /// \pre \p Res must be smaller than \p Op
821  ///
822  /// \return The newly created instruction.
823  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
824 
825  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
826  ///
827  /// \pre setBasicBlock or setMI must have been called.
828 
829  /// \pre \p Res must be a generic virtual register with scalar or
830  /// vector type. Typically this starts as s1 or <N x s1>.
831  /// \pre \p Op0 and Op1 must be generic virtual registers with the
832  /// same number of elements as \p Res. If \p Res is a scalar,
833  /// \p Op0 must be either a scalar or pointer.
834  /// \pre \p Pred must be an integer predicate.
835  ///
836  /// \return a MachineInstrBuilder for the newly created instruction.
837  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
838  const SrcOp &Op0, const SrcOp &Op1);
839 
840  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
841  ///
842  /// \pre setBasicBlock or setMI must have been called.
843 
844  /// \pre \p Res must be a generic virtual register with scalar or
845  /// vector type. Typically this starts as s1 or <N x s1>.
846  /// \pre \p Op0 and Op1 must be generic virtual registers with the
847  /// same number of elements as \p Res (or scalar, if \p Res is
848  /// scalar).
849  /// \pre \p Pred must be a floating-point predicate.
850  ///
851  /// \return a MachineInstrBuilder for the newly created instruction.
852  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
853  const SrcOp &Op0, const SrcOp &Op1);
854 
855  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
856  ///
857  /// \pre setBasicBlock or setMI must have been called.
858  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
859  /// with the same type.
860  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
861  /// vector type. If vector then it must have the same number of
862  /// elements as the other parameters.
863  ///
864  /// \return a MachineInstrBuilder for the newly created instruction.
865  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
866  const SrcOp &Op0, const SrcOp &Op1);
867 
868  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
869  /// \p Elt, \p Idx
870  ///
871  /// \pre setBasicBlock or setMI must have been called.
872  /// \pre \p Res and \p Val must be a generic virtual register
873  // with the same vector type.
874  /// \pre \p Elt and \p Idx must be a generic virtual register
875  /// with scalar type.
876  ///
877  /// \return The newly created instruction.
878  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
879  const SrcOp &Val,
880  const SrcOp &Elt,
881  const SrcOp &Idx);
882 
883  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
884  ///
885  /// \pre setBasicBlock or setMI must have been called.
886  /// \pre \p Res must be a generic virtual register with scalar type.
887  /// \pre \p Val must be a generic virtual register with vector type.
888  /// \pre \p Idx must be a generic virtual register with scalar type.
889  ///
890  /// \return The newly created instruction.
891  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
892  const SrcOp &Val,
893  const SrcOp &Idx);
894 
895  /// Build and insert `OldValRes<def>, SuccessRes<def> =
896  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
897  ///
898  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
899  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
900  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
901  ///
902  /// \pre setBasicBlock or setMI must have been called.
903  /// \pre \p OldValRes must be a generic virtual register of scalar type.
904  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
905  /// will be assigned 0 on failure and 1 on success.
906  /// \pre \p Addr must be a generic virtual register with pointer type.
907  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
908  /// registers of the same type.
909  ///
910  /// \return a MachineInstrBuilder for the newly created instruction.
912  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
913  unsigned Addr, unsigned CmpVal, unsigned NewVal,
914  MachineMemOperand &MMO);
915 
916  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
917  /// MMO`.
918  ///
919  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
920  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
921  /// Addr in \p Res.
922  ///
923  /// \pre setBasicBlock or setMI must have been called.
924  /// \pre \p OldValRes must be a generic virtual register of scalar type.
925  /// \pre \p Addr must be a generic virtual register with pointer type.
926  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
927  /// registers of the same type.
928  ///
929  /// \return a MachineInstrBuilder for the newly created instruction.
930  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
931  unsigned CmpVal, unsigned NewVal,
932  MachineMemOperand &MMO);
933 
934  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
935  ///
936  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
937  /// original value from \p Addr in \p OldValRes. The modification is
938  /// determined by the opcode.
939  ///
940  /// \pre setBasicBlock or setMI must have been called.
941  /// \pre \p OldValRes must be a generic virtual register.
942  /// \pre \p Addr must be a generic virtual register with pointer type.
943  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
944  /// same type.
945  ///
946  /// \return a MachineInstrBuilder for the newly created instruction.
947  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
948  unsigned Addr, unsigned Val,
949  MachineMemOperand &MMO);
950 
951  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
952  ///
953  /// Atomically replace the value at \p Addr with \p Val. Puts the original
954  /// value from \p Addr in \p OldValRes.
955  ///
956  /// \pre setBasicBlock or setMI must have been called.
957  /// \pre \p OldValRes must be a generic virtual register.
958  /// \pre \p Addr must be a generic virtual register with pointer type.
959  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
960  /// same type.
961  ///
962  /// \return a MachineInstrBuilder for the newly created instruction.
963  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
964  unsigned Val, MachineMemOperand &MMO);
965 
966  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
967  ///
968  /// Atomically replace the value at \p Addr with the addition of \p Val and
969  /// the original value. Puts the original value from \p Addr in \p OldValRes.
970  ///
971  /// \pre setBasicBlock or setMI must have been called.
972  /// \pre \p OldValRes must be a generic virtual register.
973  /// \pre \p Addr must be a generic virtual register with pointer type.
974  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
975  /// same type.
976  ///
977  /// \return a MachineInstrBuilder for the newly created instruction.
978  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
979  unsigned Val, MachineMemOperand &MMO);
980 
981  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
982  ///
983  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
984  /// the original value. Puts the original value from \p Addr in \p OldValRes.
985  ///
986  /// \pre setBasicBlock or setMI must have been called.
987  /// \pre \p OldValRes must be a generic virtual register.
988  /// \pre \p Addr must be a generic virtual register with pointer type.
989  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
990  /// same type.
991  ///
992  /// \return a MachineInstrBuilder for the newly created instruction.
993  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
994  unsigned Val, MachineMemOperand &MMO);
995 
996  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
997  ///
998  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
999  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1000  ///
1001  /// \pre setBasicBlock or setMI must have been called.
1002  /// \pre \p OldValRes must be a generic virtual register.
1003  /// \pre \p Addr must be a generic virtual register with pointer type.
1004  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1005  /// same type.
1006  ///
1007  /// \return a MachineInstrBuilder for the newly created instruction.
1008  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
1009  unsigned Val, MachineMemOperand &MMO);
1010 
1011  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1012  ///
1013  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1014  /// and the original value. Puts the original value from \p Addr in \p
1015  /// OldValRes.
1016  ///
1017  /// \pre setBasicBlock or setMI must have been called.
1018  /// \pre \p OldValRes must be a generic virtual register.
1019  /// \pre \p Addr must be a generic virtual register with pointer type.
1020  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1021  /// same type.
1022  ///
1023  /// \return a MachineInstrBuilder for the newly created instruction.
1024  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
1025  unsigned Val, MachineMemOperand &MMO);
1026 
1027  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1028  ///
1029  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1030  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1031  ///
1032  /// \pre setBasicBlock or setMI must have been called.
1033  /// \pre \p OldValRes must be a generic virtual register.
1034  /// \pre \p Addr must be a generic virtual register with pointer type.
1035  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1036  /// same type.
1037  ///
1038  /// \return a MachineInstrBuilder for the newly created instruction.
1039  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
1040  unsigned Val, MachineMemOperand &MMO);
1041 
1042  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1043  ///
1044  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1045  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1046  ///
1047  /// \pre setBasicBlock or setMI must have been called.
1048  /// \pre \p OldValRes must be a generic virtual register.
1049  /// \pre \p Addr must be a generic virtual register with pointer type.
1050  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1051  /// same type.
1052  ///
1053  /// \return a MachineInstrBuilder for the newly created instruction.
1054  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
1055  unsigned Val, MachineMemOperand &MMO);
1056 
1057  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1058  ///
1059  /// Atomically replace the value at \p Addr with the signed maximum of \p
1060  /// Val and the original value. Puts the original value from \p Addr in \p
1061  /// OldValRes.
1062  ///
1063  /// \pre setBasicBlock or setMI must have been called.
1064  /// \pre \p OldValRes must be a generic virtual register.
1065  /// \pre \p Addr must be a generic virtual register with pointer type.
1066  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1067  /// same type.
1068  ///
1069  /// \return a MachineInstrBuilder for the newly created instruction.
1070  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
1071  unsigned Val, MachineMemOperand &MMO);
1072 
1073  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1074  ///
1075  /// Atomically replace the value at \p Addr with the signed minimum of \p
1076  /// Val and the original value. Puts the original value from \p Addr in \p
1077  /// OldValRes.
1078  ///
1079  /// \pre setBasicBlock or setMI must have been called.
1080  /// \pre \p OldValRes must be a generic virtual register.
1081  /// \pre \p Addr must be a generic virtual register with pointer type.
1082  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1083  /// same type.
1084  ///
1085  /// \return a MachineInstrBuilder for the newly created instruction.
1086  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1087  unsigned Val, MachineMemOperand &MMO);
1088 
1089  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1090  ///
1091  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1092  /// Val and the original value. Puts the original value from \p Addr in \p
1093  /// OldValRes.
1094  ///
1095  /// \pre setBasicBlock or setMI must have been called.
1096  /// \pre \p OldValRes must be a generic virtual register.
1097  /// \pre \p Addr must be a generic virtual register with pointer type.
1098  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1099  /// same type.
1100  ///
1101  /// \return a MachineInstrBuilder for the newly created instruction.
1102  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1103  unsigned Val, MachineMemOperand &MMO);
1104 
1105  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1106  ///
1107  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1108  /// Val and the original value. Puts the original value from \p Addr in \p
1109  /// OldValRes.
1110  ///
1111  /// \pre setBasicBlock or setMI must have been called.
1112  /// \pre \p OldValRes must be a generic virtual register.
1113  /// \pre \p Addr must be a generic virtual register with pointer type.
1114  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1115  /// same type.
1116  ///
1117  /// \return a MachineInstrBuilder for the newly created instruction.
1118  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1119  unsigned Val, MachineMemOperand &MMO);
1120 
1121  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1122  ///
1123  /// G_BLOCK_ADDR computes the address of a basic block.
1124  ///
1125  /// \pre setBasicBlock or setMI must have been called.
1126  /// \pre \p Res must be a generic virtual register of a pointer type.
1127  ///
1128  /// \return The newly created instruction.
1129  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1130 
1131  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1132  ///
1133  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1134  /// truncated to their width.
1135  ///
1136  /// \pre setBasicBlock or setMI must have been called.
1137  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1138  /// with the same (scalar or vector) type).
1139  ///
1140  /// \return a MachineInstrBuilder for the newly created instruction.
1141 
1142  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1143  const SrcOp &Src1,
1144  Optional<unsigned> Flags = None) {
1145  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1146  }
1147 
1148  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1149  ///
1150  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1151  /// truncated to their width.
1152  ///
1153  /// \pre setBasicBlock or setMI must have been called.
1154  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1155  /// with the same (scalar or vector) type).
1156  ///
1157  /// \return a MachineInstrBuilder for the newly created instruction.
1158 
1159  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1160  const SrcOp &Src1,
1161  Optional<unsigned> Flags = None) {
1162  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1163  }
1164 
1165  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1166  ///
1167  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1168  /// truncated to their width.
1169  ///
1170  /// \pre setBasicBlock or setMI must have been called.
1171  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1172  /// with the same (scalar or vector) type).
1173  ///
1174  /// \return a MachineInstrBuilder for the newly created instruction.
1175  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1176  const SrcOp &Src1,
1177  Optional<unsigned> Flags = None) {
1178  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1179  }
1180 
1181  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1182  const SrcOp &Src1,
1183  Optional<unsigned> Flags = None) {
1184  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1185  }
1186 
1187  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1188  const SrcOp &Src1,
1189  Optional<unsigned> Flags = None) {
1190  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1191  }
1192 
1193  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1194  const SrcOp &Src1,
1195  Optional<unsigned> Flags = None) {
1196  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1197  }
1198 
1199  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1200  const SrcOp &Src1,
1201  Optional<unsigned> Flags = None) {
1202  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1203  }
1204 
1205  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1206  const SrcOp &Src1,
1207  Optional<unsigned> Flags = None) {
1208  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1209  }
1210 
1211  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1212  ///
1213  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1214  /// Op1.
1215  ///
1216  /// \pre setBasicBlock or setMI must have been called.
1217  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1218  /// with the same (scalar or vector) type).
1219  ///
1220  /// \return a MachineInstrBuilder for the newly created instruction.
1221 
1222  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1223  const SrcOp &Src1) {
1224  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1225  }
1226 
1227  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1228  ///
1229  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1230  /// Op1.
1231  ///
1232  /// \pre setBasicBlock or setMI must have been called.
1233  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1234  /// with the same (scalar or vector) type).
1235  ///
1236  /// \return a MachineInstrBuilder for the newly created instruction.
1237  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1238  const SrcOp &Src1) {
1239  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1240  }
1241 
1242  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1243  ArrayRef<SrcOp> SrcOps,
1244  Optional<unsigned> Flags = None);
1245 };
1246 
1247 } // End namespace llvm.
1248 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
CmpInst::Predicate Pred
unsigned getReg() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
DstType getDstOpKind() const
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
GISelCSEInfo * getCSEInfo()
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
DstOp(unsigned R)
SrcOp(const CmpInst::Predicate P)
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
unsigned getReg() const
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
DebugLoc DL
Debug location to be set to any instruction we create.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DstOp(const MachineOperand &Op)
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:63
MachineIRBuilderState & getState()
Getter for the State.
SrcOp(unsigned R)
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1364
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.