13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H 30 class MachineFunction;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
67 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
101 assert(Ty == DstType::Ty_Reg &&
"Not a register");
129 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
137 SrcOp(
unsigned) =
delete;
144 case SrcType::Ty_Predicate:
147 case SrcType::Ty_Reg:
150 case SrcType::Ty_MIB:
151 MIB.
addUse(SrcMIB->getOperand(0).getReg());
153 case SrcType::Ty_Imm:
161 case SrcType::Ty_Predicate:
162 case SrcType::Ty_Imm:
164 case SrcType::Ty_Reg:
166 case SrcType::Ty_MIB:
167 return MRI.
getType(SrcMIB->getOperand(0).getReg());
174 case SrcType::Ty_Predicate:
175 case SrcType::Ty_Imm:
177 case SrcType::Ty_Reg:
179 case SrcType::Ty_MIB:
180 return SrcMIB->getOperand(0).getReg();
187 case SrcType::Ty_Predicate:
196 case SrcType::Ty_Imm:
226 void validateTruncExt(
const LLT &Dst,
const LLT &Src,
bool IsExtend);
228 void validateBinaryOp(
const LLT &Res,
const LLT &Op0,
const LLT &Op1);
229 void validateShiftOp(
const LLT &Res,
const LLT &Op0,
const LLT &Op1);
231 void validateSelectOp(
const LLT &ResTy,
const LLT &TstTy,
const LLT &Op0Ty,
248 assert(State.
TII &&
"TargetInstrInfo is not set");
254 assert(State.
MF &&
"MachineFunction is not set");
259 assert(State.
MF &&
"MachineFunction is not set");
264 return getMF().getFunction().getParent()->getDataLayout();
279 assert(State.
MBB &&
"MachineBasicBlock is not set");
317 void stopObservingChanges();
488 const SrcOp &CarryIn);
522 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
527 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
532 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
537 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
542 unsigned getBoolExtOp(
bool IsVec,
bool IsFP)
const;
856 bool HasSideEffects);
858 bool HasSideEffects);
1220 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1237 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1253 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1259 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1265 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1271 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1277 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1283 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1289 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1304 const SrcOp &Src1) {
1305 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1319 const SrcOp &Src1) {
1320 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1325 const SrcOp &Src1) {
1326 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1333 auto NegOne = buildConstant(Dst.
getLLTTy(*getMRI()), -1);
1334 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1339 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1344 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1349 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1354 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1359 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1366 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1371 const SrcOp &Src1) {
1372 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1378 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1385 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1391 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1397 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1403 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1408 const SrcOp &Src1) {
1409 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1414 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1419 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1424 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1429 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1434 const SrcOp &Src1) {
1435 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1440 const SrcOp &Src1) {
1441 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1446 const SrcOp &Src1) {
1447 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1452 const SrcOp &Src1) {
1453 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1470 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface ...
MachineBasicBlock & getMBB()
A parsed version of the target data layout string in and methods for querying it. ...
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
This class represents lattice values for constants.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DstType getDstOpKind() const
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
The address of a basic block.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
This struct is a compact representation of a valid (non-zero power of two) alignment.
DstOp(const MachineOperand &Op)
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction's debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
Representation of each machine instruction.
MachineIRBuilderState & getState()
Getter for the State.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
Wrapper class representing virtual and physical registers.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.