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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the MachineIRBuilder class.
11 /// This is a helper class to build MachineInstr.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
16 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 
34 /// Class which stores all the state required in a MachineIRBuilder.
35 /// Since MachineIRBuilders will only store state in this object, it allows
36 /// to transfer BuilderState between different kinds of MachineIRBuilders.
38  /// MachineFunction under construction.
40  /// Information used to access the description of the opcodes.
42  /// Information used to verify types are consistent and to create virtual registers.
44  /// Debug location to be set to any instruction we create.
46 
47  /// \name Fields describing the insertion point.
48  /// @{
51  /// @}
52 
53  std::function<void(MachineInstr *)> InsertedInstr;
54 };
55 
56 /// Helper class to build MachineInstr.
57 /// It keeps internally the insertion point and debug location for all
58 /// the new instructions we want to create.
59 /// This information can be modify via the related setters.
61 
63  const TargetInstrInfo &getTII() {
64  assert(State.TII && "TargetInstrInfo is not set");
65  return *State.TII;
66  }
67 
68  void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
69 
70 protected:
71  unsigned getDestFromArg(unsigned Reg) { return Reg; }
72  unsigned getDestFromArg(LLT Ty) {
73  return getMF().getRegInfo().createGenericVirtualRegister(Ty);
74  }
75  unsigned getDestFromArg(const TargetRegisterClass *RC) {
76  return getMF().getRegInfo().createVirtualRegister(RC);
77  }
78 
79  void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg) {
80  MIB.addUse(Reg);
81  }
82 
84  MIB.addUse(UseMIB->getOperand(0).getReg());
85  }
86 
88  template<typename UseArgTy, typename ... UseArgsTy>
89  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
90  addUseFromArg(MIB, Arg1);
91  addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
92  }
93  unsigned getRegFromArg(unsigned Reg) { return Reg; }
94  unsigned getRegFromArg(const MachineInstrBuilder &MIB) {
95  return MIB->getOperand(0).getReg();
96  }
97 
98  void validateBinaryOp(unsigned Dst, unsigned Src0, unsigned Src1);
99 
100 public:
101  /// Some constructors for easy use.
102  MachineIRBuilderBase() = default;
105  setInstr(MI);
106  }
107 
108  MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
109 
110  /// Getter for the function we currently build.
112  assert(State.MF && "MachineFunction is not set");
113  return *State.MF;
114  }
115 
116  /// Getter for DebugLoc
117  const DebugLoc &getDL() { return State.DL; }
118 
119  /// Getter for MRI
120  MachineRegisterInfo *getMRI() { return State.MRI; }
121 
122  /// Getter for the State
123  MachineIRBuilderState &getState() { return State; }
124 
125  /// Getter for the basic block we currently build.
127  assert(State.MBB && "MachineBasicBlock is not set");
128  return *State.MBB;
129  }
130 
131  /// Current insertion point for new instructions.
133 
134  /// Set the insertion point before the specified position.
135  /// \pre MBB must be in getMF().
136  /// \pre II must be a valid iterator in MBB.
138  /// @}
139 
140  /// \name Setters for the insertion point.
141  /// @{
142  /// Set the MachineFunction where to build instructions.
143  void setMF(MachineFunction &);
144 
145  /// Set the insertion point to the end of \p MBB.
146  /// \pre \p MBB must be contained by getMF().
147  void setMBB(MachineBasicBlock &MBB);
148 
149  /// Set the insertion point to before MI.
150  /// \pre MI must be in getMF().
151  void setInstr(MachineInstr &MI);
152  /// @}
153 
154  /// \name Control where instructions we create are recorded (typically for
155  /// visiting again later during legalization).
156  /// @{
157  void recordInsertion(MachineInstr *InsertedInstr) const;
158  void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
159  void stopRecordingInsertions();
160  /// @}
161 
162  /// Set the debug location to \p DL for all the next build instructions.
163  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
164 
165  /// Get the current instruction's debug location.
166  DebugLoc getDebugLoc() { return State.DL; }
167 
168  /// Build and insert <empty> = \p Opcode <empty>.
169  /// The insertion point is the one set by the last call of either
170  /// setBasicBlock or setMI.
171  ///
172  /// \pre setBasicBlock or setMI must have been called.
173  ///
174  /// \return a MachineInstrBuilder for the newly created instruction.
175  MachineInstrBuilder buildInstr(unsigned Opcode);
176 
177  /// Build but don't insert <empty> = \p Opcode <empty>.
178  ///
179  /// \pre setMF, setBasicBlock or setMI must have been called.
180  ///
181  /// \return a MachineInstrBuilder for the newly created instruction.
182  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
183 
184  /// Insert an existing instruction at the insertion point.
185  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
186 
187  /// Build and insert a DBG_VALUE instruction expressing the fact that the
188  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
189  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
190  const MDNode *Expr);
191 
192  /// Build and insert a DBG_VALUE instruction expressing the fact that the
193  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
194  /// Expr).
195  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
196  const MDNode *Variable,
197  const MDNode *Expr);
198 
199  /// Build and insert a DBG_VALUE instruction expressing the fact that the
200  /// associated \p Variable lives in the stack slot specified by \p FI
201  /// (suitably modified by \p Expr).
202  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
203  const MDNode *Expr);
204 
205  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
206  /// given by \p C (suitably modified by \p Expr).
207  MachineInstrBuilder buildConstDbgValue(const Constant &C,
208  const MDNode *Variable,
209  const MDNode *Expr);
210 
211  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
212  ///
213  /// G_FRAME_INDEX materializes the address of an alloca value or other
214  /// stack-based object.
215  ///
216  /// \pre setBasicBlock or setMI must have been called.
217  /// \pre \p Res must be a generic virtual register with pointer type.
218  ///
219  /// \return a MachineInstrBuilder for the newly created instruction.
220  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
221 
222  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
223  ///
224  /// G_GLOBAL_VALUE materializes the address of the specified global
225  /// into \p Res.
226  ///
227  /// \pre setBasicBlock or setMI must have been called.
228  /// \pre \p Res must be a generic virtual register with pointer type
229  /// in the same address space as \p GV.
230  ///
231  /// \return a MachineInstrBuilder for the newly created instruction.
232  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
233 
234 
235  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
236  ///
237  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
238  /// storing the resulting pointer in \p Res.
239  ///
240  /// \pre setBasicBlock or setMI must have been called.
241  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
242  /// type.
243  /// \pre \p Op1 must be a generic virtual register with scalar type.
244  ///
245  /// \return a MachineInstrBuilder for the newly created instruction.
246  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
247  unsigned Op1);
248 
249  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
250  ///
251  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
252  /// storing the resulting pointer in \p Res. If \p Value is zero then no
253  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
254  /// \p Res.
255  ///
256  /// \pre setBasicBlock or setMI must have been called.
257  /// \pre \p Op0 must be a generic virtual register with pointer type.
258  /// \pre \p ValueTy must be a scalar type.
259  /// \pre \p Res must be 0. This is to detect confusion between
260  /// materializeGEP() and buildGEP().
261  /// \post \p Res will either be a new generic virtual register of the same
262  /// type as \p Op0 or \p Op0 itself.
263  ///
264  /// \return a MachineInstrBuilder for the newly created instruction.
265  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
266  const LLT &ValueTy,
267  uint64_t Value);
268 
269  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
270  ///
271  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
272  /// pointer properties. This has the effect of rounding the address *down* to
273  /// a specified alignment in bits.
274  ///
275  /// \pre setBasicBlock or setMI must have been called.
276  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
277  /// type.
278  /// \pre \p NumBits must be an integer representing the number of low bits to
279  /// be cleared in \p Op0.
280  ///
281  /// \return a MachineInstrBuilder for the newly created instruction.
282  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
283  uint32_t NumBits);
284 
285  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
286  /// \p Op1, \p CarryIn
287  ///
288  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
289  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
290  /// arithmetic.
291  ///
292  /// \pre setBasicBlock or setMI must have been called.
293  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
294  /// with the same scalar type.
295  /// \pre \p CarryOut and \p CarryIn must be generic virtual
296  /// registers with the same scalar type (typically s1)
297  ///
298  /// \return The newly created instruction.
299  MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0,
300  unsigned Op1, unsigned CarryIn);
301 
302 
303  /// Build and insert \p Res = G_ANYEXT \p Op0
304  ///
305  /// G_ANYEXT produces a register of the specified width, with bits 0 to
306  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
307  /// (i.e. this is neither zero nor sign-extension). For a vector register,
308  /// each element is extended individually.
309  ///
310  /// \pre setBasicBlock or setMI must have been called.
311  /// \pre \p Res must be a generic virtual register with scalar or vector type.
312  /// \pre \p Op must be a generic virtual register with scalar or vector type.
313  /// \pre \p Op must be smaller than \p Res
314  ///
315  /// \return The newly created instruction.
316 
317  MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op);
318  template <typename DstType, typename ArgType>
319  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
320  return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
321  }
322 
323  /// Build and insert \p Res = G_SEXT \p Op
324  ///
325  /// G_SEXT produces a register of the specified width, with bits 0 to
326  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
327  /// high bit of \p Op (i.e. 2s-complement sign extended).
328  ///
329  /// \pre setBasicBlock or setMI must have been called.
330  /// \pre \p Res must be a generic virtual register with scalar or vector type.
331  /// \pre \p Op must be a generic virtual register with scalar or vector type.
332  /// \pre \p Op must be smaller than \p Res
333  ///
334  /// \return The newly created instruction.
335  template <typename DstType, typename ArgType>
336  MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) {
337  return buildSExt(getDestFromArg(Res), getRegFromArg(Arg));
338  }
339  MachineInstrBuilder buildSExt(unsigned Res, unsigned Op);
340 
341  /// Build and insert \p Res = G_ZEXT \p Op
342  ///
343  /// G_ZEXT produces a register of the specified width, with bits 0 to
344  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
345  /// register, each element is extended individually.
346  ///
347  /// \pre setBasicBlock or setMI must have been called.
348  /// \pre \p Res must be a generic virtual register with scalar or vector type.
349  /// \pre \p Op must be a generic virtual register with scalar or vector type.
350  /// \pre \p Op must be smaller than \p Res
351  ///
352  /// \return The newly created instruction.
353  template <typename DstType, typename ArgType>
354  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
355  return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
356  }
357  MachineInstrBuilder buildZExt(unsigned Res, unsigned Op);
358 
359  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
360  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
361  /// ///
362  /// \pre setBasicBlock or setMI must have been called.
363  /// \pre \p Res must be a generic virtual register with scalar or vector type.
364  /// \pre \p Op must be a generic virtual register with scalar or vector type.
365  ///
366  /// \return The newly created instruction.
367  template <typename DstTy, typename UseArgTy>
368  MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
369  return buildSExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
370  }
371  MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op);
372 
373  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
374  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
375  /// ///
376  /// \pre setBasicBlock or setMI must have been called.
377  /// \pre \p Res must be a generic virtual register with scalar or vector type.
378  /// \pre \p Op must be a generic virtual register with scalar or vector type.
379  ///
380  /// \return The newly created instruction.
381  template <typename DstTy, typename UseArgTy>
382  MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
383  return buildZExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
384  }
385  MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op);
386 
387  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
388  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
389  /// ///
390  /// \pre setBasicBlock or setMI must have been called.
391  /// \pre \p Res must be a generic virtual register with scalar or vector type.
392  /// \pre \p Op must be a generic virtual register with scalar or vector type.
393  ///
394  /// \return The newly created instruction.
395  template <typename DstTy, typename UseArgTy>
396  MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
397  return buildAnyExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
398  }
399  MachineInstrBuilder buildAnyExtOrTrunc(unsigned Res, unsigned Op);
400 
401  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
402  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
403  /// \p Op.
404  /// ///
405  /// \pre setBasicBlock or setMI must have been called.
406  /// \pre \p Res must be a generic virtual register with scalar or vector type.
407  /// \pre \p Op must be a generic virtual register with scalar or vector type.
408  ///
409  /// \return The newly created instruction.
410  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res,
411  unsigned Op);
412 
413  /// Build and insert an appropriate cast between two registers of equal size.
414  template <typename DstType, typename ArgType>
415  MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg) {
416  return buildCast(getDestFromArg(Res), getRegFromArg(Arg));
417  }
418  MachineInstrBuilder buildCast(unsigned Dst, unsigned Src);
419 
420  /// Build and insert G_BR \p Dest
421  ///
422  /// G_BR is an unconditional branch to \p Dest.
423  ///
424  /// \pre setBasicBlock or setMI must have been called.
425  ///
426  /// \return a MachineInstrBuilder for the newly created instruction.
428 
429  /// Build and insert G_BRCOND \p Tst, \p Dest
430  ///
431  /// G_BRCOND is a conditional branch to \p Dest.
432  ///
433  /// \pre setBasicBlock or setMI must have been called.
434  /// \pre \p Tst must be a generic virtual register with scalar
435  /// type. At the beginning of legalization, this will be a single
436  /// bit (s1). Targets with interesting flags registers may change
437  /// this. For a wider type, whether the branch is taken must only
438  /// depend on bit 0 (for now).
439  ///
440  /// \return The newly created instruction.
441  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &BB);
442 
443  /// Build and insert G_BRINDIRECT \p Tgt
444  ///
445  /// G_BRINDIRECT is an indirect branch to \p Tgt.
446  ///
447  /// \pre setBasicBlock or setMI must have been called.
448  /// \pre \p Tgt must be a generic virtual register with pointer type.
449  ///
450  /// \return a MachineInstrBuilder for the newly created instruction.
451  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
452 
453  /// Build and insert \p Res = G_CONSTANT \p Val
454  ///
455  /// G_CONSTANT is an integer constant with the specified size and value. \p
456  /// Val will be extended or truncated to the size of \p Reg.
457  ///
458  /// \pre setBasicBlock or setMI must have been called.
459  /// \pre \p Res must be a generic virtual register with scalar or pointer
460  /// type.
461  ///
462  /// \return The newly created instruction.
463  MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val);
464 
465  /// Build and insert \p Res = G_CONSTANT \p Val
466  ///
467  /// G_CONSTANT is an integer constant with the specified size and value.
468  ///
469  /// \pre setBasicBlock or setMI must have been called.
470  /// \pre \p Res must be a generic virtual register with scalar type.
471  ///
472  /// \return The newly created instruction.
473  MachineInstrBuilder buildConstant(unsigned Res, int64_t Val);
474 
475  template <typename DstType>
476  MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val) {
477  return buildConstant(getDestFromArg(Res), Val);
478  }
479  /// Build and insert \p Res = G_FCONSTANT \p Val
480  ///
481  /// G_FCONSTANT is a floating-point constant with the specified size and
482  /// value.
483  ///
484  /// \pre setBasicBlock or setMI must have been called.
485  /// \pre \p Res must be a generic virtual register with scalar type.
486  ///
487  /// \return The newly created instruction.
488  template <typename DstType>
489  MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val) {
490  return buildFConstant(getDestFromArg(Res), Val);
491  }
492  MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val);
493 
494  template <typename DstType>
495  MachineInstrBuilder buildFConstant(DstType &&Res, double Val) {
496  return buildFConstant(getDestFromArg(Res), Val);
497  }
498  MachineInstrBuilder buildFConstant(unsigned Res, double Val);
499 
500  /// Build and insert \p Res = COPY Op
501  ///
502  /// Register-to-register COPY sets \p Res to \p Op.
503  ///
504  /// \pre setBasicBlock or setMI must have been called.
505  ///
506  /// \return a MachineInstrBuilder for the newly created instruction.
507  MachineInstrBuilder buildCopy(unsigned Res, unsigned Op);
508  template <typename DstType, typename SrcType>
509  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510  return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511  }
512 
513  /// Build and insert `Res = G_LOAD Addr, MMO`.
514  ///
515  /// Loads the value stored at \p Addr. Puts the result in \p Res.
516  ///
517  /// \pre setBasicBlock or setMI must have been called.
518  /// \pre \p Res must be a generic virtual register.
519  /// \pre \p Addr must be a generic virtual register with pointer type.
520  ///
521  /// \return a MachineInstrBuilder for the newly created instruction.
522  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
523  MachineMemOperand &MMO);
524 
525  /// Build and insert `Res = <opcode> Addr, MMO`.
526  ///
527  /// Loads the value stored at \p Addr. Puts the result in \p Res.
528  ///
529  /// \pre setBasicBlock or setMI must have been called.
530  /// \pre \p Res must be a generic virtual register.
531  /// \pre \p Addr must be a generic virtual register with pointer type.
532  ///
533  /// \return a MachineInstrBuilder for the newly created instruction.
534  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
535  unsigned Addr, MachineMemOperand &MMO);
536 
537  /// Build and insert `G_STORE Val, Addr, MMO`.
538  ///
539  /// Stores the value \p Val to \p Addr.
540  ///
541  /// \pre setBasicBlock or setMI must have been called.
542  /// \pre \p Val must be a generic virtual register.
543  /// \pre \p Addr must be a generic virtual register with pointer type.
544  ///
545  /// \return a MachineInstrBuilder for the newly created instruction.
546  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
547  MachineMemOperand &MMO);
548 
549  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
550  ///
551  /// \pre setBasicBlock or setMI must have been called.
552  /// \pre \p Res and \p Src must be generic virtual registers.
553  ///
554  /// \return a MachineInstrBuilder for the newly created instruction.
555  MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
556 
557  /// Build and insert \p Res = IMPLICIT_DEF.
558  template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
559  return buildUndef(getDestFromArg(Res));
560  }
561  MachineInstrBuilder buildUndef(unsigned Dst);
562 
563  /// Build and insert instructions to put \p Ops together at the specified p
564  /// Indices to form a larger register.
565  ///
566  /// If the types of the input registers are uniform and cover the entirity of
567  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
568  /// followed by a sequence of G_INSERT instructions.
569  ///
570  /// \pre setBasicBlock or setMI must have been called.
571  /// \pre The final element of the sequence must not extend past the end of the
572  /// destination register.
573  /// \pre The bits defined by each Op (derived from index and scalar size) must
574  /// not overlap.
575  /// \pre \p Indices must be in ascending order of bit position.
576  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
577  ArrayRef<uint64_t> Indices);
578 
579  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
580  ///
581  /// G_MERGE_VALUES combines the input elements contiguously into a larger
582  /// register.
583  ///
584  /// \pre setBasicBlock or setMI must have been called.
585  /// \pre The entire register \p Res (and no more) must be covered by the input
586  /// registers.
587  /// \pre The type of all \p Ops registers must be identical.
588  ///
589  /// \return a MachineInstrBuilder for the newly created instruction.
590  MachineInstrBuilder buildMerge(unsigned Res, ArrayRef<unsigned> Ops);
591 
592  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
593  ///
594  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
595  ///
596  /// \pre setBasicBlock or setMI must have been called.
597  /// \pre The entire register \p Res (and no more) must be covered by the input
598  /// registers.
599  /// \pre The type of all \p Res registers must be identical.
600  ///
601  /// \return a MachineInstrBuilder for the newly created instruction.
602  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op);
603 
604  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
605  unsigned Op, unsigned Index);
606 
607  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
608  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
609  /// result register definition unless \p Reg is NoReg (== 0). The second
610  /// operand will be the intrinsic's ID.
611  ///
612  /// Callers are expected to add the required definitions and uses afterwards.
613  ///
614  /// \pre setBasicBlock or setMI must have been called.
615  ///
616  /// \return a MachineInstrBuilder for the newly created instruction.
617  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
618  bool HasSideEffects);
619 
620  /// Build and insert \p Res = G_FPTRUNC \p Op
621  ///
622  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
623  ///
624  /// \pre setBasicBlock or setMI must have been called.
625  /// \pre \p Res must be a generic virtual register with scalar or vector type.
626  /// \pre \p Op must be a generic virtual register with scalar or vector type.
627  /// \pre \p Res must be smaller than \p Op
628  ///
629  /// \return The newly created instruction.
630  template <typename DstType, typename SrcType>
631  MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src) {
632  return buildFPTrunc(getDestFromArg(Res), getRegFromArg(Src));
633  }
634  MachineInstrBuilder buildFPTrunc(unsigned Res, unsigned Op);
635 
636  /// Build and insert \p Res = G_TRUNC \p Op
637  ///
638  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
639  /// truncated independently before being packed into the destination.
640  ///
641  /// \pre setBasicBlock or setMI must have been called.
642  /// \pre \p Res must be a generic virtual register with scalar or vector type.
643  /// \pre \p Op must be a generic virtual register with scalar or vector type.
644  /// \pre \p Res must be smaller than \p Op
645  ///
646  /// \return The newly created instruction.
647  MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op);
648  template <typename DstType, typename SrcType>
649  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
650  return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
651  }
652 
653  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
654  ///
655  /// \pre setBasicBlock or setMI must have been called.
656 
657  /// \pre \p Res must be a generic virtual register with scalar or
658  /// vector type. Typically this starts as s1 or <N x s1>.
659  /// \pre \p Op0 and Op1 must be generic virtual registers with the
660  /// same number of elements as \p Res. If \p Res is a scalar,
661  /// \p Op0 must be either a scalar or pointer.
662  /// \pre \p Pred must be an integer predicate.
663  ///
664  /// \return a MachineInstrBuilder for the newly created instruction.
666  unsigned Res, unsigned Op0, unsigned Op1);
667 
668  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
669  ///
670  /// \pre setBasicBlock or setMI must have been called.
671 
672  /// \pre \p Res must be a generic virtual register with scalar or
673  /// vector type. Typically this starts as s1 or <N x s1>.
674  /// \pre \p Op0 and Op1 must be generic virtual registers with the
675  /// same number of elements as \p Res (or scalar, if \p Res is
676  /// scalar).
677  /// \pre \p Pred must be a floating-point predicate.
678  ///
679  /// \return a MachineInstrBuilder for the newly created instruction.
681  unsigned Res, unsigned Op0, unsigned Op1);
682 
683  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
684  ///
685  /// \pre setBasicBlock or setMI must have been called.
686  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
687  /// with the same type.
688  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
689  /// vector type. If vector then it must have the same number of
690  /// elements as the other parameters.
691  ///
692  /// \return a MachineInstrBuilder for the newly created instruction.
693  MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst,
694  unsigned Op0, unsigned Op1);
695 
696  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
697  /// \p Elt, \p Idx
698  ///
699  /// \pre setBasicBlock or setMI must have been called.
700  /// \pre \p Res and \p Val must be a generic virtual register
701  // with the same vector type.
702  /// \pre \p Elt and \p Idx must be a generic virtual register
703  /// with scalar type.
704  ///
705  /// \return The newly created instruction.
706  MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val,
707  unsigned Elt, unsigned Idx);
708 
709  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
710  ///
711  /// \pre setBasicBlock or setMI must have been called.
712  /// \pre \p Res must be a generic virtual register with scalar type.
713  /// \pre \p Val must be a generic virtual register with vector type.
714  /// \pre \p Idx must be a generic virtual register with scalar type.
715  ///
716  /// \return The newly created instruction.
717  MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val,
718  unsigned Idx);
719 
720  /// Build and insert `OldValRes = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
721  /// MMO`.
722  ///
723  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
724  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
725  /// Addr in \p Res.
726  ///
727  /// \pre setBasicBlock or setMI must have been called.
728  /// \pre \p OldValRes must be a generic virtual register of scalar type.
729  /// \pre \p Addr must be a generic virtual register with pointer type.
730  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
731  /// registers of the same type.
732  ///
733  /// \return a MachineInstrBuilder for the newly created instruction.
734  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
735  unsigned CmpVal, unsigned NewVal,
736  MachineMemOperand &MMO);
737 };
738 
739 /// A CRTP class that contains methods for building instructions that can
740 /// be constant folded. MachineIRBuilders that want to inherit from this will
741 /// need to implement buildBinaryOp (for constant folding binary ops).
742 /// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform
743 /// additional folding for Opc.
744 template <typename Base>
746  Base &base() { return static_cast<Base &>(*this); }
747 
748 public:
750  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
751  ///
752  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
753  /// truncated to their width.
754  ///
755  /// \pre setBasicBlock or setMI must have been called.
756  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
757  /// with the same (scalar or vector) type).
758  ///
759  /// \return a MachineInstrBuilder for the newly created instruction.
760 
761  MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) {
762  return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1);
763  }
764  template <typename DstTy, typename... UseArgsTy>
765  MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
766  unsigned Res = base().getDestFromArg(Ty);
767  return base().buildAdd(Res, (base().getRegFromArg(UseArgs))...);
768  }
769 
770  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
771  ///
772  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
773  /// truncated to their width.
774  ///
775  /// \pre setBasicBlock or setMI must have been called.
776  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
777  /// with the same (scalar or vector) type).
778  ///
779  /// \return a MachineInstrBuilder for the newly created instruction.
780 
781  MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) {
782  return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1);
783  }
784  template <typename DstTy, typename... UseArgsTy>
785  MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) {
786  unsigned Res = base().getDestFromArg(Ty);
787  return base().buildSub(Res, (base().getRegFromArg(UseArgs))...);
788  }
789 
790  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
791  ///
792  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
793  /// truncated to their width.
794  ///
795  /// \pre setBasicBlock or setMI must have been called.
796  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
797  /// with the same (scalar or vector) type).
798  ///
799  /// \return a MachineInstrBuilder for the newly created instruction.
800  MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) {
801  return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1);
802  }
803  template <typename DstTy, typename... UseArgsTy>
804  MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) {
805  unsigned Res = base().getDestFromArg(Ty);
806  return base().buildMul(Res, (base().getRegFromArg(UseArgs))...);
807  }
808 
809  /// Build and insert \p Res = G_AND \p Op0, \p Op1
810  ///
811  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
812  /// Op1.
813  ///
814  /// \pre setBasicBlock or setMI must have been called.
815  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
816  /// with the same (scalar or vector) type).
817  ///
818  /// \return a MachineInstrBuilder for the newly created instruction.
819 
820  MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) {
821  return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1);
822  }
823  template <typename DstTy, typename... UseArgsTy>
824  MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
825  unsigned Res = base().getDestFromArg(Ty);
826  return base().buildAnd(Res, (base().getRegFromArg(UseArgs))...);
827  }
828 
829  /// Build and insert \p Res = G_OR \p Op0, \p Op1
830  ///
831  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
832  /// Op1.
833  ///
834  /// \pre setBasicBlock or setMI must have been called.
835  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
836  /// with the same (scalar or vector) type).
837  ///
838  /// \return a MachineInstrBuilder for the newly created instruction.
839  MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) {
840  return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1);
841  }
842  template <typename DstTy, typename... UseArgsTy>
843  MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs) {
844  unsigned Res = base().getDestFromArg(Ty);
845  return base().buildOr(Res, (base().getRegFromArg(UseArgs))...);
846  }
847 };
848 
849 class MachineIRBuilder : public FoldableInstructionsBuilder<MachineIRBuilder> {
850 public:
853  MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst,
854  unsigned Src0, unsigned Src1) {
855  validateBinaryOp(Dst, Src0, Src1);
856  return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1);
857  }
859  /// DAG like Generic method for building arbitrary instructions as above.
860  /// \Opc opcode for the instruction.
861  /// \Ty Either LLT/TargetRegisterClass/unsigned types for Dst
862  /// \Args Variadic list of uses of types(unsigned/MachineInstrBuilder)
863  /// Uses of type MachineInstrBuilder will perform
864  /// getOperand(0).getReg() to convert to register.
865  template <typename DstTy, typename... UseArgsTy>
866  MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty,
867  UseArgsTy &&... Args) {
868  auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
869  addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
870  return MIB;
871  }
872 };
873 
874 } // End namespace llvm.
875 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_OR Op0, Op1.
uint64_t CallInst * C
MachineIRBuilderBase()=default
Some constructors for easy use.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildUndef(DstType &&Res)
Build and insert Res = IMPLICIT_DEF.
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_SEXT Op.
A CRTP class that contains methods for building instructions that can be constant folded...
unsigned Reg
void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args)
MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src)
Build and insert Res = G_FPTRUNC Op.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:862
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs)
A description of a memory reference used in the backend.
std::function< void(MachineInstr *)> InsertedInstr
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineIRBuilderBase(MachineInstr &MI)
MachineBasicBlock::iterator II
MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src)
MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg)
MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_ZEXT Op.
unsigned getRegFromArg(unsigned Reg)
TargetInstrInfo - Interface to description of machine instruction set.
MachineIRBuilderBase(MachineFunction &MF)
MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs)
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
unsigned getDestFromArg(const TargetRegisterClass *RC)
MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs)
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg)
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:885
DebugLoc DL
Debug location to be set to any instruction we create.
const DebugLoc & getDL()
Getter for DebugLoc.
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
void addUsesFromArgs(MachineInstrBuilder &MIB)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
unsigned getDestFromArg(unsigned Reg)
MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
MachineIRBuilderBase(const MachineIRBuilderState &BState)
MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst, unsigned Src0, unsigned Src1)
MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_ADD Op0, Op1.
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
unsigned getDestFromArg(LLT Ty)
MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
MachineInstrBuilder buildFConstant(DstType &&Res, double Val)
MachineRegisterInfo * getMRI()
Getter for MRI.
unsigned getRegFromArg(const MachineInstrBuilder &MIB)
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg)
Build and insert an appropriate cast between two registers of equal size.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs)
LLVM Value Representation.
Definition: Value.h:73
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1373
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
print Print MemDeps of function
IRTranslator LLVM IR MI
MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_MUL Op0, Op1.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs)
void addUseFromArg(MachineInstrBuilder &MIB, const MachineInstrBuilder &UseMIB)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val)
Helper class to build MachineInstr.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.