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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
70  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
71  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
72  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
73 
75  switch (Ty) {
76  case DstType::Ty_Reg:
77  MIB.addDef(Reg);
78  break;
79  case DstType::Ty_LLT:
80  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
81  break;
82  case DstType::Ty_RC:
83  MIB.addDef(MRI.createVirtualRegister(RC));
84  break;
85  }
86  }
87 
89  switch (Ty) {
90  case DstType::Ty_RC:
91  return LLT{};
92  case DstType::Ty_LLT:
93  return LLTTy;
94  case DstType::Ty_Reg:
95  return MRI.getType(Reg);
96  }
97  llvm_unreachable("Unrecognised DstOp::DstType enum");
98  }
99 
100  Register getReg() const {
101  assert(Ty == DstType::Ty_Reg && "Not a register");
102  return Reg;
103  }
104 
106  switch (Ty) {
107  case DstType::Ty_RC:
108  return RC;
109  default:
110  llvm_unreachable("Not a RC Operand");
111  }
112  }
113 
114  DstType getDstOpKind() const { return Ty; }
115 
116 private:
117  DstType Ty;
118 };
119 
120 class SrcOp {
121  union {
125  int64_t Imm;
126  };
127 
128 public:
129  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
130  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
132  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
133  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
134  /// Use of registers held in unsigned integer variables (or more rarely signed
135  /// integers) is no longer permitted to avoid ambiguity with upcoming support
136  /// for immediates.
137  SrcOp(unsigned) = delete;
138  SrcOp(int) = delete;
139  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
141 
142  void addSrcToMIB(MachineInstrBuilder &MIB) const {
143  switch (Ty) {
144  case SrcType::Ty_Predicate:
145  MIB.addPredicate(Pred);
146  break;
147  case SrcType::Ty_Reg:
148  MIB.addUse(Reg);
149  break;
150  case SrcType::Ty_MIB:
151  MIB.addUse(SrcMIB->getOperand(0).getReg());
152  break;
153  case SrcType::Ty_Imm:
154  MIB.addImm(Imm);
155  break;
156  }
157  }
158 
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  case SrcType::Ty_Imm:
163  llvm_unreachable("Not a register operand");
164  case SrcType::Ty_Reg:
165  return MRI.getType(Reg);
166  case SrcType::Ty_MIB:
167  return MRI.getType(SrcMIB->getOperand(0).getReg());
168  }
169  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
170  }
171 
172  Register getReg() const {
173  switch (Ty) {
174  case SrcType::Ty_Predicate:
175  case SrcType::Ty_Imm:
176  llvm_unreachable("Not a register operand");
177  case SrcType::Ty_Reg:
178  return Reg;
179  case SrcType::Ty_MIB:
180  return SrcMIB->getOperand(0).getReg();
181  }
182  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
183  }
184 
186  switch (Ty) {
187  case SrcType::Ty_Predicate:
188  return Pred;
189  default:
190  llvm_unreachable("Not a register operand");
191  }
192  }
193 
194  int64_t getImm() const {
195  switch (Ty) {
196  case SrcType::Ty_Imm:
197  return Imm;
198  default:
199  llvm_unreachable("Not an immediate");
200  }
201  }
202 
203  SrcType getSrcOpKind() const { return Ty; }
204 
205 private:
206  SrcType Ty;
207 };
208 
209 class FlagsOp {
210  Optional<unsigned> Flags;
211 
212 public:
213  explicit FlagsOp(unsigned F) : Flags(F) {}
214  FlagsOp() : Flags(None) {}
215  Optional<unsigned> getFlags() const { return Flags; }
216 };
217 /// Helper class to build MachineInstr.
218 /// It keeps internally the insertion point and debug location for all
219 /// the new instructions we want to create.
220 /// This information can be modify via the related setters.
222 
223  MachineIRBuilderState State;
224 
225 protected:
226  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
227 
228  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
229  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
230 
231  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
232  const LLT &Op1Ty);
233  void recordInsertion(MachineInstr *MI) const;
234 
235 public:
236  /// Some constructors for easy use.
237  MachineIRBuilder() = default;
240  setInstr(MI);
241  }
242 
243  virtual ~MachineIRBuilder() = default;
244 
245  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
246 
248  assert(State.TII && "TargetInstrInfo is not set");
249  return *State.TII;
250  }
251 
252  /// Getter for the function we currently build.
254  assert(State.MF && "MachineFunction is not set");
255  return *State.MF;
256  }
257 
258  const MachineFunction &getMF() const {
259  assert(State.MF && "MachineFunction is not set");
260  return *State.MF;
261  }
262 
263  const DataLayout &getDataLayout() const {
264  return getMF().getFunction().getParent()->getDataLayout();
265  }
266 
267  /// Getter for DebugLoc
268  const DebugLoc &getDL() { return State.DL; }
269 
270  /// Getter for MRI
271  MachineRegisterInfo *getMRI() { return State.MRI; }
272  const MachineRegisterInfo *getMRI() const { return State.MRI; }
273 
274  /// Getter for the State
275  MachineIRBuilderState &getState() { return State; }
276 
277  /// Getter for the basic block we currently build.
278  const MachineBasicBlock &getMBB() const {
279  assert(State.MBB && "MachineBasicBlock is not set");
280  return *State.MBB;
281  }
282 
284  return const_cast<MachineBasicBlock &>(
285  const_cast<const MachineIRBuilder *>(this)->getMBB());
286  }
287 
288  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
289  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
290 
291  /// Current insertion point for new instructions.
293 
294  /// Set the insertion point before the specified position.
295  /// \pre MBB must be in getMF().
296  /// \pre II must be a valid iterator in MBB.
298  /// @}
299 
300  void setCSEInfo(GISelCSEInfo *Info);
301 
302  /// \name Setters for the insertion point.
303  /// @{
304  /// Set the MachineFunction where to build instructions.
305  void setMF(MachineFunction &MF);
306 
307  /// Set the insertion point to the end of \p MBB.
308  /// \pre \p MBB must be contained by getMF().
309  void setMBB(MachineBasicBlock &MBB);
310 
311  /// Set the insertion point to before MI.
312  /// \pre MI must be in getMF().
313  void setInstr(MachineInstr &MI);
314  /// @}
315 
316  void setChangeObserver(GISelChangeObserver &Observer);
317  void stopObservingChanges();
318  /// @}
319 
320  /// Set the debug location to \p DL for all the next build instructions.
321  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
322 
323  /// Get the current instruction's debug location.
324  DebugLoc getDebugLoc() { return State.DL; }
325 
326  /// Build and insert <empty> = \p Opcode <empty>.
327  /// The insertion point is the one set by the last call of either
328  /// setBasicBlock or setMI.
329  ///
330  /// \pre setBasicBlock or setMI must have been called.
331  ///
332  /// \return a MachineInstrBuilder for the newly created instruction.
333  MachineInstrBuilder buildInstr(unsigned Opcode);
334 
335  /// Build but don't insert <empty> = \p Opcode <empty>.
336  ///
337  /// \pre setMF, setBasicBlock or setMI must have been called.
338  ///
339  /// \return a MachineInstrBuilder for the newly created instruction.
340  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
341 
342  /// Insert an existing instruction at the insertion point.
343  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
344 
345  /// Build and insert a DBG_VALUE instruction expressing the fact that the
346  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
347  MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
348  const MDNode *Expr);
349 
350  /// Build and insert a DBG_VALUE instruction expressing the fact that the
351  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
352  /// Expr).
353  MachineInstrBuilder buildIndirectDbgValue(Register Reg,
354  const MDNode *Variable,
355  const MDNode *Expr);
356 
357  /// Build and insert a DBG_VALUE instruction expressing the fact that the
358  /// associated \p Variable lives in the stack slot specified by \p FI
359  /// (suitably modified by \p Expr).
360  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
361  const MDNode *Expr);
362 
363  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
364  /// given by \p C (suitably modified by \p Expr).
365  MachineInstrBuilder buildConstDbgValue(const Constant &C,
366  const MDNode *Variable,
367  const MDNode *Expr);
368 
369  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
370  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
371  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
372 
373  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
374  ///
375  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
376  /// the allocated memory into \p Res.
377  /// \pre setBasicBlock or setMI must have been called.
378  /// \pre \p Res must be a generic virtual register with pointer type.
379  ///
380  /// \return a MachineInstrBuilder for the newly created instruction.
381  MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
382  unsigned Align);
383 
384  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
385  ///
386  /// G_FRAME_INDEX materializes the address of an alloca value or other
387  /// stack-based object.
388  ///
389  /// \pre setBasicBlock or setMI must have been called.
390  /// \pre \p Res must be a generic virtual register with pointer type.
391  ///
392  /// \return a MachineInstrBuilder for the newly created instruction.
393  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
394 
395  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
396  ///
397  /// G_GLOBAL_VALUE materializes the address of the specified global
398  /// into \p Res.
399  ///
400  /// \pre setBasicBlock or setMI must have been called.
401  /// \pre \p Res must be a generic virtual register with pointer type
402  /// in the same address space as \p GV.
403  ///
404  /// \return a MachineInstrBuilder for the newly created instruction.
405  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
406 
407  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
408  ///
409  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
410  /// storing the resulting pointer in \p Res.
411  ///
412  /// \pre setBasicBlock or setMI must have been called.
413  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
414  /// type.
415  /// \pre \p Op1 must be a generic virtual register with scalar type.
416  ///
417  /// \return a MachineInstrBuilder for the newly created instruction.
418  MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0,
419  const SrcOp &Op1);
420 
421  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
422  ///
423  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
424  /// storing the resulting pointer in \p Res. If \p Value is zero then no
425  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
426  /// \p Res.
427  ///
428  /// \pre setBasicBlock or setMI must have been called.
429  /// \pre \p Op0 must be a generic virtual register with pointer type.
430  /// \pre \p ValueTy must be a scalar type.
431  /// \pre \p Res must be 0. This is to detect confusion between
432  /// materializeGEP() and buildGEP().
433  /// \post \p Res will either be a new generic virtual register of the same
434  /// type as \p Op0 or \p Op0 itself.
435  ///
436  /// \return a MachineInstrBuilder for the newly created instruction.
437  Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
438  const LLT &ValueTy,
439  uint64_t Value);
440 
441  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
442  ///
443  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
444  /// pointer properties. This has the effect of rounding the address *down* to
445  /// a specified alignment in bits.
446  ///
447  /// \pre setBasicBlock or setMI must have been called.
448  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
449  /// type.
450  /// \pre \p NumBits must be an integer representing the number of low bits to
451  /// be cleared in \p Op0.
452  ///
453  /// \return a MachineInstrBuilder for the newly created instruction.
454  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
455  uint32_t NumBits);
456 
457  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
458  ///
459  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
460  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
461  ///
462  /// \pre setBasicBlock or setMI must have been called.
463  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
464  /// same scalar type.
465  ////\pre \p CarryOut must be generic virtual register with scalar type
466  ///(typically s1)
467  ///
468  /// \return The newly created instruction.
469  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
470  const SrcOp &Op0, const SrcOp &Op1);
471 
472  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
473  /// \p Op1, \p CarryIn
474  ///
475  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
476  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
477  /// arithmetic.
478  ///
479  /// \pre setBasicBlock or setMI must have been called.
480  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
481  /// with the same scalar type.
482  /// \pre \p CarryOut and \p CarryIn must be generic virtual
483  /// registers with the same scalar type (typically s1)
484  ///
485  /// \return The newly created instruction.
486  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
487  const SrcOp &Op0, const SrcOp &Op1,
488  const SrcOp &CarryIn);
489 
490  /// Build and insert \p Res = G_ANYEXT \p Op0
491  ///
492  /// G_ANYEXT produces a register of the specified width, with bits 0 to
493  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
494  /// (i.e. this is neither zero nor sign-extension). For a vector register,
495  /// each element is extended individually.
496  ///
497  /// \pre setBasicBlock or setMI must have been called.
498  /// \pre \p Res must be a generic virtual register with scalar or vector type.
499  /// \pre \p Op must be a generic virtual register with scalar or vector type.
500  /// \pre \p Op must be smaller than \p Res
501  ///
502  /// \return The newly created instruction.
503 
504  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
505 
506  /// Build and insert \p Res = G_SEXT \p Op
507  ///
508  /// G_SEXT produces a register of the specified width, with bits 0 to
509  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
510  /// high bit of \p Op (i.e. 2s-complement sign extended).
511  ///
512  /// \pre setBasicBlock or setMI must have been called.
513  /// \pre \p Res must be a generic virtual register with scalar or vector type.
514  /// \pre \p Op must be a generic virtual register with scalar or vector type.
515  /// \pre \p Op must be smaller than \p Res
516  ///
517  /// \return The newly created instruction.
518  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
519 
520  /// Build and insert a G_PTRTOINT instruction.
521  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
522  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
523  }
524 
525  /// Build and insert a G_INTTOPTR instruction.
526  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
527  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
528  }
529 
530  /// Build and insert \p Dst = G_BITCAST \p Src
531  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
532  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
533  }
534 
535  /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
537  return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
538  }
539 
540  /// \return The opcode of the extension the target wants to use for boolean
541  /// values.
542  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
543 
544  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
545  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
546  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
547  bool IsFP);
548 
549  /// Build and insert \p Res = G_ZEXT \p Op
550  ///
551  /// G_ZEXT produces a register of the specified width, with bits 0 to
552  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
553  /// register, each element is extended individually.
554  ///
555  /// \pre setBasicBlock or setMI must have been called.
556  /// \pre \p Res must be a generic virtual register with scalar or vector type.
557  /// \pre \p Op must be a generic virtual register with scalar or vector type.
558  /// \pre \p Op must be smaller than \p Res
559  ///
560  /// \return The newly created instruction.
561  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
562 
563  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
564  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
565  /// ///
566  /// \pre setBasicBlock or setMI must have been called.
567  /// \pre \p Res must be a generic virtual register with scalar or vector type.
568  /// \pre \p Op must be a generic virtual register with scalar or vector type.
569  ///
570  /// \return The newly created instruction.
571  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
572 
573  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
574  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
575  /// ///
576  /// \pre setBasicBlock or setMI must have been called.
577  /// \pre \p Res must be a generic virtual register with scalar or vector type.
578  /// \pre \p Op must be a generic virtual register with scalar or vector type.
579  ///
580  /// \return The newly created instruction.
581  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
582 
583  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
584  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
585  /// ///
586  /// \pre setBasicBlock or setMI must have been called.
587  /// \pre \p Res must be a generic virtual register with scalar or vector type.
588  /// \pre \p Op must be a generic virtual register with scalar or vector type.
589  ///
590  /// \return The newly created instruction.
591  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
592 
593  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
594  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
595  /// \p Op.
596  /// ///
597  /// \pre setBasicBlock or setMI must have been called.
598  /// \pre \p Res must be a generic virtual register with scalar or vector type.
599  /// \pre \p Op must be a generic virtual register with scalar or vector type.
600  ///
601  /// \return The newly created instruction.
602  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
603  const SrcOp &Op);
604 
605  /// Build and insert an appropriate cast between two registers of equal size.
606  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
607 
608  /// Build and insert G_BR \p Dest
609  ///
610  /// G_BR is an unconditional branch to \p Dest.
611  ///
612  /// \pre setBasicBlock or setMI must have been called.
613  ///
614  /// \return a MachineInstrBuilder for the newly created instruction.
615  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
616 
617  /// Build and insert G_BRCOND \p Tst, \p Dest
618  ///
619  /// G_BRCOND is a conditional branch to \p Dest.
620  ///
621  /// \pre setBasicBlock or setMI must have been called.
622  /// \pre \p Tst must be a generic virtual register with scalar
623  /// type. At the beginning of legalization, this will be a single
624  /// bit (s1). Targets with interesting flags registers may change
625  /// this. For a wider type, whether the branch is taken must only
626  /// depend on bit 0 (for now).
627  ///
628  /// \return The newly created instruction.
629  MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
630 
631  /// Build and insert G_BRINDIRECT \p Tgt
632  ///
633  /// G_BRINDIRECT is an indirect branch to \p Tgt.
634  ///
635  /// \pre setBasicBlock or setMI must have been called.
636  /// \pre \p Tgt must be a generic virtual register with pointer type.
637  ///
638  /// \return a MachineInstrBuilder for the newly created instruction.
639  MachineInstrBuilder buildBrIndirect(Register Tgt);
640 
641  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
642  ///
643  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
644  /// jump table index \p JTI and index \p IndexReg
645  ///
646  /// \pre setBasicBlock or setMI must have been called.
647  /// \pre \p TablePtr must be a generic virtual register with pointer type.
648  /// \pre \p JTI must be be a jump table index.
649  /// \pre \p IndexReg must be a generic virtual register with pointer type.
650  ///
651  /// \return a MachineInstrBuilder for the newly created instruction.
652  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
653  Register IndexReg);
654 
655  /// Build and insert \p Res = G_CONSTANT \p Val
656  ///
657  /// G_CONSTANT is an integer constant with the specified size and value. \p
658  /// Val will be extended or truncated to the size of \p Reg.
659  ///
660  /// \pre setBasicBlock or setMI must have been called.
661  /// \pre \p Res must be a generic virtual register with scalar or pointer
662  /// type.
663  ///
664  /// \return The newly created instruction.
665  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
666  const ConstantInt &Val);
667 
668  /// Build and insert \p Res = G_CONSTANT \p Val
669  ///
670  /// G_CONSTANT is an integer constant with the specified size and value.
671  ///
672  /// \pre setBasicBlock or setMI must have been called.
673  /// \pre \p Res must be a generic virtual register with scalar type.
674  ///
675  /// \return The newly created instruction.
676  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
677  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
678 
679  /// Build and insert \p Res = G_FCONSTANT \p Val
680  ///
681  /// G_FCONSTANT is a floating-point constant with the specified size and
682  /// value.
683  ///
684  /// \pre setBasicBlock or setMI must have been called.
685  /// \pre \p Res must be a generic virtual register with scalar type.
686  ///
687  /// \return The newly created instruction.
688  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
689  const ConstantFP &Val);
690 
691  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
692  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
693 
694  /// Build and insert \p Res = COPY Op
695  ///
696  /// Register-to-register COPY sets \p Res to \p Op.
697  ///
698  /// \pre setBasicBlock or setMI must have been called.
699  ///
700  /// \return a MachineInstrBuilder for the newly created instruction.
701  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
702 
703  /// Build and insert `Res = G_LOAD Addr, MMO`.
704  ///
705  /// Loads the value stored at \p Addr. Puts the result in \p Res.
706  ///
707  /// \pre setBasicBlock or setMI must have been called.
708  /// \pre \p Res must be a generic virtual register.
709  /// \pre \p Addr must be a generic virtual register with pointer type.
710  ///
711  /// \return a MachineInstrBuilder for the newly created instruction.
712  MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
713  MachineMemOperand &MMO);
714 
715  /// Build and insert `Res = <opcode> Addr, MMO`.
716  ///
717  /// Loads the value stored at \p Addr. Puts the result in \p Res.
718  ///
719  /// \pre setBasicBlock or setMI must have been called.
720  /// \pre \p Res must be a generic virtual register.
721  /// \pre \p Addr must be a generic virtual register with pointer type.
722  ///
723  /// \return a MachineInstrBuilder for the newly created instruction.
724  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
725  const SrcOp &Addr, MachineMemOperand &MMO);
726 
727  /// Build and insert `G_STORE Val, Addr, MMO`.
728  ///
729  /// Stores the value \p Val to \p Addr.
730  ///
731  /// \pre setBasicBlock or setMI must have been called.
732  /// \pre \p Val must be a generic virtual register.
733  /// \pre \p Addr must be a generic virtual register with pointer type.
734  ///
735  /// \return a MachineInstrBuilder for the newly created instruction.
736  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
737  MachineMemOperand &MMO);
738 
739  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
740  ///
741  /// \pre setBasicBlock or setMI must have been called.
742  /// \pre \p Res and \p Src must be generic virtual registers.
743  ///
744  /// \return a MachineInstrBuilder for the newly created instruction.
745  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
746 
747  /// Build and insert \p Res = IMPLICIT_DEF.
748  MachineInstrBuilder buildUndef(const DstOp &Res);
749 
750  /// Build and insert instructions to put \p Ops together at the specified p
751  /// Indices to form a larger register.
752  ///
753  /// If the types of the input registers are uniform and cover the entirity of
754  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
755  /// followed by a sequence of G_INSERT instructions.
756  ///
757  /// \pre setBasicBlock or setMI must have been called.
758  /// \pre The final element of the sequence must not extend past the end of the
759  /// destination register.
760  /// \pre The bits defined by each Op (derived from index and scalar size) must
761  /// not overlap.
762  /// \pre \p Indices must be in ascending order of bit position.
763  void buildSequence(Register Res, ArrayRef<Register> Ops,
764  ArrayRef<uint64_t> Indices);
765 
766  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
767  ///
768  /// G_MERGE_VALUES combines the input elements contiguously into a larger
769  /// register.
770  ///
771  /// \pre setBasicBlock or setMI must have been called.
772  /// \pre The entire register \p Res (and no more) must be covered by the input
773  /// registers.
774  /// \pre The type of all \p Ops registers must be identical.
775  ///
776  /// \return a MachineInstrBuilder for the newly created instruction.
777  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
778 
779  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
780  ///
781  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
782  ///
783  /// \pre setBasicBlock or setMI must have been called.
784  /// \pre The entire register \p Res (and no more) must be covered by the input
785  /// registers.
786  /// \pre The type of all \p Res registers must be identical.
787  ///
788  /// \return a MachineInstrBuilder for the newly created instruction.
789  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
790  MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
791 
792  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
793  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
794 
795  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
796  ///
797  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
798  /// \pre setBasicBlock or setMI must have been called.
799  /// \pre The entire register \p Res (and no more) must be covered by the
800  /// input scalar registers.
801  /// \pre The type of all \p Ops registers must be identical.
802  ///
803  /// \return a MachineInstrBuilder for the newly created instruction.
804  MachineInstrBuilder buildBuildVector(const DstOp &Res,
805  ArrayRef<Register> Ops);
806 
807  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
808  /// the number of elements
809  MachineInstrBuilder buildSplatVector(const DstOp &Res,
810  const SrcOp &Src);
811 
812  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
813  ///
814  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
815  /// which have types larger than the destination vector element type, and
816  /// truncates the values to fit.
817  ///
818  /// If the operands given are already the same size as the vector elt type,
819  /// then this method will instead create a G_BUILD_VECTOR instruction.
820  ///
821  /// \pre setBasicBlock or setMI must have been called.
822  /// \pre The type of all \p Ops registers must be identical.
823  ///
824  /// \return a MachineInstrBuilder for the newly created instruction.
825  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
826  ArrayRef<Register> Ops);
827 
828  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
829  ///
830  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
831  /// vectors.
832  ///
833  /// \pre setBasicBlock or setMI must have been called.
834  /// \pre The entire register \p Res (and no more) must be covered by the input
835  /// registers.
836  /// \pre The type of all source operands must be identical.
837  ///
838  /// \return a MachineInstrBuilder for the newly created instruction.
839  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
840  ArrayRef<Register> Ops);
841 
842  MachineInstrBuilder buildInsert(Register Res, Register Src,
843  Register Op, unsigned Index);
844 
845  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
846  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
847  /// result register definition unless \p Reg is NoReg (== 0). The second
848  /// operand will be the intrinsic's ID.
849  ///
850  /// Callers are expected to add the required definitions and uses afterwards.
851  ///
852  /// \pre setBasicBlock or setMI must have been called.
853  ///
854  /// \return a MachineInstrBuilder for the newly created instruction.
856  bool HasSideEffects);
857  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
858  bool HasSideEffects);
859 
860  /// Build and insert \p Res = G_FPTRUNC \p Op
861  ///
862  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
863  ///
864  /// \pre setBasicBlock or setMI must have been called.
865  /// \pre \p Res must be a generic virtual register with scalar or vector type.
866  /// \pre \p Op must be a generic virtual register with scalar or vector type.
867  /// \pre \p Res must be smaller than \p Op
868  ///
869  /// \return The newly created instruction.
870  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
871 
872  /// Build and insert \p Res = G_TRUNC \p Op
873  ///
874  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
875  /// truncated independently before being packed into the destination.
876  ///
877  /// \pre setBasicBlock or setMI must have been called.
878  /// \pre \p Res must be a generic virtual register with scalar or vector type.
879  /// \pre \p Op must be a generic virtual register with scalar or vector type.
880  /// \pre \p Res must be smaller than \p Op
881  ///
882  /// \return The newly created instruction.
883  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
884 
885  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
886  ///
887  /// \pre setBasicBlock or setMI must have been called.
888 
889  /// \pre \p Res must be a generic virtual register with scalar or
890  /// vector type. Typically this starts as s1 or <N x s1>.
891  /// \pre \p Op0 and Op1 must be generic virtual registers with the
892  /// same number of elements as \p Res. If \p Res is a scalar,
893  /// \p Op0 must be either a scalar or pointer.
894  /// \pre \p Pred must be an integer predicate.
895  ///
896  /// \return a MachineInstrBuilder for the newly created instruction.
897  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
898  const SrcOp &Op0, const SrcOp &Op1);
899 
900  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
901  ///
902  /// \pre setBasicBlock or setMI must have been called.
903 
904  /// \pre \p Res must be a generic virtual register with scalar or
905  /// vector type. Typically this starts as s1 or <N x s1>.
906  /// \pre \p Op0 and Op1 must be generic virtual registers with the
907  /// same number of elements as \p Res (or scalar, if \p Res is
908  /// scalar).
909  /// \pre \p Pred must be a floating-point predicate.
910  ///
911  /// \return a MachineInstrBuilder for the newly created instruction.
912  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
913  const SrcOp &Op0, const SrcOp &Op1,
914  Optional<unsigned> Flags = None);
915 
916  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
917  ///
918  /// \pre setBasicBlock or setMI must have been called.
919  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
920  /// with the same type.
921  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
922  /// vector type. If vector then it must have the same number of
923  /// elements as the other parameters.
924  ///
925  /// \return a MachineInstrBuilder for the newly created instruction.
926  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
927  const SrcOp &Op0, const SrcOp &Op1,
928  Optional<unsigned> Flags = None);
929 
930  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
931  /// \p Elt, \p Idx
932  ///
933  /// \pre setBasicBlock or setMI must have been called.
934  /// \pre \p Res and \p Val must be a generic virtual register
935  // with the same vector type.
936  /// \pre \p Elt and \p Idx must be a generic virtual register
937  /// with scalar type.
938  ///
939  /// \return The newly created instruction.
940  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
941  const SrcOp &Val,
942  const SrcOp &Elt,
943  const SrcOp &Idx);
944 
945  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
946  ///
947  /// \pre setBasicBlock or setMI must have been called.
948  /// \pre \p Res must be a generic virtual register with scalar type.
949  /// \pre \p Val must be a generic virtual register with vector type.
950  /// \pre \p Idx must be a generic virtual register with scalar type.
951  ///
952  /// \return The newly created instruction.
953  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
954  const SrcOp &Val,
955  const SrcOp &Idx);
956 
957  /// Build and insert `OldValRes<def>, SuccessRes<def> =
958  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
959  ///
960  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
961  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
962  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
963  ///
964  /// \pre setBasicBlock or setMI must have been called.
965  /// \pre \p OldValRes must be a generic virtual register of scalar type.
966  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
967  /// will be assigned 0 on failure and 1 on success.
968  /// \pre \p Addr must be a generic virtual register with pointer type.
969  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
970  /// registers of the same type.
971  ///
972  /// \return a MachineInstrBuilder for the newly created instruction.
974  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
975  Register Addr, Register CmpVal, Register NewVal,
976  MachineMemOperand &MMO);
977 
978  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
979  /// MMO`.
980  ///
981  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
982  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
983  /// Addr in \p Res.
984  ///
985  /// \pre setBasicBlock or setMI must have been called.
986  /// \pre \p OldValRes must be a generic virtual register of scalar type.
987  /// \pre \p Addr must be a generic virtual register with pointer type.
988  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
989  /// registers of the same type.
990  ///
991  /// \return a MachineInstrBuilder for the newly created instruction.
992  MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
993  Register CmpVal, Register NewVal,
994  MachineMemOperand &MMO);
995 
996  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
997  ///
998  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
999  /// original value from \p Addr in \p OldValRes. The modification is
1000  /// determined by the opcode.
1001  ///
1002  /// \pre setBasicBlock or setMI must have been called.
1003  /// \pre \p OldValRes must be a generic virtual register.
1004  /// \pre \p Addr must be a generic virtual register with pointer type.
1005  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1006  /// same type.
1007  ///
1008  /// \return a MachineInstrBuilder for the newly created instruction.
1009  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1010  const SrcOp &Addr, const SrcOp &Val,
1011  MachineMemOperand &MMO);
1012 
1013  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1014  ///
1015  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1016  /// value from \p Addr in \p OldValRes.
1017  ///
1018  /// \pre setBasicBlock or setMI must have been called.
1019  /// \pre \p OldValRes must be a generic virtual register.
1020  /// \pre \p Addr must be a generic virtual register with pointer type.
1021  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1022  /// same type.
1023  ///
1024  /// \return a MachineInstrBuilder for the newly created instruction.
1025  MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1026  Register Val, MachineMemOperand &MMO);
1027 
1028  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1029  ///
1030  /// Atomically replace the value at \p Addr with the addition of \p Val and
1031  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1032  ///
1033  /// \pre setBasicBlock or setMI must have been called.
1034  /// \pre \p OldValRes must be a generic virtual register.
1035  /// \pre \p Addr must be a generic virtual register with pointer type.
1036  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1037  /// same type.
1038  ///
1039  /// \return a MachineInstrBuilder for the newly created instruction.
1040  MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1041  Register Val, MachineMemOperand &MMO);
1042 
1043  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1044  ///
1045  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1046  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1047  ///
1048  /// \pre setBasicBlock or setMI must have been called.
1049  /// \pre \p OldValRes must be a generic virtual register.
1050  /// \pre \p Addr must be a generic virtual register with pointer type.
1051  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1052  /// same type.
1053  ///
1054  /// \return a MachineInstrBuilder for the newly created instruction.
1055  MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1056  Register Val, MachineMemOperand &MMO);
1057 
1058  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1059  ///
1060  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1061  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1062  ///
1063  /// \pre setBasicBlock or setMI must have been called.
1064  /// \pre \p OldValRes must be a generic virtual register.
1065  /// \pre \p Addr must be a generic virtual register with pointer type.
1066  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1067  /// same type.
1068  ///
1069  /// \return a MachineInstrBuilder for the newly created instruction.
1070  MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1071  Register Val, MachineMemOperand &MMO);
1072 
1073  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1074  ///
1075  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1076  /// and the original value. Puts the original value from \p Addr in \p
1077  /// OldValRes.
1078  ///
1079  /// \pre setBasicBlock or setMI must have been called.
1080  /// \pre \p OldValRes must be a generic virtual register.
1081  /// \pre \p Addr must be a generic virtual register with pointer type.
1082  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1083  /// same type.
1084  ///
1085  /// \return a MachineInstrBuilder for the newly created instruction.
1086  MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1087  Register Val, MachineMemOperand &MMO);
1088 
1089  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1090  ///
1091  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1092  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1093  ///
1094  /// \pre setBasicBlock or setMI must have been called.
1095  /// \pre \p OldValRes must be a generic virtual register.
1096  /// \pre \p Addr must be a generic virtual register with pointer type.
1097  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1098  /// same type.
1099  ///
1100  /// \return a MachineInstrBuilder for the newly created instruction.
1101  MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1102  Register Val, MachineMemOperand &MMO);
1103 
1104  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1105  ///
1106  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1107  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1108  ///
1109  /// \pre setBasicBlock or setMI must have been called.
1110  /// \pre \p OldValRes must be a generic virtual register.
1111  /// \pre \p Addr must be a generic virtual register with pointer type.
1112  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1113  /// same type.
1114  ///
1115  /// \return a MachineInstrBuilder for the newly created instruction.
1116  MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1117  Register Val, MachineMemOperand &MMO);
1118 
1119  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1120  ///
1121  /// Atomically replace the value at \p Addr with the signed maximum of \p
1122  /// Val and the original value. Puts the original value from \p Addr in \p
1123  /// OldValRes.
1124  ///
1125  /// \pre setBasicBlock or setMI must have been called.
1126  /// \pre \p OldValRes must be a generic virtual register.
1127  /// \pre \p Addr must be a generic virtual register with pointer type.
1128  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1129  /// same type.
1130  ///
1131  /// \return a MachineInstrBuilder for the newly created instruction.
1132  MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1133  Register Val, MachineMemOperand &MMO);
1134 
1135  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1136  ///
1137  /// Atomically replace the value at \p Addr with the signed minimum of \p
1138  /// Val and the original value. Puts the original value from \p Addr in \p
1139  /// OldValRes.
1140  ///
1141  /// \pre setBasicBlock or setMI must have been called.
1142  /// \pre \p OldValRes must be a generic virtual register.
1143  /// \pre \p Addr must be a generic virtual register with pointer type.
1144  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1145  /// same type.
1146  ///
1147  /// \return a MachineInstrBuilder for the newly created instruction.
1148  MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1149  Register Val, MachineMemOperand &MMO);
1150 
1151  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1152  ///
1153  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1154  /// Val and the original value. Puts the original value from \p Addr in \p
1155  /// OldValRes.
1156  ///
1157  /// \pre setBasicBlock or setMI must have been called.
1158  /// \pre \p OldValRes must be a generic virtual register.
1159  /// \pre \p Addr must be a generic virtual register with pointer type.
1160  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1161  /// same type.
1162  ///
1163  /// \return a MachineInstrBuilder for the newly created instruction.
1164  MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1165  Register Val, MachineMemOperand &MMO);
1166 
1167  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1168  ///
1169  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1170  /// Val and the original value. Puts the original value from \p Addr in \p
1171  /// OldValRes.
1172  ///
1173  /// \pre setBasicBlock or setMI must have been called.
1174  /// \pre \p OldValRes must be a generic virtual register.
1175  /// \pre \p Addr must be a generic virtual register with pointer type.
1176  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1177  /// same type.
1178  ///
1179  /// \return a MachineInstrBuilder for the newly created instruction.
1180  MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1181  Register Val, MachineMemOperand &MMO);
1182 
1183  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1184  MachineInstrBuilder buildAtomicRMWFAdd(
1185  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1186  MachineMemOperand &MMO);
1187 
1188  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1189  MachineInstrBuilder buildAtomicRMWFSub(
1190  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1191  MachineMemOperand &MMO);
1192 
1193  /// Build and insert `G_FENCE Ordering, Scope`.
1194  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1195 
1196  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1197  ///
1198  /// G_BLOCK_ADDR computes the address of a basic block.
1199  ///
1200  /// \pre setBasicBlock or setMI must have been called.
1201  /// \pre \p Res must be a generic virtual register of a pointer type.
1202  ///
1203  /// \return The newly created instruction.
1204  MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1205 
1206  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1207  ///
1208  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1209  /// truncated to their width.
1210  ///
1211  /// \pre setBasicBlock or setMI must have been called.
1212  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1213  /// with the same (scalar or vector) type).
1214  ///
1215  /// \return a MachineInstrBuilder for the newly created instruction.
1216 
1217  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1218  const SrcOp &Src1,
1219  Optional<unsigned> Flags = None) {
1220  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1221  }
1222 
1223  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1224  ///
1225  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1226  /// truncated to their width.
1227  ///
1228  /// \pre setBasicBlock or setMI must have been called.
1229  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1230  /// with the same (scalar or vector) type).
1231  ///
1232  /// \return a MachineInstrBuilder for the newly created instruction.
1233 
1234  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1235  const SrcOp &Src1,
1236  Optional<unsigned> Flags = None) {
1237  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1238  }
1239 
1240  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1241  ///
1242  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1243  /// truncated to their width.
1244  ///
1245  /// \pre setBasicBlock or setMI must have been called.
1246  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1247  /// with the same (scalar or vector) type).
1248  ///
1249  /// \return a MachineInstrBuilder for the newly created instruction.
1250  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1251  const SrcOp &Src1,
1252  Optional<unsigned> Flags = None) {
1253  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1254  }
1255 
1256  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1257  const SrcOp &Src1,
1258  Optional<unsigned> Flags = None) {
1259  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1260  }
1261 
1262  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1263  const SrcOp &Src1,
1264  Optional<unsigned> Flags = None) {
1265  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1266  }
1267 
1268  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1269  const SrcOp &Src1,
1270  Optional<unsigned> Flags = None) {
1271  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1272  }
1273 
1274  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1275  const SrcOp &Src1,
1276  Optional<unsigned> Flags = None) {
1277  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1278  }
1279 
1280  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1281  const SrcOp &Src1,
1282  Optional<unsigned> Flags = None) {
1283  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1284  }
1285 
1286  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1287  const SrcOp &Src1,
1288  Optional<unsigned> Flags = None) {
1289  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1290  }
1291 
1292  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1293  ///
1294  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1295  /// Op1.
1296  ///
1297  /// \pre setBasicBlock or setMI must have been called.
1298  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1299  /// with the same (scalar or vector) type).
1300  ///
1301  /// \return a MachineInstrBuilder for the newly created instruction.
1302 
1303  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1304  const SrcOp &Src1) {
1305  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1306  }
1307 
1308  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1309  ///
1310  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1311  /// Op1.
1312  ///
1313  /// \pre setBasicBlock or setMI must have been called.
1314  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1315  /// with the same (scalar or vector) type).
1316  ///
1317  /// \return a MachineInstrBuilder for the newly created instruction.
1318  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1319  const SrcOp &Src1) {
1320  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1321  }
1322 
1323  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1324  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1325  const SrcOp &Src1) {
1326  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1327  }
1328 
1329  /// Build and insert a bitwise not,
1330  /// \p NegOne = G_CONSTANT -1
1331  /// \p Res = G_OR \p Op0, NegOne
1332  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1333  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1334  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1335  }
1336 
1337  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1338  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1339  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1340  }
1341 
1342  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1343  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1344  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1345  }
1346 
1347  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1349  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1350  }
1351 
1352  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1353  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1354  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1355  }
1356 
1357  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1359  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1360  }
1361 
1362  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1363  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1364  const SrcOp &Src1,
1365  Optional<unsigned> Flags = None) {
1366  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1367  }
1368 
1369  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1370  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1371  const SrcOp &Src1) {
1372  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1373  }
1374 
1375  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1376  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1377  const SrcOp &Src1, const SrcOp &Src2) {
1378  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1379  }
1380 
1381  /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1382  MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1383  const SrcOp &Src1, const SrcOp &Src2,
1384  Optional<unsigned> Flags = None) {
1385  return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1386  }
1387 
1388  /// Build and insert \p Res = G_FNEG \p Op0
1389  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
1390  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
1391  }
1392 
1393  /// Build and insert \p Res = G_FABS \p Op0
1394  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1395  Optional<unsigned> Flags = None) {
1396  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1397  }
1398 
1399  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1401  Optional<unsigned> Flags = None) {
1402  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1403  }
1404 
1405  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1407  const SrcOp &Src1) {
1408  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1409  }
1410 
1411  /// Build and insert \p Res = G_UITOFP \p Src0
1412  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1413  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1414  }
1415 
1416  /// Build and insert \p Res = G_SITOFP \p Src0
1417  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1418  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1419  }
1420 
1421  /// Build and insert \p Res = G_FPTOUI \p Src0
1422  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1423  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1424  }
1425 
1426  /// Build and insert \p Res = G_FPTOSI \p Src0
1427  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1428  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1429  }
1430 
1431  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1432  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1433  const SrcOp &Src1) {
1434  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1435  }
1436 
1437  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1438  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1439  const SrcOp &Src1) {
1440  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1441  }
1442 
1443  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1444  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1445  const SrcOp &Src1) {
1446  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1447  }
1448 
1449  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1450  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1451  const SrcOp &Src1) {
1452  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1453  }
1454 
1455  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1456  ///
1457  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1458  /// the jump table index \p JTI.
1459  ///
1460  /// \return a MachineInstrBuilder for the newly created instruction.
1461  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1462 
1463  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1464  ArrayRef<SrcOp> SrcOps,
1465  Optional<unsigned> Flags = None);
1466 };
1467 
1468 } // End namespace llvm.
1469 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
CmpInst::Predicate Pred
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DstType getDstOpKind() const
DstOp(Register R)
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
SrcOp(Register R)
int64_t getImm() const
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
MachineBasicBlock::iterator II
SrcOp(int64_t V)
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
DstOp(unsigned R)
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FNEG Op0.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
#define P(N)
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
DstOp(const MachineOperand &Op)
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Register getReg() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineIRBuilderState & getState()
Getter for the State.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
uint32_t Size
Definition: Profile.cpp:46
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1397
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(uint64_t V)
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.