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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
62  unsigned Reg;
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  unsigned getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
122  unsigned Reg;
124  };
125 
126 public:
127  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128  SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
131  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 
133  void addSrcToMIB(MachineInstrBuilder &MIB) const {
134  switch (Ty) {
135  case SrcType::Ty_Predicate:
136  MIB.addPredicate(Pred);
137  break;
138  case SrcType::Ty_Reg:
139  MIB.addUse(Reg);
140  break;
141  case SrcType::Ty_MIB:
142  MIB.addUse(SrcMIB->getOperand(0).getReg());
143  break;
144  }
145  }
146 
148  switch (Ty) {
149  case SrcType::Ty_Predicate:
150  llvm_unreachable("Not a register operand");
151  case SrcType::Ty_Reg:
152  return MRI.getType(Reg);
153  case SrcType::Ty_MIB:
154  return MRI.getType(SrcMIB->getOperand(0).getReg());
155  }
156  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
157  }
158 
159  unsigned getReg() const {
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return Reg;
165  case SrcType::Ty_MIB:
166  return SrcMIB->getOperand(0).getReg();
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
172  switch (Ty) {
173  case SrcType::Ty_Predicate:
174  return Pred;
175  default:
176  llvm_unreachable("Not a register operand");
177  }
178  }
179 
180  SrcType getSrcOpKind() const { return Ty; }
181 
182 private:
183  SrcType Ty;
184 };
185 
186 class FlagsOp {
187  Optional<unsigned> Flags;
188 
189 public:
190  explicit FlagsOp(unsigned F) : Flags(F) {}
191  FlagsOp() : Flags(None) {}
192  Optional<unsigned> getFlags() const { return Flags; }
193 };
194 /// Helper class to build MachineInstr.
195 /// It keeps internally the insertion point and debug location for all
196 /// the new instructions we want to create.
197 /// This information can be modify via the related setters.
199 
200  MachineIRBuilderState State;
201 
202 protected:
203  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
204 
205  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
206  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
207 
208  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
209  const LLT &Op1Ty);
210  void recordInsertion(MachineInstr *MI) const;
211 
212 public:
213  /// Some constructors for easy use.
214  MachineIRBuilder() = default;
217  setInstr(MI);
218  }
219 
220  virtual ~MachineIRBuilder() = default;
221 
222  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
223 
225  assert(State.TII && "TargetInstrInfo is not set");
226  return *State.TII;
227  }
228 
229  /// Getter for the function we currently build.
231  assert(State.MF && "MachineFunction is not set");
232  return *State.MF;
233  }
234 
235  const MachineFunction &getMF() const {
236  assert(State.MF && "MachineFunction is not set");
237  return *State.MF;
238  }
239 
240  const DataLayout &getDataLayout() const {
241  return getMF().getFunction().getParent()->getDataLayout();
242  }
243 
244  /// Getter for DebugLoc
245  const DebugLoc &getDL() { return State.DL; }
246 
247  /// Getter for MRI
248  MachineRegisterInfo *getMRI() { return State.MRI; }
249  const MachineRegisterInfo *getMRI() const { return State.MRI; }
250 
251  /// Getter for the State
252  MachineIRBuilderState &getState() { return State; }
253 
254  /// Getter for the basic block we currently build.
255  const MachineBasicBlock &getMBB() const {
256  assert(State.MBB && "MachineBasicBlock is not set");
257  return *State.MBB;
258  }
259 
261  return const_cast<MachineBasicBlock &>(
262  const_cast<const MachineIRBuilder *>(this)->getMBB());
263  }
264 
265  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
266  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
267 
268  /// Current insertion point for new instructions.
270 
271  /// Set the insertion point before the specified position.
272  /// \pre MBB must be in getMF().
273  /// \pre II must be a valid iterator in MBB.
275  /// @}
276 
277  void setCSEInfo(GISelCSEInfo *Info);
278 
279  /// \name Setters for the insertion point.
280  /// @{
281  /// Set the MachineFunction where to build instructions.
282  void setMF(MachineFunction &MF);
283 
284  /// Set the insertion point to the end of \p MBB.
285  /// \pre \p MBB must be contained by getMF().
286  void setMBB(MachineBasicBlock &MBB);
287 
288  /// Set the insertion point to before MI.
289  /// \pre MI must be in getMF().
290  void setInstr(MachineInstr &MI);
291  /// @}
292 
293  void setChangeObserver(GISelChangeObserver &Observer);
294  void stopObservingChanges();
295  /// @}
296 
297  /// Set the debug location to \p DL for all the next build instructions.
298  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
299 
300  /// Get the current instruction's debug location.
301  DebugLoc getDebugLoc() { return State.DL; }
302 
303  /// Build and insert <empty> = \p Opcode <empty>.
304  /// The insertion point is the one set by the last call of either
305  /// setBasicBlock or setMI.
306  ///
307  /// \pre setBasicBlock or setMI must have been called.
308  ///
309  /// \return a MachineInstrBuilder for the newly created instruction.
310  MachineInstrBuilder buildInstr(unsigned Opcode);
311 
312  /// Build but don't insert <empty> = \p Opcode <empty>.
313  ///
314  /// \pre setMF, setBasicBlock or setMI must have been called.
315  ///
316  /// \return a MachineInstrBuilder for the newly created instruction.
317  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
318 
319  /// Insert an existing instruction at the insertion point.
320  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
321 
322  /// Build and insert a DBG_VALUE instruction expressing the fact that the
323  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
324  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
325  const MDNode *Expr);
326 
327  /// Build and insert a DBG_VALUE instruction expressing the fact that the
328  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
329  /// Expr).
330  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
331  const MDNode *Variable,
332  const MDNode *Expr);
333 
334  /// Build and insert a DBG_VALUE instruction expressing the fact that the
335  /// associated \p Variable lives in the stack slot specified by \p FI
336  /// (suitably modified by \p Expr).
337  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
338  const MDNode *Expr);
339 
340  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
341  /// given by \p C (suitably modified by \p Expr).
342  MachineInstrBuilder buildConstDbgValue(const Constant &C,
343  const MDNode *Variable,
344  const MDNode *Expr);
345 
346  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
347  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
348  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
349 
350  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
351  ///
352  /// G_FRAME_INDEX materializes the address of an alloca value or other
353  /// stack-based object.
354  ///
355  /// \pre setBasicBlock or setMI must have been called.
356  /// \pre \p Res must be a generic virtual register with pointer type.
357  ///
358  /// \return a MachineInstrBuilder for the newly created instruction.
359  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
360 
361  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
362  ///
363  /// G_GLOBAL_VALUE materializes the address of the specified global
364  /// into \p Res.
365  ///
366  /// \pre setBasicBlock or setMI must have been called.
367  /// \pre \p Res must be a generic virtual register with pointer type
368  /// in the same address space as \p GV.
369  ///
370  /// \return a MachineInstrBuilder for the newly created instruction.
371  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
372 
373 
374  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
375  ///
376  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
377  /// storing the resulting pointer in \p Res.
378  ///
379  /// \pre setBasicBlock or setMI must have been called.
380  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
381  /// type.
382  /// \pre \p Op1 must be a generic virtual register with scalar type.
383  ///
384  /// \return a MachineInstrBuilder for the newly created instruction.
385  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
386  unsigned Op1);
387 
388  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
389  ///
390  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
391  /// storing the resulting pointer in \p Res. If \p Value is zero then no
392  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
393  /// \p Res.
394  ///
395  /// \pre setBasicBlock or setMI must have been called.
396  /// \pre \p Op0 must be a generic virtual register with pointer type.
397  /// \pre \p ValueTy must be a scalar type.
398  /// \pre \p Res must be 0. This is to detect confusion between
399  /// materializeGEP() and buildGEP().
400  /// \post \p Res will either be a new generic virtual register of the same
401  /// type as \p Op0 or \p Op0 itself.
402  ///
403  /// \return a MachineInstrBuilder for the newly created instruction.
404  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
405  const LLT &ValueTy,
406  uint64_t Value);
407 
408  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
409  ///
410  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
411  /// pointer properties. This has the effect of rounding the address *down* to
412  /// a specified alignment in bits.
413  ///
414  /// \pre setBasicBlock or setMI must have been called.
415  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
416  /// type.
417  /// \pre \p NumBits must be an integer representing the number of low bits to
418  /// be cleared in \p Op0.
419  ///
420  /// \return a MachineInstrBuilder for the newly created instruction.
421  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
422  uint32_t NumBits);
423 
424  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
425  /// \p Op1, \p CarryIn
426  ///
427  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
428  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
429  /// arithmetic.
430  ///
431  /// \pre setBasicBlock or setMI must have been called.
432  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
433  /// with the same scalar type.
434  /// \pre \p CarryOut and \p CarryIn must be generic virtual
435  /// registers with the same scalar type (typically s1)
436  ///
437  /// \return The newly created instruction.
438  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
439  const SrcOp &Op0, const SrcOp &Op1,
440  const SrcOp &CarryIn);
441 
442  /// Build and insert \p Res = G_ANYEXT \p Op0
443  ///
444  /// G_ANYEXT produces a register of the specified width, with bits 0 to
445  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
446  /// (i.e. this is neither zero nor sign-extension). For a vector register,
447  /// each element is extended individually.
448  ///
449  /// \pre setBasicBlock or setMI must have been called.
450  /// \pre \p Res must be a generic virtual register with scalar or vector type.
451  /// \pre \p Op must be a generic virtual register with scalar or vector type.
452  /// \pre \p Op must be smaller than \p Res
453  ///
454  /// \return The newly created instruction.
455 
456  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
457 
458  /// Build and insert \p Res = G_SEXT \p Op
459  ///
460  /// G_SEXT produces a register of the specified width, with bits 0 to
461  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
462  /// high bit of \p Op (i.e. 2s-complement sign extended).
463  ///
464  /// \pre setBasicBlock or setMI must have been called.
465  /// \pre \p Res must be a generic virtual register with scalar or vector type.
466  /// \pre \p Op must be a generic virtual register with scalar or vector type.
467  /// \pre \p Op must be smaller than \p Res
468  ///
469  /// \return The newly created instruction.
470  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
471 
472  /// Build and insert a G_PTRTOINT instruction.
473  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
474  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
475  }
476 
477  /// Build and insert \p Dst = G_BITCAST \p Src
478  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
479  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
480  }
481 
482  /// \return The opcode of the extension the target wants to use for boolean
483  /// values.
484  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
485 
486  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
487  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
488  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
489  bool IsFP);
490 
491  /// Build and insert \p Res = G_ZEXT \p Op
492  ///
493  /// G_ZEXT produces a register of the specified width, with bits 0 to
494  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
495  /// register, each element is extended individually.
496  ///
497  /// \pre setBasicBlock or setMI must have been called.
498  /// \pre \p Res must be a generic virtual register with scalar or vector type.
499  /// \pre \p Op must be a generic virtual register with scalar or vector type.
500  /// \pre \p Op must be smaller than \p Res
501  ///
502  /// \return The newly created instruction.
503  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
504 
505  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
506  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
507  /// ///
508  /// \pre setBasicBlock or setMI must have been called.
509  /// \pre \p Res must be a generic virtual register with scalar or vector type.
510  /// \pre \p Op must be a generic virtual register with scalar or vector type.
511  ///
512  /// \return The newly created instruction.
513  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
514 
515  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
516  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
517  /// ///
518  /// \pre setBasicBlock or setMI must have been called.
519  /// \pre \p Res must be a generic virtual register with scalar or vector type.
520  /// \pre \p Op must be a generic virtual register with scalar or vector type.
521  ///
522  /// \return The newly created instruction.
523  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
524 
525  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
526  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
527  /// ///
528  /// \pre setBasicBlock or setMI must have been called.
529  /// \pre \p Res must be a generic virtual register with scalar or vector type.
530  /// \pre \p Op must be a generic virtual register with scalar or vector type.
531  ///
532  /// \return The newly created instruction.
533  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
534 
535  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
536  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
537  /// \p Op.
538  /// ///
539  /// \pre setBasicBlock or setMI must have been called.
540  /// \pre \p Res must be a generic virtual register with scalar or vector type.
541  /// \pre \p Op must be a generic virtual register with scalar or vector type.
542  ///
543  /// \return The newly created instruction.
544  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
545  const SrcOp &Op);
546 
547  /// Build and insert an appropriate cast between two registers of equal size.
548  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
549 
550  /// Build and insert G_BR \p Dest
551  ///
552  /// G_BR is an unconditional branch to \p Dest.
553  ///
554  /// \pre setBasicBlock or setMI must have been called.
555  ///
556  /// \return a MachineInstrBuilder for the newly created instruction.
557  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
558 
559  /// Build and insert G_BRCOND \p Tst, \p Dest
560  ///
561  /// G_BRCOND is a conditional branch to \p Dest.
562  ///
563  /// \pre setBasicBlock or setMI must have been called.
564  /// \pre \p Tst must be a generic virtual register with scalar
565  /// type. At the beginning of legalization, this will be a single
566  /// bit (s1). Targets with interesting flags registers may change
567  /// this. For a wider type, whether the branch is taken must only
568  /// depend on bit 0 (for now).
569  ///
570  /// \return The newly created instruction.
571  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
572 
573  /// Build and insert G_BRINDIRECT \p Tgt
574  ///
575  /// G_BRINDIRECT is an indirect branch to \p Tgt.
576  ///
577  /// \pre setBasicBlock or setMI must have been called.
578  /// \pre \p Tgt must be a generic virtual register with pointer type.
579  ///
580  /// \return a MachineInstrBuilder for the newly created instruction.
581  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
582 
583  /// Build and insert \p Res = G_CONSTANT \p Val
584  ///
585  /// G_CONSTANT is an integer constant with the specified size and value. \p
586  /// Val will be extended or truncated to the size of \p Reg.
587  ///
588  /// \pre setBasicBlock or setMI must have been called.
589  /// \pre \p Res must be a generic virtual register with scalar or pointer
590  /// type.
591  ///
592  /// \return The newly created instruction.
593  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
594  const ConstantInt &Val);
595 
596  /// Build and insert \p Res = G_CONSTANT \p Val
597  ///
598  /// G_CONSTANT is an integer constant with the specified size and value.
599  ///
600  /// \pre setBasicBlock or setMI must have been called.
601  /// \pre \p Res must be a generic virtual register with scalar type.
602  ///
603  /// \return The newly created instruction.
604  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
605  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
606 
607  /// Build and insert \p Res = G_FCONSTANT \p Val
608  ///
609  /// G_FCONSTANT is a floating-point constant with the specified size and
610  /// value.
611  ///
612  /// \pre setBasicBlock or setMI must have been called.
613  /// \pre \p Res must be a generic virtual register with scalar type.
614  ///
615  /// \return The newly created instruction.
616  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
617  const ConstantFP &Val);
618 
619  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
620 
621  /// Build and insert \p Res = COPY Op
622  ///
623  /// Register-to-register COPY sets \p Res to \p Op.
624  ///
625  /// \pre setBasicBlock or setMI must have been called.
626  ///
627  /// \return a MachineInstrBuilder for the newly created instruction.
628  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
629 
630  /// Build and insert `Res = G_LOAD Addr, MMO`.
631  ///
632  /// Loads the value stored at \p Addr. Puts the result in \p Res.
633  ///
634  /// \pre setBasicBlock or setMI must have been called.
635  /// \pre \p Res must be a generic virtual register.
636  /// \pre \p Addr must be a generic virtual register with pointer type.
637  ///
638  /// \return a MachineInstrBuilder for the newly created instruction.
639  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
640  MachineMemOperand &MMO);
641 
642  /// Build and insert `Res = <opcode> Addr, MMO`.
643  ///
644  /// Loads the value stored at \p Addr. Puts the result in \p Res.
645  ///
646  /// \pre setBasicBlock or setMI must have been called.
647  /// \pre \p Res must be a generic virtual register.
648  /// \pre \p Addr must be a generic virtual register with pointer type.
649  ///
650  /// \return a MachineInstrBuilder for the newly created instruction.
651  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
652  unsigned Addr, MachineMemOperand &MMO);
653 
654  /// Build and insert `G_STORE Val, Addr, MMO`.
655  ///
656  /// Stores the value \p Val to \p Addr.
657  ///
658  /// \pre setBasicBlock or setMI must have been called.
659  /// \pre \p Val must be a generic virtual register.
660  /// \pre \p Addr must be a generic virtual register with pointer type.
661  ///
662  /// \return a MachineInstrBuilder for the newly created instruction.
663  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
664  MachineMemOperand &MMO);
665 
666  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
667  ///
668  /// \pre setBasicBlock or setMI must have been called.
669  /// \pre \p Res and \p Src must be generic virtual registers.
670  ///
671  /// \return a MachineInstrBuilder for the newly created instruction.
672  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
673 
674  /// Build and insert \p Res = IMPLICIT_DEF.
675  MachineInstrBuilder buildUndef(const DstOp &Res);
676 
677  /// Build and insert instructions to put \p Ops together at the specified p
678  /// Indices to form a larger register.
679  ///
680  /// If the types of the input registers are uniform and cover the entirity of
681  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
682  /// followed by a sequence of G_INSERT instructions.
683  ///
684  /// \pre setBasicBlock or setMI must have been called.
685  /// \pre The final element of the sequence must not extend past the end of the
686  /// destination register.
687  /// \pre The bits defined by each Op (derived from index and scalar size) must
688  /// not overlap.
689  /// \pre \p Indices must be in ascending order of bit position.
690  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
691  ArrayRef<uint64_t> Indices);
692 
693  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
694  ///
695  /// G_MERGE_VALUES combines the input elements contiguously into a larger
696  /// register.
697  ///
698  /// \pre setBasicBlock or setMI must have been called.
699  /// \pre The entire register \p Res (and no more) must be covered by the input
700  /// registers.
701  /// \pre The type of all \p Ops registers must be identical.
702  ///
703  /// \return a MachineInstrBuilder for the newly created instruction.
704  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
705 
706  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
707  ///
708  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
709  ///
710  /// \pre setBasicBlock or setMI must have been called.
711  /// \pre The entire register \p Res (and no more) must be covered by the input
712  /// registers.
713  /// \pre The type of all \p Res registers must be identical.
714  ///
715  /// \return a MachineInstrBuilder for the newly created instruction.
716  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
717  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
718 
719  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
720  ///
721  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
722  /// \pre setBasicBlock or setMI must have been called.
723  /// \pre The entire register \p Res (and no more) must be covered by the
724  /// input scalar registers.
725  /// \pre The type of all \p Ops registers must be identical.
726  ///
727  /// \return a MachineInstrBuilder for the newly created instruction.
728  MachineInstrBuilder buildBuildVector(const DstOp &Res,
729  ArrayRef<unsigned> Ops);
730 
731  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
732  /// the number of elements
733  MachineInstrBuilder buildSplatVector(const DstOp &Res,
734  const SrcOp &Src);
735 
736  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
737  ///
738  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
739  /// which have types larger than the destination vector element type, and
740  /// truncates the values to fit.
741  ///
742  /// If the operands given are already the same size as the vector elt type,
743  /// then this method will instead create a G_BUILD_VECTOR instruction.
744  ///
745  /// \pre setBasicBlock or setMI must have been called.
746  /// \pre The type of all \p Ops registers must be identical.
747  ///
748  /// \return a MachineInstrBuilder for the newly created instruction.
749  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
750  ArrayRef<unsigned> Ops);
751 
752  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
753  ///
754  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
755  /// vectors.
756  ///
757  /// \pre setBasicBlock or setMI must have been called.
758  /// \pre The entire register \p Res (and no more) must be covered by the input
759  /// registers.
760  /// \pre The type of all source operands must be identical.
761  ///
762  /// \return a MachineInstrBuilder for the newly created instruction.
763  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
764  ArrayRef<unsigned> Ops);
765 
766  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
767  unsigned Op, unsigned Index);
768 
769  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
770  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
771  /// result register definition unless \p Reg is NoReg (== 0). The second
772  /// operand will be the intrinsic's ID.
773  ///
774  /// Callers are expected to add the required definitions and uses afterwards.
775  ///
776  /// \pre setBasicBlock or setMI must have been called.
777  ///
778  /// \return a MachineInstrBuilder for the newly created instruction.
779  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
780  bool HasSideEffects);
781 
782  /// Build and insert \p Res = G_FPTRUNC \p Op
783  ///
784  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
785  ///
786  /// \pre setBasicBlock or setMI must have been called.
787  /// \pre \p Res must be a generic virtual register with scalar or vector type.
788  /// \pre \p Op must be a generic virtual register with scalar or vector type.
789  /// \pre \p Res must be smaller than \p Op
790  ///
791  /// \return The newly created instruction.
792  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
793 
794  /// Build and insert \p Res = G_TRUNC \p Op
795  ///
796  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
797  /// truncated independently before being packed into the destination.
798  ///
799  /// \pre setBasicBlock or setMI must have been called.
800  /// \pre \p Res must be a generic virtual register with scalar or vector type.
801  /// \pre \p Op must be a generic virtual register with scalar or vector type.
802  /// \pre \p Res must be smaller than \p Op
803  ///
804  /// \return The newly created instruction.
805  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
806 
807  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
808  ///
809  /// \pre setBasicBlock or setMI must have been called.
810 
811  /// \pre \p Res must be a generic virtual register with scalar or
812  /// vector type. Typically this starts as s1 or <N x s1>.
813  /// \pre \p Op0 and Op1 must be generic virtual registers with the
814  /// same number of elements as \p Res. If \p Res is a scalar,
815  /// \p Op0 must be either a scalar or pointer.
816  /// \pre \p Pred must be an integer predicate.
817  ///
818  /// \return a MachineInstrBuilder for the newly created instruction.
819  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
820  const SrcOp &Op0, const SrcOp &Op1);
821 
822  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
823  ///
824  /// \pre setBasicBlock or setMI must have been called.
825 
826  /// \pre \p Res must be a generic virtual register with scalar or
827  /// vector type. Typically this starts as s1 or <N x s1>.
828  /// \pre \p Op0 and Op1 must be generic virtual registers with the
829  /// same number of elements as \p Res (or scalar, if \p Res is
830  /// scalar).
831  /// \pre \p Pred must be a floating-point predicate.
832  ///
833  /// \return a MachineInstrBuilder for the newly created instruction.
834  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
835  const SrcOp &Op0, const SrcOp &Op1);
836 
837  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
838  ///
839  /// \pre setBasicBlock or setMI must have been called.
840  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
841  /// with the same type.
842  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
843  /// vector type. If vector then it must have the same number of
844  /// elements as the other parameters.
845  ///
846  /// \return a MachineInstrBuilder for the newly created instruction.
847  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
848  const SrcOp &Op0, const SrcOp &Op1);
849 
850  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
851  /// \p Elt, \p Idx
852  ///
853  /// \pre setBasicBlock or setMI must have been called.
854  /// \pre \p Res and \p Val must be a generic virtual register
855  // with the same vector type.
856  /// \pre \p Elt and \p Idx must be a generic virtual register
857  /// with scalar type.
858  ///
859  /// \return The newly created instruction.
860  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
861  const SrcOp &Val,
862  const SrcOp &Elt,
863  const SrcOp &Idx);
864 
865  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
866  ///
867  /// \pre setBasicBlock or setMI must have been called.
868  /// \pre \p Res must be a generic virtual register with scalar type.
869  /// \pre \p Val must be a generic virtual register with vector type.
870  /// \pre \p Idx must be a generic virtual register with scalar type.
871  ///
872  /// \return The newly created instruction.
873  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
874  const SrcOp &Val,
875  const SrcOp &Idx);
876 
877  /// Build and insert `OldValRes<def>, SuccessRes<def> =
878  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
879  ///
880  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
881  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
882  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
883  ///
884  /// \pre setBasicBlock or setMI must have been called.
885  /// \pre \p OldValRes must be a generic virtual register of scalar type.
886  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
887  /// will be assigned 0 on failure and 1 on success.
888  /// \pre \p Addr must be a generic virtual register with pointer type.
889  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
890  /// registers of the same type.
891  ///
892  /// \return a MachineInstrBuilder for the newly created instruction.
894  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
895  unsigned Addr, unsigned CmpVal, unsigned NewVal,
896  MachineMemOperand &MMO);
897 
898  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
899  /// MMO`.
900  ///
901  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
902  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
903  /// Addr in \p Res.
904  ///
905  /// \pre setBasicBlock or setMI must have been called.
906  /// \pre \p OldValRes must be a generic virtual register of scalar type.
907  /// \pre \p Addr must be a generic virtual register with pointer type.
908  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
909  /// registers of the same type.
910  ///
911  /// \return a MachineInstrBuilder for the newly created instruction.
912  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
913  unsigned CmpVal, unsigned NewVal,
914  MachineMemOperand &MMO);
915 
916  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
917  ///
918  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
919  /// original value from \p Addr in \p OldValRes. The modification is
920  /// determined by the opcode.
921  ///
922  /// \pre setBasicBlock or setMI must have been called.
923  /// \pre \p OldValRes must be a generic virtual register.
924  /// \pre \p Addr must be a generic virtual register with pointer type.
925  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
926  /// same type.
927  ///
928  /// \return a MachineInstrBuilder for the newly created instruction.
929  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
930  unsigned Addr, unsigned Val,
931  MachineMemOperand &MMO);
932 
933  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
934  ///
935  /// Atomically replace the value at \p Addr with \p Val. Puts the original
936  /// value from \p Addr in \p OldValRes.
937  ///
938  /// \pre setBasicBlock or setMI must have been called.
939  /// \pre \p OldValRes must be a generic virtual register.
940  /// \pre \p Addr must be a generic virtual register with pointer type.
941  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
942  /// same type.
943  ///
944  /// \return a MachineInstrBuilder for the newly created instruction.
945  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
946  unsigned Val, MachineMemOperand &MMO);
947 
948  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
949  ///
950  /// Atomically replace the value at \p Addr with the addition of \p Val and
951  /// the original value. Puts the original value from \p Addr in \p OldValRes.
952  ///
953  /// \pre setBasicBlock or setMI must have been called.
954  /// \pre \p OldValRes must be a generic virtual register.
955  /// \pre \p Addr must be a generic virtual register with pointer type.
956  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
957  /// same type.
958  ///
959  /// \return a MachineInstrBuilder for the newly created instruction.
960  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
961  unsigned Val, MachineMemOperand &MMO);
962 
963  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
964  ///
965  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
966  /// the original value. Puts the original value from \p Addr in \p OldValRes.
967  ///
968  /// \pre setBasicBlock or setMI must have been called.
969  /// \pre \p OldValRes must be a generic virtual register.
970  /// \pre \p Addr must be a generic virtual register with pointer type.
971  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
972  /// same type.
973  ///
974  /// \return a MachineInstrBuilder for the newly created instruction.
975  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
976  unsigned Val, MachineMemOperand &MMO);
977 
978  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
979  ///
980  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
981  /// the original value. Puts the original value from \p Addr in \p OldValRes.
982  ///
983  /// \pre setBasicBlock or setMI must have been called.
984  /// \pre \p OldValRes must be a generic virtual register.
985  /// \pre \p Addr must be a generic virtual register with pointer type.
986  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
987  /// same type.
988  ///
989  /// \return a MachineInstrBuilder for the newly created instruction.
990  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
991  unsigned Val, MachineMemOperand &MMO);
992 
993  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
994  ///
995  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
996  /// and the original value. Puts the original value from \p Addr in \p
997  /// OldValRes.
998  ///
999  /// \pre setBasicBlock or setMI must have been called.
1000  /// \pre \p OldValRes must be a generic virtual register.
1001  /// \pre \p Addr must be a generic virtual register with pointer type.
1002  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1003  /// same type.
1004  ///
1005  /// \return a MachineInstrBuilder for the newly created instruction.
1006  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
1007  unsigned Val, MachineMemOperand &MMO);
1008 
1009  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1010  ///
1011  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1012  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1013  ///
1014  /// \pre setBasicBlock or setMI must have been called.
1015  /// \pre \p OldValRes must be a generic virtual register.
1016  /// \pre \p Addr must be a generic virtual register with pointer type.
1017  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1018  /// same type.
1019  ///
1020  /// \return a MachineInstrBuilder for the newly created instruction.
1021  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
1022  unsigned Val, MachineMemOperand &MMO);
1023 
1024  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1025  ///
1026  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1027  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1028  ///
1029  /// \pre setBasicBlock or setMI must have been called.
1030  /// \pre \p OldValRes must be a generic virtual register.
1031  /// \pre \p Addr must be a generic virtual register with pointer type.
1032  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1033  /// same type.
1034  ///
1035  /// \return a MachineInstrBuilder for the newly created instruction.
1036  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
1037  unsigned Val, MachineMemOperand &MMO);
1038 
1039  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1040  ///
1041  /// Atomically replace the value at \p Addr with the signed maximum of \p
1042  /// Val and the original value. Puts the original value from \p Addr in \p
1043  /// OldValRes.
1044  ///
1045  /// \pre setBasicBlock or setMI must have been called.
1046  /// \pre \p OldValRes must be a generic virtual register.
1047  /// \pre \p Addr must be a generic virtual register with pointer type.
1048  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1049  /// same type.
1050  ///
1051  /// \return a MachineInstrBuilder for the newly created instruction.
1052  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
1053  unsigned Val, MachineMemOperand &MMO);
1054 
1055  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1056  ///
1057  /// Atomically replace the value at \p Addr with the signed minimum of \p
1058  /// Val and the original value. Puts the original value from \p Addr in \p
1059  /// OldValRes.
1060  ///
1061  /// \pre setBasicBlock or setMI must have been called.
1062  /// \pre \p OldValRes must be a generic virtual register.
1063  /// \pre \p Addr must be a generic virtual register with pointer type.
1064  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1065  /// same type.
1066  ///
1067  /// \return a MachineInstrBuilder for the newly created instruction.
1068  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1069  unsigned Val, MachineMemOperand &MMO);
1070 
1071  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1072  ///
1073  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1074  /// Val and the original value. Puts the original value from \p Addr in \p
1075  /// OldValRes.
1076  ///
1077  /// \pre setBasicBlock or setMI must have been called.
1078  /// \pre \p OldValRes must be a generic virtual register.
1079  /// \pre \p Addr must be a generic virtual register with pointer type.
1080  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1081  /// same type.
1082  ///
1083  /// \return a MachineInstrBuilder for the newly created instruction.
1084  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1085  unsigned Val, MachineMemOperand &MMO);
1086 
1087  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1088  ///
1089  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1090  /// Val and the original value. Puts the original value from \p Addr in \p
1091  /// OldValRes.
1092  ///
1093  /// \pre setBasicBlock or setMI must have been called.
1094  /// \pre \p OldValRes must be a generic virtual register.
1095  /// \pre \p Addr must be a generic virtual register with pointer type.
1096  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1097  /// same type.
1098  ///
1099  /// \return a MachineInstrBuilder for the newly created instruction.
1100  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1101  unsigned Val, MachineMemOperand &MMO);
1102 
1103  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1104  ///
1105  /// G_BLOCK_ADDR computes the address of a basic block.
1106  ///
1107  /// \pre setBasicBlock or setMI must have been called.
1108  /// \pre \p Res must be a generic virtual register of a pointer type.
1109  ///
1110  /// \return The newly created instruction.
1111  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1112 
1113  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1114  ///
1115  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1116  /// truncated to their width.
1117  ///
1118  /// \pre setBasicBlock or setMI must have been called.
1119  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1120  /// with the same (scalar or vector) type).
1121  ///
1122  /// \return a MachineInstrBuilder for the newly created instruction.
1123 
1124  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1125  const SrcOp &Src1,
1126  Optional<unsigned> Flags = None) {
1127  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1128  }
1129 
1130  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1131  ///
1132  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1133  /// truncated to their width.
1134  ///
1135  /// \pre setBasicBlock or setMI must have been called.
1136  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1137  /// with the same (scalar or vector) type).
1138  ///
1139  /// \return a MachineInstrBuilder for the newly created instruction.
1140 
1141  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1142  const SrcOp &Src1,
1143  Optional<unsigned> Flags = None) {
1144  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1145  }
1146 
1147  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1148  ///
1149  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1150  /// truncated to their width.
1151  ///
1152  /// \pre setBasicBlock or setMI must have been called.
1153  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1154  /// with the same (scalar or vector) type).
1155  ///
1156  /// \return a MachineInstrBuilder for the newly created instruction.
1157  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1158  const SrcOp &Src1,
1159  Optional<unsigned> Flags = None) {
1160  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1161  }
1162 
1163  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1164  const SrcOp &Src1,
1165  Optional<unsigned> Flags = None) {
1166  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1167  }
1168 
1169  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1170  const SrcOp &Src1,
1171  Optional<unsigned> Flags = None) {
1172  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1173  }
1174 
1175  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1176  const SrcOp &Src1,
1177  Optional<unsigned> Flags = None) {
1178  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1179  }
1180 
1181  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1182  const SrcOp &Src1,
1183  Optional<unsigned> Flags = None) {
1184  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1185  }
1186 
1187  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1188  const SrcOp &Src1,
1189  Optional<unsigned> Flags = None) {
1190  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1191  }
1192 
1193  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1194  ///
1195  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1196  /// Op1.
1197  ///
1198  /// \pre setBasicBlock or setMI must have been called.
1199  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1200  /// with the same (scalar or vector) type).
1201  ///
1202  /// \return a MachineInstrBuilder for the newly created instruction.
1203 
1204  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1205  const SrcOp &Src1) {
1206  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1207  }
1208 
1209  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1210  ///
1211  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1212  /// Op1.
1213  ///
1214  /// \pre setBasicBlock or setMI must have been called.
1215  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1216  /// with the same (scalar or vector) type).
1217  ///
1218  /// \return a MachineInstrBuilder for the newly created instruction.
1219  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1220  const SrcOp &Src1) {
1221  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1222  }
1223 
1224  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1225  ArrayRef<SrcOp> SrcOps,
1226  Optional<unsigned> Flags = None);
1227 };
1228 
1229 } // End namespace llvm.
1230 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:68
CmpInst::Predicate Pred
unsigned getReg() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
DstType getDstOpKind() const
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
GISelCSEInfo * getCSEInfo()
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
DstOp(unsigned R)
SrcOp(const CmpInst::Predicate P)
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
unsigned getReg() const
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
DebugLoc DL
Debug location to be set to any instruction we create.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DstOp(const MachineOperand &Op)
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:63
MachineIRBuilderState & getState()
Getter for the State.
SrcOp(unsigned R)
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1364
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.