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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the MachineIRBuilder class.
11 /// This is a helper class to build MachineInstr.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
16 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 };
56 
57 class DstOp {
58  union {
60  unsigned Reg;
62  };
63 
64 public:
65  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
66  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
67  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
68  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
69 
71  switch (Ty) {
72  case DstType::Ty_Reg:
73  MIB.addDef(Reg);
74  break;
75  case DstType::Ty_LLT:
76  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
77  break;
78  case DstType::Ty_RC:
79  MIB.addDef(MRI.createVirtualRegister(RC));
80  break;
81  }
82  }
83 
84  DstType getType() const { return Ty; }
85 
87  switch (Ty) {
88  case DstType::Ty_RC:
89  return LLT{};
90  case DstType::Ty_LLT:
91  return LLTTy;
92  case DstType::Ty_Reg:
93  return MRI.getType(Reg);
94  }
95  }
96 
97  DstType getDstOpKind() const { return Ty; }
98 
99 private:
100  DstType Ty;
101 };
102 
103 class SrcOp {
104  union {
106  unsigned Reg;
108  };
109 
110 public:
111  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
112  SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
113  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
114  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
115 
116  void addSrcToMIB(MachineInstrBuilder &MIB) const {
117  switch (Ty) {
118  case SrcType::Ty_Predicate:
119  MIB.addPredicate(Pred);
120  break;
121  case SrcType::Ty_Reg:
122  MIB.addUse(Reg);
123  break;
124  case SrcType::Ty_MIB:
125  MIB.addUse(SrcMIB->getOperand(0).getReg());
126  break;
127  }
128  }
129 
131  switch (Ty) {
132  case SrcType::Ty_Predicate:
133  llvm_unreachable("Not a register operand");
134  case SrcType::Ty_Reg:
135  return MRI.getType(Reg);
136  case SrcType::Ty_MIB:
137  return MRI.getType(SrcMIB->getOperand(0).getReg());
138  }
139  }
140 
141  unsigned getReg() const {
142  switch (Ty) {
143  case SrcType::Ty_Predicate:
144  llvm_unreachable("Not a register operand");
145  case SrcType::Ty_Reg:
146  return Reg;
147  case SrcType::Ty_MIB:
148  return SrcMIB->getOperand(0).getReg();
149  }
150  }
151 
153  switch (Ty) {
154  case SrcType::Ty_Predicate:
155  return Pred;
156  default:
157  llvm_unreachable("Not a register operand");
158  }
159  }
160 
161  SrcType getSrcOpKind() const { return Ty; }
162 
163 private:
164  SrcType Ty;
165 };
166 
167 class FlagsOp {
168  Optional<unsigned> Flags;
169 
170 public:
171  explicit FlagsOp(unsigned F) : Flags(F) {}
172  FlagsOp() : Flags(None) {}
173  Optional<unsigned> getFlags() const { return Flags; }
174 };
175 /// Helper class to build MachineInstr.
176 /// It keeps internally the insertion point and debug location for all
177 /// the new instructions we want to create.
178 /// This information can be modify via the related setters.
180 
181  MachineIRBuilderState State;
182 
183 protected:
184  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
185 
186  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
187 
188  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
189  const LLT &Op1Ty);
190  void recordInsertion(MachineInstr *MI) const;
191 
192 public:
193  /// Some constructors for easy use.
194  MachineIRBuilder() = default;
197  setInstr(MI);
198  }
199 
200  virtual ~MachineIRBuilder() = default;
201 
202  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
203 
205  assert(State.TII && "TargetInstrInfo is not set");
206  return *State.TII;
207  }
208 
209  /// Getter for the function we currently build.
211  assert(State.MF && "MachineFunction is not set");
212  return *State.MF;
213  }
214 
215  /// Getter for DebugLoc
216  const DebugLoc &getDL() { return State.DL; }
217 
218  /// Getter for MRI
219  MachineRegisterInfo *getMRI() { return State.MRI; }
220 
221  /// Getter for the State
222  MachineIRBuilderState &getState() { return State; }
223 
224  /// Getter for the basic block we currently build.
226  assert(State.MBB && "MachineBasicBlock is not set");
227  return *State.MBB;
228  }
229 
230  /// Current insertion point for new instructions.
232 
233  /// Set the insertion point before the specified position.
234  /// \pre MBB must be in getMF().
235  /// \pre II must be a valid iterator in MBB.
237  /// @}
238 
239  /// \name Setters for the insertion point.
240  /// @{
241  /// Set the MachineFunction where to build instructions.
242  void setMF(MachineFunction &);
243 
244  /// Set the insertion point to the end of \p MBB.
245  /// \pre \p MBB must be contained by getMF().
246  void setMBB(MachineBasicBlock &MBB);
247 
248  /// Set the insertion point to before MI.
249  /// \pre MI must be in getMF().
250  void setInstr(MachineInstr &MI);
251  /// @}
252 
253  void setChangeObserver(GISelChangeObserver &Observer);
254  void stopObservingChanges();
255  /// @}
256 
257  /// Set the debug location to \p DL for all the next build instructions.
258  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
259 
260  /// Get the current instruction's debug location.
261  DebugLoc getDebugLoc() { return State.DL; }
262 
263  /// Build and insert <empty> = \p Opcode <empty>.
264  /// The insertion point is the one set by the last call of either
265  /// setBasicBlock or setMI.
266  ///
267  /// \pre setBasicBlock or setMI must have been called.
268  ///
269  /// \return a MachineInstrBuilder for the newly created instruction.
270  MachineInstrBuilder buildInstr(unsigned Opcode);
271 
272  /// Build but don't insert <empty> = \p Opcode <empty>.
273  ///
274  /// \pre setMF, setBasicBlock or setMI must have been called.
275  ///
276  /// \return a MachineInstrBuilder for the newly created instruction.
277  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
278 
279  /// Insert an existing instruction at the insertion point.
280  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
281 
282  /// Build and insert a DBG_VALUE instruction expressing the fact that the
283  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
284  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
285  const MDNode *Expr);
286 
287  /// Build and insert a DBG_VALUE instruction expressing the fact that the
288  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
289  /// Expr).
290  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
291  const MDNode *Variable,
292  const MDNode *Expr);
293 
294  /// Build and insert a DBG_VALUE instruction expressing the fact that the
295  /// associated \p Variable lives in the stack slot specified by \p FI
296  /// (suitably modified by \p Expr).
297  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
298  const MDNode *Expr);
299 
300  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
301  /// given by \p C (suitably modified by \p Expr).
302  MachineInstrBuilder buildConstDbgValue(const Constant &C,
303  const MDNode *Variable,
304  const MDNode *Expr);
305 
306  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
307  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
308  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
309 
310  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
311  ///
312  /// G_FRAME_INDEX materializes the address of an alloca value or other
313  /// stack-based object.
314  ///
315  /// \pre setBasicBlock or setMI must have been called.
316  /// \pre \p Res must be a generic virtual register with pointer type.
317  ///
318  /// \return a MachineInstrBuilder for the newly created instruction.
319  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
320 
321  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
322  ///
323  /// G_GLOBAL_VALUE materializes the address of the specified global
324  /// into \p Res.
325  ///
326  /// \pre setBasicBlock or setMI must have been called.
327  /// \pre \p Res must be a generic virtual register with pointer type
328  /// in the same address space as \p GV.
329  ///
330  /// \return a MachineInstrBuilder for the newly created instruction.
331  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
332 
333 
334  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
335  ///
336  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
337  /// storing the resulting pointer in \p Res.
338  ///
339  /// \pre setBasicBlock or setMI must have been called.
340  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
341  /// type.
342  /// \pre \p Op1 must be a generic virtual register with scalar type.
343  ///
344  /// \return a MachineInstrBuilder for the newly created instruction.
345  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
346  unsigned Op1);
347 
348  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
349  ///
350  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
351  /// storing the resulting pointer in \p Res. If \p Value is zero then no
352  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
353  /// \p Res.
354  ///
355  /// \pre setBasicBlock or setMI must have been called.
356  /// \pre \p Op0 must be a generic virtual register with pointer type.
357  /// \pre \p ValueTy must be a scalar type.
358  /// \pre \p Res must be 0. This is to detect confusion between
359  /// materializeGEP() and buildGEP().
360  /// \post \p Res will either be a new generic virtual register of the same
361  /// type as \p Op0 or \p Op0 itself.
362  ///
363  /// \return a MachineInstrBuilder for the newly created instruction.
364  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
365  const LLT &ValueTy,
366  uint64_t Value);
367 
368  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
369  ///
370  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
371  /// pointer properties. This has the effect of rounding the address *down* to
372  /// a specified alignment in bits.
373  ///
374  /// \pre setBasicBlock or setMI must have been called.
375  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
376  /// type.
377  /// \pre \p NumBits must be an integer representing the number of low bits to
378  /// be cleared in \p Op0.
379  ///
380  /// \return a MachineInstrBuilder for the newly created instruction.
381  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
382  uint32_t NumBits);
383 
384  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
385  /// \p Op1, \p CarryIn
386  ///
387  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
388  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
389  /// arithmetic.
390  ///
391  /// \pre setBasicBlock or setMI must have been called.
392  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
393  /// with the same scalar type.
394  /// \pre \p CarryOut and \p CarryIn must be generic virtual
395  /// registers with the same scalar type (typically s1)
396  ///
397  /// \return The newly created instruction.
398  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
399  const SrcOp &Op0, const SrcOp &Op1,
400  const SrcOp &CarryIn);
401 
402  /// Build and insert \p Res = G_ANYEXT \p Op0
403  ///
404  /// G_ANYEXT produces a register of the specified width, with bits 0 to
405  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
406  /// (i.e. this is neither zero nor sign-extension). For a vector register,
407  /// each element is extended individually.
408  ///
409  /// \pre setBasicBlock or setMI must have been called.
410  /// \pre \p Res must be a generic virtual register with scalar or vector type.
411  /// \pre \p Op must be a generic virtual register with scalar or vector type.
412  /// \pre \p Op must be smaller than \p Res
413  ///
414  /// \return The newly created instruction.
415 
416  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
417 
418  /// Build and insert \p Res = G_SEXT \p Op
419  ///
420  /// G_SEXT produces a register of the specified width, with bits 0 to
421  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
422  /// high bit of \p Op (i.e. 2s-complement sign extended).
423  ///
424  /// \pre setBasicBlock or setMI must have been called.
425  /// \pre \p Res must be a generic virtual register with scalar or vector type.
426  /// \pre \p Op must be a generic virtual register with scalar or vector type.
427  /// \pre \p Op must be smaller than \p Res
428  ///
429  /// \return The newly created instruction.
430  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
431 
432  /// Build and insert \p Res = G_ZEXT \p Op
433  ///
434  /// G_ZEXT produces a register of the specified width, with bits 0 to
435  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
436  /// register, each element is extended individually.
437  ///
438  /// \pre setBasicBlock or setMI must have been called.
439  /// \pre \p Res must be a generic virtual register with scalar or vector type.
440  /// \pre \p Op must be a generic virtual register with scalar or vector type.
441  /// \pre \p Op must be smaller than \p Res
442  ///
443  /// \return The newly created instruction.
444  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
445 
446  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
447  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
448  /// ///
449  /// \pre setBasicBlock or setMI must have been called.
450  /// \pre \p Res must be a generic virtual register with scalar or vector type.
451  /// \pre \p Op must be a generic virtual register with scalar or vector type.
452  ///
453  /// \return The newly created instruction.
454  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
455 
456  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
457  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
458  /// ///
459  /// \pre setBasicBlock or setMI must have been called.
460  /// \pre \p Res must be a generic virtual register with scalar or vector type.
461  /// \pre \p Op must be a generic virtual register with scalar or vector type.
462  ///
463  /// \return The newly created instruction.
464  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
465 
466  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
467  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
468  /// ///
469  /// \pre setBasicBlock or setMI must have been called.
470  /// \pre \p Res must be a generic virtual register with scalar or vector type.
471  /// \pre \p Op must be a generic virtual register with scalar or vector type.
472  ///
473  /// \return The newly created instruction.
474  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
475 
476  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
477  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
478  /// \p Op.
479  /// ///
480  /// \pre setBasicBlock or setMI must have been called.
481  /// \pre \p Res must be a generic virtual register with scalar or vector type.
482  /// \pre \p Op must be a generic virtual register with scalar or vector type.
483  ///
484  /// \return The newly created instruction.
485  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
486  const SrcOp &Op);
487 
488  /// Build and insert an appropriate cast between two registers of equal size.
489  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
490 
491  /// Build and insert G_BR \p Dest
492  ///
493  /// G_BR is an unconditional branch to \p Dest.
494  ///
495  /// \pre setBasicBlock or setMI must have been called.
496  ///
497  /// \return a MachineInstrBuilder for the newly created instruction.
498  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
499 
500  /// Build and insert G_BRCOND \p Tst, \p Dest
501  ///
502  /// G_BRCOND is a conditional branch to \p Dest.
503  ///
504  /// \pre setBasicBlock or setMI must have been called.
505  /// \pre \p Tst must be a generic virtual register with scalar
506  /// type. At the beginning of legalization, this will be a single
507  /// bit (s1). Targets with interesting flags registers may change
508  /// this. For a wider type, whether the branch is taken must only
509  /// depend on bit 0 (for now).
510  ///
511  /// \return The newly created instruction.
512  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
513 
514  /// Build and insert G_BRINDIRECT \p Tgt
515  ///
516  /// G_BRINDIRECT is an indirect branch to \p Tgt.
517  ///
518  /// \pre setBasicBlock or setMI must have been called.
519  /// \pre \p Tgt must be a generic virtual register with pointer type.
520  ///
521  /// \return a MachineInstrBuilder for the newly created instruction.
522  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
523 
524  /// Build and insert \p Res = G_CONSTANT \p Val
525  ///
526  /// G_CONSTANT is an integer constant with the specified size and value. \p
527  /// Val will be extended or truncated to the size of \p Reg.
528  ///
529  /// \pre setBasicBlock or setMI must have been called.
530  /// \pre \p Res must be a generic virtual register with scalar or pointer
531  /// type.
532  ///
533  /// \return The newly created instruction.
534  MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val);
535 
536  /// Build and insert \p Res = G_CONSTANT \p Val
537  ///
538  /// G_CONSTANT is an integer constant with the specified size and value.
539  ///
540  /// \pre setBasicBlock or setMI must have been called.
541  /// \pre \p Res must be a generic virtual register with scalar type.
542  ///
543  /// \return The newly created instruction.
544  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
545 
546  /// Build and insert \p Res = G_FCONSTANT \p Val
547  ///
548  /// G_FCONSTANT is a floating-point constant with the specified size and
549  /// value.
550  ///
551  /// \pre setBasicBlock or setMI must have been called.
552  /// \pre \p Res must be a generic virtual register with scalar type.
553  ///
554  /// \return The newly created instruction.
555  MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val);
556 
557  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
558 
559  /// Build and insert \p Res = COPY Op
560  ///
561  /// Register-to-register COPY sets \p Res to \p Op.
562  ///
563  /// \pre setBasicBlock or setMI must have been called.
564  ///
565  /// \return a MachineInstrBuilder for the newly created instruction.
566  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
567 
568  /// Build and insert `Res = G_LOAD Addr, MMO`.
569  ///
570  /// Loads the value stored at \p Addr. Puts the result in \p Res.
571  ///
572  /// \pre setBasicBlock or setMI must have been called.
573  /// \pre \p Res must be a generic virtual register.
574  /// \pre \p Addr must be a generic virtual register with pointer type.
575  ///
576  /// \return a MachineInstrBuilder for the newly created instruction.
577  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
578  MachineMemOperand &MMO);
579 
580  /// Build and insert `Res = <opcode> Addr, MMO`.
581  ///
582  /// Loads the value stored at \p Addr. Puts the result in \p Res.
583  ///
584  /// \pre setBasicBlock or setMI must have been called.
585  /// \pre \p Res must be a generic virtual register.
586  /// \pre \p Addr must be a generic virtual register with pointer type.
587  ///
588  /// \return a MachineInstrBuilder for the newly created instruction.
589  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
590  unsigned Addr, MachineMemOperand &MMO);
591 
592  /// Build and insert `G_STORE Val, Addr, MMO`.
593  ///
594  /// Stores the value \p Val to \p Addr.
595  ///
596  /// \pre setBasicBlock or setMI must have been called.
597  /// \pre \p Val must be a generic virtual register.
598  /// \pre \p Addr must be a generic virtual register with pointer type.
599  ///
600  /// \return a MachineInstrBuilder for the newly created instruction.
601  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
602  MachineMemOperand &MMO);
603 
604  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
605  ///
606  /// \pre setBasicBlock or setMI must have been called.
607  /// \pre \p Res and \p Src must be generic virtual registers.
608  ///
609  /// \return a MachineInstrBuilder for the newly created instruction.
610  MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
611 
612  /// Build and insert \p Res = IMPLICIT_DEF.
613  MachineInstrBuilder buildUndef(const DstOp &Res);
614 
615  /// Build and insert instructions to put \p Ops together at the specified p
616  /// Indices to form a larger register.
617  ///
618  /// If the types of the input registers are uniform and cover the entirity of
619  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
620  /// followed by a sequence of G_INSERT instructions.
621  ///
622  /// \pre setBasicBlock or setMI must have been called.
623  /// \pre The final element of the sequence must not extend past the end of the
624  /// destination register.
625  /// \pre The bits defined by each Op (derived from index and scalar size) must
626  /// not overlap.
627  /// \pre \p Indices must be in ascending order of bit position.
628  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
629  ArrayRef<uint64_t> Indices);
630 
631  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
632  ///
633  /// G_MERGE_VALUES combines the input elements contiguously into a larger
634  /// register.
635  ///
636  /// \pre setBasicBlock or setMI must have been called.
637  /// \pre The entire register \p Res (and no more) must be covered by the input
638  /// registers.
639  /// \pre The type of all \p Ops registers must be identical.
640  ///
641  /// \return a MachineInstrBuilder for the newly created instruction.
642  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
643 
644  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
645  ///
646  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
647  ///
648  /// \pre setBasicBlock or setMI must have been called.
649  /// \pre The entire register \p Res (and no more) must be covered by the input
650  /// registers.
651  /// \pre The type of all \p Res registers must be identical.
652  ///
653  /// \return a MachineInstrBuilder for the newly created instruction.
654  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
655  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
656 
657  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
658  ///
659  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
660  /// \pre setBasicBlock or setMI must have been called.
661  /// \pre The entire register \p Res (and no more) must be covered by the
662  /// input scalar registers.
663  /// \pre The type of all \p Ops registers must be identical.
664  ///
665  /// \return a MachineInstrBuilder for the newly created instruction.
666  MachineInstrBuilder buildBuildVector(const DstOp &Res,
667  ArrayRef<unsigned> Ops);
668 
669  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
670  ///
671  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
672  /// which have types larger than the destination vector element type, and
673  /// truncates the values to fit.
674  ///
675  /// If the operands given are already the same size as the vector elt type,
676  /// then this method will instead create a G_BUILD_VECTOR instruction.
677  ///
678  /// \pre setBasicBlock or setMI must have been called.
679  /// \pre The type of all \p Ops registers must be identical.
680  ///
681  /// \return a MachineInstrBuilder for the newly created instruction.
682  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
683  ArrayRef<unsigned> Ops);
684 
685  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
686  ///
687  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
688  /// vectors.
689  ///
690  /// \pre setBasicBlock or setMI must have been called.
691  /// \pre The entire register \p Res (and no more) must be covered by the input
692  /// registers.
693  /// \pre The type of all source operands must be identical.
694  ///
695  /// \return a MachineInstrBuilder for the newly created instruction.
696  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
697  ArrayRef<unsigned> Ops);
698 
699  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
700  unsigned Op, unsigned Index);
701 
702  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
703  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
704  /// result register definition unless \p Reg is NoReg (== 0). The second
705  /// operand will be the intrinsic's ID.
706  ///
707  /// Callers are expected to add the required definitions and uses afterwards.
708  ///
709  /// \pre setBasicBlock or setMI must have been called.
710  ///
711  /// \return a MachineInstrBuilder for the newly created instruction.
712  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
713  bool HasSideEffects);
714 
715  /// Build and insert \p Res = G_FPTRUNC \p Op
716  ///
717  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
718  ///
719  /// \pre setBasicBlock or setMI must have been called.
720  /// \pre \p Res must be a generic virtual register with scalar or vector type.
721  /// \pre \p Op must be a generic virtual register with scalar or vector type.
722  /// \pre \p Res must be smaller than \p Op
723  ///
724  /// \return The newly created instruction.
725  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
726 
727  /// Build and insert \p Res = G_TRUNC \p Op
728  ///
729  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
730  /// truncated independently before being packed into the destination.
731  ///
732  /// \pre setBasicBlock or setMI must have been called.
733  /// \pre \p Res must be a generic virtual register with scalar or vector type.
734  /// \pre \p Op must be a generic virtual register with scalar or vector type.
735  /// \pre \p Res must be smaller than \p Op
736  ///
737  /// \return The newly created instruction.
738  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
739 
740  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
741  ///
742  /// \pre setBasicBlock or setMI must have been called.
743 
744  /// \pre \p Res must be a generic virtual register with scalar or
745  /// vector type. Typically this starts as s1 or <N x s1>.
746  /// \pre \p Op0 and Op1 must be generic virtual registers with the
747  /// same number of elements as \p Res. If \p Res is a scalar,
748  /// \p Op0 must be either a scalar or pointer.
749  /// \pre \p Pred must be an integer predicate.
750  ///
751  /// \return a MachineInstrBuilder for the newly created instruction.
752  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
753  const SrcOp &Op0, const SrcOp &Op1);
754 
755  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
756  ///
757  /// \pre setBasicBlock or setMI must have been called.
758 
759  /// \pre \p Res must be a generic virtual register with scalar or
760  /// vector type. Typically this starts as s1 or <N x s1>.
761  /// \pre \p Op0 and Op1 must be generic virtual registers with the
762  /// same number of elements as \p Res (or scalar, if \p Res is
763  /// scalar).
764  /// \pre \p Pred must be a floating-point predicate.
765  ///
766  /// \return a MachineInstrBuilder for the newly created instruction.
767  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
768  const SrcOp &Op0, const SrcOp &Op1);
769 
770  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
771  ///
772  /// \pre setBasicBlock or setMI must have been called.
773  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
774  /// with the same type.
775  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
776  /// vector type. If vector then it must have the same number of
777  /// elements as the other parameters.
778  ///
779  /// \return a MachineInstrBuilder for the newly created instruction.
780  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
781  const SrcOp &Op0, const SrcOp &Op1);
782 
783  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
784  /// \p Elt, \p Idx
785  ///
786  /// \pre setBasicBlock or setMI must have been called.
787  /// \pre \p Res and \p Val must be a generic virtual register
788  // with the same vector type.
789  /// \pre \p Elt and \p Idx must be a generic virtual register
790  /// with scalar type.
791  ///
792  /// \return The newly created instruction.
793  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
794  const SrcOp &Val,
795  const SrcOp &Elt,
796  const SrcOp &Idx);
797 
798  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
799  ///
800  /// \pre setBasicBlock or setMI must have been called.
801  /// \pre \p Res must be a generic virtual register with scalar type.
802  /// \pre \p Val must be a generic virtual register with vector type.
803  /// \pre \p Idx must be a generic virtual register with scalar type.
804  ///
805  /// \return The newly created instruction.
806  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
807  const SrcOp &Val,
808  const SrcOp &Idx);
809 
810  /// Build and insert `OldValRes<def>, SuccessRes<def> =
811  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
812  ///
813  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
814  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
815  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
816  ///
817  /// \pre setBasicBlock or setMI must have been called.
818  /// \pre \p OldValRes must be a generic virtual register of scalar type.
819  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
820  /// will be assigned 0 on failure and 1 on success.
821  /// \pre \p Addr must be a generic virtual register with pointer type.
822  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
823  /// registers of the same type.
824  ///
825  /// \return a MachineInstrBuilder for the newly created instruction.
827  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
828  unsigned Addr, unsigned CmpVal, unsigned NewVal,
829  MachineMemOperand &MMO);
830 
831  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
832  /// MMO`.
833  ///
834  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
835  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
836  /// Addr in \p Res.
837  ///
838  /// \pre setBasicBlock or setMI must have been called.
839  /// \pre \p OldValRes must be a generic virtual register of scalar type.
840  /// \pre \p Addr must be a generic virtual register with pointer type.
841  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
842  /// registers of the same type.
843  ///
844  /// \return a MachineInstrBuilder for the newly created instruction.
845  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
846  unsigned CmpVal, unsigned NewVal,
847  MachineMemOperand &MMO);
848 
849  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
850  ///
851  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
852  /// original value from \p Addr in \p OldValRes. The modification is
853  /// determined by the opcode.
854  ///
855  /// \pre setBasicBlock or setMI must have been called.
856  /// \pre \p OldValRes must be a generic virtual register.
857  /// \pre \p Addr must be a generic virtual register with pointer type.
858  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
859  /// same type.
860  ///
861  /// \return a MachineInstrBuilder for the newly created instruction.
862  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
863  unsigned Addr, unsigned Val,
864  MachineMemOperand &MMO);
865 
866  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
867  ///
868  /// Atomically replace the value at \p Addr with \p Val. Puts the original
869  /// value from \p Addr in \p OldValRes.
870  ///
871  /// \pre setBasicBlock or setMI must have been called.
872  /// \pre \p OldValRes must be a generic virtual register.
873  /// \pre \p Addr must be a generic virtual register with pointer type.
874  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
875  /// same type.
876  ///
877  /// \return a MachineInstrBuilder for the newly created instruction.
878  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
879  unsigned Val, MachineMemOperand &MMO);
880 
881  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
882  ///
883  /// Atomically replace the value at \p Addr with the addition of \p Val and
884  /// the original value. Puts the original value from \p Addr in \p OldValRes.
885  ///
886  /// \pre setBasicBlock or setMI must have been called.
887  /// \pre \p OldValRes must be a generic virtual register.
888  /// \pre \p Addr must be a generic virtual register with pointer type.
889  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
890  /// same type.
891  ///
892  /// \return a MachineInstrBuilder for the newly created instruction.
893  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
894  unsigned Val, MachineMemOperand &MMO);
895 
896  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
897  ///
898  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
899  /// the original value. Puts the original value from \p Addr in \p OldValRes.
900  ///
901  /// \pre setBasicBlock or setMI must have been called.
902  /// \pre \p OldValRes must be a generic virtual register.
903  /// \pre \p Addr must be a generic virtual register with pointer type.
904  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
905  /// same type.
906  ///
907  /// \return a MachineInstrBuilder for the newly created instruction.
908  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
909  unsigned Val, MachineMemOperand &MMO);
910 
911  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
912  ///
913  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
914  /// the original value. Puts the original value from \p Addr in \p OldValRes.
915  ///
916  /// \pre setBasicBlock or setMI must have been called.
917  /// \pre \p OldValRes must be a generic virtual register.
918  /// \pre \p Addr must be a generic virtual register with pointer type.
919  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
920  /// same type.
921  ///
922  /// \return a MachineInstrBuilder for the newly created instruction.
923  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
924  unsigned Val, MachineMemOperand &MMO);
925 
926  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
927  ///
928  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
929  /// and the original value. Puts the original value from \p Addr in \p
930  /// OldValRes.
931  ///
932  /// \pre setBasicBlock or setMI must have been called.
933  /// \pre \p OldValRes must be a generic virtual register.
934  /// \pre \p Addr must be a generic virtual register with pointer type.
935  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
936  /// same type.
937  ///
938  /// \return a MachineInstrBuilder for the newly created instruction.
939  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
940  unsigned Val, MachineMemOperand &MMO);
941 
942  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
943  ///
944  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
945  /// the original value. Puts the original value from \p Addr in \p OldValRes.
946  ///
947  /// \pre setBasicBlock or setMI must have been called.
948  /// \pre \p OldValRes must be a generic virtual register.
949  /// \pre \p Addr must be a generic virtual register with pointer type.
950  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
951  /// same type.
952  ///
953  /// \return a MachineInstrBuilder for the newly created instruction.
954  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
955  unsigned Val, MachineMemOperand &MMO);
956 
957  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
958  ///
959  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
960  /// the original value. Puts the original value from \p Addr in \p OldValRes.
961  ///
962  /// \pre setBasicBlock or setMI must have been called.
963  /// \pre \p OldValRes must be a generic virtual register.
964  /// \pre \p Addr must be a generic virtual register with pointer type.
965  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
966  /// same type.
967  ///
968  /// \return a MachineInstrBuilder for the newly created instruction.
969  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
970  unsigned Val, MachineMemOperand &MMO);
971 
972  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
973  ///
974  /// Atomically replace the value at \p Addr with the signed maximum of \p
975  /// Val and the original value. Puts the original value from \p Addr in \p
976  /// OldValRes.
977  ///
978  /// \pre setBasicBlock or setMI must have been called.
979  /// \pre \p OldValRes must be a generic virtual register.
980  /// \pre \p Addr must be a generic virtual register with pointer type.
981  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
982  /// same type.
983  ///
984  /// \return a MachineInstrBuilder for the newly created instruction.
985  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
986  unsigned Val, MachineMemOperand &MMO);
987 
988  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
989  ///
990  /// Atomically replace the value at \p Addr with the signed minimum of \p
991  /// Val and the original value. Puts the original value from \p Addr in \p
992  /// OldValRes.
993  ///
994  /// \pre setBasicBlock or setMI must have been called.
995  /// \pre \p OldValRes must be a generic virtual register.
996  /// \pre \p Addr must be a generic virtual register with pointer type.
997  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
998  /// same type.
999  ///
1000  /// \return a MachineInstrBuilder for the newly created instruction.
1001  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1002  unsigned Val, MachineMemOperand &MMO);
1003 
1004  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1005  ///
1006  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1007  /// Val and the original value. Puts the original value from \p Addr in \p
1008  /// OldValRes.
1009  ///
1010  /// \pre setBasicBlock or setMI must have been called.
1011  /// \pre \p OldValRes must be a generic virtual register.
1012  /// \pre \p Addr must be a generic virtual register with pointer type.
1013  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1014  /// same type.
1015  ///
1016  /// \return a MachineInstrBuilder for the newly created instruction.
1017  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1018  unsigned Val, MachineMemOperand &MMO);
1019 
1020  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1021  ///
1022  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1023  /// Val and the original value. Puts the original value from \p Addr in \p
1024  /// OldValRes.
1025  ///
1026  /// \pre setBasicBlock or setMI must have been called.
1027  /// \pre \p OldValRes must be a generic virtual register.
1028  /// \pre \p Addr must be a generic virtual register with pointer type.
1029  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1030  /// same type.
1031  ///
1032  /// \return a MachineInstrBuilder for the newly created instruction.
1033  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1034  unsigned Val, MachineMemOperand &MMO);
1035 
1036  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1037  ///
1038  /// G_BLOCK_ADDR computes the address of a basic block.
1039  ///
1040  /// \pre setBasicBlock or setMI must have been called.
1041  /// \pre \p Res must be a generic virtual register of a pointer type.
1042  ///
1043  /// \return The newly created instruction.
1044  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1045 
1046  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1047  ///
1048  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1049  /// truncated to their width.
1050  ///
1051  /// \pre setBasicBlock or setMI must have been called.
1052  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1053  /// with the same (scalar or vector) type).
1054  ///
1055  /// \return a MachineInstrBuilder for the newly created instruction.
1056 
1057  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1058  const SrcOp &Src1) {
1059  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1});
1060  }
1061 
1062  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1063  ///
1064  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1065  /// truncated to their width.
1066  ///
1067  /// \pre setBasicBlock or setMI must have been called.
1068  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1069  /// with the same (scalar or vector) type).
1070  ///
1071  /// \return a MachineInstrBuilder for the newly created instruction.
1072 
1073  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1074  const SrcOp &Src1) {
1075  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1});
1076  }
1077 
1078  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1079  ///
1080  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1081  /// truncated to their width.
1082  ///
1083  /// \pre setBasicBlock or setMI must have been called.
1084  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1085  /// with the same (scalar or vector) type).
1086  ///
1087  /// \return a MachineInstrBuilder for the newly created instruction.
1088  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1089  const SrcOp &Src1) {
1090  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1});
1091  }
1092 
1093  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1094  ///
1095  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1096  /// Op1.
1097  ///
1098  /// \pre setBasicBlock or setMI must have been called.
1099  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1100  /// with the same (scalar or vector) type).
1101  ///
1102  /// \return a MachineInstrBuilder for the newly created instruction.
1103 
1104  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1105  const SrcOp &Src1) {
1106  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1107  }
1108 
1109  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1110  ///
1111  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1112  /// Op1.
1113  ///
1114  /// \pre setBasicBlock or setMI must have been called.
1115  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1116  /// with the same (scalar or vector) type).
1117  ///
1118  /// \return a MachineInstrBuilder for the newly created instruction.
1119  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1120  const SrcOp &Src1) {
1121  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1122  }
1123 
1124  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1125  ArrayRef<SrcOp> SrcOps);
1126 };
1127 
1128 } // End namespace llvm.
1129 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
uint64_t CallInst * C
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
CmpInst::Predicate Pred
This class represents lattice values for constants.
Definition: AllocatorList.h:24
DstType getDstOpKind() const
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
DstType getType() const
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:864
F(f)
MachineIRBuilder(MachineInstr &MI)
The address of a basic block.
Definition: Constants.h:840
A description of a memory reference used in the backend.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SUB Op0, Op1.
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_MUL Op0, Op1.
DstOp(unsigned R)
SrcOp(const CmpInst::Predicate P)
MachineFunction & getMF()
Getter for the function we currently build.
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
unsigned getReg() const
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
Helper class to build MachineInstr.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:642
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_ADD Op0, Op1.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineIRBuilderState & getState()
Getter for the State.
SrcOp(unsigned R)
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1373
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.