LLVM  9.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
29 
30 using namespace llvm;
31 
32 static cl::opt<int>
33  PrintRegMaskNumRegs("print-regmask-num-regs",
34  cl::desc("Number of registers to limit to when "
35  "printing regmask operands in IR dumps. "
36  "unlimited = -1"),
37  cl::init(32), cl::Hidden);
38 
40  if (const MachineInstr *MI = MO.getParent())
41  if (const MachineBasicBlock *MBB = MI->getParent())
42  if (const MachineFunction *MF = MBB->getParent())
43  return MF;
44  return nullptr;
45 }
47  return const_cast<MachineFunction *>(
48  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
49 }
50 
51 void MachineOperand::setReg(unsigned Reg) {
52  if (getReg() == Reg)
53  return; // No change.
54 
55  // Clear the IsRenamable bit to keep it conservatively correct.
56  IsRenamable = false;
57 
58  // Otherwise, we have to change the register. If this operand is embedded
59  // into a machine function, we need to update the old and new register's
60  // use/def lists.
61  if (MachineFunction *MF = getMFIfAvailable(*this)) {
62  MachineRegisterInfo &MRI = MF->getRegInfo();
64  SmallContents.RegNo = Reg;
65  MRI.addRegOperandToUseList(this);
66  return;
67  }
68 
69  // Otherwise, just change the register, no problem. :)
70  SmallContents.RegNo = Reg;
71 }
72 
73 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
74  const TargetRegisterInfo &TRI) {
76  if (SubIdx && getSubReg())
77  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
78  setReg(Reg);
79  if (SubIdx)
80  setSubReg(SubIdx);
81 }
82 
85  if (getSubReg()) {
86  Reg = TRI.getSubReg(Reg, getSubReg());
87  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
88  // That won't happen in legal code.
89  setSubReg(0);
90  if (isDef())
91  setIsUndef(false);
92  }
93  setReg(Reg);
94 }
95 
96 /// Change a def to a use, or a use to a def.
98  assert(isReg() && "Wrong MachineOperand accessor");
99  assert((!Val || !isDebug()) && "Marking a debug operation as def");
100  if (IsDef == Val)
101  return;
102  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
103  // MRI may keep uses and defs in different list positions.
104  if (MachineFunction *MF = getMFIfAvailable(*this)) {
105  MachineRegisterInfo &MRI = MF->getRegInfo();
106  MRI.removeRegOperandFromUseList(this);
107  IsDef = Val;
108  MRI.addRegOperandToUseList(this);
109  return;
110  }
111  IsDef = Val;
112 }
113 
115  assert(isReg() && "Wrong MachineOperand accessor");
117  "isRenamable should only be checked on physical registers");
118  if (!IsRenamable)
119  return false;
120 
121  const MachineInstr *MI = getParent();
122  if (!MI)
123  return true;
124 
125  if (isDef())
127 
128  assert(isUse() && "Reg is not def or use");
130 }
131 
133  assert(isReg() && "Wrong MachineOperand accessor");
135  "setIsRenamable should only be called on physical registers");
136  IsRenamable = Val;
137 }
138 
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
141 void MachineOperand::removeRegFromUses() {
142  if (!isReg() || !isOnRegUseList())
143  return;
144 
145  if (MachineFunction *MF = getMFIfAvailable(*this))
146  MF->getRegInfo().removeRegOperandFromUseList(this);
147 }
148 
149 /// ChangeToImmediate - Replace this operand with a new immediate operand of
150 /// the specified value. If an operand is known to be an immediate already,
151 /// the setImm method should be used.
153  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
154 
155  removeRegFromUses();
156 
157  OpKind = MO_Immediate;
158  Contents.ImmVal = ImmVal;
159 }
160 
162  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163 
164  removeRegFromUses();
165 
166  OpKind = MO_FPImmediate;
167  Contents.CFP = FPImm;
168 }
169 
170 void MachineOperand::ChangeToES(const char *SymName,
171  unsigned char TargetFlags) {
172  assert((!isReg() || !isTied()) &&
173  "Cannot change a tied operand into an external symbol");
174 
175  removeRegFromUses();
176 
177  OpKind = MO_ExternalSymbol;
178  Contents.OffsetedInfo.Val.SymbolName = SymName;
179  setOffset(0); // Offset is always 0.
180  setTargetFlags(TargetFlags);
181 }
182 
184  assert((!isReg() || !isTied()) &&
185  "Cannot change a tied operand into an MCSymbol");
186 
187  removeRegFromUses();
188 
189  OpKind = MO_MCSymbol;
190  Contents.Sym = Sym;
191 }
192 
194  assert((!isReg() || !isTied()) &&
195  "Cannot change a tied operand into a FrameIndex");
196 
197  removeRegFromUses();
198 
199  OpKind = MO_FrameIndex;
200  setIndex(Idx);
201 }
202 
203 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
204  unsigned char TargetFlags) {
205  assert((!isReg() || !isTied()) &&
206  "Cannot change a tied operand into a FrameIndex");
207 
208  removeRegFromUses();
209 
210  OpKind = MO_TargetIndex;
211  setIndex(Idx);
212  setOffset(Offset);
213  setTargetFlags(TargetFlags);
214 }
215 
216 /// ChangeToRegister - Replace this operand with a new register operand of
217 /// the specified value. If an operand is known to be an register already,
218 /// the setReg method should be used.
219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
220  bool isKill, bool isDead, bool isUndef,
221  bool isDebug) {
222  MachineRegisterInfo *RegInfo = nullptr;
223  if (MachineFunction *MF = getMFIfAvailable(*this))
224  RegInfo = &MF->getRegInfo();
225  // If this operand is already a register operand, remove it from the
226  // register's use/def lists.
227  bool WasReg = isReg();
228  if (RegInfo && WasReg)
229  RegInfo->removeRegOperandFromUseList(this);
230 
231  // Change this to a register and set the reg#.
232  assert(!(isDead && !isDef) && "Dead flag on non-def");
233  assert(!(isKill && isDef) && "Kill flag on def");
234  OpKind = MO_Register;
235  SmallContents.RegNo = Reg;
236  SubReg_TargetFlags = 0;
237  IsDef = isDef;
238  IsImp = isImp;
239  IsDeadOrKill = isKill | isDead;
240  IsRenamable = false;
241  IsUndef = isUndef;
242  IsInternalRead = false;
243  IsEarlyClobber = false;
244  IsDebug = isDebug;
245  // Ensure isOnRegUseList() returns false.
246  Contents.Reg.Prev = nullptr;
247  // Preserve the tie when the operand was already a register.
248  if (!WasReg)
249  TiedTo = 0;
250 
251  // If this operand is embedded in a function, add the operand to the
252  // register's use/def list.
253  if (RegInfo)
254  RegInfo->addRegOperandToUseList(this);
255 }
256 
257 /// isIdenticalTo - Return true if this operand is identical to the specified
258 /// operand. Note that this should stay in sync with the hash_value overload
259 /// below.
261  if (getType() != Other.getType() ||
262  getTargetFlags() != Other.getTargetFlags())
263  return false;
264 
265  switch (getType()) {
267  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
268  getSubReg() == Other.getSubReg();
270  return getImm() == Other.getImm();
272  return getCImm() == Other.getCImm();
274  return getFPImm() == Other.getFPImm();
276  return getMBB() == Other.getMBB();
278  return getIndex() == Other.getIndex();
281  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
283  return getIndex() == Other.getIndex();
285  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
287  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
288  getOffset() == Other.getOffset();
290  return getBlockAddress() == Other.getBlockAddress() &&
291  getOffset() == Other.getOffset();
294  // Shallow compare of the two RegMasks
295  const uint32_t *RegMask = getRegMask();
296  const uint32_t *OtherRegMask = Other.getRegMask();
297  if (RegMask == OtherRegMask)
298  return true;
299 
300  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
301  // Calculate the size of the RegMask
302  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
303  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
304 
305  // Deep compare of the two RegMasks
306  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
307  }
308  // We don't know the size of the RegMask, so we can't deep compare the two
309  // reg masks.
310  return false;
311  }
313  return getMCSymbol() == Other.getMCSymbol();
315  return getCFIIndex() == Other.getCFIIndex();
317  return getMetadata() == Other.getMetadata();
319  return getIntrinsicID() == Other.getIntrinsicID();
321  return getPredicate() == Other.getPredicate();
322  }
323  llvm_unreachable("Invalid machine operand type");
324 }
325 
326 // Note: this must stay exactly in sync with isIdenticalTo above.
328  switch (MO.getType()) {
330  // Register operands don't have target flags.
331  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
333  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
335  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
337  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
339  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
341  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
344  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
345  MO.getOffset());
347  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
349  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
350  MO.getSymbolName());
352  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
353  MO.getOffset());
355  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
356  MO.getOffset());
359  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
367  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
369  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
370  }
371  llvm_unreachable("Invalid machine operand type");
372 }
373 
374 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
375 // it.
376 static void tryToGetTargetInfo(const MachineOperand &MO,
377  const TargetRegisterInfo *&TRI,
378  const TargetIntrinsicInfo *&IntrinsicInfo) {
379  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
380  TRI = MF->getSubtarget().getRegisterInfo();
381  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
382  }
383 }
384 
385 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
386  const auto *TII = MF.getSubtarget().getInstrInfo();
387  assert(TII && "expected instruction info");
388  auto Indices = TII->getSerializableTargetIndices();
389  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
390  return I.first == Index;
391  });
392  if (Found != Indices.end())
393  return Found->second;
394  return nullptr;
395 }
396 
397 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
399  for (const auto &I : Flags) {
400  if (I.first == TF) {
401  return I.second;
402  }
403  }
404  return nullptr;
405 }
406 
407 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
408  const TargetRegisterInfo *TRI) {
409  if (!TRI) {
410  OS << "%dwarfreg." << DwarfReg;
411  return;
412  }
413 
414  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
415  if (Reg == -1) {
416  OS << "<badreg>";
417  return;
418  }
419  OS << printReg(Reg, TRI);
420 }
421 
422 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
423  ModuleSlotTracker &MST) {
424  OS << "%ir-block.";
425  if (BB.hasName()) {
427  return;
428  }
429  Optional<int> Slot;
430  if (const Function *F = BB.getParent()) {
431  if (F == MST.getCurrentFunction()) {
432  Slot = MST.getLocalSlot(&BB);
433  } else if (const Module *M = F->getParent()) {
434  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
435  CustomMST.incorporateFunction(*F);
436  Slot = CustomMST.getLocalSlot(&BB);
437  }
438  }
439  if (Slot)
441  else
442  OS << "<unknown>";
443 }
444 
445 static void printIRValueReference(raw_ostream &OS, const Value &V,
446  ModuleSlotTracker &MST) {
447  if (isa<GlobalValue>(V)) {
448  V.printAsOperand(OS, /*PrintType=*/false, MST);
449  return;
450  }
451  if (isa<Constant>(V)) {
452  // Machine memory operands can load/store to/from constant value pointers.
453  OS << '`';
454  V.printAsOperand(OS, /*PrintType=*/true, MST);
455  OS << '`';
456  return;
457  }
458  OS << "%ir.";
459  if (V.hasName()) {
461  return;
462  }
463  int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
465 }
466 
468  SyncScope::ID SSID,
470  switch (SSID) {
471  case SyncScope::System:
472  break;
473  default:
474  if (SSNs.empty())
475  Context.getSyncScopeNames(SSNs);
476 
477  OS << "syncscope(\"";
478  printEscapedString(SSNs[SSID], OS);
479  OS << "\") ";
480  break;
481  }
482 }
483 
484 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
485  unsigned TMMOFlag) {
487  for (const auto &I : Flags) {
488  if (I.first == TMMOFlag) {
489  return I.second;
490  }
491  }
492  return nullptr;
493 }
494 
495 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
496  const MachineFrameInfo *MFI) {
497  StringRef Name;
498  if (MFI) {
499  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
500  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
501  if (Alloca->hasName())
502  Name = Alloca->getName();
503  if (IsFixed)
504  FrameIndex -= MFI->getObjectIndexBegin();
505  }
506  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
507 }
508 
510  const TargetRegisterInfo *TRI) {
511  OS << "%subreg.";
512  if (TRI)
513  OS << TRI->getSubRegIndexName(Index);
514  else
515  OS << Index;
516 }
517 
519  const MachineOperand &Op) {
520  if (!Op.getTargetFlags())
521  return;
522  const MachineFunction *MF = getMFIfAvailable(Op);
523  if (!MF)
524  return;
525 
526  const auto *TII = MF->getSubtarget().getInstrInfo();
527  assert(TII && "expected instruction info");
529  OS << "target-flags(";
530  const bool HasDirectFlags = Flags.first;
531  const bool HasBitmaskFlags = Flags.second;
532  if (!HasDirectFlags && !HasBitmaskFlags) {
533  OS << "<unknown>) ";
534  return;
535  }
536  if (HasDirectFlags) {
537  if (const auto *Name = getTargetFlagName(TII, Flags.first))
538  OS << Name;
539  else
540  OS << "<unknown target flag>";
541  }
542  if (!HasBitmaskFlags) {
543  OS << ") ";
544  return;
545  }
546  bool IsCommaNeeded = HasDirectFlags;
547  unsigned BitMask = Flags.second;
549  for (const auto &Mask : BitMasks) {
550  // Check if the flag's bitmask has the bits of the current mask set.
551  if ((BitMask & Mask.first) == Mask.first) {
552  if (IsCommaNeeded)
553  OS << ", ";
554  IsCommaNeeded = true;
555  OS << Mask.second;
556  // Clear the bits which were serialized from the flag's bitmask.
557  BitMask &= ~(Mask.first);
558  }
559  }
560  if (BitMask) {
561  // When the resulting flag's bitmask isn't zero, we know that we didn't
562  // serialize all of the bit flags.
563  if (IsCommaNeeded)
564  OS << ", ";
565  OS << "<unknown bitmask target flag>";
566  }
567  OS << ") ";
568 }
569 
571  OS << "<mcsymbol " << Sym << ">";
572 }
573 
575  unsigned FrameIndex,
576  bool IsFixed, StringRef Name) {
577  if (IsFixed) {
578  OS << "%fixed-stack." << FrameIndex;
579  return;
580  }
581 
582  OS << "%stack." << FrameIndex;
583  if (!Name.empty())
584  OS << '.' << Name;
585 }
586 
588  if (Offset == 0)
589  return;
590  if (Offset < 0) {
591  OS << " - " << -Offset;
592  return;
593  }
594  OS << " + " << Offset;
595 }
596 
598  if (Slot == -1)
599  OS << "<badref>";
600  else
601  OS << Slot;
602 }
603 
604 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
605  const TargetRegisterInfo *TRI) {
606  switch (CFI.getOperation()) {
608  OS << "same_value ";
609  if (MCSymbol *Label = CFI.getLabel())
610  MachineOperand::printSymbol(OS, *Label);
611  printCFIRegister(CFI.getRegister(), OS, TRI);
612  break;
614  OS << "remember_state ";
615  if (MCSymbol *Label = CFI.getLabel())
616  MachineOperand::printSymbol(OS, *Label);
617  break;
619  OS << "restore_state ";
620  if (MCSymbol *Label = CFI.getLabel())
621  MachineOperand::printSymbol(OS, *Label);
622  break;
624  OS << "offset ";
625  if (MCSymbol *Label = CFI.getLabel())
626  MachineOperand::printSymbol(OS, *Label);
627  printCFIRegister(CFI.getRegister(), OS, TRI);
628  OS << ", " << CFI.getOffset();
629  break;
631  OS << "def_cfa_register ";
632  if (MCSymbol *Label = CFI.getLabel())
633  MachineOperand::printSymbol(OS, *Label);
634  printCFIRegister(CFI.getRegister(), OS, TRI);
635  break;
637  OS << "def_cfa_offset ";
638  if (MCSymbol *Label = CFI.getLabel())
639  MachineOperand::printSymbol(OS, *Label);
640  OS << CFI.getOffset();
641  break;
643  OS << "def_cfa ";
644  if (MCSymbol *Label = CFI.getLabel())
645  MachineOperand::printSymbol(OS, *Label);
646  printCFIRegister(CFI.getRegister(), OS, TRI);
647  OS << ", " << CFI.getOffset();
648  break;
650  OS << "rel_offset ";
651  if (MCSymbol *Label = CFI.getLabel())
652  MachineOperand::printSymbol(OS, *Label);
653  printCFIRegister(CFI.getRegister(), OS, TRI);
654  OS << ", " << CFI.getOffset();
655  break;
657  OS << "adjust_cfa_offset ";
658  if (MCSymbol *Label = CFI.getLabel())
659  MachineOperand::printSymbol(OS, *Label);
660  OS << CFI.getOffset();
661  break;
663  OS << "restore ";
664  if (MCSymbol *Label = CFI.getLabel())
665  MachineOperand::printSymbol(OS, *Label);
666  printCFIRegister(CFI.getRegister(), OS, TRI);
667  break;
669  OS << "escape ";
670  if (MCSymbol *Label = CFI.getLabel())
671  MachineOperand::printSymbol(OS, *Label);
672  if (!CFI.getValues().empty()) {
673  size_t e = CFI.getValues().size() - 1;
674  for (size_t i = 0; i < e; ++i)
675  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
676  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
677  }
678  break;
679  }
681  OS << "undefined ";
682  if (MCSymbol *Label = CFI.getLabel())
683  MachineOperand::printSymbol(OS, *Label);
684  printCFIRegister(CFI.getRegister(), OS, TRI);
685  break;
687  OS << "register ";
688  if (MCSymbol *Label = CFI.getLabel())
689  MachineOperand::printSymbol(OS, *Label);
690  printCFIRegister(CFI.getRegister(), OS, TRI);
691  OS << ", ";
692  printCFIRegister(CFI.getRegister2(), OS, TRI);
693  break;
695  OS << "window_save ";
696  if (MCSymbol *Label = CFI.getLabel())
697  MachineOperand::printSymbol(OS, *Label);
698  break;
700  OS << "negate_ra_sign_state ";
701  if (MCSymbol *Label = CFI.getLabel())
702  MachineOperand::printSymbol(OS, *Label);
703  break;
704  default:
705  // TODO: Print the other CFI Operations.
706  OS << "<unserializable cfi directive>";
707  break;
708  }
709 }
710 
712  const TargetIntrinsicInfo *IntrinsicInfo) const {
713  print(OS, LLT{}, TRI, IntrinsicInfo);
714 }
715 
716 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
717  const TargetRegisterInfo *TRI,
718  const TargetIntrinsicInfo *IntrinsicInfo) const {
719  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
720  ModuleSlotTracker DummyMST(nullptr);
721  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
722  /*ShouldPrintRegisterTies=*/true,
723  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
724 }
725 
727  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
728  bool ShouldPrintRegisterTies,
729  unsigned TiedOperandIdx,
730  const TargetRegisterInfo *TRI,
731  const TargetIntrinsicInfo *IntrinsicInfo) const {
732  printTargetFlags(OS, *this);
733  switch (getType()) {
735  unsigned Reg = getReg();
736  if (isImplicit())
737  OS << (isDef() ? "implicit-def " : "implicit ");
738  else if (PrintDef && isDef())
739  // Print the 'def' flag only when the operand is defined after '='.
740  OS << "def ";
741  if (isInternalRead())
742  OS << "internal ";
743  if (isDead())
744  OS << "dead ";
745  if (isKill())
746  OS << "killed ";
747  if (isUndef())
748  OS << "undef ";
749  if (isEarlyClobber())
750  OS << "early-clobber ";
752  OS << "renamable ";
753  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
754  // simply infer it when parsing and do not need to print it.
755 
756  const MachineRegisterInfo *MRI = nullptr;
758  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
759  MRI = &MF->getRegInfo();
760  }
761  }
762 
763  OS << printReg(Reg, TRI, 0, MRI);
764  // Print the sub register.
765  if (unsigned SubReg = getSubReg()) {
766  if (TRI)
767  OS << '.' << TRI->getSubRegIndexName(SubReg);
768  else
769  OS << ".subreg" << SubReg;
770  }
771  // Print the register class / bank.
773  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
774  const MachineRegisterInfo &MRI = MF->getRegInfo();
775  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
776  OS << ':';
777  OS << printRegClassOrBank(Reg, MRI, TRI);
778  }
779  }
780  }
781  // Print ties.
782  if (ShouldPrintRegisterTies && isTied() && !isDef())
783  OS << "(tied-def " << TiedOperandIdx << ")";
784  // Print types.
785  if (TypeToPrint.isValid())
786  OS << '(' << TypeToPrint << ')';
787  break;
788  }
790  OS << getImm();
791  break;
793  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
794  break;
796  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
797  break;
799  OS << printMBBReference(*getMBB());
800  break;
802  int FrameIndex = getIndex();
803  bool IsFixed = false;
804  const MachineFrameInfo *MFI = nullptr;
805  if (const MachineFunction *MF = getMFIfAvailable(*this))
806  MFI = &MF->getFrameInfo();
807  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
808  break;
809  }
811  OS << "%const." << getIndex();
813  break;
815  OS << "target-index(";
816  const char *Name = "<unknown>";
817  if (const MachineFunction *MF = getMFIfAvailable(*this))
818  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
819  Name = TargetIndexName;
820  OS << Name << ')';
822  break;
823  }
826  break;
828  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
830  break;
833  OS << '&';
834  if (Name.empty()) {
835  OS << "\"\"";
836  } else {
837  printLLVMNameWithoutPrefix(OS, Name);
838  }
840  break;
841  }
843  OS << "blockaddress(";
844  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
845  MST);
846  OS << ", ";
847  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
848  OS << ')';
850  break;
851  }
853  OS << "<regmask";
854  if (TRI) {
855  unsigned NumRegsInMask = 0;
856  unsigned NumRegsEmitted = 0;
857  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
858  unsigned MaskWord = i / 32;
859  unsigned MaskBit = i % 32;
860  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
861  if (PrintRegMaskNumRegs < 0 ||
862  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
863  OS << " " << printReg(i, TRI);
864  NumRegsEmitted++;
865  }
866  NumRegsInMask++;
867  }
868  }
869  if (NumRegsEmitted != NumRegsInMask)
870  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
871  } else {
872  OS << " ...";
873  }
874  OS << ">";
875  break;
876  }
878  const uint32_t *RegMask = getRegLiveOut();
879  OS << "liveout(";
880  if (!TRI) {
881  OS << "<unknown>";
882  } else {
883  bool IsCommaNeeded = false;
884  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
885  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
886  if (IsCommaNeeded)
887  OS << ", ";
888  OS << printReg(Reg, TRI);
889  IsCommaNeeded = true;
890  }
891  }
892  }
893  OS << ")";
894  break;
895  }
897  getMetadata()->printAsOperand(OS, MST);
898  break;
900  printSymbol(OS, *getMCSymbol());
901  break;
903  if (const MachineFunction *MF = getMFIfAvailable(*this))
904  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
905  else
906  OS << "<cfi directive>";
907  break;
908  }
911  if (ID < Intrinsic::num_intrinsics)
912  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
913  else if (IntrinsicInfo)
914  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
915  else
916  OS << "intrinsic(" << ID << ')';
917  break;
918  }
920  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
921  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
922  << CmpInst::getPredicateName(Pred) << ')';
923  break;
924  }
925  }
926 }
927 
928 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
929 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
930 #endif
931 
932 //===----------------------------------------------------------------------===//
933 // MachineMemOperand Implementation
934 //===----------------------------------------------------------------------===//
935 
936 /// getAddrSpace - Return the LLVM IR address space number that this pointer
937 /// points into.
938 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
939 
940 /// isDereferenceable - Return true if V is always dereferenceable for
941 /// Offset + Size byte.
943  const DataLayout &DL) const {
944  if (!V.is<const Value *>())
945  return false;
946 
947  const Value *BasePtr = V.get<const Value *>();
948  if (BasePtr == nullptr)
949  return false;
950 
952  BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
953 }
954 
955 /// getConstantPool - Return a MachinePointerInfo record that refers to the
956 /// constant pool.
959 }
960 
961 /// getFixedStack - Return a MachinePointerInfo record that refers to the
962 /// the specified FrameIndex.
964  int FI, int64_t Offset) {
966 }
967 
970 }
971 
973  return MachinePointerInfo(MF.getPSVManager().getGOT());
974 }
975 
977  int64_t Offset, uint8_t ID) {
979 }
980 
983 }
984 
986  uint64_t s, uint64_t a,
987  const AAMDNodes &AAInfo,
988  const MDNode *Ranges, SyncScope::ID SSID,
989  AtomicOrdering Ordering,
990  AtomicOrdering FailureOrdering)
991  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
992  AAInfo(AAInfo), Ranges(Ranges) {
993  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
994  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
995  "invalid pointer value");
996  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
997  assert((isLoad() || isStore()) && "Not a load/store!");
998 
999  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1000  assert(getSyncScopeID() == SSID && "Value truncated");
1001  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1002  assert(getOrdering() == Ordering && "Value truncated");
1003  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1004  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1005 }
1006 
1007 /// Profile - Gather unique data for the object.
1008 ///
1010  ID.AddInteger(getOffset());
1011  ID.AddInteger(Size);
1012  ID.AddPointer(getOpaqueValue());
1013  ID.AddInteger(getFlags());
1015 }
1016 
1018  // The Value and Offset may differ due to CSE. But the flags and size
1019  // should be the same.
1020  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1021  assert(MMO->getSize() == getSize() && "Size mismatch!");
1022 
1023  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1024  // Update the alignment value.
1025  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1026  // Also update the base and offset, because the new alignment may
1027  // not be applicable with the old ones.
1028  PtrInfo = MMO->PtrInfo;
1029  }
1030 }
1031 
1032 /// getAlignment - Return the minimum known alignment in bytes of the
1033 /// actual memory reference.
1035  return MinAlign(getBaseAlignment(), getOffset());
1036 }
1037 
1039  ModuleSlotTracker DummyMST(nullptr);
1040  print(OS, DummyMST);
1041 }
1042 
1045  LLVMContext Ctx;
1046  print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1047 }
1048 
1051  const LLVMContext &Context,
1052  const MachineFrameInfo *MFI,
1053  const TargetInstrInfo *TII) const {
1054  OS << '(';
1055  if (isVolatile())
1056  OS << "volatile ";
1057  if (isNonTemporal())
1058  OS << "non-temporal ";
1059  if (isDereferenceable())
1060  OS << "dereferenceable ";
1061  if (isInvariant())
1062  OS << "invariant ";
1065  << "\" ";
1068  << "\" ";
1071  << "\" ";
1072 
1073  assert((isLoad() || isStore()) &&
1074  "machine memory operand must be a load or store (or both)");
1075  if (isLoad())
1076  OS << "load ";
1077  if (isStore())
1078  OS << "store ";
1079 
1080  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1081 
1083  OS << toIRString(getOrdering()) << ' ';
1085  OS << toIRString(getFailureOrdering()) << ' ';
1086 
1088  OS << "unknown-size";
1089  else
1090  OS << getSize();
1091 
1092  if (const Value *Val = getValue()) {
1093  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1094  printIRValueReference(OS, *Val, MST);
1095  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1096  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1097  assert(PVal && "Expected a pseudo source value");
1098  switch (PVal->kind()) {
1100  OS << "stack";
1101  break;
1103  OS << "got";
1104  break;
1106  OS << "jump-table";
1107  break;
1109  OS << "constant-pool";
1110  break;
1112  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1113  bool IsFixed = true;
1114  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1115  break;
1116  }
1118  OS << "call-entry ";
1119  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1120  OS, /*PrintType=*/false, MST);
1121  break;
1123  OS << "call-entry &";
1125  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1126  break;
1128  // FIXME: This is not necessarily the correct MIR serialization format for
1129  // a custom pseudo source value, but at least it allows
1130  // -print-machineinstrs to work on a target with custom pseudo source
1131  // values.
1132  OS << "custom ";
1133  PVal->printCustom(OS);
1134  break;
1135  }
1136  }
1138  if (getBaseAlignment() != getSize())
1139  OS << ", align " << getBaseAlignment();
1140  auto AAInfo = getAAInfo();
1141  if (AAInfo.TBAA) {
1142  OS << ", !tbaa ";
1143  AAInfo.TBAA->printAsOperand(OS, MST);
1144  }
1145  if (AAInfo.Scope) {
1146  OS << ", !alias.scope ";
1147  AAInfo.Scope->printAsOperand(OS, MST);
1148  }
1149  if (AAInfo.NoAlias) {
1150  OS << ", !noalias ";
1151  AAInfo.NoAlias->printAsOperand(OS, MST);
1152  }
1153  if (getRanges()) {
1154  OS << ", !range ";
1155  getRanges()->printAsOperand(OS, MST);
1156  }
1157  // FIXME: Implement addrspace printing/parsing in MIR.
1158  // For now, print this even though parsing it is not available in MIR.
1159  if (unsigned AS = getAddrSpace())
1160  OS << ", addrspace " << AS;
1161 
1162  OS << ')';
1163 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:51
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
LLVMContext & Context
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
MachineBasicBlock * getMBB() const
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:660
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:464
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:657
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:926
const uint32_t * RegMask
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned Reg
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:854
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
uint64_t getSize() const
Return the size in bytes of the memory reference.
void printEscapedString(StringRef Name, raw_ostream &Out)
Print each character of the specified string, escaping it if it is not printable or if it is an escap...
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, uint64_t a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:362
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:863
F(f)
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void print(raw_ostream &OS) const
Support for operator<<.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:113
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:865
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:257
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:625
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:60
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
const char * getSymbolName() const
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getCFIIndex() const
union llvm::MachineOperand::@164::@167::@168 Val
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
Immediate >64bit operand.
PseudoSourceValueManager & getPSVManager() const
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4430
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:558
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:336
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
struct llvm::MachineOperand::@164::@166 Reg
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:305
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:250
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
unsigned getRegister2() const
Definition: MCDwarf.h:568
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getOffset() const
Definition: MCDwarf.h:573
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:557
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:645
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:580
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:840
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4224
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:560
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:397
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:663
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
bool isIntPredicate() const
Definition: InstrTypes.h:738
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:600
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:71
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
This file provides utility analysis objects describing memory locations.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:213
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:916
Flags getFlags() const
Return the raw flags of the source value,.
void setSubReg(unsigned subReg)
uint32_t Size
Definition: Profile.cpp:46
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:134
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4266
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:72
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:122
Address of indexed Constant in Constant Pool.
bool isDereferenceableAndAlignedPointer(const Value *V, unsigned Align, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:128
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MDNode * getMetadata() const
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:59
static void printIRValueReference(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.