LLVM  7.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/Analysis/Loads.h"
22 #include "llvm/IR/Constants.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<int>
31  PrintRegMaskNumRegs("print-regmask-num-regs",
32  cl::desc("Number of registers to limit to when "
33  "printing regmask operands in IR dumps. "
34  "unlimited = -1"),
35  cl::init(32), cl::Hidden);
36 
38  if (const MachineInstr *MI = MO.getParent())
39  if (const MachineBasicBlock *MBB = MI->getParent())
40  if (const MachineFunction *MF = MBB->getParent())
41  return MF;
42  return nullptr;
43 }
45  return const_cast<MachineFunction *>(
46  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
47 }
48 
49 void MachineOperand::setReg(unsigned Reg) {
50  if (getReg() == Reg)
51  return; // No change.
52 
53  // Otherwise, we have to change the register. If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineFunction *MF = getMFIfAvailable(*this)) {
57  MachineRegisterInfo &MRI = MF->getRegInfo();
59  SmallContents.RegNo = Reg;
60  MRI.addRegOperandToUseList(this);
61  return;
62  }
63 
64  // Otherwise, just change the register, no problem. :)
65  SmallContents.RegNo = Reg;
66 }
67 
68 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
69  const TargetRegisterInfo &TRI) {
71  if (SubIdx && getSubReg())
72  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
73  setReg(Reg);
74  if (SubIdx)
75  setSubReg(SubIdx);
76 }
77 
80  if (getSubReg()) {
81  Reg = TRI.getSubReg(Reg, getSubReg());
82  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
83  // That won't happen in legal code.
84  setSubReg(0);
85  if (isDef())
86  setIsUndef(false);
87  }
88  setReg(Reg);
89 }
90 
91 /// Change a def to a use, or a use to a def.
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96  return;
97  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
98  // MRI may keep uses and defs in different list positions.
99  if (MachineFunction *MF = getMFIfAvailable(*this)) {
100  MachineRegisterInfo &MRI = MF->getRegInfo();
101  MRI.removeRegOperandFromUseList(this);
102  IsDef = Val;
103  MRI.addRegOperandToUseList(this);
104  return;
105  }
106  IsDef = Val;
107 }
108 
110  assert(isReg() && "Wrong MachineOperand accessor");
112  "isRenamable should only be checked on physical registers");
113  return IsRenamable;
114 }
115 
117  assert(isReg() && "Wrong MachineOperand accessor");
119  "setIsRenamable should only be called on physical registers");
120  if (const MachineInstr *MI = getParent())
121  if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
122  (isUse() && MI->hasExtraSrcRegAllocReq()))
123  assert(!Val && "isRenamable should be false for "
124  "hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
125  IsRenamable = Val;
126 }
127 
129  if (const MachineInstr *MI = getParent())
130  if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
131  (isUse() && MI->hasExtraSrcRegAllocReq()))
132  return;
133 
134  setIsRenamable(true);
135 }
136 
137 // If this operand is currently a register operand, and if this is in a
138 // function, deregister the operand from the register's use/def list.
139 void MachineOperand::removeRegFromUses() {
140  if (!isReg() || !isOnRegUseList())
141  return;
142 
143  if (MachineFunction *MF = getMFIfAvailable(*this))
144  MF->getRegInfo().removeRegOperandFromUseList(this);
145 }
146 
147 /// ChangeToImmediate - Replace this operand with a new immediate operand of
148 /// the specified value. If an operand is known to be an immediate already,
149 /// the setImm method should be used.
151  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
152 
153  removeRegFromUses();
154 
155  OpKind = MO_Immediate;
156  Contents.ImmVal = ImmVal;
157 }
158 
160  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
161 
162  removeRegFromUses();
163 
164  OpKind = MO_FPImmediate;
165  Contents.CFP = FPImm;
166 }
167 
168 void MachineOperand::ChangeToES(const char *SymName,
169  unsigned char TargetFlags) {
170  assert((!isReg() || !isTied()) &&
171  "Cannot change a tied operand into an external symbol");
172 
173  removeRegFromUses();
174 
175  OpKind = MO_ExternalSymbol;
176  Contents.OffsetedInfo.Val.SymbolName = SymName;
177  setOffset(0); // Offset is always 0.
178  setTargetFlags(TargetFlags);
179 }
180 
182  assert((!isReg() || !isTied()) &&
183  "Cannot change a tied operand into an MCSymbol");
184 
185  removeRegFromUses();
186 
187  OpKind = MO_MCSymbol;
188  Contents.Sym = Sym;
189 }
190 
192  assert((!isReg() || !isTied()) &&
193  "Cannot change a tied operand into a FrameIndex");
194 
195  removeRegFromUses();
196 
197  OpKind = MO_FrameIndex;
198  setIndex(Idx);
199 }
200 
201 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
202  unsigned char TargetFlags) {
203  assert((!isReg() || !isTied()) &&
204  "Cannot change a tied operand into a FrameIndex");
205 
206  removeRegFromUses();
207 
208  OpKind = MO_TargetIndex;
209  setIndex(Idx);
210  setOffset(Offset);
211  setTargetFlags(TargetFlags);
212 }
213 
214 /// ChangeToRegister - Replace this operand with a new register operand of
215 /// the specified value. If an operand is known to be an register already,
216 /// the setReg method should be used.
217 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
218  bool isKill, bool isDead, bool isUndef,
219  bool isDebug) {
220  MachineRegisterInfo *RegInfo = nullptr;
221  if (MachineFunction *MF = getMFIfAvailable(*this))
222  RegInfo = &MF->getRegInfo();
223  // If this operand is already a register operand, remove it from the
224  // register's use/def lists.
225  bool WasReg = isReg();
226  if (RegInfo && WasReg)
227  RegInfo->removeRegOperandFromUseList(this);
228 
229  // Change this to a register and set the reg#.
230  assert(!(isDead && !isDef) && "Dead flag on non-def");
231  assert(!(isKill && isDef) && "Kill flag on def");
232  OpKind = MO_Register;
233  SmallContents.RegNo = Reg;
234  SubReg_TargetFlags = 0;
235  IsDef = isDef;
236  IsImp = isImp;
237  IsDeadOrKill = isKill | isDead;
238  IsRenamable = false;
239  IsUndef = isUndef;
240  IsInternalRead = false;
241  IsEarlyClobber = false;
242  IsDebug = isDebug;
243  // Ensure isOnRegUseList() returns false.
244  Contents.Reg.Prev = nullptr;
245  // Preserve the tie when the operand was already a register.
246  if (!WasReg)
247  TiedTo = 0;
248 
249  // If this operand is embedded in a function, add the operand to the
250  // register's use/def list.
251  if (RegInfo)
252  RegInfo->addRegOperandToUseList(this);
253 }
254 
255 /// isIdenticalTo - Return true if this operand is identical to the specified
256 /// operand. Note that this should stay in sync with the hash_value overload
257 /// below.
259  if (getType() != Other.getType() ||
260  getTargetFlags() != Other.getTargetFlags())
261  return false;
262 
263  switch (getType()) {
265  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
266  getSubReg() == Other.getSubReg();
268  return getImm() == Other.getImm();
270  return getCImm() == Other.getCImm();
272  return getFPImm() == Other.getFPImm();
274  return getMBB() == Other.getMBB();
276  return getIndex() == Other.getIndex();
279  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
281  return getIndex() == Other.getIndex();
283  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
285  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
286  getOffset() == Other.getOffset();
288  return getBlockAddress() == Other.getBlockAddress() &&
289  getOffset() == Other.getOffset();
292  // Shallow compare of the two RegMasks
293  const uint32_t *RegMask = getRegMask();
294  const uint32_t *OtherRegMask = Other.getRegMask();
295  if (RegMask == OtherRegMask)
296  return true;
297 
298  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
299  // Calculate the size of the RegMask
300  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
301  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
302 
303  // Deep compare of the two RegMasks
304  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
305  }
306  // We don't know the size of the RegMask, so we can't deep compare the two
307  // reg masks.
308  return false;
309  }
311  return getMCSymbol() == Other.getMCSymbol();
313  return getCFIIndex() == Other.getCFIIndex();
315  return getMetadata() == Other.getMetadata();
317  return getIntrinsicID() == Other.getIntrinsicID();
319  return getPredicate() == Other.getPredicate();
320  }
321  llvm_unreachable("Invalid machine operand type");
322 }
323 
324 // Note: this must stay exactly in sync with isIdenticalTo above.
326  switch (MO.getType()) {
328  // Register operands don't have target flags.
329  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
331  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
333  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
335  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
337  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
339  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
342  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
343  MO.getOffset());
345  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
347  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
348  MO.getSymbolName());
350  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
351  MO.getOffset());
353  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
354  MO.getOffset());
357  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
359  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
367  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
368  }
369  llvm_unreachable("Invalid machine operand type");
370 }
371 
372 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
373 // it.
374 static void tryToGetTargetInfo(const MachineOperand &MO,
375  const TargetRegisterInfo *&TRI,
376  const TargetIntrinsicInfo *&IntrinsicInfo) {
377  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
378  TRI = MF->getSubtarget().getRegisterInfo();
379  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
380  }
381 }
382 
383 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
384  const auto *TII = MF.getSubtarget().getInstrInfo();
385  assert(TII && "expected instruction info");
386  auto Indices = TII->getSerializableTargetIndices();
387  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
388  return I.first == Index;
389  });
390  if (Found != Indices.end())
391  return Found->second;
392  return nullptr;
393 }
394 
395 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
397  for (const auto &I : Flags) {
398  if (I.first == TF) {
399  return I.second;
400  }
401  }
402  return nullptr;
403 }
404 
405 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
406  const TargetRegisterInfo *TRI) {
407  if (!TRI) {
408  OS << "%dwarfreg." << DwarfReg;
409  return;
410  }
411 
412  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
413  if (Reg == -1) {
414  OS << "<badreg>";
415  return;
416  }
417  OS << printReg(Reg, TRI);
418 }
419 
420 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
421  ModuleSlotTracker &MST) {
422  OS << "%ir-block.";
423  if (BB.hasName()) {
425  return;
426  }
427  Optional<int> Slot;
428  if (const Function *F = BB.getParent()) {
429  if (F == MST.getCurrentFunction()) {
430  Slot = MST.getLocalSlot(&BB);
431  } else if (const Module *M = F->getParent()) {
432  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
433  CustomMST.incorporateFunction(*F);
434  Slot = CustomMST.getLocalSlot(&BB);
435  }
436  }
437  if (Slot)
439  else
440  OS << "<unknown>";
441 }
442 
444  const TargetRegisterInfo *TRI) {
445  OS << "%subreg.";
446  if (TRI)
447  OS << TRI->getSubRegIndexName(Index);
448  else
449  OS << Index;
450 }
451 
453  const MachineOperand &Op) {
454  if (!Op.getTargetFlags())
455  return;
456  const MachineFunction *MF = getMFIfAvailable(Op);
457  if (!MF)
458  return;
459 
460  const auto *TII = MF->getSubtarget().getInstrInfo();
461  assert(TII && "expected instruction info");
463  OS << "target-flags(";
464  const bool HasDirectFlags = Flags.first;
465  const bool HasBitmaskFlags = Flags.second;
466  if (!HasDirectFlags && !HasBitmaskFlags) {
467  OS << "<unknown>) ";
468  return;
469  }
470  if (HasDirectFlags) {
471  if (const auto *Name = getTargetFlagName(TII, Flags.first))
472  OS << Name;
473  else
474  OS << "<unknown target flag>";
475  }
476  if (!HasBitmaskFlags) {
477  OS << ") ";
478  return;
479  }
480  bool IsCommaNeeded = HasDirectFlags;
481  unsigned BitMask = Flags.second;
483  for (const auto &Mask : BitMasks) {
484  // Check if the flag's bitmask has the bits of the current mask set.
485  if ((BitMask & Mask.first) == Mask.first) {
486  if (IsCommaNeeded)
487  OS << ", ";
488  IsCommaNeeded = true;
489  OS << Mask.second;
490  // Clear the bits which were serialized from the flag's bitmask.
491  BitMask &= ~(Mask.first);
492  }
493  }
494  if (BitMask) {
495  // When the resulting flag's bitmask isn't zero, we know that we didn't
496  // serialize all of the bit flags.
497  if (IsCommaNeeded)
498  OS << ", ";
499  OS << "<unknown bitmask target flag>";
500  }
501  OS << ") ";
502 }
503 
505  OS << "<mcsymbol " << Sym << ">";
506 }
507 
509  unsigned FrameIndex,
510  bool IsFixed, StringRef Name) {
511  if (IsFixed) {
512  OS << "%fixed-stack." << FrameIndex;
513  return;
514  }
515 
516  OS << "%stack." << FrameIndex;
517  if (!Name.empty())
518  OS << '.' << Name;
519 }
520 
522  if (Offset == 0)
523  return;
524  if (Offset < 0) {
525  OS << " - " << -Offset;
526  return;
527  }
528  OS << " + " << Offset;
529 }
530 
532  if (Slot == -1)
533  OS << "<badref>";
534  else
535  OS << Slot;
536 }
537 
538 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
539  const TargetRegisterInfo *TRI) {
540  switch (CFI.getOperation()) {
542  OS << "same_value ";
543  if (MCSymbol *Label = CFI.getLabel())
544  MachineOperand::printSymbol(OS, *Label);
545  printCFIRegister(CFI.getRegister(), OS, TRI);
546  break;
548  OS << "remember_state ";
549  if (MCSymbol *Label = CFI.getLabel())
550  MachineOperand::printSymbol(OS, *Label);
551  break;
553  OS << "restore_state ";
554  if (MCSymbol *Label = CFI.getLabel())
555  MachineOperand::printSymbol(OS, *Label);
556  break;
558  OS << "offset ";
559  if (MCSymbol *Label = CFI.getLabel())
560  MachineOperand::printSymbol(OS, *Label);
561  printCFIRegister(CFI.getRegister(), OS, TRI);
562  OS << ", " << CFI.getOffset();
563  break;
565  OS << "def_cfa_register ";
566  if (MCSymbol *Label = CFI.getLabel())
567  MachineOperand::printSymbol(OS, *Label);
568  printCFIRegister(CFI.getRegister(), OS, TRI);
569  break;
571  OS << "def_cfa_offset ";
572  if (MCSymbol *Label = CFI.getLabel())
573  MachineOperand::printSymbol(OS, *Label);
574  OS << CFI.getOffset();
575  break;
577  OS << "def_cfa ";
578  if (MCSymbol *Label = CFI.getLabel())
579  MachineOperand::printSymbol(OS, *Label);
580  printCFIRegister(CFI.getRegister(), OS, TRI);
581  OS << ", " << CFI.getOffset();
582  break;
584  OS << "rel_offset ";
585  if (MCSymbol *Label = CFI.getLabel())
586  MachineOperand::printSymbol(OS, *Label);
587  printCFIRegister(CFI.getRegister(), OS, TRI);
588  OS << ", " << CFI.getOffset();
589  break;
591  OS << "adjust_cfa_offset ";
592  if (MCSymbol *Label = CFI.getLabel())
593  MachineOperand::printSymbol(OS, *Label);
594  OS << CFI.getOffset();
595  break;
597  OS << "restore ";
598  if (MCSymbol *Label = CFI.getLabel())
599  MachineOperand::printSymbol(OS, *Label);
600  printCFIRegister(CFI.getRegister(), OS, TRI);
601  break;
603  OS << "escape ";
604  if (MCSymbol *Label = CFI.getLabel())
605  MachineOperand::printSymbol(OS, *Label);
606  if (!CFI.getValues().empty()) {
607  size_t e = CFI.getValues().size() - 1;
608  for (size_t i = 0; i < e; ++i)
609  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
610  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
611  }
612  break;
613  }
615  OS << "undefined ";
616  if (MCSymbol *Label = CFI.getLabel())
617  MachineOperand::printSymbol(OS, *Label);
618  printCFIRegister(CFI.getRegister(), OS, TRI);
619  break;
621  OS << "register ";
622  if (MCSymbol *Label = CFI.getLabel())
623  MachineOperand::printSymbol(OS, *Label);
624  printCFIRegister(CFI.getRegister(), OS, TRI);
625  OS << ", ";
626  printCFIRegister(CFI.getRegister2(), OS, TRI);
627  break;
629  OS << "window_save ";
630  if (MCSymbol *Label = CFI.getLabel())
631  MachineOperand::printSymbol(OS, *Label);
632  break;
633  default:
634  // TODO: Print the other CFI Operations.
635  OS << "<unserializable cfi directive>";
636  break;
637  }
638 }
639 
641  const TargetIntrinsicInfo *IntrinsicInfo) const {
642  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
643  ModuleSlotTracker DummyMST(nullptr);
644  print(OS, DummyMST, LLT{}, /*PrintDef=*/false, /*IsStandalone=*/true,
645  /*ShouldPrintRegisterTies=*/true,
646  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
647 }
648 
650  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
651  bool ShouldPrintRegisterTies,
652  unsigned TiedOperandIdx,
653  const TargetRegisterInfo *TRI,
654  const TargetIntrinsicInfo *IntrinsicInfo) const {
655  printTargetFlags(OS, *this);
656  switch (getType()) {
658  unsigned Reg = getReg();
659  if (isImplicit())
660  OS << (isDef() ? "implicit-def " : "implicit ");
661  else if (PrintDef && isDef())
662  // Print the 'def' flag only when the operand is defined after '='.
663  OS << "def ";
664  if (isInternalRead())
665  OS << "internal ";
666  if (isDead())
667  OS << "dead ";
668  if (isKill())
669  OS << "killed ";
670  if (isUndef())
671  OS << "undef ";
672  if (isEarlyClobber())
673  OS << "early-clobber ";
674  if (isDebug())
675  OS << "debug-use ";
677  OS << "renamable ";
678  OS << printReg(Reg, TRI);
679  // Print the sub register.
680  if (unsigned SubReg = getSubReg()) {
681  if (TRI)
682  OS << '.' << TRI->getSubRegIndexName(SubReg);
683  else
684  OS << ".subreg" << SubReg;
685  }
686  // Print the register class / bank.
688  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
689  const MachineRegisterInfo &MRI = MF->getRegInfo();
690  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
691  OS << ':';
692  OS << printRegClassOrBank(Reg, MRI, TRI);
693  }
694  }
695  }
696  // Print ties.
697  if (ShouldPrintRegisterTies && isTied() && !isDef())
698  OS << "(tied-def " << TiedOperandIdx << ")";
699  // Print types.
700  if (TypeToPrint.isValid())
701  OS << '(' << TypeToPrint << ')';
702  break;
703  }
705  OS << getImm();
706  break;
708  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
709  break;
711  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
712  break;
714  OS << printMBBReference(*getMBB());
715  break;
717  int FrameIndex = getIndex();
718  bool IsFixed = false;
719  StringRef Name;
720  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
721  const MachineFrameInfo &MFI = MF->getFrameInfo();
722  IsFixed = MFI.isFixedObjectIndex(FrameIndex);
723  if (const AllocaInst *Alloca = MFI.getObjectAllocation(FrameIndex))
724  if (Alloca->hasName())
725  Name = Alloca->getName();
726  if (IsFixed)
727  FrameIndex -= MFI.getObjectIndexBegin();
728  }
729  printStackObjectReference(OS, FrameIndex, IsFixed, Name);
730  break;
731  }
733  OS << "%const." << getIndex();
735  break;
737  OS << "target-index(";
738  const char *Name = "<unknown>";
739  if (const MachineFunction *MF = getMFIfAvailable(*this))
740  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
741  Name = TargetIndexName;
742  OS << Name << ')';
744  break;
745  }
748  break;
750  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
752  break;
755  OS << '&';
756  if (Name.empty()) {
757  OS << "\"\"";
758  } else {
759  printLLVMNameWithoutPrefix(OS, Name);
760  }
762  break;
763  }
765  OS << "blockaddress(";
766  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
767  MST);
768  OS << ", ";
769  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
770  OS << ')';
772  break;
773  }
775  OS << "<regmask";
776  if (TRI) {
777  unsigned NumRegsInMask = 0;
778  unsigned NumRegsEmitted = 0;
779  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
780  unsigned MaskWord = i / 32;
781  unsigned MaskBit = i % 32;
782  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
783  if (PrintRegMaskNumRegs < 0 ||
784  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
785  OS << " " << printReg(i, TRI);
786  NumRegsEmitted++;
787  }
788  NumRegsInMask++;
789  }
790  }
791  if (NumRegsEmitted != NumRegsInMask)
792  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
793  } else {
794  OS << " ...";
795  }
796  OS << ">";
797  break;
798  }
800  const uint32_t *RegMask = getRegLiveOut();
801  OS << "liveout(";
802  if (!TRI) {
803  OS << "<unknown>";
804  } else {
805  bool IsCommaNeeded = false;
806  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
807  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
808  if (IsCommaNeeded)
809  OS << ", ";
810  OS << printReg(Reg, TRI);
811  IsCommaNeeded = true;
812  }
813  }
814  }
815  OS << ")";
816  break;
817  }
819  getMetadata()->printAsOperand(OS, MST);
820  break;
822  printSymbol(OS, *getMCSymbol());
823  break;
825  if (const MachineFunction *MF = getMFIfAvailable(*this))
826  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
827  else
828  OS << "<cfi directive>";
829  break;
830  }
833  if (ID < Intrinsic::num_intrinsics)
834  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
835  else if (IntrinsicInfo)
836  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
837  else
838  OS << "intrinsic(" << ID << ')';
839  break;
840  }
842  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
843  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
844  << CmpInst::getPredicateName(Pred) << ')';
845  break;
846  }
847  }
848 }
849 
850 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
851 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
852 #endif
853 
854 //===----------------------------------------------------------------------===//
855 // MachineMemOperand Implementation
856 //===----------------------------------------------------------------------===//
857 
858 /// getAddrSpace - Return the LLVM IR address space number that this pointer
859 /// points into.
860 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
861 
862 /// isDereferenceable - Return true if V is always dereferenceable for
863 /// Offset + Size byte.
865  const DataLayout &DL) const {
866  if (!V.is<const Value *>())
867  return false;
868 
869  const Value *BasePtr = V.get<const Value *>();
870  if (BasePtr == nullptr)
871  return false;
872 
874  BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
875 }
876 
877 /// getConstantPool - Return a MachinePointerInfo record that refers to the
878 /// constant pool.
881 }
882 
883 /// getFixedStack - Return a MachinePointerInfo record that refers to the
884 /// the specified FrameIndex.
886  int FI, int64_t Offset) {
888 }
889 
892 }
893 
895  return MachinePointerInfo(MF.getPSVManager().getGOT());
896 }
897 
899  int64_t Offset, uint8_t ID) {
901 }
902 
905 }
906 
908  uint64_t s, unsigned int a,
909  const AAMDNodes &AAInfo,
910  const MDNode *Ranges, SyncScope::ID SSID,
911  AtomicOrdering Ordering,
912  AtomicOrdering FailureOrdering)
913  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
914  AAInfo(AAInfo), Ranges(Ranges) {
915  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
916  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
917  "invalid pointer value");
918  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
919  assert((isLoad() || isStore()) && "Not a load/store!");
920 
921  AtomicInfo.SSID = static_cast<unsigned>(SSID);
922  assert(getSyncScopeID() == SSID && "Value truncated");
923  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
924  assert(getOrdering() == Ordering && "Value truncated");
925  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
926  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
927 }
928 
929 /// Profile - Gather unique data for the object.
930 ///
932  ID.AddInteger(getOffset());
933  ID.AddInteger(Size);
935  ID.AddInteger(getFlags());
937 }
938 
940  // The Value and Offset may differ due to CSE. But the flags and size
941  // should be the same.
942  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
943  assert(MMO->getSize() == getSize() && "Size mismatch!");
944 
945  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
946  // Update the alignment value.
947  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
948  // Also update the base and offset, because the new alignment may
949  // not be applicable with the old ones.
950  PtrInfo = MMO->PtrInfo;
951  }
952 }
953 
954 /// getAlignment - Return the minimum known alignment in bytes of the
955 /// actual memory reference.
957  return MinAlign(getBaseAlignment(), getOffset());
958 }
959 
961  ModuleSlotTracker DummyMST(nullptr);
962  print(OS, DummyMST);
963 }
965  assert((isLoad() || isStore()) && "SV has to be a load, store or both.");
966 
967  if (isVolatile())
968  OS << "Volatile ";
969 
970  if (isLoad())
971  OS << "LD";
972  if (isStore())
973  OS << "ST";
974  OS << getSize();
975 
976  // Print the address information.
977  OS << "[";
978  if (const Value *V = getValue())
979  V->printAsOperand(OS, /*PrintType=*/false, MST);
980  else if (const PseudoSourceValue *PSV = getPseudoValue())
981  PSV->printCustom(OS);
982  else
983  OS << "<unknown>";
984 
985  unsigned AS = getAddrSpace();
986  if (AS != 0)
987  OS << "(addrspace=" << AS << ')';
988 
989  // If the alignment of the memory reference itself differs from the alignment
990  // of the base pointer, print the base alignment explicitly, next to the base
991  // pointer.
992  if (getBaseAlignment() != getAlignment())
993  OS << "(align=" << getBaseAlignment() << ")";
994 
995  if (getOffset() != 0)
996  OS << "+" << getOffset();
997  OS << "]";
998 
999  // Print the alignment of the reference.
1001  OS << "(align=" << getAlignment() << ")";
1002 
1003  // Print TBAA info.
1004  if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
1005  OS << "(tbaa=";
1006  if (TBAAInfo->getNumOperands() > 0)
1007  TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
1008  else
1009  OS << "<unknown>";
1010  OS << ")";
1011  }
1012 
1013  // Print AA scope info.
1014  if (const MDNode *ScopeInfo = getAAInfo().Scope) {
1015  OS << "(alias.scope=";
1016  if (ScopeInfo->getNumOperands() > 0)
1017  for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
1018  ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
1019  if (i != ie - 1)
1020  OS << ",";
1021  }
1022  else
1023  OS << "<unknown>";
1024  OS << ")";
1025  }
1026 
1027  // Print AA noalias scope info.
1028  if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
1029  OS << "(noalias=";
1030  if (NoAliasInfo->getNumOperands() > 0)
1031  for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
1032  NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
1033  if (i != ie - 1)
1034  OS << ",";
1035  }
1036  else
1037  OS << "<unknown>";
1038  OS << ")";
1039  }
1040 
1041  if (const MDNode *Ranges = getRanges()) {
1042  unsigned NumRanges = Ranges->getNumOperands();
1043  if (NumRanges != 0) {
1044  OS << "(ranges=";
1045 
1046  for (unsigned I = 0; I != NumRanges; ++I) {
1047  Ranges->getOperand(I)->printAsOperand(OS, MST);
1048  if (I != NumRanges - 1)
1049  OS << ',';
1050  }
1051 
1052  OS << ')';
1053  }
1054  }
1055 
1056  if (isNonTemporal())
1057  OS << "(nontemporal)";
1058  if (isDereferenceable())
1059  OS << "(dereferenceable)";
1060  if (isInvariant())
1061  OS << "(invariant)";
1062  if (getFlags() & MOTargetFlag1)
1063  OS << "(flag1)";
1064  if (getFlags() & MOTargetFlag2)
1065  OS << "(flag2)";
1066  if (getFlags() & MOTargetFlag3)
1067  OS << "(flag3)";
1068 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:52
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
MachineBasicBlock * getMBB() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
const uint32_t * RegMask
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:775
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
uint64_t getSize() const
Return the size in bytes of the memory reference.
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:354
Metadata node.
Definition: Metadata.h:862
The two locations do not alias at all.
Definition: AliasAnalysis.h:85
F(f)
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1067
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
struct llvm::MachineOperand::@146::@148 Reg
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void print(raw_ostream &OS) const
Support for operator<<.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:114
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:844
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
A description of a memory reference used in the backend.
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:591
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
const MDNode * getRanges() const
Return the range tag for the memory reference.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:61
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const char * getSymbolName() const
void setIsRenamableIfNoExtraRegAllocReq()
Set IsRenamable to true if there are no extra register allocation requirements placed on this operand...
unsigned getCFIIndex() const
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
Immediate >64bit operand.
PseudoSourceValueManager & getPSVManager() const
union llvm::MachineOperand::@146::@149::@150 Val
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4428
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:493
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:306
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:602
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:251
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
unsigned getRegister2() const
Definition: MCDwarf.h:503
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getOffset() const
Definition: MCDwarf.h:508
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:492
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:885
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:842
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:515
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:761
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:3580
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:495
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:394
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
bool isIntPredicate() const
Definition: InstrTypes.h:977
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:602
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
An opaque object representing a hash code.
Definition: Hashing.h:72
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
void setSubReg(unsigned subReg)
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:135
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:3624
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:123
Address of indexed Constant in Constant Pool.
bool isDereferenceableAndAlignedPointer(const Value *V, unsigned Align, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:129
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1073
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MDNode * getMetadata() const
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:60
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.