LLVM  8.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<int>
34  PrintRegMaskNumRegs("print-regmask-num-regs",
35  cl::desc("Number of registers to limit to when "
36  "printing regmask operands in IR dumps. "
37  "unlimited = -1"),
38  cl::init(32), cl::Hidden);
39 
41  if (const MachineInstr *MI = MO.getParent())
42  if (const MachineBasicBlock *MBB = MI->getParent())
43  if (const MachineFunction *MF = MBB->getParent())
44  return MF;
45  return nullptr;
46 }
48  return const_cast<MachineFunction *>(
49  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50 }
51 
52 void MachineOperand::setReg(unsigned Reg) {
53  if (getReg() == Reg)
54  return; // No change.
55 
56  // Clear the IsRenamable bit to keep it conservatively correct.
57  IsRenamable = false;
58 
59  // Otherwise, we have to change the register. If this operand is embedded
60  // into a machine function, we need to update the old and new register's
61  // use/def lists.
62  if (MachineFunction *MF = getMFIfAvailable(*this)) {
63  MachineRegisterInfo &MRI = MF->getRegInfo();
65  SmallContents.RegNo = Reg;
66  MRI.addRegOperandToUseList(this);
67  return;
68  }
69 
70  // Otherwise, just change the register, no problem. :)
71  SmallContents.RegNo = Reg;
72 }
73 
74 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75  const TargetRegisterInfo &TRI) {
77  if (SubIdx && getSubReg())
78  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79  setReg(Reg);
80  if (SubIdx)
81  setSubReg(SubIdx);
82 }
83 
86  if (getSubReg()) {
87  Reg = TRI.getSubReg(Reg, getSubReg());
88  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89  // That won't happen in legal code.
90  setSubReg(0);
91  if (isDef())
92  setIsUndef(false);
93  }
94  setReg(Reg);
95 }
96 
97 /// Change a def to a use, or a use to a def.
99  assert(isReg() && "Wrong MachineOperand accessor");
100  assert((!Val || !isDebug()) && "Marking a debug operation as def");
101  if (IsDef == Val)
102  return;
103  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104  // MRI may keep uses and defs in different list positions.
105  if (MachineFunction *MF = getMFIfAvailable(*this)) {
106  MachineRegisterInfo &MRI = MF->getRegInfo();
107  MRI.removeRegOperandFromUseList(this);
108  IsDef = Val;
109  MRI.addRegOperandToUseList(this);
110  return;
111  }
112  IsDef = Val;
113 }
114 
116  assert(isReg() && "Wrong MachineOperand accessor");
118  "isRenamable should only be checked on physical registers");
119  if (!IsRenamable)
120  return false;
121 
122  const MachineInstr *MI = getParent();
123  if (!MI)
124  return true;
125 
126  if (isDef())
128 
129  assert(isUse() && "Reg is not def or use");
131 }
132 
134  assert(isReg() && "Wrong MachineOperand accessor");
136  "setIsRenamable should only be called on physical registers");
137  IsRenamable = Val;
138 }
139 
140 // If this operand is currently a register operand, and if this is in a
141 // function, deregister the operand from the register's use/def list.
142 void MachineOperand::removeRegFromUses() {
143  if (!isReg() || !isOnRegUseList())
144  return;
145 
146  if (MachineFunction *MF = getMFIfAvailable(*this))
147  MF->getRegInfo().removeRegOperandFromUseList(this);
148 }
149 
150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 /// the specified value. If an operand is known to be an immediate already,
152 /// the setImm method should be used.
154  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155 
156  removeRegFromUses();
157 
158  OpKind = MO_Immediate;
159  Contents.ImmVal = ImmVal;
160 }
161 
163  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164 
165  removeRegFromUses();
166 
167  OpKind = MO_FPImmediate;
168  Contents.CFP = FPImm;
169 }
170 
171 void MachineOperand::ChangeToES(const char *SymName,
172  unsigned char TargetFlags) {
173  assert((!isReg() || !isTied()) &&
174  "Cannot change a tied operand into an external symbol");
175 
176  removeRegFromUses();
177 
178  OpKind = MO_ExternalSymbol;
179  Contents.OffsetedInfo.Val.SymbolName = SymName;
180  setOffset(0); // Offset is always 0.
181  setTargetFlags(TargetFlags);
182 }
183 
185  assert((!isReg() || !isTied()) &&
186  "Cannot change a tied operand into an MCSymbol");
187 
188  removeRegFromUses();
189 
190  OpKind = MO_MCSymbol;
191  Contents.Sym = Sym;
192 }
193 
195  assert((!isReg() || !isTied()) &&
196  "Cannot change a tied operand into a FrameIndex");
197 
198  removeRegFromUses();
199 
200  OpKind = MO_FrameIndex;
201  setIndex(Idx);
202 }
203 
204 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
205  unsigned char TargetFlags) {
206  assert((!isReg() || !isTied()) &&
207  "Cannot change a tied operand into a FrameIndex");
208 
209  removeRegFromUses();
210 
211  OpKind = MO_TargetIndex;
212  setIndex(Idx);
213  setOffset(Offset);
214  setTargetFlags(TargetFlags);
215 }
216 
217 /// ChangeToRegister - Replace this operand with a new register operand of
218 /// the specified value. If an operand is known to be an register already,
219 /// the setReg method should be used.
220 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
221  bool isKill, bool isDead, bool isUndef,
222  bool isDebug) {
223  MachineRegisterInfo *RegInfo = nullptr;
224  if (MachineFunction *MF = getMFIfAvailable(*this))
225  RegInfo = &MF->getRegInfo();
226  // If this operand is already a register operand, remove it from the
227  // register's use/def lists.
228  bool WasReg = isReg();
229  if (RegInfo && WasReg)
230  RegInfo->removeRegOperandFromUseList(this);
231 
232  // Change this to a register and set the reg#.
233  assert(!(isDead && !isDef) && "Dead flag on non-def");
234  assert(!(isKill && isDef) && "Kill flag on def");
235  OpKind = MO_Register;
236  SmallContents.RegNo = Reg;
237  SubReg_TargetFlags = 0;
238  IsDef = isDef;
239  IsImp = isImp;
240  IsDeadOrKill = isKill | isDead;
241  IsRenamable = false;
242  IsUndef = isUndef;
243  IsInternalRead = false;
244  IsEarlyClobber = false;
245  IsDebug = isDebug;
246  // Ensure isOnRegUseList() returns false.
247  Contents.Reg.Prev = nullptr;
248  // Preserve the tie when the operand was already a register.
249  if (!WasReg)
250  TiedTo = 0;
251 
252  // If this operand is embedded in a function, add the operand to the
253  // register's use/def list.
254  if (RegInfo)
255  RegInfo->addRegOperandToUseList(this);
256 }
257 
258 /// isIdenticalTo - Return true if this operand is identical to the specified
259 /// operand. Note that this should stay in sync with the hash_value overload
260 /// below.
262  if (getType() != Other.getType() ||
263  getTargetFlags() != Other.getTargetFlags())
264  return false;
265 
266  switch (getType()) {
268  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
269  getSubReg() == Other.getSubReg();
271  return getImm() == Other.getImm();
273  return getCImm() == Other.getCImm();
275  return getFPImm() == Other.getFPImm();
277  return getMBB() == Other.getMBB();
279  return getIndex() == Other.getIndex();
282  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
284  return getIndex() == Other.getIndex();
286  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
288  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
289  getOffset() == Other.getOffset();
291  return getBlockAddress() == Other.getBlockAddress() &&
292  getOffset() == Other.getOffset();
295  // Shallow compare of the two RegMasks
296  const uint32_t *RegMask = getRegMask();
297  const uint32_t *OtherRegMask = Other.getRegMask();
298  if (RegMask == OtherRegMask)
299  return true;
300 
301  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
302  // Calculate the size of the RegMask
303  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
304  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
305 
306  // Deep compare of the two RegMasks
307  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
308  }
309  // We don't know the size of the RegMask, so we can't deep compare the two
310  // reg masks.
311  return false;
312  }
314  return getMCSymbol() == Other.getMCSymbol();
316  return getCFIIndex() == Other.getCFIIndex();
318  return getMetadata() == Other.getMetadata();
320  return getIntrinsicID() == Other.getIntrinsicID();
322  return getPredicate() == Other.getPredicate();
323  }
324  llvm_unreachable("Invalid machine operand type");
325 }
326 
327 // Note: this must stay exactly in sync with isIdenticalTo above.
329  switch (MO.getType()) {
331  // Register operands don't have target flags.
332  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
334  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
336  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
338  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
340  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
342  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
345  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
346  MO.getOffset());
348  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
350  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
351  MO.getSymbolName());
353  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
354  MO.getOffset());
356  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
357  MO.getOffset());
360  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
362  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
364  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
366  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
370  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
371  }
372  llvm_unreachable("Invalid machine operand type");
373 }
374 
375 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
376 // it.
377 static void tryToGetTargetInfo(const MachineOperand &MO,
378  const TargetRegisterInfo *&TRI,
379  const TargetIntrinsicInfo *&IntrinsicInfo) {
380  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
381  TRI = MF->getSubtarget().getRegisterInfo();
382  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
383  }
384 }
385 
386 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
387  const auto *TII = MF.getSubtarget().getInstrInfo();
388  assert(TII && "expected instruction info");
389  auto Indices = TII->getSerializableTargetIndices();
390  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
391  return I.first == Index;
392  });
393  if (Found != Indices.end())
394  return Found->second;
395  return nullptr;
396 }
397 
398 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
400  for (const auto &I : Flags) {
401  if (I.first == TF) {
402  return I.second;
403  }
404  }
405  return nullptr;
406 }
407 
408 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
409  const TargetRegisterInfo *TRI) {
410  if (!TRI) {
411  OS << "%dwarfreg." << DwarfReg;
412  return;
413  }
414 
415  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
416  if (Reg == -1) {
417  OS << "<badreg>";
418  return;
419  }
420  OS << printReg(Reg, TRI);
421 }
422 
423 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
424  ModuleSlotTracker &MST) {
425  OS << "%ir-block.";
426  if (BB.hasName()) {
428  return;
429  }
430  Optional<int> Slot;
431  if (const Function *F = BB.getParent()) {
432  if (F == MST.getCurrentFunction()) {
433  Slot = MST.getLocalSlot(&BB);
434  } else if (const Module *M = F->getParent()) {
435  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
436  CustomMST.incorporateFunction(*F);
437  Slot = CustomMST.getLocalSlot(&BB);
438  }
439  }
440  if (Slot)
442  else
443  OS << "<unknown>";
444 }
445 
446 static void printIRValueReference(raw_ostream &OS, const Value &V,
447  ModuleSlotTracker &MST) {
448  if (isa<GlobalValue>(V)) {
449  V.printAsOperand(OS, /*PrintType=*/false, MST);
450  return;
451  }
452  if (isa<Constant>(V)) {
453  // Machine memory operands can load/store to/from constant value pointers.
454  OS << '`';
455  V.printAsOperand(OS, /*PrintType=*/true, MST);
456  OS << '`';
457  return;
458  }
459  OS << "%ir.";
460  if (V.hasName()) {
462  return;
463  }
464  int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
466 }
467 
469  SyncScope::ID SSID,
471  switch (SSID) {
472  case SyncScope::System:
473  break;
474  default:
475  if (SSNs.empty())
476  Context.getSyncScopeNames(SSNs);
477 
478  OS << "syncscope(\"";
479  printEscapedString(SSNs[SSID], OS);
480  OS << "\") ";
481  break;
482  }
483 }
484 
485 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
486  unsigned TMMOFlag) {
488  for (const auto &I : Flags) {
489  if (I.first == TMMOFlag) {
490  return I.second;
491  }
492  }
493  return nullptr;
494 }
495 
496 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
497  const MachineFrameInfo *MFI) {
498  StringRef Name;
499  if (MFI) {
500  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
501  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
502  if (Alloca->hasName())
503  Name = Alloca->getName();
504  if (IsFixed)
505  FrameIndex -= MFI->getObjectIndexBegin();
506  }
507  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
508 }
509 
511  const TargetRegisterInfo *TRI) {
512  OS << "%subreg.";
513  if (TRI)
514  OS << TRI->getSubRegIndexName(Index);
515  else
516  OS << Index;
517 }
518 
520  const MachineOperand &Op) {
521  if (!Op.getTargetFlags())
522  return;
523  const MachineFunction *MF = getMFIfAvailable(Op);
524  if (!MF)
525  return;
526 
527  const auto *TII = MF->getSubtarget().getInstrInfo();
528  assert(TII && "expected instruction info");
530  OS << "target-flags(";
531  const bool HasDirectFlags = Flags.first;
532  const bool HasBitmaskFlags = Flags.second;
533  if (!HasDirectFlags && !HasBitmaskFlags) {
534  OS << "<unknown>) ";
535  return;
536  }
537  if (HasDirectFlags) {
538  if (const auto *Name = getTargetFlagName(TII, Flags.first))
539  OS << Name;
540  else
541  OS << "<unknown target flag>";
542  }
543  if (!HasBitmaskFlags) {
544  OS << ") ";
545  return;
546  }
547  bool IsCommaNeeded = HasDirectFlags;
548  unsigned BitMask = Flags.second;
550  for (const auto &Mask : BitMasks) {
551  // Check if the flag's bitmask has the bits of the current mask set.
552  if ((BitMask & Mask.first) == Mask.first) {
553  if (IsCommaNeeded)
554  OS << ", ";
555  IsCommaNeeded = true;
556  OS << Mask.second;
557  // Clear the bits which were serialized from the flag's bitmask.
558  BitMask &= ~(Mask.first);
559  }
560  }
561  if (BitMask) {
562  // When the resulting flag's bitmask isn't zero, we know that we didn't
563  // serialize all of the bit flags.
564  if (IsCommaNeeded)
565  OS << ", ";
566  OS << "<unknown bitmask target flag>";
567  }
568  OS << ") ";
569 }
570 
572  OS << "<mcsymbol " << Sym << ">";
573 }
574 
576  unsigned FrameIndex,
577  bool IsFixed, StringRef Name) {
578  if (IsFixed) {
579  OS << "%fixed-stack." << FrameIndex;
580  return;
581  }
582 
583  OS << "%stack." << FrameIndex;
584  if (!Name.empty())
585  OS << '.' << Name;
586 }
587 
589  if (Offset == 0)
590  return;
591  if (Offset < 0) {
592  OS << " - " << -Offset;
593  return;
594  }
595  OS << " + " << Offset;
596 }
597 
599  if (Slot == -1)
600  OS << "<badref>";
601  else
602  OS << Slot;
603 }
604 
605 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
606  const TargetRegisterInfo *TRI) {
607  switch (CFI.getOperation()) {
609  OS << "same_value ";
610  if (MCSymbol *Label = CFI.getLabel())
611  MachineOperand::printSymbol(OS, *Label);
612  printCFIRegister(CFI.getRegister(), OS, TRI);
613  break;
615  OS << "remember_state ";
616  if (MCSymbol *Label = CFI.getLabel())
617  MachineOperand::printSymbol(OS, *Label);
618  break;
620  OS << "restore_state ";
621  if (MCSymbol *Label = CFI.getLabel())
622  MachineOperand::printSymbol(OS, *Label);
623  break;
625  OS << "offset ";
626  if (MCSymbol *Label = CFI.getLabel())
627  MachineOperand::printSymbol(OS, *Label);
628  printCFIRegister(CFI.getRegister(), OS, TRI);
629  OS << ", " << CFI.getOffset();
630  break;
632  OS << "def_cfa_register ";
633  if (MCSymbol *Label = CFI.getLabel())
634  MachineOperand::printSymbol(OS, *Label);
635  printCFIRegister(CFI.getRegister(), OS, TRI);
636  break;
638  OS << "def_cfa_offset ";
639  if (MCSymbol *Label = CFI.getLabel())
640  MachineOperand::printSymbol(OS, *Label);
641  OS << CFI.getOffset();
642  break;
644  OS << "def_cfa ";
645  if (MCSymbol *Label = CFI.getLabel())
646  MachineOperand::printSymbol(OS, *Label);
647  printCFIRegister(CFI.getRegister(), OS, TRI);
648  OS << ", " << CFI.getOffset();
649  break;
651  OS << "rel_offset ";
652  if (MCSymbol *Label = CFI.getLabel())
653  MachineOperand::printSymbol(OS, *Label);
654  printCFIRegister(CFI.getRegister(), OS, TRI);
655  OS << ", " << CFI.getOffset();
656  break;
658  OS << "adjust_cfa_offset ";
659  if (MCSymbol *Label = CFI.getLabel())
660  MachineOperand::printSymbol(OS, *Label);
661  OS << CFI.getOffset();
662  break;
664  OS << "restore ";
665  if (MCSymbol *Label = CFI.getLabel())
666  MachineOperand::printSymbol(OS, *Label);
667  printCFIRegister(CFI.getRegister(), OS, TRI);
668  break;
670  OS << "escape ";
671  if (MCSymbol *Label = CFI.getLabel())
672  MachineOperand::printSymbol(OS, *Label);
673  if (!CFI.getValues().empty()) {
674  size_t e = CFI.getValues().size() - 1;
675  for (size_t i = 0; i < e; ++i)
676  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
677  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
678  }
679  break;
680  }
682  OS << "undefined ";
683  if (MCSymbol *Label = CFI.getLabel())
684  MachineOperand::printSymbol(OS, *Label);
685  printCFIRegister(CFI.getRegister(), OS, TRI);
686  break;
688  OS << "register ";
689  if (MCSymbol *Label = CFI.getLabel())
690  MachineOperand::printSymbol(OS, *Label);
691  printCFIRegister(CFI.getRegister(), OS, TRI);
692  OS << ", ";
693  printCFIRegister(CFI.getRegister2(), OS, TRI);
694  break;
696  OS << "window_save ";
697  if (MCSymbol *Label = CFI.getLabel())
698  MachineOperand::printSymbol(OS, *Label);
699  break;
700  default:
701  // TODO: Print the other CFI Operations.
702  OS << "<unserializable cfi directive>";
703  break;
704  }
705 }
706 
708  const TargetIntrinsicInfo *IntrinsicInfo) const {
709  print(OS, LLT{}, TRI, IntrinsicInfo);
710 }
711 
712 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
713  const TargetRegisterInfo *TRI,
714  const TargetIntrinsicInfo *IntrinsicInfo) const {
715  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
716  ModuleSlotTracker DummyMST(nullptr);
717  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
718  /*ShouldPrintRegisterTies=*/true,
719  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
720 }
721 
723  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
724  bool ShouldPrintRegisterTies,
725  unsigned TiedOperandIdx,
726  const TargetRegisterInfo *TRI,
727  const TargetIntrinsicInfo *IntrinsicInfo) const {
728  printTargetFlags(OS, *this);
729  switch (getType()) {
731  unsigned Reg = getReg();
732  if (isImplicit())
733  OS << (isDef() ? "implicit-def " : "implicit ");
734  else if (PrintDef && isDef())
735  // Print the 'def' flag only when the operand is defined after '='.
736  OS << "def ";
737  if (isInternalRead())
738  OS << "internal ";
739  if (isDead())
740  OS << "dead ";
741  if (isKill())
742  OS << "killed ";
743  if (isUndef())
744  OS << "undef ";
745  if (isEarlyClobber())
746  OS << "early-clobber ";
748  OS << "renamable ";
749  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
750  // simply infer it when parsing and do not need to print it.
751 
752  const MachineRegisterInfo *MRI = nullptr;
754  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
755  MRI = &MF->getRegInfo();
756  }
757  }
758 
759  OS << printReg(Reg, TRI, 0, MRI);
760  // Print the sub register.
761  if (unsigned SubReg = getSubReg()) {
762  if (TRI)
763  OS << '.' << TRI->getSubRegIndexName(SubReg);
764  else
765  OS << ".subreg" << SubReg;
766  }
767  // Print the register class / bank.
769  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
770  const MachineRegisterInfo &MRI = MF->getRegInfo();
771  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
772  OS << ':';
773  OS << printRegClassOrBank(Reg, MRI, TRI);
774  }
775  }
776  }
777  // Print ties.
778  if (ShouldPrintRegisterTies && isTied() && !isDef())
779  OS << "(tied-def " << TiedOperandIdx << ")";
780  // Print types.
781  if (TypeToPrint.isValid())
782  OS << '(' << TypeToPrint << ')';
783  break;
784  }
786  OS << getImm();
787  break;
789  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
790  break;
792  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
793  break;
795  OS << printMBBReference(*getMBB());
796  break;
798  int FrameIndex = getIndex();
799  bool IsFixed = false;
800  const MachineFrameInfo *MFI = nullptr;
801  if (const MachineFunction *MF = getMFIfAvailable(*this))
802  MFI = &MF->getFrameInfo();
803  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
804  break;
805  }
807  OS << "%const." << getIndex();
809  break;
811  OS << "target-index(";
812  const char *Name = "<unknown>";
813  if (const MachineFunction *MF = getMFIfAvailable(*this))
814  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
815  Name = TargetIndexName;
816  OS << Name << ')';
818  break;
819  }
822  break;
824  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
826  break;
829  OS << '&';
830  if (Name.empty()) {
831  OS << "\"\"";
832  } else {
833  printLLVMNameWithoutPrefix(OS, Name);
834  }
836  break;
837  }
839  OS << "blockaddress(";
840  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
841  MST);
842  OS << ", ";
843  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
844  OS << ')';
846  break;
847  }
849  OS << "<regmask";
850  if (TRI) {
851  unsigned NumRegsInMask = 0;
852  unsigned NumRegsEmitted = 0;
853  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
854  unsigned MaskWord = i / 32;
855  unsigned MaskBit = i % 32;
856  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
857  if (PrintRegMaskNumRegs < 0 ||
858  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
859  OS << " " << printReg(i, TRI);
860  NumRegsEmitted++;
861  }
862  NumRegsInMask++;
863  }
864  }
865  if (NumRegsEmitted != NumRegsInMask)
866  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
867  } else {
868  OS << " ...";
869  }
870  OS << ">";
871  break;
872  }
874  const uint32_t *RegMask = getRegLiveOut();
875  OS << "liveout(";
876  if (!TRI) {
877  OS << "<unknown>";
878  } else {
879  bool IsCommaNeeded = false;
880  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
881  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
882  if (IsCommaNeeded)
883  OS << ", ";
884  OS << printReg(Reg, TRI);
885  IsCommaNeeded = true;
886  }
887  }
888  }
889  OS << ")";
890  break;
891  }
893  getMetadata()->printAsOperand(OS, MST);
894  break;
896  printSymbol(OS, *getMCSymbol());
897  break;
899  if (const MachineFunction *MF = getMFIfAvailable(*this))
900  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
901  else
902  OS << "<cfi directive>";
903  break;
904  }
907  if (ID < Intrinsic::num_intrinsics)
908  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
909  else if (IntrinsicInfo)
910  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
911  else
912  OS << "intrinsic(" << ID << ')';
913  break;
914  }
916  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
917  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
918  << CmpInst::getPredicateName(Pred) << ')';
919  break;
920  }
921  }
922 }
923 
924 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
925 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
926 #endif
927 
928 //===----------------------------------------------------------------------===//
929 // MachineMemOperand Implementation
930 //===----------------------------------------------------------------------===//
931 
932 /// getAddrSpace - Return the LLVM IR address space number that this pointer
933 /// points into.
934 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
935 
936 /// isDereferenceable - Return true if V is always dereferenceable for
937 /// Offset + Size byte.
939  const DataLayout &DL) const {
940  if (!V.is<const Value *>())
941  return false;
942 
943  const Value *BasePtr = V.get<const Value *>();
944  if (BasePtr == nullptr)
945  return false;
946 
948  BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
949 }
950 
951 /// getConstantPool - Return a MachinePointerInfo record that refers to the
952 /// constant pool.
955 }
956 
957 /// getFixedStack - Return a MachinePointerInfo record that refers to the
958 /// the specified FrameIndex.
960  int FI, int64_t Offset) {
962 }
963 
966 }
967 
969  return MachinePointerInfo(MF.getPSVManager().getGOT());
970 }
971 
973  int64_t Offset, uint8_t ID) {
975 }
976 
979 }
980 
982  uint64_t s, uint64_t a,
983  const AAMDNodes &AAInfo,
984  const MDNode *Ranges, SyncScope::ID SSID,
985  AtomicOrdering Ordering,
986  AtomicOrdering FailureOrdering)
987  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
988  AAInfo(AAInfo), Ranges(Ranges) {
989  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
990  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
991  "invalid pointer value");
992  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
993  assert((isLoad() || isStore()) && "Not a load/store!");
994 
995  AtomicInfo.SSID = static_cast<unsigned>(SSID);
996  assert(getSyncScopeID() == SSID && "Value truncated");
997  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
998  assert(getOrdering() == Ordering && "Value truncated");
999  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1000  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1001 }
1002 
1003 /// Profile - Gather unique data for the object.
1004 ///
1006  ID.AddInteger(getOffset());
1007  ID.AddInteger(Size);
1008  ID.AddPointer(getOpaqueValue());
1009  ID.AddInteger(getFlags());
1011 }
1012 
1014  // The Value and Offset may differ due to CSE. But the flags and size
1015  // should be the same.
1016  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1017  assert(MMO->getSize() == getSize() && "Size mismatch!");
1018 
1019  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1020  // Update the alignment value.
1021  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1022  // Also update the base and offset, because the new alignment may
1023  // not be applicable with the old ones.
1024  PtrInfo = MMO->PtrInfo;
1025  }
1026 }
1027 
1028 /// getAlignment - Return the minimum known alignment in bytes of the
1029 /// actual memory reference.
1031  return MinAlign(getBaseAlignment(), getOffset());
1032 }
1033 
1035  ModuleSlotTracker DummyMST(nullptr);
1036  print(OS, DummyMST);
1037 }
1038 
1041  LLVMContext Ctx;
1042  print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1043 }
1044 
1047  const LLVMContext &Context,
1048  const MachineFrameInfo *MFI,
1049  const TargetInstrInfo *TII) const {
1050  OS << '(';
1051  if (isVolatile())
1052  OS << "volatile ";
1053  if (isNonTemporal())
1054  OS << "non-temporal ";
1055  if (isDereferenceable())
1056  OS << "dereferenceable ";
1057  if (isInvariant())
1058  OS << "invariant ";
1061  << "\" ";
1064  << "\" ";
1067  << "\" ";
1068 
1069  assert((isLoad() || isStore()) &&
1070  "machine memory operand must be a load or store (or both)");
1071  if (isLoad())
1072  OS << "load ";
1073  if (isStore())
1074  OS << "store ";
1075 
1076  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1077 
1079  OS << toIRString(getOrdering()) << ' ';
1081  OS << toIRString(getFailureOrdering()) << ' ';
1082 
1084  OS << "unknown-size";
1085  else
1086  OS << getSize();
1087 
1088  if (const Value *Val = getValue()) {
1089  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1090  printIRValueReference(OS, *Val, MST);
1091  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1092  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1093  assert(PVal && "Expected a pseudo source value");
1094  switch (PVal->kind()) {
1096  OS << "stack";
1097  break;
1099  OS << "got";
1100  break;
1102  OS << "jump-table";
1103  break;
1105  OS << "constant-pool";
1106  break;
1108  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1109  bool IsFixed = true;
1110  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1111  break;
1112  }
1114  OS << "call-entry ";
1115  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1116  OS, /*PrintType=*/false, MST);
1117  break;
1119  OS << "call-entry &";
1121  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1122  break;
1124  // FIXME: This is not necessarily the correct MIR serialization format for
1125  // a custom pseudo source value, but at least it allows
1126  // -print-machineinstrs to work on a target with custom pseudo source
1127  // values.
1128  OS << "custom ";
1129  PVal->printCustom(OS);
1130  break;
1131  }
1132  }
1134  if (getBaseAlignment() != getSize())
1135  OS << ", align " << getBaseAlignment();
1136  auto AAInfo = getAAInfo();
1137  if (AAInfo.TBAA) {
1138  OS << ", !tbaa ";
1139  AAInfo.TBAA->printAsOperand(OS, MST);
1140  }
1141  if (AAInfo.Scope) {
1142  OS << ", !alias.scope ";
1143  AAInfo.Scope->printAsOperand(OS, MST);
1144  }
1145  if (AAInfo.NoAlias) {
1146  OS << ", !noalias ";
1147  AAInfo.NoAlias->printAsOperand(OS, MST);
1148  }
1149  if (getRanges()) {
1150  OS << ", !range ";
1151  getRanges()->printAsOperand(OS, MST);
1152  }
1153  // FIXME: Implement addrspace printing/parsing in MIR.
1154  // For now, print this even though parsing it is not available in MIR.
1155  if (unsigned AS = getAddrSpace())
1156  OS << ", addrspace " << AS;
1157 
1158  OS << ')';
1159 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:52
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
LLVMContext & Context
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
MachineBasicBlock * getMBB() const
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:661
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:658
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:927
const uint32_t * RegMask
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned Reg
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:856
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
union llvm::MachineOperand::@159::@162::@163 Val
uint64_t getSize() const
Return the size in bytes of the memory reference.
void printEscapedString(StringRef Name, raw_ostream &Out)
Print each character of the specified string, escaping it if it is not printable or if it is an escap...
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, uint64_t a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:864
F(f)
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void print(raw_ostream &OS) const
Support for operator<<.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:114
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:862
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:627
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:61
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:59
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
const char * getSymbolName() const
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
unsigned getCFIIndex() const
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
Immediate >64bit operand.
struct llvm::MachineOperand::@159::@161 Reg
PseudoSourceValueManager & getPSVManager() const
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4431
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:553
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:337
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:306
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:610
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:419
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:251
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
unsigned getRegister2() const
Definition: MCDwarf.h:563
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getOffset() const
Definition: MCDwarf.h:568
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:552
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:641
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1076
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:575
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:842
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4199
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:555
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:644
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:399
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:664
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
bool isIntPredicate() const
Definition: InstrTypes.h:734
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:70
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:601
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:72
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
This file provides utility analysis objects describing memory locations.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:917
Flags getFlags() const
Return the raw flags of the source value,.
void setSubReg(unsigned subReg)
uint32_t Size
Definition: Profile.cpp:47
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:135
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4241
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:123
Address of indexed Constant in Constant Pool.
bool isDereferenceableAndAlignedPointer(const Value *V, unsigned Align, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:129
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MDNode * getMetadata() const
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:60
static void printIRValueReference(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.