LLVM  7.0.0svn
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
29 
30 using namespace llvm;
31 
32 static cl::opt<int>
33  PrintRegMaskNumRegs("print-regmask-num-regs",
34  cl::desc("Number of registers to limit to when "
35  "printing regmask operands in IR dumps. "
36  "unlimited = -1"),
37  cl::init(32), cl::Hidden);
38 
40  if (const MachineInstr *MI = MO.getParent())
41  if (const MachineBasicBlock *MBB = MI->getParent())
42  if (const MachineFunction *MF = MBB->getParent())
43  return MF;
44  return nullptr;
45 }
47  return const_cast<MachineFunction *>(
48  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
49 }
50 
51 void MachineOperand::setReg(unsigned Reg) {
52  if (getReg() == Reg)
53  return; // No change.
54 
55  // Clear the IsRenamable bit to keep it conservatively correct.
56  IsRenamable = false;
57 
58  // Otherwise, we have to change the register. If this operand is embedded
59  // into a machine function, we need to update the old and new register's
60  // use/def lists.
61  if (MachineFunction *MF = getMFIfAvailable(*this)) {
62  MachineRegisterInfo &MRI = MF->getRegInfo();
64  SmallContents.RegNo = Reg;
65  MRI.addRegOperandToUseList(this);
66  return;
67  }
68 
69  // Otherwise, just change the register, no problem. :)
70  SmallContents.RegNo = Reg;
71 }
72 
73 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
74  const TargetRegisterInfo &TRI) {
76  if (SubIdx && getSubReg())
77  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
78  setReg(Reg);
79  if (SubIdx)
80  setSubReg(SubIdx);
81 }
82 
85  if (getSubReg()) {
86  Reg = TRI.getSubReg(Reg, getSubReg());
87  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
88  // That won't happen in legal code.
89  setSubReg(0);
90  if (isDef())
91  setIsUndef(false);
92  }
93  setReg(Reg);
94 }
95 
96 /// Change a def to a use, or a use to a def.
98  assert(isReg() && "Wrong MachineOperand accessor");
99  assert((!Val || !isDebug()) && "Marking a debug operation as def");
100  if (IsDef == Val)
101  return;
102  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
103  // MRI may keep uses and defs in different list positions.
104  if (MachineFunction *MF = getMFIfAvailable(*this)) {
105  MachineRegisterInfo &MRI = MF->getRegInfo();
106  MRI.removeRegOperandFromUseList(this);
107  IsDef = Val;
108  MRI.addRegOperandToUseList(this);
109  return;
110  }
111  IsDef = Val;
112 }
113 
115  assert(isReg() && "Wrong MachineOperand accessor");
117  "isRenamable should only be checked on physical registers");
118  if (!IsRenamable)
119  return false;
120 
121  const MachineInstr *MI = getParent();
122  if (!MI)
123  return true;
124 
125  if (isDef())
127 
128  assert(isUse() && "Reg is not def or use");
130 }
131 
133  assert(isReg() && "Wrong MachineOperand accessor");
135  "setIsRenamable should only be called on physical registers");
136  IsRenamable = Val;
137 }
138 
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
141 void MachineOperand::removeRegFromUses() {
142  if (!isReg() || !isOnRegUseList())
143  return;
144 
145  if (MachineFunction *MF = getMFIfAvailable(*this))
146  MF->getRegInfo().removeRegOperandFromUseList(this);
147 }
148 
149 /// ChangeToImmediate - Replace this operand with a new immediate operand of
150 /// the specified value. If an operand is known to be an immediate already,
151 /// the setImm method should be used.
153  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
154 
155  removeRegFromUses();
156 
157  OpKind = MO_Immediate;
158  Contents.ImmVal = ImmVal;
159 }
160 
162  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163 
164  removeRegFromUses();
165 
166  OpKind = MO_FPImmediate;
167  Contents.CFP = FPImm;
168 }
169 
170 void MachineOperand::ChangeToES(const char *SymName,
171  unsigned char TargetFlags) {
172  assert((!isReg() || !isTied()) &&
173  "Cannot change a tied operand into an external symbol");
174 
175  removeRegFromUses();
176 
177  OpKind = MO_ExternalSymbol;
178  Contents.OffsetedInfo.Val.SymbolName = SymName;
179  setOffset(0); // Offset is always 0.
180  setTargetFlags(TargetFlags);
181 }
182 
184  assert((!isReg() || !isTied()) &&
185  "Cannot change a tied operand into an MCSymbol");
186 
187  removeRegFromUses();
188 
189  OpKind = MO_MCSymbol;
190  Contents.Sym = Sym;
191 }
192 
194  assert((!isReg() || !isTied()) &&
195  "Cannot change a tied operand into a FrameIndex");
196 
197  removeRegFromUses();
198 
199  OpKind = MO_FrameIndex;
200  setIndex(Idx);
201 }
202 
203 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
204  unsigned char TargetFlags) {
205  assert((!isReg() || !isTied()) &&
206  "Cannot change a tied operand into a FrameIndex");
207 
208  removeRegFromUses();
209 
210  OpKind = MO_TargetIndex;
211  setIndex(Idx);
212  setOffset(Offset);
213  setTargetFlags(TargetFlags);
214 }
215 
216 /// ChangeToRegister - Replace this operand with a new register operand of
217 /// the specified value. If an operand is known to be an register already,
218 /// the setReg method should be used.
219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
220  bool isKill, bool isDead, bool isUndef,
221  bool isDebug) {
222  MachineRegisterInfo *RegInfo = nullptr;
223  if (MachineFunction *MF = getMFIfAvailable(*this))
224  RegInfo = &MF->getRegInfo();
225  // If this operand is already a register operand, remove it from the
226  // register's use/def lists.
227  bool WasReg = isReg();
228  if (RegInfo && WasReg)
229  RegInfo->removeRegOperandFromUseList(this);
230 
231  // Change this to a register and set the reg#.
232  assert(!(isDead && !isDef) && "Dead flag on non-def");
233  assert(!(isKill && isDef) && "Kill flag on def");
234  OpKind = MO_Register;
235  SmallContents.RegNo = Reg;
236  SubReg_TargetFlags = 0;
237  IsDef = isDef;
238  IsImp = isImp;
239  IsDeadOrKill = isKill | isDead;
240  IsRenamable = false;
241  IsUndef = isUndef;
242  IsInternalRead = false;
243  IsEarlyClobber = false;
244  IsDebug = isDebug;
245  // Ensure isOnRegUseList() returns false.
246  Contents.Reg.Prev = nullptr;
247  // Preserve the tie when the operand was already a register.
248  if (!WasReg)
249  TiedTo = 0;
250 
251  // If this operand is embedded in a function, add the operand to the
252  // register's use/def list.
253  if (RegInfo)
254  RegInfo->addRegOperandToUseList(this);
255 }
256 
257 /// isIdenticalTo - Return true if this operand is identical to the specified
258 /// operand. Note that this should stay in sync with the hash_value overload
259 /// below.
261  if (getType() != Other.getType() ||
262  getTargetFlags() != Other.getTargetFlags())
263  return false;
264 
265  switch (getType()) {
267  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
268  getSubReg() == Other.getSubReg();
270  return getImm() == Other.getImm();
272  return getCImm() == Other.getCImm();
274  return getFPImm() == Other.getFPImm();
276  return getMBB() == Other.getMBB();
278  return getIndex() == Other.getIndex();
281  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
283  return getIndex() == Other.getIndex();
285  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
287  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
288  getOffset() == Other.getOffset();
290  return getBlockAddress() == Other.getBlockAddress() &&
291  getOffset() == Other.getOffset();
294  // Shallow compare of the two RegMasks
295  const uint32_t *RegMask = getRegMask();
296  const uint32_t *OtherRegMask = Other.getRegMask();
297  if (RegMask == OtherRegMask)
298  return true;
299 
300  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
301  // Calculate the size of the RegMask
302  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
303  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
304 
305  // Deep compare of the two RegMasks
306  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
307  }
308  // We don't know the size of the RegMask, so we can't deep compare the two
309  // reg masks.
310  return false;
311  }
313  return getMCSymbol() == Other.getMCSymbol();
315  return getCFIIndex() == Other.getCFIIndex();
317  return getMetadata() == Other.getMetadata();
319  return getIntrinsicID() == Other.getIntrinsicID();
321  return getPredicate() == Other.getPredicate();
322  }
323  llvm_unreachable("Invalid machine operand type");
324 }
325 
326 // Note: this must stay exactly in sync with isIdenticalTo above.
328  switch (MO.getType()) {
330  // Register operands don't have target flags.
331  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
333  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
335  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
337  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
339  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
341  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
344  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
345  MO.getOffset());
347  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
349  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
350  MO.getSymbolName());
352  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
353  MO.getOffset());
355  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
356  MO.getOffset());
359  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
367  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
369  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
370  }
371  llvm_unreachable("Invalid machine operand type");
372 }
373 
374 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
375 // it.
376 static void tryToGetTargetInfo(const MachineOperand &MO,
377  const TargetRegisterInfo *&TRI,
378  const TargetIntrinsicInfo *&IntrinsicInfo) {
379  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
380  TRI = MF->getSubtarget().getRegisterInfo();
381  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
382  }
383 }
384 
385 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
386  const auto *TII = MF.getSubtarget().getInstrInfo();
387  assert(TII && "expected instruction info");
388  auto Indices = TII->getSerializableTargetIndices();
389  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
390  return I.first == Index;
391  });
392  if (Found != Indices.end())
393  return Found->second;
394  return nullptr;
395 }
396 
397 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
399  for (const auto &I : Flags) {
400  if (I.first == TF) {
401  return I.second;
402  }
403  }
404  return nullptr;
405 }
406 
407 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
408  const TargetRegisterInfo *TRI) {
409  if (!TRI) {
410  OS << "%dwarfreg." << DwarfReg;
411  return;
412  }
413 
414  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
415  if (Reg == -1) {
416  OS << "<badreg>";
417  return;
418  }
419  OS << printReg(Reg, TRI);
420 }
421 
422 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
423  ModuleSlotTracker &MST) {
424  OS << "%ir-block.";
425  if (BB.hasName()) {
427  return;
428  }
429  Optional<int> Slot;
430  if (const Function *F = BB.getParent()) {
431  if (F == MST.getCurrentFunction()) {
432  Slot = MST.getLocalSlot(&BB);
433  } else if (const Module *M = F->getParent()) {
434  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
435  CustomMST.incorporateFunction(*F);
436  Slot = CustomMST.getLocalSlot(&BB);
437  }
438  }
439  if (Slot)
441  else
442  OS << "<unknown>";
443 }
444 
445 static void printIRValueReference(raw_ostream &OS, const Value &V,
446  ModuleSlotTracker &MST) {
447  if (isa<GlobalValue>(V)) {
448  V.printAsOperand(OS, /*PrintType=*/false, MST);
449  return;
450  }
451  if (isa<Constant>(V)) {
452  // Machine memory operands can load/store to/from constant value pointers.
453  OS << '`';
454  V.printAsOperand(OS, /*PrintType=*/true, MST);
455  OS << '`';
456  return;
457  }
458  OS << "%ir.";
459  if (V.hasName()) {
461  return;
462  }
464 }
465 
467  SyncScope::ID SSID,
469  switch (SSID) {
470  case SyncScope::System:
471  break;
472  default:
473  if (SSNs.empty())
474  Context.getSyncScopeNames(SSNs);
475 
476  OS << "syncscope(\"";
477  printEscapedString(SSNs[SSID], OS);
478  OS << "\") ";
479  break;
480  }
481 }
482 
483 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
484  unsigned TMMOFlag) {
486  for (const auto &I : Flags) {
487  if (I.first == TMMOFlag) {
488  return I.second;
489  }
490  }
491  return nullptr;
492 }
493 
494 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
495  const MachineFrameInfo *MFI) {
496  StringRef Name;
497  if (MFI) {
498  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
499  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
500  if (Alloca->hasName())
501  Name = Alloca->getName();
502  if (IsFixed)
503  FrameIndex -= MFI->getObjectIndexBegin();
504  }
505  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
506 }
507 
509  const TargetRegisterInfo *TRI) {
510  OS << "%subreg.";
511  if (TRI)
512  OS << TRI->getSubRegIndexName(Index);
513  else
514  OS << Index;
515 }
516 
518  const MachineOperand &Op) {
519  if (!Op.getTargetFlags())
520  return;
521  const MachineFunction *MF = getMFIfAvailable(Op);
522  if (!MF)
523  return;
524 
525  const auto *TII = MF->getSubtarget().getInstrInfo();
526  assert(TII && "expected instruction info");
528  OS << "target-flags(";
529  const bool HasDirectFlags = Flags.first;
530  const bool HasBitmaskFlags = Flags.second;
531  if (!HasDirectFlags && !HasBitmaskFlags) {
532  OS << "<unknown>) ";
533  return;
534  }
535  if (HasDirectFlags) {
536  if (const auto *Name = getTargetFlagName(TII, Flags.first))
537  OS << Name;
538  else
539  OS << "<unknown target flag>";
540  }
541  if (!HasBitmaskFlags) {
542  OS << ") ";
543  return;
544  }
545  bool IsCommaNeeded = HasDirectFlags;
546  unsigned BitMask = Flags.second;
548  for (const auto &Mask : BitMasks) {
549  // Check if the flag's bitmask has the bits of the current mask set.
550  if ((BitMask & Mask.first) == Mask.first) {
551  if (IsCommaNeeded)
552  OS << ", ";
553  IsCommaNeeded = true;
554  OS << Mask.second;
555  // Clear the bits which were serialized from the flag's bitmask.
556  BitMask &= ~(Mask.first);
557  }
558  }
559  if (BitMask) {
560  // When the resulting flag's bitmask isn't zero, we know that we didn't
561  // serialize all of the bit flags.
562  if (IsCommaNeeded)
563  OS << ", ";
564  OS << "<unknown bitmask target flag>";
565  }
566  OS << ") ";
567 }
568 
570  OS << "<mcsymbol " << Sym << ">";
571 }
572 
574  unsigned FrameIndex,
575  bool IsFixed, StringRef Name) {
576  if (IsFixed) {
577  OS << "%fixed-stack." << FrameIndex;
578  return;
579  }
580 
581  OS << "%stack." << FrameIndex;
582  if (!Name.empty())
583  OS << '.' << Name;
584 }
585 
587  if (Offset == 0)
588  return;
589  if (Offset < 0) {
590  OS << " - " << -Offset;
591  return;
592  }
593  OS << " + " << Offset;
594 }
595 
597  if (Slot == -1)
598  OS << "<badref>";
599  else
600  OS << Slot;
601 }
602 
603 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
604  const TargetRegisterInfo *TRI) {
605  switch (CFI.getOperation()) {
607  OS << "same_value ";
608  if (MCSymbol *Label = CFI.getLabel())
609  MachineOperand::printSymbol(OS, *Label);
610  printCFIRegister(CFI.getRegister(), OS, TRI);
611  break;
613  OS << "remember_state ";
614  if (MCSymbol *Label = CFI.getLabel())
615  MachineOperand::printSymbol(OS, *Label);
616  break;
618  OS << "restore_state ";
619  if (MCSymbol *Label = CFI.getLabel())
620  MachineOperand::printSymbol(OS, *Label);
621  break;
623  OS << "offset ";
624  if (MCSymbol *Label = CFI.getLabel())
625  MachineOperand::printSymbol(OS, *Label);
626  printCFIRegister(CFI.getRegister(), OS, TRI);
627  OS << ", " << CFI.getOffset();
628  break;
630  OS << "def_cfa_register ";
631  if (MCSymbol *Label = CFI.getLabel())
632  MachineOperand::printSymbol(OS, *Label);
633  printCFIRegister(CFI.getRegister(), OS, TRI);
634  break;
636  OS << "def_cfa_offset ";
637  if (MCSymbol *Label = CFI.getLabel())
638  MachineOperand::printSymbol(OS, *Label);
639  OS << CFI.getOffset();
640  break;
642  OS << "def_cfa ";
643  if (MCSymbol *Label = CFI.getLabel())
644  MachineOperand::printSymbol(OS, *Label);
645  printCFIRegister(CFI.getRegister(), OS, TRI);
646  OS << ", " << CFI.getOffset();
647  break;
649  OS << "rel_offset ";
650  if (MCSymbol *Label = CFI.getLabel())
651  MachineOperand::printSymbol(OS, *Label);
652  printCFIRegister(CFI.getRegister(), OS, TRI);
653  OS << ", " << CFI.getOffset();
654  break;
656  OS << "adjust_cfa_offset ";
657  if (MCSymbol *Label = CFI.getLabel())
658  MachineOperand::printSymbol(OS, *Label);
659  OS << CFI.getOffset();
660  break;
662  OS << "restore ";
663  if (MCSymbol *Label = CFI.getLabel())
664  MachineOperand::printSymbol(OS, *Label);
665  printCFIRegister(CFI.getRegister(), OS, TRI);
666  break;
668  OS << "escape ";
669  if (MCSymbol *Label = CFI.getLabel())
670  MachineOperand::printSymbol(OS, *Label);
671  if (!CFI.getValues().empty()) {
672  size_t e = CFI.getValues().size() - 1;
673  for (size_t i = 0; i < e; ++i)
674  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
675  OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
676  }
677  break;
678  }
680  OS << "undefined ";
681  if (MCSymbol *Label = CFI.getLabel())
682  MachineOperand::printSymbol(OS, *Label);
683  printCFIRegister(CFI.getRegister(), OS, TRI);
684  break;
686  OS << "register ";
687  if (MCSymbol *Label = CFI.getLabel())
688  MachineOperand::printSymbol(OS, *Label);
689  printCFIRegister(CFI.getRegister(), OS, TRI);
690  OS << ", ";
691  printCFIRegister(CFI.getRegister2(), OS, TRI);
692  break;
694  OS << "window_save ";
695  if (MCSymbol *Label = CFI.getLabel())
696  MachineOperand::printSymbol(OS, *Label);
697  break;
698  default:
699  // TODO: Print the other CFI Operations.
700  OS << "<unserializable cfi directive>";
701  break;
702  }
703 }
704 
706  const TargetIntrinsicInfo *IntrinsicInfo) const {
707  print(OS, LLT{}, TRI, IntrinsicInfo);
708 }
709 
710 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
711  const TargetRegisterInfo *TRI,
712  const TargetIntrinsicInfo *IntrinsicInfo) const {
713  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
714  ModuleSlotTracker DummyMST(nullptr);
715  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
716  /*ShouldPrintRegisterTies=*/true,
717  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
718 }
719 
721  LLT TypeToPrint, bool PrintDef, bool IsStandalone,
722  bool ShouldPrintRegisterTies,
723  unsigned TiedOperandIdx,
724  const TargetRegisterInfo *TRI,
725  const TargetIntrinsicInfo *IntrinsicInfo) const {
726  printTargetFlags(OS, *this);
727  switch (getType()) {
729  unsigned Reg = getReg();
730  if (isImplicit())
731  OS << (isDef() ? "implicit-def " : "implicit ");
732  else if (PrintDef && isDef())
733  // Print the 'def' flag only when the operand is defined after '='.
734  OS << "def ";
735  if (isInternalRead())
736  OS << "internal ";
737  if (isDead())
738  OS << "dead ";
739  if (isKill())
740  OS << "killed ";
741  if (isUndef())
742  OS << "undef ";
743  if (isEarlyClobber())
744  OS << "early-clobber ";
745  if (isDebug())
746  OS << "debug-use ";
748  OS << "renamable ";
749 
750  const MachineRegisterInfo *MRI = nullptr;
752  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
753  MRI = &MF->getRegInfo();
754  }
755  }
756 
757  OS << printReg(Reg, TRI, 0, MRI);
758  // Print the sub register.
759  if (unsigned SubReg = getSubReg()) {
760  if (TRI)
761  OS << '.' << TRI->getSubRegIndexName(SubReg);
762  else
763  OS << ".subreg" << SubReg;
764  }
765  // Print the register class / bank.
767  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
768  const MachineRegisterInfo &MRI = MF->getRegInfo();
769  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
770  OS << ':';
771  OS << printRegClassOrBank(Reg, MRI, TRI);
772  }
773  }
774  }
775  // Print ties.
776  if (ShouldPrintRegisterTies && isTied() && !isDef())
777  OS << "(tied-def " << TiedOperandIdx << ")";
778  // Print types.
779  if (TypeToPrint.isValid())
780  OS << '(' << TypeToPrint << ')';
781  break;
782  }
784  OS << getImm();
785  break;
787  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
788  break;
790  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
791  break;
793  OS << printMBBReference(*getMBB());
794  break;
796  int FrameIndex = getIndex();
797  bool IsFixed = false;
798  const MachineFrameInfo *MFI = nullptr;
799  if (const MachineFunction *MF = getMFIfAvailable(*this))
800  MFI = &MF->getFrameInfo();
801  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
802  break;
803  }
805  OS << "%const." << getIndex();
807  break;
809  OS << "target-index(";
810  const char *Name = "<unknown>";
811  if (const MachineFunction *MF = getMFIfAvailable(*this))
812  if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
813  Name = TargetIndexName;
814  OS << Name << ')';
816  break;
817  }
820  break;
822  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
824  break;
827  OS << '&';
828  if (Name.empty()) {
829  OS << "\"\"";
830  } else {
831  printLLVMNameWithoutPrefix(OS, Name);
832  }
834  break;
835  }
837  OS << "blockaddress(";
838  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
839  MST);
840  OS << ", ";
841  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
842  OS << ')';
844  break;
845  }
847  OS << "<regmask";
848  if (TRI) {
849  unsigned NumRegsInMask = 0;
850  unsigned NumRegsEmitted = 0;
851  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
852  unsigned MaskWord = i / 32;
853  unsigned MaskBit = i % 32;
854  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
855  if (PrintRegMaskNumRegs < 0 ||
856  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
857  OS << " " << printReg(i, TRI);
858  NumRegsEmitted++;
859  }
860  NumRegsInMask++;
861  }
862  }
863  if (NumRegsEmitted != NumRegsInMask)
864  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
865  } else {
866  OS << " ...";
867  }
868  OS << ">";
869  break;
870  }
872  const uint32_t *RegMask = getRegLiveOut();
873  OS << "liveout(";
874  if (!TRI) {
875  OS << "<unknown>";
876  } else {
877  bool IsCommaNeeded = false;
878  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
879  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
880  if (IsCommaNeeded)
881  OS << ", ";
882  OS << printReg(Reg, TRI);
883  IsCommaNeeded = true;
884  }
885  }
886  }
887  OS << ")";
888  break;
889  }
891  getMetadata()->printAsOperand(OS, MST);
892  break;
894  printSymbol(OS, *getMCSymbol());
895  break;
897  if (const MachineFunction *MF = getMFIfAvailable(*this))
898  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
899  else
900  OS << "<cfi directive>";
901  break;
902  }
905  if (ID < Intrinsic::num_intrinsics)
906  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
907  else if (IntrinsicInfo)
908  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
909  else
910  OS << "intrinsic(" << ID << ')';
911  break;
912  }
914  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
915  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
916  << CmpInst::getPredicateName(Pred) << ')';
917  break;
918  }
919  }
920 }
921 
922 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
923 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
924 #endif
925 
926 //===----------------------------------------------------------------------===//
927 // MachineMemOperand Implementation
928 //===----------------------------------------------------------------------===//
929 
930 /// getAddrSpace - Return the LLVM IR address space number that this pointer
931 /// points into.
932 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
933 
934 /// isDereferenceable - Return true if V is always dereferenceable for
935 /// Offset + Size byte.
937  const DataLayout &DL) const {
938  if (!V.is<const Value *>())
939  return false;
940 
941  const Value *BasePtr = V.get<const Value *>();
942  if (BasePtr == nullptr)
943  return false;
944 
946  BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
947 }
948 
949 /// getConstantPool - Return a MachinePointerInfo record that refers to the
950 /// constant pool.
953 }
954 
955 /// getFixedStack - Return a MachinePointerInfo record that refers to the
956 /// the specified FrameIndex.
958  int FI, int64_t Offset) {
960 }
961 
964 }
965 
967  return MachinePointerInfo(MF.getPSVManager().getGOT());
968 }
969 
971  int64_t Offset, uint8_t ID) {
973 }
974 
977 }
978 
980  uint64_t s, uint64_t a,
981  const AAMDNodes &AAInfo,
982  const MDNode *Ranges, SyncScope::ID SSID,
983  AtomicOrdering Ordering,
984  AtomicOrdering FailureOrdering)
985  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
986  AAInfo(AAInfo), Ranges(Ranges) {
987  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
988  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
989  "invalid pointer value");
990  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
991  assert((isLoad() || isStore()) && "Not a load/store!");
992 
993  AtomicInfo.SSID = static_cast<unsigned>(SSID);
994  assert(getSyncScopeID() == SSID && "Value truncated");
995  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
996  assert(getOrdering() == Ordering && "Value truncated");
997  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
998  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
999 }
1000 
1001 /// Profile - Gather unique data for the object.
1002 ///
1004  ID.AddInteger(getOffset());
1005  ID.AddInteger(Size);
1006  ID.AddPointer(getOpaqueValue());
1007  ID.AddInteger(getFlags());
1009 }
1010 
1012  // The Value and Offset may differ due to CSE. But the flags and size
1013  // should be the same.
1014  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1015  assert(MMO->getSize() == getSize() && "Size mismatch!");
1016 
1017  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1018  // Update the alignment value.
1019  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1020  // Also update the base and offset, because the new alignment may
1021  // not be applicable with the old ones.
1022  PtrInfo = MMO->PtrInfo;
1023  }
1024 }
1025 
1026 /// getAlignment - Return the minimum known alignment in bytes of the
1027 /// actual memory reference.
1029  return MinAlign(getBaseAlignment(), getOffset());
1030 }
1031 
1033  ModuleSlotTracker DummyMST(nullptr);
1034  print(OS, DummyMST);
1035 }
1036 
1039  LLVMContext Ctx;
1040  print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1041 }
1042 
1045  const LLVMContext &Context,
1046  const MachineFrameInfo *MFI,
1047  const TargetInstrInfo *TII) const {
1048  OS << '(';
1049  if (isVolatile())
1050  OS << "volatile ";
1051  if (isNonTemporal())
1052  OS << "non-temporal ";
1053  if (isDereferenceable())
1054  OS << "dereferenceable ";
1055  if (isInvariant())
1056  OS << "invariant ";
1059  << "\" ";
1062  << "\" ";
1065  << "\" ";
1066 
1067  assert((isLoad() || isStore()) &&
1068  "machine memory operand must be a load or store (or both)");
1069  if (isLoad())
1070  OS << "load ";
1071  if (isStore())
1072  OS << "store ";
1073 
1074  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1075 
1077  OS << toIRString(getOrdering()) << ' ';
1079  OS << toIRString(getFailureOrdering()) << ' ';
1080 
1081  OS << getSize();
1082  if (const Value *Val = getValue()) {
1083  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1084  printIRValueReference(OS, *Val, MST);
1085  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1086  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1087  assert(PVal && "Expected a pseudo source value");
1088  switch (PVal->kind()) {
1090  OS << "stack";
1091  break;
1093  OS << "got";
1094  break;
1096  OS << "jump-table";
1097  break;
1099  OS << "constant-pool";
1100  break;
1102  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1103  bool IsFixed = true;
1104  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1105  break;
1106  }
1108  OS << "call-entry ";
1109  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1110  OS, /*PrintType=*/false, MST);
1111  break;
1113  OS << "call-entry &";
1115  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1116  break;
1118  // FIXME: This is not necessarily the correct MIR serialization format for
1119  // a custom pseudo source value, but at least it allows
1120  // -print-machineinstrs to work on a target with custom pseudo source
1121  // values.
1122  OS << "custom ";
1123  PVal->printCustom(OS);
1124  break;
1125  }
1126  }
1128  if (getBaseAlignment() != getSize())
1129  OS << ", align " << getBaseAlignment();
1130  auto AAInfo = getAAInfo();
1131  if (AAInfo.TBAA) {
1132  OS << ", !tbaa ";
1133  AAInfo.TBAA->printAsOperand(OS, MST);
1134  }
1135  if (AAInfo.Scope) {
1136  OS << ", !alias.scope ";
1137  AAInfo.Scope->printAsOperand(OS, MST);
1138  }
1139  if (AAInfo.NoAlias) {
1140  OS << ", !noalias ";
1141  AAInfo.NoAlias->printAsOperand(OS, MST);
1142  }
1143  if (getRanges()) {
1144  OS << ", !range ";
1145  getRanges()->printAsOperand(OS, MST);
1146  }
1147  // FIXME: Implement addrspace printing/parsing in MIR.
1148  // For now, print this even though parsing it is not available in MIR.
1149  if (unsigned AS = getAddrSpace())
1150  OS << ", addrspace " << AS;
1151 
1152  OS << ')';
1153 }
unsigned getTargetFlags() const
uint64_t CallInst * C
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
Definition: FoldingSet.cpp:52
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
LLVMContext & Context
unsigned getAddrSpace() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
MachineBasicBlock * getMBB() const
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:659
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:656
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:779
const uint32_t * RegMask
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur...
const Function * getCurrentFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
unsigned Reg
unsigned getSubReg() const
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:849
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
uint64_t getSize() const
Return the size in bytes of the memory reference.
void printEscapedString(StringRef Name, raw_ostream &Out)
Print each character of the specified string, escaping it if it is not printable or if it is an escap...
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, uint64_t a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment...
MachineBasicBlock reference.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:862
F(f)
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:452
Manage lifetime of a slot tracker for printing IR.
struct llvm::MachineOperand::@147::@149 Reg
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
void print(raw_ostream &OS) const
Support for operator<<.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:114
Mask of preserved registers.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Function * getFunction() const
Definition: Constants.h:862
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
A description of a memory reference used in the backend.
const void * getOpaqueValue() const
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:613
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
void AddInteger(signed I)
Definition: FoldingSet.cpp:61
union llvm::MachineOperand::@147::@150::@151 Val
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
const char * getSymbolName() const
unsigned getCFIIndex() const
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
Immediate >64bit operand.
PseudoSourceValueManager & getPSVManager() const
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
int getObjectIndexBegin() const
Return the minimum frame object index.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4431
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual const TargetInstrInfo * getInstrInfo() const
MCSymbol * getLabel() const
Definition: MCDwarf.h:546
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:330
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const Value * getValue() const
Return the base address of the memory access.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:59
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:306
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:610
Address of a global value.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
unsigned const MachineRegisterInfo * MRI
bool hasName() const
Definition: Value.h:251
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
unsigned getRegister2() const
Definition: MCDwarf.h:556
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const GlobalValue * getGlobal() const
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getOffset() const
Definition: MCDwarf.h:561
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
OpType getOperation() const
Definition: MCDwarf.h:545
bool isValid() const
const PseudoSourceValue * getPseudoValue() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:885
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:936
void setOffset(int64_t Offset)
StringRef getValues() const
Definition: MCDwarf.h:568
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:835
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
This class contains a discriminated union of information about pointers in memory operands...
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4143
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment...
TargetIntrinsicInfo - Interface to description of machine instruction set.
unsigned getRegister() const
Definition: MCDwarf.h:548
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:398
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:662
int64_t getImm() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
MCSymbol reference (for debug/eh info)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
bool isIntPredicate() const
Definition: InstrTypes.h:977
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:602
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:72
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:62
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
int64_t getOffset() const
Return the offset from the symbol in this operand.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:769
Flags getFlags() const
Return the raw flags of the source value,.
void setSubReg(unsigned subReg)
Abstract Stack Frame Index.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This file defines passes to print out IR in various granularities.
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:135
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4185
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MCSymbol * getMCSymbol() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
Floating-point immediate operand.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:123
Address of indexed Constant in Constant Pool.
bool isDereferenceableAndAlignedPointer(const Value *V, unsigned Align, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested...
Definition: Loads.cpp:129
const ConstantInt * getCImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MDNode * getMetadata() const
bool isImplicit() const
an instruction to allocate memory on the stack
Definition: Instructions.h:60
static void printIRValueReference(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Metadata reference (for debug info)
unsigned getPredicate() const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.