LLVM  10.0.0svn
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
21 
22 using namespace llvm;
23 
25  : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
28  const EVT &VT) {
29  if (VA.isRegLoc()) {
30  assignValueToReg(VReg, VA, VT);
31  } else if (VA.isMemLoc()) {
32  assignValueToAddress(VReg, VA);
33  } else {
34  return false;
35  }
36  return true;
37 }
38 
40  ArrayRef<CCValAssign> ArgLocs,
41  unsigned ArgLocsStartIndex,
42  const EVT &VT) {
43  for (unsigned i = 0; i < VRegs.size(); ++i)
44  if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
45  return false;
46  return true;
47 }
48 
51  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
52  std::reverse(VRegs.begin(), VRegs.end());
53 }
54 
58  unsigned SplitLength;
59  const Function &F = MIRBuilder.getMF().getFunction();
60  const DataLayout &DL = F.getParent()->getDataLayout();
61  const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
62  MIRBuilder.getMF().getSubtarget().getTargetLowering());
63 
64  for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
65  ++ArgsIndex, ArgLocsIndex += SplitLength) {
66  EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
67  SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
68  F.getCallingConv(), VT);
69  assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
70 
71  if (SplitLength > 1) {
72  VRegs.clear();
73  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
74  F.getContext(), F.getCallingConv(), VT);
75  for (unsigned i = 0; i < SplitLength; ++i)
76  VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
77 
78  if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
79  VT))
80  return false;
81  } else {
82  if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
83  return false;
84  }
85  }
86  return true;
87 }
88 
89 namespace {
90 class IncomingValueHandler : public MipsCallLowering::MipsHandler {
91 public:
92  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
93  : MipsHandler(MIRBuilder, MRI) {}
94 
95 private:
96  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
97  const EVT &VT) override;
98 
99  Register getStackAddress(const CCValAssign &VA,
100  MachineMemOperand *&MMO) override;
101 
102  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
103 
104  bool handleSplit(SmallVectorImpl<Register> &VRegs,
105  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
106  Register ArgsReg, const EVT &VT) override;
107 
108  virtual void markPhysRegUsed(unsigned PhysReg) {
109  MIRBuilder.getMRI()->addLiveIn(PhysReg);
110  MIRBuilder.getMBB().addLiveIn(PhysReg);
111  }
112 
113  void buildLoad(Register Val, const CCValAssign &VA) {
114  MachineMemOperand *MMO;
115  Register Addr = getStackAddress(VA, MMO);
116  MIRBuilder.buildLoad(Val, Addr, *MMO);
117  }
118 };
119 
120 class CallReturnHandler : public IncomingValueHandler {
121 public:
122  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
123  MachineInstrBuilder &MIB)
124  : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
125 
126 private:
127  void markPhysRegUsed(unsigned PhysReg) override {
128  MIB.addDef(PhysReg, RegState::Implicit);
129  }
130 
131  MachineInstrBuilder &MIB;
132 };
133 
134 } // end anonymous namespace
135 
136 void IncomingValueHandler::assignValueToReg(Register ValVReg,
137  const CCValAssign &VA,
138  const EVT &VT) {
139  const MipsSubtarget &STI =
140  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
141  Register PhysReg = VA.getLocReg();
142  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
143  const MipsSubtarget &STI =
144  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
145 
146  MIRBuilder
147  .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
149  .addDef(ValVReg)
150  .addUse(PhysReg + (STI.isLittle() ? 0 : 1))
151  .addUse(PhysReg + (STI.isLittle() ? 1 : 0))
152  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
153  *STI.getRegBankInfo());
154  markPhysRegUsed(PhysReg);
155  markPhysRegUsed(PhysReg + 1);
156  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
157  MIRBuilder.buildInstr(Mips::MTC1)
158  .addDef(ValVReg)
159  .addUse(PhysReg)
160  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
161  *STI.getRegBankInfo());
162  markPhysRegUsed(PhysReg);
163  } else {
164  switch (VA.getLocInfo()) {
165  case CCValAssign::LocInfo::SExt:
166  case CCValAssign::LocInfo::ZExt:
167  case CCValAssign::LocInfo::AExt: {
168  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
169  MIRBuilder.buildTrunc(ValVReg, Copy);
170  break;
171  }
172  default:
173  MIRBuilder.buildCopy(ValVReg, PhysReg);
174  break;
175  }
176  markPhysRegUsed(PhysReg);
177  }
178 }
179 
180 Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
181  MachineMemOperand *&MMO) {
182  MachineFunction &MF = MIRBuilder.getMF();
183  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
184  unsigned Offset = VA.getLocMemOffset();
185  MachineFrameInfo &MFI = MF.getFrameInfo();
186 
187  int FI = MFI.CreateFixedObject(Size, Offset, true);
188  MachinePointerInfo MPO =
189  MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
190 
192  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
193  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
194 
195  Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
196  MIRBuilder.buildFrameIndex(AddrReg, FI);
197 
198  return AddrReg;
199 }
200 
201 void IncomingValueHandler::assignValueToAddress(Register ValVReg,
202  const CCValAssign &VA) {
203  if (VA.getLocInfo() == CCValAssign::SExt ||
204  VA.getLocInfo() == CCValAssign::ZExt ||
205  VA.getLocInfo() == CCValAssign::AExt) {
206  Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
207  buildLoad(LoadReg, VA);
208  MIRBuilder.buildTrunc(ValVReg, LoadReg);
209  } else
210  buildLoad(ValVReg, VA);
211 }
212 
213 bool IncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
214  ArrayRef<CCValAssign> ArgLocs,
215  unsigned ArgLocsStartIndex,
216  Register ArgsReg, const EVT &VT) {
217  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
218  return false;
219  setLeastSignificantFirst(VRegs);
220  MIRBuilder.buildMerge(ArgsReg, VRegs);
221  return true;
222 }
223 
224 namespace {
225 class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
226 public:
227  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
228  MachineInstrBuilder &MIB)
229  : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
230 
231 private:
232  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
233  const EVT &VT) override;
234 
235  Register getStackAddress(const CCValAssign &VA,
236  MachineMemOperand *&MMO) override;
237 
238  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
239 
240  bool handleSplit(SmallVectorImpl<Register> &VRegs,
241  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
242  Register ArgsReg, const EVT &VT) override;
243 
244  Register extendRegister(Register ValReg, const CCValAssign &VA);
245 
246  MachineInstrBuilder &MIB;
247 };
248 } // end anonymous namespace
249 
250 void OutgoingValueHandler::assignValueToReg(Register ValVReg,
251  const CCValAssign &VA,
252  const EVT &VT) {
253  Register PhysReg = VA.getLocReg();
254  const MipsSubtarget &STI =
255  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
256 
257  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
258  MIRBuilder
259  .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
261  .addDef(PhysReg + (STI.isLittle() ? 1 : 0))
262  .addUse(ValVReg)
263  .addImm(1)
264  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
265  *STI.getRegBankInfo());
266  MIRBuilder
267  .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
269  .addDef(PhysReg + (STI.isLittle() ? 0 : 1))
270  .addUse(ValVReg)
271  .addImm(0)
272  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
273  *STI.getRegBankInfo());
274  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
275  MIRBuilder.buildInstr(Mips::MFC1)
276  .addDef(PhysReg)
277  .addUse(ValVReg)
278  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
279  *STI.getRegBankInfo());
280  } else {
281  Register ExtReg = extendRegister(ValVReg, VA);
282  MIRBuilder.buildCopy(PhysReg, ExtReg);
283  MIB.addUse(PhysReg, RegState::Implicit);
284  }
285 }
286 
287 Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
288  MachineMemOperand *&MMO) {
289  MachineFunction &MF = MIRBuilder.getMF();
291 
292  LLT p0 = LLT::pointer(0, 32);
293  LLT s32 = LLT::scalar(32);
294  Register SPReg = MRI.createGenericVirtualRegister(p0);
295  MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
296 
297  Register OffsetReg = MRI.createGenericVirtualRegister(s32);
298  unsigned Offset = VA.getLocMemOffset();
299  MIRBuilder.buildConstant(OffsetReg, Offset);
300 
301  Register AddrReg = MRI.createGenericVirtualRegister(p0);
302  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
303 
304  MachinePointerInfo MPO =
305  MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
306  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
307  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
308  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align);
309 
310  return AddrReg;
311 }
312 
313 void OutgoingValueHandler::assignValueToAddress(Register ValVReg,
314  const CCValAssign &VA) {
315  MachineMemOperand *MMO;
316  Register Addr = getStackAddress(VA, MMO);
317  Register ExtReg = extendRegister(ValVReg, VA);
318  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
319 }
320 
321 Register OutgoingValueHandler::extendRegister(Register ValReg,
322  const CCValAssign &VA) {
323  LLT LocTy{VA.getLocVT()};
324  switch (VA.getLocInfo()) {
325  case CCValAssign::SExt: {
326  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
327  MIRBuilder.buildSExt(ExtReg, ValReg);
328  return ExtReg;
329  }
330  case CCValAssign::ZExt: {
331  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
332  MIRBuilder.buildZExt(ExtReg, ValReg);
333  return ExtReg;
334  }
335  case CCValAssign::AExt: {
336  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
337  MIRBuilder.buildAnyExt(ExtReg, ValReg);
338  return ExtReg;
339  }
340  // TODO : handle upper extends
341  case CCValAssign::Full:
342  return ValReg;
343  default:
344  break;
345  }
346  llvm_unreachable("unable to extend register");
347 }
348 
349 bool OutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
350  ArrayRef<CCValAssign> ArgLocs,
351  unsigned ArgLocsStartIndex,
352  Register ArgsReg, const EVT &VT) {
353  MIRBuilder.buildUnmerge(VRegs, ArgsReg);
354  setLeastSignificantFirst(VRegs);
355  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
356  return false;
357 
358  return true;
359 }
360 
361 static bool isSupportedType(Type *T) {
362  if (T->isIntegerTy())
363  return true;
364  if (T->isPointerTy())
365  return true;
366  if (T->isFloatingPointTy())
367  return true;
368  return false;
369 }
370 
371 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
372  const ISD::ArgFlagsTy &Flags) {
373  // > does not mean loss of information as type RegisterVT can't hold type VT,
374  // it means that type VT is split into multiple registers of type RegisterVT
375  if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
377  if (Flags.isSExt())
378  return CCValAssign::LocInfo::SExt;
379  if (Flags.isZExt())
380  return CCValAssign::LocInfo::ZExt;
381  return CCValAssign::LocInfo::AExt;
382 }
383 
384 template <typename T>
386  const SmallVectorImpl<T> &Arguments) {
387  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
388  const CCValAssign &VA = ArgLocs[i];
390  Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
391  if (VA.isMemLoc())
392  ArgLocs[i] =
394  VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
395  else
396  ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
397  VA.getLocReg(), VA.getLocVT(), LocInfo);
398  }
399 }
400 
402  const Value *Val,
403  ArrayRef<Register> VRegs) const {
404 
405  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
406 
407  if (Val != nullptr && !isSupportedType(Val->getType()))
408  return false;
409 
410  if (!VRegs.empty()) {
411  MachineFunction &MF = MIRBuilder.getMF();
412  const Function &F = MF.getFunction();
413  const DataLayout &DL = MF.getDataLayout();
414  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
415  LLVMContext &Ctx = Val->getType()->getContext();
416 
417  SmallVector<EVT, 4> SplitEVTs;
418  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
419  assert(VRegs.size() == SplitEVTs.size() &&
420  "For each split Type there should be exactly one VReg.");
421 
422  SmallVector<ArgInfo, 8> RetInfos;
423  SmallVector<unsigned, 8> OrigArgIndices;
424 
425  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
426  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
427  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
428  splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
429  }
430 
432  subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
433 
435  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
436  F.getContext());
437  CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
438  setLocInfo(ArgLocs, Outs);
439 
440  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
441  if (!RetHandler.handle(ArgLocs, RetInfos)) {
442  return false;
443  }
444  }
445  MIRBuilder.insertInstr(Ret);
446  return true;
447 }
448 
450  MachineIRBuilder &MIRBuilder, const Function &F,
451  ArrayRef<ArrayRef<Register>> VRegs) const {
452 
453  // Quick exit if there aren't any args.
454  if (F.arg_empty())
455  return true;
456 
457  if (F.isVarArg()) {
458  return false;
459  }
460 
461  for (auto &Arg : F.args()) {
462  if (!isSupportedType(Arg.getType()))
463  return false;
464  }
465 
466  MachineFunction &MF = MIRBuilder.getMF();
467  const DataLayout &DL = MF.getDataLayout();
468  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
469 
470  SmallVector<ArgInfo, 8> ArgInfos;
471  SmallVector<unsigned, 8> OrigArgIndices;
472  unsigned i = 0;
473  for (auto &Arg : F.args()) {
474  ArgInfo AInfo(VRegs[i], Arg.getType());
475  setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
476  splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
477  ++i;
478  }
479 
481  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
482 
484  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
485  F.getContext());
486 
487  const MipsTargetMachine &TM =
488  static_cast<const MipsTargetMachine &>(MF.getTarget());
489  const MipsABIInfo &ABI = TM.getABI();
490  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
491  1);
492  CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
493  setLocInfo(ArgLocs, Ins);
494 
495  IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
496  if (!Handler.handle(ArgLocs, ArgInfos))
497  return false;
498 
499  return true;
500 }
501 
503  CallLoweringInfo &Info) const {
504 
505  if (Info.CallConv != CallingConv::C)
506  return false;
507 
508  for (auto &Arg : Info.OrigArgs) {
509  if (!isSupportedType(Arg.Ty))
510  return false;
511  if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
512  return false;
513  }
514 
515  if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedType(Info.OrigRet.Ty))
516  return false;
517 
518  MachineFunction &MF = MIRBuilder.getMF();
519  const Function &F = MF.getFunction();
520  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
521  const MipsTargetMachine &TM =
522  static_cast<const MipsTargetMachine &>(MF.getTarget());
523  const MipsABIInfo &ABI = TM.getABI();
524 
525  MachineInstrBuilder CallSeqStart =
526  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
527 
528  const bool IsCalleeGlobalPIC =
529  Info.Callee.isGlobal() && TM.isPositionIndependent();
530 
531  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
532  Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
533  MIB.addDef(Mips::SP, RegState::Implicit);
534  if (IsCalleeGlobalPIC) {
535  Register CalleeReg =
537  MachineInstr *CalleeGlobalValue =
538  MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
539  if (!Info.Callee.getGlobal()->hasLocalLinkage())
540  CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
541  MIB.addUse(CalleeReg);
542  } else
543  MIB.add(Info.Callee);
546 
547  TargetLowering::ArgListTy FuncOrigArgs;
548  FuncOrigArgs.reserve(Info.OrigArgs.size());
549 
550  SmallVector<ArgInfo, 8> ArgInfos;
551  SmallVector<unsigned, 8> OrigArgIndices;
552  unsigned i = 0;
553  for (auto &Arg : Info.OrigArgs) {
554 
556  Entry.Ty = Arg.Ty;
557  FuncOrigArgs.push_back(Entry);
558 
559  splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
560  ++i;
561  }
562 
564  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
565 
567  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
568  F.getContext());
569 
571  const char *Call =
572  Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
573  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
574  setLocInfo(ArgLocs, Outs);
575 
576  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
577  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
578  return false;
579  }
580 
581  unsigned NextStackOffset = CCInfo.getNextStackOffset();
583  unsigned StackAlignment = TFL->getStackAlignment();
584  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
585  CallSeqStart.addImm(NextStackOffset).addImm(0);
586 
587  if (IsCalleeGlobalPIC) {
588  MIRBuilder.buildCopy(
589  Register(Mips::GP),
591  MIB.addDef(Mips::GP, RegState::Implicit);
592  }
593  MIRBuilder.insertInstr(MIB);
594  if (MIB->getOpcode() == Mips::JALRPseudo) {
595  const MipsSubtarget &STI =
596  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
597  MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
598  *STI.getRegBankInfo());
599  }
600 
601  if (!Info.OrigRet.Ty->isVoidTy()) {
602  ArgInfos.clear();
603  SmallVector<unsigned, 8> OrigRetIndices;
604 
605  splitToValueTypes(Info.OrigRet, 0, ArgInfos, OrigRetIndices);
606 
608  subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
609 
611  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
612  F.getContext());
613 
614  CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call);
615  setLocInfo(ArgLocs, Ins);
616 
617  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
618  if (!Handler.handle(ArgLocs, ArgInfos))
619  return false;
620  }
621 
622  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
623 
624  return true;
625 }
626 
627 template <typename T>
628 void MipsCallLowering::subTargetRegTypeForCallingConv(
630  ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
631  const DataLayout &DL = F.getParent()->getDataLayout();
632  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
633 
634  unsigned ArgNo = 0;
635  for (auto &Arg : Args) {
636 
637  EVT VT = TLI.getValueType(DL, Arg.Ty);
638  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
639  F.getCallingConv(), VT);
640  unsigned NumRegs = TLI.getNumRegistersForCallingConv(
641  F.getContext(), F.getCallingConv(), VT);
642 
643  for (unsigned i = 0; i < NumRegs; ++i) {
644  ISD::ArgFlagsTy Flags = Arg.Flags;
645 
646  if (i == 0)
648  else
649  Flags.setOrigAlign(1);
650 
651  ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
652  0);
653  }
654  ++ArgNo;
655  }
656 }
657 
658 void MipsCallLowering::splitToValueTypes(
659  const ArgInfo &OrigArg, unsigned OriginalIndex,
660  SmallVectorImpl<ArgInfo> &SplitArgs,
661  SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
662 
663  // TODO : perform structure and array split. For now we only deal with
664  // types that pass isSupportedType check.
665  SplitArgs.push_back(OrigArg);
666  SplitArgsOrigIndices.push_back(OriginalIndex);
667 }
const RegisterBankInfo * getRegBankInfo() const override
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
MachineOperand Callee
Destination of the call.
Definition: CallLowering.h:70
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
bool hasLocalLinkage() const
Definition: GlobalValue.h:445
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
void setTargetFlags(unsigned F)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
bool assignVRegs(ArrayRef< Register > VRegs, ArrayRef< CCValAssign > ArgLocs, unsigned ArgLocsStartIndex, const EVT &VT)
unsigned getValNo() const
unsigned const TargetRegisterInfo * TRI
F(f)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
bool isMemLoc() const
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:161
CCAssignFn * CCAssignFnForCall() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:48
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getSizeInBits() const
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:261
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
bool arg_empty() const
Definition: Function.h:729
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MipsCallLowering(const MipsTargetLowering &TLI)
void setOrigAlign(unsigned A)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:614
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:43
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:223
const GlobalValue * getGlobal() const
Helper class to build MachineInstr.
AMDGPU Lower Kernel Arguments
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static void setLocInfo(SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< T > &Arguments)
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
The memory access writes data.
SmallVector< ArgInfo, 8 > OrigArgs
List of descriptors of the arguments passed to the function.
Definition: CallLowering.h:76
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
bool isLittle() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const MipsRegisterInfo * getRegisterInfo() const override
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
Information about stack frame layout on the target.
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const TargetInstrInfo & getTII()
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void setLeastSignificantFirst(SmallVectorImpl< Register > &VRegs)
This file declares the MachineIRBuilder class.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:130
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:126
unsigned AllocateStack(unsigned Size, unsigned Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
CallingConv::ID CallConv
Calling convention to be used for the call.
Definition: CallLowering.h:66
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
virtual const TargetFrameLowering * getFrameLowering() const
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSupportedType(Type *T)
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:73
CCAssignFn * CCAssignFnForReturn() const
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, const ISD::ArgFlagsTy &Flags)
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
bool isFP64bit() const
ArgInfo OrigRet
Descriptor for the return type of the function.
Definition: CallLowering.h:73
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool handle(ArrayRef< CCValAssign > ArgLocs, ArrayRef< CallLowering::ArgInfo > Args)
iterator_range< arg_iterator > args()
Definition: Function.h:719
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143