LLVM  9.0.0svn
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/CodeGen/Analysis.h"
20 
21 using namespace llvm;
22 
24  : CallLowering(&TLI) {}
25 
26 bool MipsCallLowering::MipsHandler::assign(unsigned VReg,
27  const CCValAssign &VA) {
28  if (VA.isRegLoc()) {
29  assignValueToReg(VReg, VA);
30  } else if (VA.isMemLoc()) {
31  assignValueToAddress(VReg, VA);
32  } else {
33  return false;
34  }
35  return true;
36 }
37 
39  ArrayRef<CCValAssign> ArgLocs,
40  unsigned ArgLocsStartIndex) {
41  for (unsigned i = 0; i < VRegs.size(); ++i)
42  if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i]))
43  return false;
44  return true;
45 }
46 
49  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
50  std::reverse(VRegs.begin(), VRegs.end());
51 }
52 
56  unsigned SplitLength;
57  const Function &F = MIRBuilder.getMF().getFunction();
58  const DataLayout &DL = F.getParent()->getDataLayout();
59  const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
60  MIRBuilder.getMF().getSubtarget().getTargetLowering());
61 
62  for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
63  ++ArgsIndex, ArgLocsIndex += SplitLength) {
64  EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
65  SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
66  F.getCallingConv(), VT);
67  if (SplitLength > 1) {
68  VRegs.clear();
69  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
70  F.getContext(), F.getCallingConv(), VT);
71  for (unsigned i = 0; i < SplitLength; ++i)
72  VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
73 
74  if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg))
75  return false;
76  } else {
77  if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex]))
78  return false;
79  }
80  }
81  return true;
82 }
83 
84 namespace {
85 class IncomingValueHandler : public MipsCallLowering::MipsHandler {
86 public:
87  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
88  : MipsHandler(MIRBuilder, MRI) {}
89 
90 private:
91  void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
92 
93  unsigned getStackAddress(const CCValAssign &VA,
94  MachineMemOperand *&MMO) override;
95 
96  void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
97 
98  bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
99  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
100  unsigned ArgsReg) override;
101 
102  virtual void markPhysRegUsed(unsigned PhysReg) {
103  MIRBuilder.getMBB().addLiveIn(PhysReg);
104  }
105 
106  void buildLoad(unsigned Val, const CCValAssign &VA) {
107  MachineMemOperand *MMO;
108  unsigned Addr = getStackAddress(VA, MMO);
109  MIRBuilder.buildLoad(Val, Addr, *MMO);
110  }
111 };
112 
113 class CallReturnHandler : public IncomingValueHandler {
114 public:
115  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
116  MachineInstrBuilder &MIB)
117  : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
118 
119 private:
120  void markPhysRegUsed(unsigned PhysReg) override {
121  MIB.addDef(PhysReg, RegState::Implicit);
122  }
123 
124  MachineInstrBuilder &MIB;
125 };
126 
127 } // end anonymous namespace
128 
129 void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
130  const CCValAssign &VA) {
131  unsigned PhysReg = VA.getLocReg();
132  switch (VA.getLocInfo()) {
133  case CCValAssign::LocInfo::SExt:
134  case CCValAssign::LocInfo::ZExt:
135  case CCValAssign::LocInfo::AExt: {
136  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
137  MIRBuilder.buildTrunc(ValVReg, Copy);
138  break;
139  }
140  default:
141  MIRBuilder.buildCopy(ValVReg, PhysReg);
142  break;
143  }
144  markPhysRegUsed(PhysReg);
145 }
146 
147 unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
148  MachineMemOperand *&MMO) {
149  MachineFunction &MF = MIRBuilder.getMF();
150  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
151  unsigned Offset = VA.getLocMemOffset();
152  MachineFrameInfo &MFI = MF.getFrameInfo();
153 
154  int FI = MFI.CreateFixedObject(Size, Offset, true);
155  MachinePointerInfo MPO =
156  MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
157 
159  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
160  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
161 
162  unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
163  MIRBuilder.buildFrameIndex(AddrReg, FI);
164 
165  return AddrReg;
166 }
167 
168 void IncomingValueHandler::assignValueToAddress(unsigned ValVReg,
169  const CCValAssign &VA) {
170  if (VA.getLocInfo() == CCValAssign::SExt ||
171  VA.getLocInfo() == CCValAssign::ZExt ||
172  VA.getLocInfo() == CCValAssign::AExt) {
173  unsigned LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
174  buildLoad(LoadReg, VA);
175  MIRBuilder.buildTrunc(ValVReg, LoadReg);
176  } else
177  buildLoad(ValVReg, VA);
178 }
179 
180 bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
181  ArrayRef<CCValAssign> ArgLocs,
182  unsigned ArgLocsStartIndex,
183  unsigned ArgsReg) {
184  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
185  return false;
186  setLeastSignificantFirst(VRegs);
187  MIRBuilder.buildMerge(ArgsReg, VRegs);
188  return true;
189 }
190 
191 namespace {
192 class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
193 public:
194  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
195  MachineInstrBuilder &MIB)
196  : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
197 
198 private:
199  void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
200 
201  unsigned getStackAddress(const CCValAssign &VA,
202  MachineMemOperand *&MMO) override;
203 
204  void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
205 
206  bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
207  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
208  unsigned ArgsReg) override;
209 
210  unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
211 
212  MachineInstrBuilder &MIB;
213 };
214 } // end anonymous namespace
215 
216 void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
217  const CCValAssign &VA) {
218  unsigned PhysReg = VA.getLocReg();
219  unsigned ExtReg = extendRegister(ValVReg, VA);
220  MIRBuilder.buildCopy(PhysReg, ExtReg);
221  MIB.addUse(PhysReg, RegState::Implicit);
222 }
223 
224 unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
225  MachineMemOperand *&MMO) {
226  MachineFunction &MF = MIRBuilder.getMF();
228 
229  LLT p0 = LLT::pointer(0, 32);
230  LLT s32 = LLT::scalar(32);
231  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
232  MIRBuilder.buildCopy(SPReg, Mips::SP);
233 
234  unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
235  unsigned Offset = VA.getLocMemOffset();
236  MIRBuilder.buildConstant(OffsetReg, Offset);
237 
238  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
239  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
240 
241  MachinePointerInfo MPO =
242  MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
243  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
244  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
245  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align);
246 
247  return AddrReg;
248 }
249 
250 void OutgoingValueHandler::assignValueToAddress(unsigned ValVReg,
251  const CCValAssign &VA) {
252  MachineMemOperand *MMO;
253  unsigned Addr = getStackAddress(VA, MMO);
254  unsigned ExtReg = extendRegister(ValVReg, VA);
255  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
256 }
257 
258 unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
259  const CCValAssign &VA) {
260  LLT LocTy{VA.getLocVT()};
261  switch (VA.getLocInfo()) {
262  case CCValAssign::SExt: {
263  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
264  MIRBuilder.buildSExt(ExtReg, ValReg);
265  return ExtReg;
266  }
267  case CCValAssign::ZExt: {
268  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
269  MIRBuilder.buildZExt(ExtReg, ValReg);
270  return ExtReg;
271  }
272  case CCValAssign::AExt: {
273  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
274  MIRBuilder.buildAnyExt(ExtReg, ValReg);
275  return ExtReg;
276  }
277  // TODO : handle upper extends
278  case CCValAssign::Full:
279  return ValReg;
280  default:
281  break;
282  }
283  llvm_unreachable("unable to extend register");
284 }
285 
286 bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
287  ArrayRef<CCValAssign> ArgLocs,
288  unsigned ArgLocsStartIndex,
289  unsigned ArgsReg) {
290  MIRBuilder.buildUnmerge(VRegs, ArgsReg);
291  setLeastSignificantFirst(VRegs);
292  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
293  return false;
294 
295  return true;
296 }
297 
298 static bool isSupportedType(Type *T) {
299  if (T->isIntegerTy())
300  return true;
301  if (T->isPointerTy())
302  return true;
303  return false;
304 }
305 
306 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
307  const ISD::ArgFlagsTy &Flags) {
308  // > does not mean loss of information as type RegisterVT can't hold type VT,
309  // it means that type VT is split into multiple registers of type RegisterVT
310  if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
312  if (Flags.isSExt())
313  return CCValAssign::LocInfo::SExt;
314  if (Flags.isZExt())
315  return CCValAssign::LocInfo::ZExt;
316  return CCValAssign::LocInfo::AExt;
317 }
318 
319 template <typename T>
321  const SmallVectorImpl<T> &Arguments) {
322  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
323  const CCValAssign &VA = ArgLocs[i];
325  Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
326  if (VA.isMemLoc())
327  ArgLocs[i] =
329  VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
330  else
331  ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
332  VA.getLocReg(), VA.getLocVT(), LocInfo);
333  }
334 }
335 
337  const Value *Val,
338  ArrayRef<unsigned> VRegs) const {
339 
340  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
341 
342  if (Val != nullptr && !isSupportedType(Val->getType()))
343  return false;
344 
345  if (!VRegs.empty()) {
346  MachineFunction &MF = MIRBuilder.getMF();
347  const Function &F = MF.getFunction();
348  const DataLayout &DL = MF.getDataLayout();
349  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
350  LLVMContext &Ctx = Val->getType()->getContext();
351 
352  SmallVector<EVT, 4> SplitEVTs;
353  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
354  assert(VRegs.size() == SplitEVTs.size() &&
355  "For each split Type there should be exactly one VReg.");
356 
357  SmallVector<ArgInfo, 8> RetInfos;
358  SmallVector<unsigned, 8> OrigArgIndices;
359 
360  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
361  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
362  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
363  splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
364  }
365 
367  subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
368 
370  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
371  F.getContext());
372  CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
373  setLocInfo(ArgLocs, Outs);
374 
375  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
376  if (!RetHandler.handle(ArgLocs, RetInfos)) {
377  return false;
378  }
379  }
380  MIRBuilder.insertInstr(Ret);
381  return true;
382 }
383 
385  const Function &F,
386  ArrayRef<unsigned> VRegs) const {
387 
388  // Quick exit if there aren't any args.
389  if (F.arg_empty())
390  return true;
391 
392  if (F.isVarArg()) {
393  return false;
394  }
395 
396  for (auto &Arg : F.args()) {
397  if (!isSupportedType(Arg.getType()))
398  return false;
399  }
400 
401  MachineFunction &MF = MIRBuilder.getMF();
402  const DataLayout &DL = MF.getDataLayout();
403  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
404 
405  SmallVector<ArgInfo, 8> ArgInfos;
406  SmallVector<unsigned, 8> OrigArgIndices;
407  unsigned i = 0;
408  for (auto &Arg : F.args()) {
409  ArgInfo AInfo(VRegs[i], Arg.getType());
410  setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
411  splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
412  ++i;
413  }
414 
416  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
417 
419  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
420  F.getContext());
421 
422  const MipsTargetMachine &TM =
423  static_cast<const MipsTargetMachine &>(MF.getTarget());
424  const MipsABIInfo &ABI = TM.getABI();
425  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
426  1);
427  CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
428  setLocInfo(ArgLocs, Ins);
429 
430  IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
431  if (!Handler.handle(ArgLocs, ArgInfos))
432  return false;
433 
434  return true;
435 }
436 
438  CallingConv::ID CallConv,
439  const MachineOperand &Callee,
440  const ArgInfo &OrigRet,
441  ArrayRef<ArgInfo> OrigArgs) const {
442 
443  if (CallConv != CallingConv::C)
444  return false;
445 
446  for (auto &Arg : OrigArgs) {
447  if (!isSupportedType(Arg.Ty))
448  return false;
449  if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
450  return false;
451  }
452  if (OrigRet.Reg && !isSupportedType(OrigRet.Ty))
453  return false;
454 
455  MachineFunction &MF = MIRBuilder.getMF();
456  const Function &F = MF.getFunction();
457  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
458  const MipsTargetMachine &TM =
459  static_cast<const MipsTargetMachine &>(MF.getTarget());
460  const MipsABIInfo &ABI = TM.getABI();
461 
462  MachineInstrBuilder CallSeqStart =
463  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
464 
465  // FIXME: Add support for pic calling sequences, long call sequences for O32,
466  // N32 and N64. First handle the case when Callee.isReg().
467  if (Callee.isReg())
468  return false;
469 
470  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
471  MIB.addDef(Mips::SP, RegState::Implicit);
472  MIB.add(Callee);
475 
476  TargetLowering::ArgListTy FuncOrigArgs;
477  FuncOrigArgs.reserve(OrigArgs.size());
478 
479  SmallVector<ArgInfo, 8> ArgInfos;
480  SmallVector<unsigned, 8> OrigArgIndices;
481  unsigned i = 0;
482  for (auto &Arg : OrigArgs) {
483 
485  Entry.Ty = Arg.Ty;
486  FuncOrigArgs.push_back(Entry);
487 
488  splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
489  ++i;
490  }
491 
493  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
494 
496  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
497  F.getContext());
498 
499  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
500  const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
501  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
502  setLocInfo(ArgLocs, Outs);
503 
504  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
505  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
506  return false;
507  }
508 
509  unsigned NextStackOffset = CCInfo.getNextStackOffset();
511  unsigned StackAlignment = TFL->getStackAlignment();
512  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
513  CallSeqStart.addImm(NextStackOffset).addImm(0);
514 
515  MIRBuilder.insertInstr(MIB);
516 
517  if (OrigRet.Reg) {
518 
519  ArgInfos.clear();
520  SmallVector<unsigned, 8> OrigRetIndices;
521 
522  splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
523 
525  subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
526 
528  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
529  F.getContext());
530 
531  CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
532  setLocInfo(ArgLocs, Ins);
533 
534  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
535  if (!Handler.handle(ArgLocs, ArgInfos))
536  return false;
537  }
538 
539  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
540 
541  return true;
542 }
543 
544 template <typename T>
545 void MipsCallLowering::subTargetRegTypeForCallingConv(
547  ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
548  const DataLayout &DL = F.getParent()->getDataLayout();
549  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
550 
551  unsigned ArgNo = 0;
552  for (auto &Arg : Args) {
553 
554  EVT VT = TLI.getValueType(DL, Arg.Ty);
555  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
556  F.getCallingConv(), VT);
557  unsigned NumRegs = TLI.getNumRegistersForCallingConv(
558  F.getContext(), F.getCallingConv(), VT);
559 
560  for (unsigned i = 0; i < NumRegs; ++i) {
561  ISD::ArgFlagsTy Flags = Arg.Flags;
562 
563  if (i == 0)
565  else
566  Flags.setOrigAlign(1);
567 
568  ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
569  0);
570  }
571  ++ArgNo;
572  }
573 }
574 
575 void MipsCallLowering::splitToValueTypes(
576  const ArgInfo &OrigArg, unsigned OriginalIndex,
577  SmallVectorImpl<ArgInfo> &SplitArgs,
578  SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
579 
580  // TODO : perform structure and array split. For now we only deal with
581  // types that pass isSupportedType check.
582  SplitArgs.push_back(OrigArg);
583  SplitArgsOrigIndices.push_back(OriginalIndex);
584 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned Reg
unsigned getValNo() const
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
bool isMemLoc() const
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
CCAssignFn * CCAssignFnForCall() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:48
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool assignVRegs(ArrayRef< unsigned > VRegs, ArrayRef< CCValAssign > ArgLocs, unsigned Index)
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
unsigned getSizeInBits() const
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
bool arg_empty() const
Definition: Function.h:698
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MipsCallLowering(const MipsTargetLowering &TLI)
void setOrigAlign(unsigned A)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:83
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:223
Helper class to build MachineInstr.
AMDGPU Lower Kernel Arguments
void setLeastSignificantFirst(SmallVectorImpl< unsigned > &VRegs)
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static void setLocInfo(SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< T > &Arguments)
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
The memory access writes data.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
CCValAssign - Represent assignment of one arg/retval to a location.
Information about stack frame layout on the target.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:130
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:644
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
virtual const TargetFrameLowering * getFrameLowering() const
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSupportedType(Type *T)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCAssignFn * CCAssignFnForReturn() const
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, const ISD::ArgFlagsTy &Flags)
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getLocReg() const
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool handle(ArrayRef< CCValAssign > ArgLocs, ArrayRef< CallLowering::ArgInfo > Args)
iterator_range< arg_iterator > args()
Definition: Function.h:688
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143