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MipsDisassembler.cpp
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1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Mips Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "Mips.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/Debug.h"
28 #include <cassert>
29 #include <cstdint>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mips-disassembler"
34 
36 
37 namespace {
38 
39 class MipsDisassembler : public MCDisassembler {
40  bool IsMicroMips;
41  bool IsBigEndian;
42 
43 public:
44  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
45  : MCDisassembler(STI, Ctx),
46  IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
47  IsBigEndian(IsBigEndian) {}
48 
49  bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
50  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
51  bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
52 
53  bool hasMips32r6() const {
54  return STI.getFeatureBits()[Mips::FeatureMips32r6];
55  }
56 
57  bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
58 
59  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
60 
61  bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
62 
63  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
64 
65  bool hasCOP3() const {
66  // Only present in MIPS-I and MIPS-II
67  return !hasMips32() && !hasMips3();
68  }
69 
70  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
71  ArrayRef<uint8_t> Bytes, uint64_t Address,
72  raw_ostream &VStream,
73  raw_ostream &CStream) const override;
74 };
75 
76 } // end anonymous namespace
77 
78 // Forward declare these because the autogenerated code will reference them.
79 // Definitions are further down.
81  unsigned RegNo,
82  uint64_t Address,
83  const void *Decoder);
84 
86  unsigned RegNo,
87  uint64_t Address,
88  const void *Decoder);
89 
91  unsigned RegNo,
92  uint64_t Address,
93  const void *Decoder);
94 
96  unsigned RegNo,
97  uint64_t Address,
98  const void *Decoder);
99 
101  unsigned RegNo,
102  uint64_t Address,
103  const void *Decoder);
104 
106  unsigned RegNo,
107  uint64_t Address,
108  const void *Decoder);
109 
111  unsigned Insn,
112  uint64_t Address,
113  const void *Decoder);
114 
116  unsigned RegNo,
117  uint64_t Address,
118  const void *Decoder);
119 
121  unsigned RegNo,
122  uint64_t Address,
123  const void *Decoder);
124 
126  unsigned RegNo,
127  uint64_t Address,
128  const void *Decoder);
129 
131  unsigned RegNo,
132  uint64_t Address,
133  const void *Decoder);
134 
136  unsigned RegNo,
137  uint64_t Address,
138  const void *Decoder);
139 
140 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
141  uint64_t Address,
142  const void *Decoder);
143 
145  unsigned Insn,
146  uint64_t Address,
147  const void *Decoder);
148 
150  unsigned RegNo,
151  uint64_t Address,
152  const void *Decoder);
153 
155  unsigned RegNo,
156  uint64_t Address,
157  const void *Decoder);
158 
160  unsigned RegNo,
161  uint64_t Address,
162  const void *Decoder);
163 
165  unsigned RegNo,
166  uint64_t Address,
167  const void *Decoder);
168 
170  unsigned RegNo,
171  uint64_t Address,
172  const void *Decoder);
173 
175  unsigned RegNo,
176  uint64_t Address,
177  const void *Decoder);
178 
180  unsigned RegNo,
181  uint64_t Address,
182  const void *Decoder);
183 
185  unsigned RegNo,
186  uint64_t Address,
187  const void *Decoder);
188 
190  unsigned RegNo,
191  uint64_t Address,
192  const void *Decoder);
193 
195  unsigned RegNo,
196  uint64_t Address,
197  const void *Decoder);
198 
200  unsigned RegNo,
201  uint64_t Address,
202  const void *Decoder);
203 
205  unsigned Offset,
206  uint64_t Address,
207  const void *Decoder);
208 
210  unsigned Offset,
211  uint64_t Address,
212  const void *Decoder);
213 
215  unsigned Insn,
216  uint64_t Address,
217  const void *Decoder);
218 
220  unsigned Offset,
221  uint64_t Address,
222  const void *Decoder);
223 
225  unsigned Offset,
226  uint64_t Address,
227  const void *Decoder);
228 
230  unsigned Offset,
231  uint64_t Address,
232  const void *Decoder);
233 
234 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
235 // shifted left by 1 bit.
237  unsigned Offset,
238  uint64_t Address,
239  const void *Decoder);
240 
241 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
242 // shifted left by 1 bit.
244  unsigned Offset,
245  uint64_t Address,
246  const void *Decoder);
247 
248 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
249 // shifted left by 1 bit.
251  unsigned Offset,
252  uint64_t Address,
253  const void *Decoder);
254 
255 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
256 // shifted left by 1 bit.
258  unsigned Offset,
259  uint64_t Address,
260  const void *Decoder);
261 
262 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
263 // shifted left by 1 bit.
265  unsigned Insn,
266  uint64_t Address,
267  const void *Decoder);
268 
269 static DecodeStatus DecodeMem(MCInst &Inst,
270  unsigned Insn,
271  uint64_t Address,
272  const void *Decoder);
273 
274 static DecodeStatus DecodeMemEVA(MCInst &Inst,
275  unsigned Insn,
276  uint64_t Address,
277  const void *Decoder);
278 
280  unsigned Insn,
281  uint64_t Address,
282  const void *Decoder);
283 
284 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
285  const void *Decoder);
286 
288  unsigned Insn,
289  uint64_t Address,
290  const void *Decoder);
291 
292 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
293  unsigned Insn,
294  uint64_t Address,
295  const void *Decoder);
296 
297 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
298  unsigned Insn,
299  uint64_t Address,
300  const void *Decoder);
301 
302 static DecodeStatus DecodeSyncI(MCInst &Inst,
303  unsigned Insn,
304  uint64_t Address,
305  const void *Decoder);
306 
307 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
308  unsigned Insn,
309  uint64_t Address,
310  const void *Decoder);
311 
312 static DecodeStatus DecodeSynciR6(MCInst &Inst,
313  unsigned Insn,
314  uint64_t Address,
315  const void *Decoder);
316 
317 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
318  uint64_t Address, const void *Decoder);
319 
320 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
321  unsigned Insn,
322  uint64_t Address,
323  const void *Decoder);
324 
326  unsigned Insn,
327  uint64_t Address,
328  const void *Decoder);
329 
331  unsigned Insn,
332  uint64_t Address,
333  const void *Decoder);
334 
336  unsigned Insn,
337  uint64_t Address,
338  const void *Decoder);
339 
340 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
341  unsigned Insn,
342  uint64_t Address,
343  const void *Decoder);
344 
346  unsigned Insn,
347  uint64_t Address,
348  const void *Decoder);
349 
351  unsigned Insn,
352  uint64_t Address,
353  const void *Decoder);
354 
355 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
356  uint64_t Address,
357  const void *Decoder);
358 
359 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
360  uint64_t Address,
361  const void *Decoder);
362 
363 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
364  const void *Decoder);
365 
366 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
367  const void *Decoder);
368 
369 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
370  uint64_t Address, const void *Decoder);
371 
372 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
373  uint64_t Address,
374  const void *Decoder);
375 
377  unsigned Insn,
378  uint64_t Address,
379  const void *Decoder);
380 
382  unsigned Value,
383  uint64_t Address,
384  const void *Decoder);
385 
386 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
387  unsigned Value,
388  uint64_t Address,
389  const void *Decoder);
390 
392  unsigned Value,
393  uint64_t Address,
394  const void *Decoder);
395 
396 template <unsigned Bits, int Offset, int Scale>
397 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
398  uint64_t Address,
399  const void *Decoder);
400 
401 template <unsigned Bits, int Offset>
402 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
403  uint64_t Address,
404  const void *Decoder) {
405  return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
406  Decoder);
407 }
408 
409 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
410 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
411  uint64_t Address,
412  const void *Decoder);
413 
414 static DecodeStatus DecodeInsSize(MCInst &Inst,
415  unsigned Insn,
416  uint64_t Address,
417  const void *Decoder);
418 
419 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
420  uint64_t Address, const void *Decoder);
421 
422 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
423  uint64_t Address, const void *Decoder);
424 
425 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
426  uint64_t Address, const void *Decoder);
427 
428 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
429  uint64_t Address, const void *Decoder);
430 
431 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
432  uint64_t Address, const void *Decoder);
433 
434 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
435 /// handle.
436 template <typename InsnType>
437 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
438  const void *Decoder);
439 
440 template <typename InsnType>
441 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
442  const void *Decoder);
443 
444 template <typename InsnType>
445 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
446  const void *Decoder);
447 
448 template <typename InsnType>
449 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
450  const void *Decoder);
451 
452 template <typename InsnType>
453 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
454  const void *Decoder);
455 
456 template <typename InsnType>
457 static DecodeStatus
458 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
459  const void *Decoder);
460 
461 template <typename InsnType>
462 static DecodeStatus
463 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
464  const void *Decoder);
465 
466 template <typename InsnType>
467 static DecodeStatus
468 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
469  const void *Decoder);
470 
471 template <typename InsnType>
472 static DecodeStatus
473 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
474  const void *Decoder);
475 
476 template <typename InsnType>
477 static DecodeStatus
478 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
479  const void *Decoder);
480 
481 template <typename InsnType>
482 static DecodeStatus
483 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
484  const void *Decoder);
485 
486 template <typename InsnType>
487 static DecodeStatus
488 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
489  const void *Decoder);
490 
491 template <typename InsnType>
492 static DecodeStatus
493 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
494  const void *Decoder);
495 
496 template <typename InsnType>
497 static DecodeStatus
498 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
499  const void *Decoder);
500 
501 template <typename InsnType>
502 static DecodeStatus
503 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
504  const void *Decoder);
505 
506 template <typename InsnType>
507 static DecodeStatus
508 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
509  const void *Decoder);
510 
511 template <typename InsnType>
512 static DecodeStatus
513 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
514  const void *Decoder);
515 
516 template <typename InsnType>
517 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
518  const void *Decoder);
519 
520 template <typename InsnType>
521 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
522  const void *Decoder);
523 
524 template <typename InsnType>
525 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
526  const void *Decoder);
527 
528 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
529  uint64_t Address,
530  const void *Decoder);
531 
532 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
533  uint64_t Address,
534  const void *Decoder);
535 
536 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
537  uint64_t Address,
538  const void *Decoder);
539 
540 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
541  uint64_t Address, const void *Decoder);
542 
543 namespace llvm {
544 
549 
550 } // end namespace llvm
551 
553  const Target &T,
554  const MCSubtargetInfo &STI,
555  MCContext &Ctx) {
556  return new MipsDisassembler(STI, Ctx, true);
557 }
558 
560  const Target &T,
561  const MCSubtargetInfo &STI,
562  MCContext &Ctx) {
563  return new MipsDisassembler(STI, Ctx, false);
564 }
565 
567  // Register the disassembler.
576 }
577 
578 #include "MipsGenDisassemblerTables.inc"
579 
580 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
581  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
582  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
583  return *(RegInfo->getRegClass(RC).begin() + RegNo);
584 }
585 
586 template <typename InsnType>
587 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
588  const void *Decoder) {
589  using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
590 
591  // The size of the n field depends on the element size
592  // The register class also depends on this.
593  InsnType tmp = fieldFromInstruction(insn, 17, 5);
594  unsigned NSize = 0;
595  DecodeFN RegDecoder = nullptr;
596  if ((tmp & 0x18) == 0x00) { // INSVE_B
597  NSize = 4;
598  RegDecoder = DecodeMSA128BRegisterClass;
599  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
600  NSize = 3;
601  RegDecoder = DecodeMSA128HRegisterClass;
602  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
603  NSize = 2;
604  RegDecoder = DecodeMSA128WRegisterClass;
605  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
606  NSize = 1;
607  RegDecoder = DecodeMSA128DRegisterClass;
608  } else
609  llvm_unreachable("Invalid encoding");
610 
611  assert(NSize != 0 && RegDecoder != nullptr);
612 
613  // $wd
614  tmp = fieldFromInstruction(insn, 6, 5);
615  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
616  return MCDisassembler::Fail;
617  // $wd_in
618  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
619  return MCDisassembler::Fail;
620  // $n
621  tmp = fieldFromInstruction(insn, 16, NSize);
623  // $ws
624  tmp = fieldFromInstruction(insn, 11, 5);
625  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
626  return MCDisassembler::Fail;
627  // $n2
629 
631 }
632 
633 template <typename InsnType>
634 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
635  const void *Decoder) {
636  InsnType Rs = fieldFromInstruction(insn, 16, 5);
637  InsnType Imm = fieldFromInstruction(insn, 0, 16);
638  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
639  Rs)));
640  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
641  Rs)));
643 
645 }
646 
647 template <typename InsnType>
648 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
649  const void *Decoder) {
650  InsnType Rs = fieldFromInstruction(insn, 21, 5);
651  InsnType Imm = fieldFromInstruction(insn, 0, 16);
652  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
653  Rs)));
654  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
655  Rs)));
657 
659 }
660 
661 template <typename InsnType>
662 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
663  uint64_t Address,
664  const void *Decoder) {
665  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
666  // (otherwise we would have matched the ADDI instruction from the earlier
667  // ISA's instead).
668  //
669  // We have:
670  // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
671  // BOVC if rs >= rt
672  // BEQZALC if rs == 0 && rt != 0
673  // BEQC if rs < rt && rs != 0
674 
675  InsnType Rs = fieldFromInstruction(insn, 21, 5);
676  InsnType Rt = fieldFromInstruction(insn, 16, 5);
677  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
678  bool HasRs = false;
679 
680  if (Rs >= Rt) {
681  MI.setOpcode(Mips::BOVC);
682  HasRs = true;
683  } else if (Rs != 0 && Rs < Rt) {
684  MI.setOpcode(Mips::BEQC);
685  HasRs = true;
686  } else
687  MI.setOpcode(Mips::BEQZALC);
688 
689  if (HasRs)
690  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
691  Rs)));
692 
693  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
694  Rt)));
696 
698 }
699 
700 template <typename InsnType>
702  uint64_t Address,
703  const void *Decoder) {
704  InsnType Rt = fieldFromInstruction(insn, 21, 5);
705  InsnType Rs = fieldFromInstruction(insn, 16, 5);
706  int64_t Imm = 0;
707 
708  if (Rs >= Rt) {
709  MI.setOpcode(Mips::BOVC_MMR6);
710  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
711  Rt)));
712  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
713  Rs)));
714  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
715  } else if (Rs != 0 && Rs < Rt) {
716  MI.setOpcode(Mips::BEQC_MMR6);
717  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
718  Rs)));
719  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
720  Rt)));
721  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
722  } else {
723  MI.setOpcode(Mips::BEQZALC_MMR6);
724  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
725  Rt)));
726  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
727  }
728 
730 
732 }
733 
734 template <typename InsnType>
735 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
736  uint64_t Address,
737  const void *Decoder) {
738  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
739  // (otherwise we would have matched the ADDI instruction from the earlier
740  // ISA's instead).
741  //
742  // We have:
743  // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
744  // BNVC if rs >= rt
745  // BNEZALC if rs == 0 && rt != 0
746  // BNEC if rs < rt && rs != 0
747 
748  InsnType Rs = fieldFromInstruction(insn, 21, 5);
749  InsnType Rt = fieldFromInstruction(insn, 16, 5);
750  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
751  bool HasRs = false;
752 
753  if (Rs >= Rt) {
754  MI.setOpcode(Mips::BNVC);
755  HasRs = true;
756  } else if (Rs != 0 && Rs < Rt) {
757  MI.setOpcode(Mips::BNEC);
758  HasRs = true;
759  } else
760  MI.setOpcode(Mips::BNEZALC);
761 
762  if (HasRs)
763  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
764  Rs)));
765 
766  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
767  Rt)));
769 
771 }
772 
773 template <typename InsnType>
775  uint64_t Address,
776  const void *Decoder) {
777  InsnType Rt = fieldFromInstruction(insn, 21, 5);
778  InsnType Rs = fieldFromInstruction(insn, 16, 5);
779  int64_t Imm = 0;
780 
781  if (Rs >= Rt) {
782  MI.setOpcode(Mips::BNVC_MMR6);
783  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
784  Rt)));
785  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
786  Rs)));
787  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
788  } else if (Rs != 0 && Rs < Rt) {
789  MI.setOpcode(Mips::BNEC_MMR6);
790  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
791  Rs)));
792  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
793  Rt)));
794  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
795  } else {
796  MI.setOpcode(Mips::BNEZALC_MMR6);
797  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
798  Rt)));
799  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
800  }
801 
803 
805 }
806 
807 template <typename InsnType>
809  uint64_t Address,
810  const void *Decoder) {
811  // We have:
812  // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
813  // Invalid if rt == 0
814  // BGTZC_MMR6 if rs == 0 && rt != 0
815  // BLTZC_MMR6 if rs == rt && rt != 0
816  // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
817 
818  InsnType Rt = fieldFromInstruction(insn, 21, 5);
819  InsnType Rs = fieldFromInstruction(insn, 16, 5);
820  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
821  bool HasRs = false;
822 
823  if (Rt == 0)
824  return MCDisassembler::Fail;
825  else if (Rs == 0)
826  MI.setOpcode(Mips::BGTZC_MMR6);
827  else if (Rs == Rt)
828  MI.setOpcode(Mips::BLTZC_MMR6);
829  else {
830  MI.setOpcode(Mips::BLTC_MMR6);
831  HasRs = true;
832  }
833 
834  if (HasRs)
835  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
836  Rs)));
837 
838  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
839  Rt)));
840 
842 
844 }
845 
846 template <typename InsnType>
848  uint64_t Address,
849  const void *Decoder) {
850  // We have:
851  // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
852  // Invalid if rt == 0
853  // BLEZC_MMR6 if rs == 0 && rt != 0
854  // BGEZC_MMR6 if rs == rt && rt != 0
855  // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
856 
857  InsnType Rt = fieldFromInstruction(insn, 21, 5);
858  InsnType Rs = fieldFromInstruction(insn, 16, 5);
859  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
860  bool HasRs = false;
861 
862  if (Rt == 0)
863  return MCDisassembler::Fail;
864  else if (Rs == 0)
865  MI.setOpcode(Mips::BLEZC_MMR6);
866  else if (Rs == Rt)
867  MI.setOpcode(Mips::BGEZC_MMR6);
868  else {
869  HasRs = true;
870  MI.setOpcode(Mips::BGEC_MMR6);
871  }
872 
873  if (HasRs)
874  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
875  Rs)));
876 
877  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
878  Rt)));
879 
881 
883 }
884 
885 template <typename InsnType>
886 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
887  uint64_t Address,
888  const void *Decoder) {
889  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
890  // (otherwise we would have matched the BLEZL instruction from the earlier
891  // ISA's instead).
892  //
893  // We have:
894  // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
895  // Invalid if rs == 0
896  // BLEZC if rs == 0 && rt != 0
897  // BGEZC if rs == rt && rt != 0
898  // BGEC if rs != rt && rs != 0 && rt != 0
899 
900  InsnType Rs = fieldFromInstruction(insn, 21, 5);
901  InsnType Rt = fieldFromInstruction(insn, 16, 5);
902  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
903  bool HasRs = false;
904 
905  if (Rt == 0)
906  return MCDisassembler::Fail;
907  else if (Rs == 0)
908  MI.setOpcode(Mips::BLEZC);
909  else if (Rs == Rt)
910  MI.setOpcode(Mips::BGEZC);
911  else {
912  HasRs = true;
913  MI.setOpcode(Mips::BGEC);
914  }
915 
916  if (HasRs)
917  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
918  Rs)));
919 
920  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
921  Rt)));
922 
924 
926 }
927 
928 template <typename InsnType>
929 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
930  uint64_t Address,
931  const void *Decoder) {
932  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
933  // (otherwise we would have matched the BGTZL instruction from the earlier
934  // ISA's instead).
935  //
936  // We have:
937  // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
938  // Invalid if rs == 0
939  // BGTZC if rs == 0 && rt != 0
940  // BLTZC if rs == rt && rt != 0
941  // BLTC if rs != rt && rs != 0 && rt != 0
942 
943  bool HasRs = false;
944 
945  InsnType Rs = fieldFromInstruction(insn, 21, 5);
946  InsnType Rt = fieldFromInstruction(insn, 16, 5);
947  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
948 
949  if (Rt == 0)
950  return MCDisassembler::Fail;
951  else if (Rs == 0)
952  MI.setOpcode(Mips::BGTZC);
953  else if (Rs == Rt)
954  MI.setOpcode(Mips::BLTZC);
955  else {
956  MI.setOpcode(Mips::BLTC);
957  HasRs = true;
958  }
959 
960  if (HasRs)
961  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
962  Rs)));
963 
964  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
965  Rt)));
966 
968 
970 }
971 
972 template <typename InsnType>
973 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
974  uint64_t Address,
975  const void *Decoder) {
976  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
977  // (otherwise we would have matched the BGTZ instruction from the earlier
978  // ISA's instead).
979  //
980  // We have:
981  // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
982  // BGTZ if rt == 0
983  // BGTZALC if rs == 0 && rt != 0
984  // BLTZALC if rs != 0 && rs == rt
985  // BLTUC if rs != 0 && rs != rt
986 
987  InsnType Rs = fieldFromInstruction(insn, 21, 5);
988  InsnType Rt = fieldFromInstruction(insn, 16, 5);
989  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
990  bool HasRs = false;
991  bool HasRt = false;
992 
993  if (Rt == 0) {
994  MI.setOpcode(Mips::BGTZ);
995  HasRs = true;
996  } else if (Rs == 0) {
997  MI.setOpcode(Mips::BGTZALC);
998  HasRt = true;
999  } else if (Rs == Rt) {
1000  MI.setOpcode(Mips::BLTZALC);
1001  HasRs = true;
1002  } else {
1003  MI.setOpcode(Mips::BLTUC);
1004  HasRs = true;
1005  HasRt = true;
1006  }
1007 
1008  if (HasRs)
1009  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1010  Rs)));
1011 
1012  if (HasRt)
1013  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1014  Rt)));
1015 
1017 
1018  return MCDisassembler::Success;
1019 }
1020 
1021 template <typename InsnType>
1022 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1023  uint64_t Address,
1024  const void *Decoder) {
1025  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1026  // (otherwise we would have matched the BLEZL instruction from the earlier
1027  // ISA's instead).
1028  //
1029  // We have:
1030  // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1031  // Invalid if rs == 0
1032  // BLEZALC if rs == 0 && rt != 0
1033  // BGEZALC if rs == rt && rt != 0
1034  // BGEUC if rs != rt && rs != 0 && rt != 0
1035 
1036  InsnType Rs = fieldFromInstruction(insn, 21, 5);
1037  InsnType Rt = fieldFromInstruction(insn, 16, 5);
1038  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1039  bool HasRs = false;
1040 
1041  if (Rt == 0)
1042  return MCDisassembler::Fail;
1043  else if (Rs == 0)
1044  MI.setOpcode(Mips::BLEZALC);
1045  else if (Rs == Rt)
1046  MI.setOpcode(Mips::BGEZALC);
1047  else {
1048  HasRs = true;
1049  MI.setOpcode(Mips::BGEUC);
1050  }
1051 
1052  if (HasRs)
1053  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1054  Rs)));
1055  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1056  Rt)));
1057 
1059 
1060  return MCDisassembler::Success;
1061 }
1062 
1063 // Override the generated disassembler to produce DEXT all the time. This is
1064 // for feature / behaviour parity with binutils.
1065 template <typename InsnType>
1066 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1067  const void *Decoder) {
1068  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1069  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1070  unsigned Size = 0;
1071  unsigned Pos = 0;
1072 
1073  switch (MI.getOpcode()) {
1074  case Mips::DEXT:
1075  Pos = Lsb;
1076  Size = Msbd + 1;
1077  break;
1078  case Mips::DEXTM:
1079  Pos = Lsb;
1080  Size = Msbd + 1 + 32;
1081  break;
1082  case Mips::DEXTU:
1083  Pos = Lsb + 32;
1084  Size = Msbd + 1;
1085  break;
1086  default:
1087  llvm_unreachable("Unknown DEXT instruction!");
1088  }
1089 
1090  MI.setOpcode(Mips::DEXT);
1091 
1092  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1093  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1094 
1095  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1096  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1098  MI.addOperand(MCOperand::createImm(Size));
1099 
1100  return MCDisassembler::Success;
1101 }
1102 
1103 // Override the generated disassembler to produce DINS all the time. This is
1104 // for feature / behaviour parity with binutils.
1105 template <typename InsnType>
1106 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1107  const void *Decoder) {
1108  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1109  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1110  unsigned Size = 0;
1111  unsigned Pos = 0;
1112 
1113  switch (MI.getOpcode()) {
1114  case Mips::DINS:
1115  Pos = Lsb;
1116  Size = Msbd + 1 - Pos;
1117  break;
1118  case Mips::DINSM:
1119  Pos = Lsb;
1120  Size = Msbd + 33 - Pos;
1121  break;
1122  case Mips::DINSU:
1123  Pos = Lsb + 32;
1124  // mbsd = pos + size - 33
1125  // mbsd - pos + 33 = size
1126  Size = Msbd + 33 - Pos;
1127  break;
1128  default:
1129  llvm_unreachable("Unknown DINS instruction!");
1130  }
1131 
1132  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1133  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1134 
1135  MI.setOpcode(Mips::DINS);
1136  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1137  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1139  MI.addOperand(MCOperand::createImm(Size));
1140 
1141  return MCDisassembler::Success;
1142 }
1143 
1144 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1145 template <typename InsnType>
1146 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1147  const void *Decoder) {
1148  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1149  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1150  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1151  Rt)));
1152  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1153  Rs)));
1154  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1155  Rt)));
1156  return MCDisassembler::Success;
1157 }
1158 
1159 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1160 /// according to the given endianness.
1162  uint64_t &Size, uint32_t &Insn,
1163  bool IsBigEndian) {
1164  // We want to read exactly 2 Bytes of data.
1165  if (Bytes.size() < 2) {
1166  Size = 0;
1167  return MCDisassembler::Fail;
1168  }
1169 
1170  if (IsBigEndian) {
1171  Insn = (Bytes[0] << 8) | Bytes[1];
1172  } else {
1173  Insn = (Bytes[1] << 8) | Bytes[0];
1174  }
1175 
1176  return MCDisassembler::Success;
1177 }
1178 
1179 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1180 /// according to the given endianness.
1182  uint64_t &Size, uint32_t &Insn,
1183  bool IsBigEndian, bool IsMicroMips) {
1184  // We want to read exactly 4 Bytes of data.
1185  if (Bytes.size() < 4) {
1186  Size = 0;
1187  return MCDisassembler::Fail;
1188  }
1189 
1190  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1191  // always precede the low 16 bits in the instruction stream (that is, they
1192  // are placed at lower addresses in the instruction stream).
1193  //
1194  // microMIPS byte ordering:
1195  // Big-endian: 0 | 1 | 2 | 3
1196  // Little-endian: 1 | 0 | 3 | 2
1197 
1198  if (IsBigEndian) {
1199  // Encoded as a big-endian 32-bit word in the stream.
1200  Insn =
1201  (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1202  } else {
1203  if (IsMicroMips) {
1204  Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1205  (Bytes[1] << 24);
1206  } else {
1207  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1208  (Bytes[3] << 24);
1209  }
1210  }
1211 
1212  return MCDisassembler::Success;
1213 }
1214 
1215 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1216  ArrayRef<uint8_t> Bytes,
1217  uint64_t Address,
1218  raw_ostream &VStream,
1219  raw_ostream &CStream) const {
1220  uint32_t Insn;
1221  DecodeStatus Result;
1222  Size = 0;
1223 
1224  if (IsMicroMips) {
1225  Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1226  if (Result == MCDisassembler::Fail)
1227  return MCDisassembler::Fail;
1228 
1229  if (hasMips32r6()) {
1230  LLVM_DEBUG(
1231  dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1232  // Calling the auto-generated decoder function for microMIPS32R6
1233  // 16-bit instructions.
1234  Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1235  Address, this, STI);
1236  if (Result != MCDisassembler::Fail) {
1237  Size = 2;
1238  return Result;
1239  }
1240  }
1241 
1242  LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1243  // Calling the auto-generated decoder function for microMIPS 16-bit
1244  // instructions.
1245  Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1246  this, STI);
1247  if (Result != MCDisassembler::Fail) {
1248  Size = 2;
1249  return Result;
1250  }
1251 
1252  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1253  if (Result == MCDisassembler::Fail)
1254  return MCDisassembler::Fail;
1255 
1256  if (hasMips32r6()) {
1257  LLVM_DEBUG(
1258  dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1259  // Calling the auto-generated decoder function.
1260  Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1261  this, STI);
1262  if (Result != MCDisassembler::Fail) {
1263  Size = 4;
1264  return Result;
1265  }
1266  }
1267 
1268  LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1269  // Calling the auto-generated decoder function.
1270  Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1271  this, STI);
1272  if (Result != MCDisassembler::Fail) {
1273  Size = 4;
1274  return Result;
1275  }
1276 
1277  if (isFP64()) {
1278  LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1279  Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1280  Address, this, STI);
1281  if (Result != MCDisassembler::Fail) {
1282  Size = 4;
1283  return Result;
1284  }
1285  }
1286 
1287  // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1288  // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1289  // could form a valid instruction. The two bytes we rejected as an
1290  // instruction could have actually beeen an inline constant pool that is
1291  // unconditionally branched over.
1292  Size = 2;
1293  return MCDisassembler::Fail;
1294  }
1295 
1296  // Attempt to read the instruction so that we can attempt to decode it. If
1297  // the buffer is not 4 bytes long, let the higher level logic figure out
1298  // what to do with a size of zero and MCDisassembler::Fail.
1299  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1300  if (Result == MCDisassembler::Fail)
1301  return MCDisassembler::Fail;
1302 
1303  // The only instruction size for standard encoded MIPS.
1304  Size = 4;
1305 
1306  if (hasCOP3()) {
1307  LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1308  Result =
1309  decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1310  if (Result != MCDisassembler::Fail)
1311  return Result;
1312  }
1313 
1314  if (hasMips32r6() && isGP64()) {
1315  LLVM_DEBUG(
1316  dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1317  Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1318  Address, this, STI);
1319  if (Result != MCDisassembler::Fail)
1320  return Result;
1321  }
1322 
1323  if (hasMips32r6() && isPTR64()) {
1324  LLVM_DEBUG(
1325  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1326  Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1327  Address, this, STI);
1328  if (Result != MCDisassembler::Fail)
1329  return Result;
1330  }
1331 
1332  if (hasMips32r6()) {
1333  LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1334  Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1335  Address, this, STI);
1336  if (Result != MCDisassembler::Fail)
1337  return Result;
1338  }
1339 
1340  if (hasMips2() && isPTR64()) {
1341  LLVM_DEBUG(
1342  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1343  Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1344  Address, this, STI);
1345  if (Result != MCDisassembler::Fail)
1346  return Result;
1347  }
1348 
1349  if (hasCnMips()) {
1350  LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1351  Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1352  Address, this, STI);
1353  if (Result != MCDisassembler::Fail)
1354  return Result;
1355  }
1356 
1357  if (isGP64()) {
1358  LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1359  Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1360  Address, this, STI);
1361  if (Result != MCDisassembler::Fail)
1362  return Result;
1363  }
1364 
1365  if (isFP64()) {
1366  LLVM_DEBUG(
1367  dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1368  Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1369  Address, this, STI);
1370  if (Result != MCDisassembler::Fail)
1371  return Result;
1372  }
1373 
1374  LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1375  // Calling the auto-generated decoder function.
1376  Result =
1377  decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1378  if (Result != MCDisassembler::Fail)
1379  return Result;
1380 
1381  return MCDisassembler::Fail;
1382 }
1383 
1385  unsigned RegNo,
1386  uint64_t Address,
1387  const void *Decoder) {
1388  return MCDisassembler::Fail;
1389 }
1390 
1392  unsigned RegNo,
1393  uint64_t Address,
1394  const void *Decoder) {
1395  if (RegNo > 31)
1396  return MCDisassembler::Fail;
1397 
1398  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1399  Inst.addOperand(MCOperand::createReg(Reg));
1400  return MCDisassembler::Success;
1401 }
1402 
1404  unsigned RegNo,
1405  uint64_t Address,
1406  const void *Decoder) {
1407  if (RegNo > 7)
1408  return MCDisassembler::Fail;
1409  unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1410  Inst.addOperand(MCOperand::createReg(Reg));
1411  return MCDisassembler::Success;
1412 }
1413 
1415  unsigned RegNo,
1416  uint64_t Address,
1417  const void *Decoder) {
1418  if (RegNo > 7)
1419  return MCDisassembler::Fail;
1420  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1421  Inst.addOperand(MCOperand::createReg(Reg));
1422  return MCDisassembler::Success;
1423 }
1424 
1426  unsigned RegNo,
1427  uint64_t Address,
1428  const void *Decoder) {
1429  if (RegNo > 7)
1430  return MCDisassembler::Fail;
1431  unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1432  Inst.addOperand(MCOperand::createReg(Reg));
1433  return MCDisassembler::Success;
1434 }
1435 
1437  unsigned RegNo,
1438  uint64_t Address,
1439  const void *Decoder) {
1440  if (RegNo > 31)
1441  return MCDisassembler::Fail;
1442  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1443  Inst.addOperand(MCOperand::createReg(Reg));
1444  return MCDisassembler::Success;
1445 }
1446 
1448  unsigned RegNo,
1449  uint64_t Address,
1450  const void *Decoder) {
1451  if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1452  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1453 
1454  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1455 }
1456 
1458  unsigned RegNo,
1459  uint64_t Address,
1460  const void *Decoder) {
1461  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1462 }
1463 
1465  unsigned RegNo,
1466  uint64_t Address,
1467  const void *Decoder) {
1468  if (RegNo > 31)
1469  return MCDisassembler::Fail;
1470 
1471  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1472  Inst.addOperand(MCOperand::createReg(Reg));
1473  return MCDisassembler::Success;
1474 }
1475 
1477  unsigned RegNo,
1478  uint64_t Address,
1479  const void *Decoder) {
1480  if (RegNo > 31)
1481  return MCDisassembler::Fail;
1482 
1483  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1484  Inst.addOperand(MCOperand::createReg(Reg));
1485  return MCDisassembler::Success;
1486 }
1487 
1489  unsigned RegNo,
1490  uint64_t Address,
1491  const void *Decoder) {
1492  if (RegNo > 31)
1493  return MCDisassembler::Fail;
1494  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1495  Inst.addOperand(MCOperand::createReg(Reg));
1496  return MCDisassembler::Success;
1497 }
1498 
1500  unsigned RegNo,
1501  uint64_t Address,
1502  const void *Decoder) {
1503  if (RegNo > 7)
1504  return MCDisassembler::Fail;
1505  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1506  Inst.addOperand(MCOperand::createReg(Reg));
1507  return MCDisassembler::Success;
1508 }
1509 
1510 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1511  uint64_t Address,
1512  const void *Decoder) {
1513  if (RegNo > 31)
1514  return MCDisassembler::Fail;
1515 
1516  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1517  Inst.addOperand(MCOperand::createReg(Reg));
1518  return MCDisassembler::Success;
1519 }
1520 
1522  unsigned Insn,
1523  uint64_t Address,
1524  const void *Decoder) {
1525  int Offset = SignExtend32<16>(Insn & 0xffff);
1526  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1527  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1528 
1529  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1530  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1531 
1532  if (Inst.getOpcode() == Mips::SC ||
1533  Inst.getOpcode() == Mips::SCD)
1534  Inst.addOperand(MCOperand::createReg(Reg));
1535 
1536  Inst.addOperand(MCOperand::createReg(Reg));
1537  Inst.addOperand(MCOperand::createReg(Base));
1538  Inst.addOperand(MCOperand::createImm(Offset));
1539 
1540  return MCDisassembler::Success;
1541 }
1542 
1544  unsigned Insn,
1545  uint64_t Address,
1546  const void *Decoder) {
1547  int Offset = SignExtend32<9>(Insn >> 7);
1548  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1549  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1550 
1551  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1552  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1553 
1554  if (Inst.getOpcode() == Mips::SCE)
1555  Inst.addOperand(MCOperand::createReg(Reg));
1556 
1557  Inst.addOperand(MCOperand::createReg(Reg));
1558  Inst.addOperand(MCOperand::createReg(Base));
1559  Inst.addOperand(MCOperand::createImm(Offset));
1560 
1561  return MCDisassembler::Success;
1562 }
1563 
1565  unsigned Insn,
1566  uint64_t Address,
1567  const void *Decoder) {
1568  int Offset = SignExtend32<16>(Insn & 0xffff);
1569  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1570  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1571 
1572  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1573  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1574 
1575  Inst.addOperand(MCOperand::createReg(Reg));
1576  Inst.addOperand(MCOperand::createReg(Base));
1577  Inst.addOperand(MCOperand::createImm(Offset));
1578 
1579  return MCDisassembler::Success;
1580 }
1581 
1583  unsigned Insn,
1584  uint64_t Address,
1585  const void *Decoder) {
1586  int Offset = SignExtend32<16>(Insn & 0xffff);
1587  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1588  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1589 
1590  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1591 
1592  Inst.addOperand(MCOperand::createReg(Base));
1593  Inst.addOperand(MCOperand::createImm(Offset));
1594  Inst.addOperand(MCOperand::createImm(Hint));
1595 
1596  return MCDisassembler::Success;
1597 }
1598 
1600  unsigned Insn,
1601  uint64_t Address,
1602  const void *Decoder) {
1603  int Offset = SignExtend32<12>(Insn & 0xfff);
1604  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1605  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1606 
1607  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1608 
1609  Inst.addOperand(MCOperand::createReg(Base));
1610  Inst.addOperand(MCOperand::createImm(Offset));
1611  Inst.addOperand(MCOperand::createImm(Hint));
1612 
1613  return MCDisassembler::Success;
1614 }
1615 
1617  unsigned Insn,
1618  uint64_t Address,
1619  const void *Decoder) {
1620  int Offset = SignExtend32<9>(Insn & 0x1ff);
1621  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1622  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1623 
1624  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1625 
1626  Inst.addOperand(MCOperand::createReg(Base));
1627  Inst.addOperand(MCOperand::createImm(Offset));
1628  Inst.addOperand(MCOperand::createImm(Hint));
1629 
1630  return MCDisassembler::Success;
1631 }
1632 
1634  unsigned Insn,
1635  uint64_t Address,
1636  const void *Decoder) {
1637  int Offset = SignExtend32<9>(Insn >> 7);
1638  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1639  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1640 
1641  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1642 
1643  Inst.addOperand(MCOperand::createReg(Base));
1644  Inst.addOperand(MCOperand::createImm(Offset));
1645  Inst.addOperand(MCOperand::createImm(Hint));
1646 
1647  return MCDisassembler::Success;
1648 }
1649 
1651  unsigned Insn,
1652  uint64_t Address,
1653  const void *Decoder) {
1654  int Offset = SignExtend32<16>(Insn & 0xffff);
1655  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1656 
1657  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1658 
1659  Inst.addOperand(MCOperand::createReg(Base));
1660  Inst.addOperand(MCOperand::createImm(Offset));
1661 
1662  return MCDisassembler::Success;
1663 }
1664 
1665 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1666  uint64_t Address, const void *Decoder) {
1667  int Offset = SignExtend32<16>(Insn & 0xffff);
1668  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1669 
1670  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1671 
1672  Inst.addOperand(MCOperand::createReg(Base));
1673  Inst.addOperand(MCOperand::createImm(Offset));
1674 
1675  return MCDisassembler::Success;
1676 }
1677 
1679  unsigned Insn,
1680  uint64_t Address,
1681  const void *Decoder) {
1682  int Immediate = SignExtend32<16>(Insn & 0xffff);
1683  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1684 
1685  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1686 
1687  Inst.addOperand(MCOperand::createReg(Base));
1688  Inst.addOperand(MCOperand::createImm(Immediate));
1689 
1690  return MCDisassembler::Success;
1691 }
1692 
1693 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1694  uint64_t Address, const void *Decoder) {
1695  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1696  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1697  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1698 
1699  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1700  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1701 
1702  Inst.addOperand(MCOperand::createReg(Reg));
1703  Inst.addOperand(MCOperand::createReg(Base));
1704 
1705  // The immediate field of an LD/ST instruction is scaled which means it must
1706  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1707  // data format.
1708  // .b - 1 byte
1709  // .h - 2 bytes
1710  // .w - 4 bytes
1711  // .d - 8 bytes
1712  switch(Inst.getOpcode())
1713  {
1714  default:
1715  assert(false && "Unexpected instruction");
1716  return MCDisassembler::Fail;
1717  break;
1718  case Mips::LD_B:
1719  case Mips::ST_B:
1720  Inst.addOperand(MCOperand::createImm(Offset));
1721  break;
1722  case Mips::LD_H:
1723  case Mips::ST_H:
1724  Inst.addOperand(MCOperand::createImm(Offset * 2));
1725  break;
1726  case Mips::LD_W:
1727  case Mips::ST_W:
1728  Inst.addOperand(MCOperand::createImm(Offset * 4));
1729  break;
1730  case Mips::LD_D:
1731  case Mips::ST_D:
1732  Inst.addOperand(MCOperand::createImm(Offset * 8));
1733  break;
1734  }
1735 
1736  return MCDisassembler::Success;
1737 }
1738 
1740  unsigned Insn,
1741  uint64_t Address,
1742  const void *Decoder) {
1743  unsigned Offset = Insn & 0xf;
1744  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1745  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1746 
1747  switch (Inst.getOpcode()) {
1748  case Mips::LBU16_MM:
1749  case Mips::LHU16_MM:
1750  case Mips::LW16_MM:
1751  if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1753  return MCDisassembler::Fail;
1754  break;
1755  case Mips::SB16_MM:
1756  case Mips::SB16_MMR6:
1757  case Mips::SH16_MM:
1758  case Mips::SH16_MMR6:
1759  case Mips::SW16_MM:
1760  case Mips::SW16_MMR6:
1761  if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1763  return MCDisassembler::Fail;
1764  break;
1765  }
1766 
1767  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1769  return MCDisassembler::Fail;
1770 
1771  switch (Inst.getOpcode()) {
1772  case Mips::LBU16_MM:
1773  if (Offset == 0xf)
1774  Inst.addOperand(MCOperand::createImm(-1));
1775  else
1776  Inst.addOperand(MCOperand::createImm(Offset));
1777  break;
1778  case Mips::SB16_MM:
1779  case Mips::SB16_MMR6:
1780  Inst.addOperand(MCOperand::createImm(Offset));
1781  break;
1782  case Mips::LHU16_MM:
1783  case Mips::SH16_MM:
1784  case Mips::SH16_MMR6:
1785  Inst.addOperand(MCOperand::createImm(Offset << 1));
1786  break;
1787  case Mips::LW16_MM:
1788  case Mips::SW16_MM:
1789  case Mips::SW16_MMR6:
1790  Inst.addOperand(MCOperand::createImm(Offset << 2));
1791  break;
1792  }
1793 
1794  return MCDisassembler::Success;
1795 }
1796 
1798  unsigned Insn,
1799  uint64_t Address,
1800  const void *Decoder) {
1801  unsigned Offset = Insn & 0x1F;
1802  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1803 
1804  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1805 
1806  Inst.addOperand(MCOperand::createReg(Reg));
1807  Inst.addOperand(MCOperand::createReg(Mips::SP));
1808  Inst.addOperand(MCOperand::createImm(Offset << 2));
1809 
1810  return MCDisassembler::Success;
1811 }
1812 
1814  unsigned Insn,
1815  uint64_t Address,
1816  const void *Decoder) {
1817  unsigned Offset = Insn & 0x7F;
1818  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1819 
1820  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1821 
1822  Inst.addOperand(MCOperand::createReg(Reg));
1823  Inst.addOperand(MCOperand::createReg(Mips::GP));
1824  Inst.addOperand(MCOperand::createImm(Offset << 2));
1825 
1826  return MCDisassembler::Success;
1827 }
1828 
1830  unsigned Insn,
1831  uint64_t Address,
1832  const void *Decoder) {
1833  int Offset;
1834  switch (Inst.getOpcode()) {
1835  case Mips::LWM16_MMR6:
1836  case Mips::SWM16_MMR6:
1837  Offset = fieldFromInstruction(Insn, 4, 4);
1838  break;
1839  default:
1840  Offset = SignExtend32<4>(Insn & 0xf);
1841  break;
1842  }
1843 
1844  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1846  return MCDisassembler::Fail;
1847 
1848  Inst.addOperand(MCOperand::createReg(Mips::SP));
1849  Inst.addOperand(MCOperand::createImm(Offset << 2));
1850 
1851  return MCDisassembler::Success;
1852 }
1853 
1855  unsigned Insn,
1856  uint64_t Address,
1857  const void *Decoder) {
1858  int Offset = SignExtend32<9>(Insn & 0x1ff);
1859  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1860  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1861 
1862  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1863  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1864 
1865  if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1866  Inst.addOperand(MCOperand::createReg(Reg));
1867 
1868  Inst.addOperand(MCOperand::createReg(Reg));
1869  Inst.addOperand(MCOperand::createReg(Base));
1870  Inst.addOperand(MCOperand::createImm(Offset));
1871 
1872  return MCDisassembler::Success;
1873 }
1874 
1876  unsigned Insn,
1877  uint64_t Address,
1878  const void *Decoder) {
1879  int Offset = SignExtend32<12>(Insn & 0x0fff);
1880  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1881  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1882 
1883  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1884  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1885 
1886  switch (Inst.getOpcode()) {
1887  case Mips::SWM32_MM:
1888  case Mips::LWM32_MM:
1889  if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1891  return MCDisassembler::Fail;
1892  Inst.addOperand(MCOperand::createReg(Base));
1893  Inst.addOperand(MCOperand::createImm(Offset));
1894  break;
1895  case Mips::SC_MM:
1896  Inst.addOperand(MCOperand::createReg(Reg));
1898  default:
1899  Inst.addOperand(MCOperand::createReg(Reg));
1900  if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1901  Inst.addOperand(MCOperand::createReg(Reg+1));
1902 
1903  Inst.addOperand(MCOperand::createReg(Base));
1904  Inst.addOperand(MCOperand::createImm(Offset));
1905  }
1906 
1907  return MCDisassembler::Success;
1908 }
1909 
1911  unsigned Insn,
1912  uint64_t Address,
1913  const void *Decoder) {
1914  int Offset = SignExtend32<16>(Insn & 0xffff);
1915  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1916  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1917 
1918  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1919  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1920 
1921  Inst.addOperand(MCOperand::createReg(Reg));
1922  Inst.addOperand(MCOperand::createReg(Base));
1923  Inst.addOperand(MCOperand::createImm(Offset));
1924 
1925  return MCDisassembler::Success;
1926 }
1927 
1929  unsigned Insn,
1930  uint64_t Address,
1931  const void *Decoder) {
1932  int Offset = SignExtend32<16>(Insn & 0xffff);
1933  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1934  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1935 
1936  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1937  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1938 
1939  Inst.addOperand(MCOperand::createReg(Reg));
1940  Inst.addOperand(MCOperand::createReg(Base));
1941  Inst.addOperand(MCOperand::createImm(Offset));
1942 
1943  return MCDisassembler::Success;
1944 }
1945 
1946 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1947  uint64_t Address, const void *Decoder) {
1948  // This function is the same as DecodeFMem but with the Reg and Base fields
1949  // swapped according to microMIPS spec.
1950  int Offset = SignExtend32<16>(Insn & 0xffff);
1951  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1952  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1953 
1954  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1955  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1956 
1957  Inst.addOperand(MCOperand::createReg(Reg));
1958  Inst.addOperand(MCOperand::createReg(Base));
1959  Inst.addOperand(MCOperand::createImm(Offset));
1960 
1961  return MCDisassembler::Success;
1962 }
1963 
1965  unsigned Insn,
1966  uint64_t Address,
1967  const void *Decoder) {
1968  int Offset = SignExtend32<16>(Insn & 0xffff);
1969  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1970  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1971 
1972  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1973  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1974 
1975  Inst.addOperand(MCOperand::createReg(Reg));
1976  Inst.addOperand(MCOperand::createReg(Base));
1977  Inst.addOperand(MCOperand::createImm(Offset));
1978 
1979  return MCDisassembler::Success;
1980 }
1981 
1983  unsigned Insn,
1984  uint64_t Address,
1985  const void *Decoder) {
1986  int Offset = SignExtend32<16>(Insn & 0xffff);
1987  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1988  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1989 
1990  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1991  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1992 
1993  Inst.addOperand(MCOperand::createReg(Reg));
1994  Inst.addOperand(MCOperand::createReg(Base));
1995  Inst.addOperand(MCOperand::createImm(Offset));
1996 
1997  return MCDisassembler::Success;
1998 }
1999 
2001  unsigned Insn,
2002  uint64_t Address,
2003  const void *Decoder) {
2004  int Offset = SignExtend32<11>(Insn & 0x07ff);
2005  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2006  unsigned Base = fieldFromInstruction(Insn, 11, 5);
2007 
2008  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2009  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2010 
2011  Inst.addOperand(MCOperand::createReg(Reg));
2012  Inst.addOperand(MCOperand::createReg(Base));
2013  Inst.addOperand(MCOperand::createImm(Offset));
2014 
2015  return MCDisassembler::Success;
2016 }
2017 
2018 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2019  uint64_t Address, const void *Decoder) {
2020  int Offset = SignExtend32<11>(Insn & 0x07ff);
2021  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2022  unsigned Base = fieldFromInstruction(Insn, 16, 5);
2023 
2024  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2025  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2026 
2027  Inst.addOperand(MCOperand::createReg(Reg));
2028  Inst.addOperand(MCOperand::createReg(Base));
2029  Inst.addOperand(MCOperand::createImm(Offset));
2030 
2031  return MCDisassembler::Success;
2032 }
2033 
2035  unsigned Insn,
2036  uint64_t Address,
2037  const void *Decoder) {
2038  int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2039  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2040  unsigned Base = fieldFromInstruction(Insn, 21, 5);
2041 
2042  Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2043  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2044 
2045  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2046  Inst.addOperand(MCOperand::createReg(Rt));
2047  }
2048 
2049  Inst.addOperand(MCOperand::createReg(Rt));
2050  Inst.addOperand(MCOperand::createReg(Base));
2051  Inst.addOperand(MCOperand::createImm(Offset));
2052 
2053  return MCDisassembler::Success;
2054 }
2055 
2057  unsigned RegNo,
2058  uint64_t Address,
2059  const void *Decoder) {
2060  // Currently only hardware register 29 is supported.
2061  if (RegNo != 29)
2062  return MCDisassembler::Fail;
2063  Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2064  return MCDisassembler::Success;
2065 }
2066 
2068  unsigned RegNo,
2069  uint64_t Address,
2070  const void *Decoder) {
2071  if (RegNo > 30 || RegNo %2)
2072  return MCDisassembler::Fail;
2073 
2074  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2075  Inst.addOperand(MCOperand::createReg(Reg));
2076  return MCDisassembler::Success;
2077 }
2078 
2080  unsigned RegNo,
2081  uint64_t Address,
2082  const void *Decoder) {
2083  if (RegNo >= 4)
2084  return MCDisassembler::Fail;
2085 
2086  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2087  Inst.addOperand(MCOperand::createReg(Reg));
2088  return MCDisassembler::Success;
2089 }
2090 
2092  unsigned RegNo,
2093  uint64_t Address,
2094  const void *Decoder) {
2095  if (RegNo >= 4)
2096  return MCDisassembler::Fail;
2097 
2098  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2099  Inst.addOperand(MCOperand::createReg(Reg));
2100  return MCDisassembler::Success;
2101 }
2102 
2104  unsigned RegNo,
2105  uint64_t Address,
2106  const void *Decoder) {
2107  if (RegNo >= 4)
2108  return MCDisassembler::Fail;
2109 
2110  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2111  Inst.addOperand(MCOperand::createReg(Reg));
2112  return MCDisassembler::Success;
2113 }
2114 
2116  unsigned RegNo,
2117  uint64_t Address,
2118  const void *Decoder) {
2119  if (RegNo > 31)
2120  return MCDisassembler::Fail;
2121 
2122  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2123  Inst.addOperand(MCOperand::createReg(Reg));
2124  return MCDisassembler::Success;
2125 }
2126 
2128  unsigned RegNo,
2129  uint64_t Address,
2130  const void *Decoder) {
2131  if (RegNo > 31)
2132  return MCDisassembler::Fail;
2133 
2134  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2135  Inst.addOperand(MCOperand::createReg(Reg));
2136  return MCDisassembler::Success;
2137 }
2138 
2140  unsigned RegNo,
2141  uint64_t Address,
2142  const void *Decoder) {
2143  if (RegNo > 31)
2144  return MCDisassembler::Fail;
2145 
2146  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2147  Inst.addOperand(MCOperand::createReg(Reg));
2148  return MCDisassembler::Success;
2149 }
2150 
2152  unsigned RegNo,
2153  uint64_t Address,
2154  const void *Decoder) {
2155  if (RegNo > 31)
2156  return MCDisassembler::Fail;
2157 
2158  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2159  Inst.addOperand(MCOperand::createReg(Reg));
2160  return MCDisassembler::Success;
2161 }
2162 
2164  unsigned RegNo,
2165  uint64_t Address,
2166  const void *Decoder) {
2167  if (RegNo > 7)
2168  return MCDisassembler::Fail;
2169 
2170  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2171  Inst.addOperand(MCOperand::createReg(Reg));
2172  return MCDisassembler::Success;
2173 }
2174 
2176  unsigned RegNo,
2177  uint64_t Address,
2178  const void *Decoder) {
2179  if (RegNo > 31)
2180  return MCDisassembler::Fail;
2181 
2182  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2183  Inst.addOperand(MCOperand::createReg(Reg));
2184  return MCDisassembler::Success;
2185 }
2186 
2188  unsigned RegNo,
2189  uint64_t Address,
2190  const void *Decoder) {
2191  if (RegNo > 31)
2192  return MCDisassembler::Fail;
2193 
2194  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2195  Inst.addOperand(MCOperand::createReg(Reg));
2196  return MCDisassembler::Success;
2197 }
2198 
2200  unsigned Offset,
2201  uint64_t Address,
2202  const void *Decoder) {
2203  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2204  Inst.addOperand(MCOperand::createImm(BranchOffset));
2205  return MCDisassembler::Success;
2206 }
2207 
2209  unsigned Offset,
2210  uint64_t Address,
2211  const void *Decoder) {
2212  int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2213  Inst.addOperand(MCOperand::createImm(BranchOffset));
2214  return MCDisassembler::Success;
2215 }
2216 
2218  unsigned Insn,
2219  uint64_t Address,
2220  const void *Decoder) {
2221  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2222  Inst.addOperand(MCOperand::createImm(JumpOffset));
2223  return MCDisassembler::Success;
2224 }
2225 
2227  unsigned Offset,
2228  uint64_t Address,
2229  const void *Decoder) {
2230  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2231 
2232  Inst.addOperand(MCOperand::createImm(BranchOffset));
2233  return MCDisassembler::Success;
2234 }
2235 
2237  unsigned Offset,
2238  uint64_t Address,
2239  const void *Decoder) {
2240  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2241 
2242  Inst.addOperand(MCOperand::createImm(BranchOffset));
2243  return MCDisassembler::Success;
2244 }
2245 
2247  unsigned Offset,
2248  uint64_t Address,
2249  const void *Decoder) {
2250  int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2251 
2252  Inst.addOperand(MCOperand::createImm(BranchOffset));
2253  return MCDisassembler::Success;
2254 }
2255 
2257  unsigned Offset,
2258  uint64_t Address,
2259  const void *Decoder) {
2260  int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2261  Inst.addOperand(MCOperand::createImm(BranchOffset));
2262  return MCDisassembler::Success;
2263 }
2264 
2266  unsigned Offset,
2267  uint64_t Address,
2268  const void *Decoder) {
2269  int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2270  Inst.addOperand(MCOperand::createImm(BranchOffset));
2271  return MCDisassembler::Success;
2272 }
2273 
2275  unsigned Offset,
2276  uint64_t Address,
2277  const void *Decoder) {
2278  int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2279  Inst.addOperand(MCOperand::createImm(BranchOffset));
2280  return MCDisassembler::Success;
2281 }
2282 
2284  unsigned Offset,
2285  uint64_t Address,
2286  const void *Decoder) {
2287  int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2288 
2289  Inst.addOperand(MCOperand::createImm(BranchOffset));
2290  return MCDisassembler::Success;
2291 }
2292 
2294  unsigned Insn,
2295  uint64_t Address,
2296  const void *Decoder) {
2297  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2298  Inst.addOperand(MCOperand::createImm(JumpOffset));
2299  return MCDisassembler::Success;
2300 }
2301 
2303  unsigned Value,
2304  uint64_t Address,
2305  const void *Decoder) {
2306  if (Value == 0)
2308  else if (Value == 0x7)
2309  Inst.addOperand(MCOperand::createImm(-1));
2310  else
2311  Inst.addOperand(MCOperand::createImm(Value << 2));
2312  return MCDisassembler::Success;
2313 }
2314 
2316  unsigned Value,
2317  uint64_t Address,
2318  const void *Decoder) {
2319  if (Value == 0x7F)
2320  Inst.addOperand(MCOperand::createImm(-1));
2321  else
2322  Inst.addOperand(MCOperand::createImm(Value));
2323  return MCDisassembler::Success;
2324 }
2325 
2327  unsigned Value,
2328  uint64_t Address,
2329  const void *Decoder) {
2330  Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2331  return MCDisassembler::Success;
2332 }
2333 
2334 template <unsigned Bits, int Offset, int Scale>
2335 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2336  uint64_t Address,
2337  const void *Decoder) {
2338  Value &= ((1 << Bits) - 1);
2339  Value *= Scale;
2340  Inst.addOperand(MCOperand::createImm(Value + Offset));
2341  return MCDisassembler::Success;
2342 }
2343 
2344 template <unsigned Bits, int Offset, int ScaleBy>
2345 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2346  uint64_t Address,
2347  const void *Decoder) {
2348  int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2349  Inst.addOperand(MCOperand::createImm(Imm + Offset));
2350  return MCDisassembler::Success;
2351 }
2352 
2354  unsigned Insn,
2355  uint64_t Address,
2356  const void *Decoder) {
2357  // First we need to grab the pos(lsb) from MCInst.
2358  // This function only handles the 32 bit variants of ins, as dins
2359  // variants are handled differently.
2360  int Pos = Inst.getOperand(2).getImm();
2361  int Size = (int) Insn - Pos + 1;
2362  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2363  return MCDisassembler::Success;
2364 }
2365 
2366 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2367  uint64_t Address, const void *Decoder) {
2368  Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2369  return MCDisassembler::Success;
2370 }
2371 
2372 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2373  uint64_t Address, const void *Decoder) {
2374  Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2375  return MCDisassembler::Success;
2376 }
2377 
2378 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2379  uint64_t Address, const void *Decoder) {
2380  int32_t DecodedValue;
2381  switch (Insn) {
2382  case 0: DecodedValue = 256; break;
2383  case 1: DecodedValue = 257; break;
2384  case 510: DecodedValue = -258; break;
2385  case 511: DecodedValue = -257; break;
2386  default: DecodedValue = SignExtend32<9>(Insn); break;
2387  }
2388  Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2389  return MCDisassembler::Success;
2390 }
2391 
2392 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2393  uint64_t Address, const void *Decoder) {
2394  // Insn must be >= 0, since it is unsigned that condition is always true.
2395  assert(Insn < 16);
2396  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2397  255, 32768, 65535};
2398  Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2399  return MCDisassembler::Success;
2400 }
2401 
2403  unsigned Insn,
2404  uint64_t Address,
2405  const void *Decoder) {
2406  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2407  Mips::S6, Mips::S7, Mips::FP};
2408  unsigned RegNum;
2409 
2410  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2411 
2412  // Empty register lists are not allowed.
2413  if (RegLst == 0)
2414  return MCDisassembler::Fail;
2415 
2416  RegNum = RegLst & 0xf;
2417 
2418  // RegLst values 10-15, and 26-31 are reserved.
2419  if (RegNum > 9)
2420  return MCDisassembler::Fail;
2421 
2422  for (unsigned i = 0; i < RegNum; i++)
2423  Inst.addOperand(MCOperand::createReg(Regs[i]));
2424 
2425  if (RegLst & 0x10)
2427 
2428  return MCDisassembler::Success;
2429 }
2430 
2431 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2432  uint64_t Address,
2433  const void *Decoder) {
2434  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2435  unsigned RegLst;
2436  switch(Inst.getOpcode()) {
2437  default:
2438  RegLst = fieldFromInstruction(Insn, 4, 2);
2439  break;
2440  case Mips::LWM16_MMR6:
2441  case Mips::SWM16_MMR6:
2442  RegLst = fieldFromInstruction(Insn, 8, 2);
2443  break;
2444  }
2445  unsigned RegNum = RegLst & 0x3;
2446 
2447  for (unsigned i = 0; i <= RegNum; i++)
2448  Inst.addOperand(MCOperand::createReg(Regs[i]));
2449 
2451 
2452  return MCDisassembler::Success;
2453 }
2454 
2455 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2456  uint64_t Address,
2457  const void *Decoder) {
2458  unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2459  if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2461  return MCDisassembler::Fail;
2462 
2463  unsigned RegRs;
2464  if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2465  RegRs = fieldFromInstruction(Insn, 0, 2) |
2466  (fieldFromInstruction(Insn, 3, 1) << 2);
2467  else
2468  RegRs = fieldFromInstruction(Insn, 1, 3);
2469  if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2471  return MCDisassembler::Fail;
2472 
2473  unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2474  if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2476  return MCDisassembler::Fail;
2477 
2478  return MCDisassembler::Success;
2479 }
2480 
2481 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2482  uint64_t Address, const void *Decoder) {
2483  switch (RegPair) {
2484  default:
2485  return MCDisassembler::Fail;
2486  case 0:
2487  Inst.addOperand(MCOperand::createReg(Mips::A1));
2488  Inst.addOperand(MCOperand::createReg(Mips::A2));
2489  break;
2490  case 1:
2491  Inst.addOperand(MCOperand::createReg(Mips::A1));
2492  Inst.addOperand(MCOperand::createReg(Mips::A3));
2493  break;
2494  case 2:
2495  Inst.addOperand(MCOperand::createReg(Mips::A2));
2496  Inst.addOperand(MCOperand::createReg(Mips::A3));
2497  break;
2498  case 3:
2499  Inst.addOperand(MCOperand::createReg(Mips::A0));
2500  Inst.addOperand(MCOperand::createReg(Mips::S5));
2501  break;
2502  case 4:
2503  Inst.addOperand(MCOperand::createReg(Mips::A0));
2504  Inst.addOperand(MCOperand::createReg(Mips::S6));
2505  break;
2506  case 5:
2507  Inst.addOperand(MCOperand::createReg(Mips::A0));
2508  Inst.addOperand(MCOperand::createReg(Mips::A1));
2509  break;
2510  case 6:
2511  Inst.addOperand(MCOperand::createReg(Mips::A0));
2512  Inst.addOperand(MCOperand::createReg(Mips::A2));
2513  break;
2514  case 7:
2515  Inst.addOperand(MCOperand::createReg(Mips::A0));
2516  Inst.addOperand(MCOperand::createReg(Mips::A3));
2517  break;
2518  }
2519 
2520  return MCDisassembler::Success;
2521 }
2522 
2523 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2524  uint64_t Address, const void *Decoder) {
2525  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2526  return MCDisassembler::Success;
2527 }
2528 
2529 template <typename InsnType>
2531  uint64_t Address,
2532  const void *Decoder) {
2533  // We have:
2534  // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2535  // Invalid if rt == 0
2536  // BGTZALC_MMR6 if rs == 0 && rt != 0
2537  // BLTZALC_MMR6 if rs != 0 && rs == rt
2538  // BLTUC_MMR6 if rs != 0 && rs != rt
2539 
2540  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2541  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2542  InsnType Imm = 0;
2543  bool HasRs = false;
2544  bool HasRt = false;
2545 
2546  if (Rt == 0)
2547  return MCDisassembler::Fail;
2548  else if (Rs == 0) {
2549  MI.setOpcode(Mips::BGTZALC_MMR6);
2550  HasRt = true;
2551  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2552  }
2553  else if (Rs == Rt) {
2554  MI.setOpcode(Mips::BLTZALC_MMR6);
2555  HasRs = true;
2556  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2557  }
2558  else {
2559  MI.setOpcode(Mips::BLTUC_MMR6);
2560  HasRs = true;
2561  HasRt = true;
2562  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2563  }
2564 
2565  if (HasRs)
2566  MI.addOperand(
2567  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2568 
2569  if (HasRt)
2570  MI.addOperand(
2571  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2572 
2574 
2575  return MCDisassembler::Success;
2576 }
2577 
2578 template <typename InsnType>
2580  uint64_t Address,
2581  const void *Decoder) {
2582  // We have:
2583  // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2584  // Invalid if rt == 0
2585  // BLEZALC_MMR6 if rs == 0 && rt != 0
2586  // BGEZALC_MMR6 if rs == rt && rt != 0
2587  // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2588 
2589  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2590  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2591  InsnType Imm = 0;
2592  bool HasRs = false;
2593 
2594  if (Rt == 0)
2595  return MCDisassembler::Fail;
2596  else if (Rs == 0) {
2597  MI.setOpcode(Mips::BLEZALC_MMR6);
2598  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2599  }
2600  else if (Rs == Rt) {
2601  MI.setOpcode(Mips::BGEZALC_MMR6);
2602  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2603  }
2604  else {
2605  HasRs = true;
2606  MI.setOpcode(Mips::BGEUC_MMR6);
2607  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2608  }
2609 
2610  if (HasRs)
2611  MI.addOperand(
2612  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2613  MI.addOperand(
2614  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2615 
2617 
2618  return MCDisassembler::Success;
2619 }
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn&#39;t handle.
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned Reg
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Target & getTheMipselTarget()
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
SI optimize exec mask operations pre RA
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
const FeatureBitset & getFeatureBits() const
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:62
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Target & getTheMips64Target()
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int64_t getImm() const
Definition: MCInst.h:75
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Target & getTheMips64elTarget()
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
void setOpcode(unsigned Op)
Definition: MCInst.h:170
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness...
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheMipsTarget()
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:748
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:72
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Definition: MCInst.h:171
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_DEBUG(X)
Definition: Debug.h:122
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)