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MipsDisassembler.cpp
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1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Mips.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/Debug.h"
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mips-disassembler"
35 
37 
38 namespace {
39 
40 class MipsDisassembler : public MCDisassembler {
41  bool IsMicroMips;
42  bool IsBigEndian;
43 
44 public:
45  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46  : MCDisassembler(STI, Ctx),
47  IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
48  IsBigEndian(IsBigEndian) {}
49 
50  bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52  bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
53 
54  bool hasMips32r6() const {
55  return STI.getFeatureBits()[Mips::FeatureMips32r6];
56  }
57 
58  bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
59 
60  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
61 
62  bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
63 
64  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
65 
66  bool hasCOP3() const {
67  // Only present in MIPS-I and MIPS-II
68  return !hasMips32() && !hasMips3();
69  }
70 
71  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
72  ArrayRef<uint8_t> Bytes, uint64_t Address,
73  raw_ostream &VStream,
74  raw_ostream &CStream) const override;
75 };
76 
77 } // end anonymous namespace
78 
79 // Forward declare these because the autogenerated code will reference them.
80 // Definitions are further down.
82  unsigned RegNo,
83  uint64_t Address,
84  const void *Decoder);
85 
87  unsigned RegNo,
88  uint64_t Address,
89  const void *Decoder);
90 
92  unsigned RegNo,
93  uint64_t Address,
94  const void *Decoder);
95 
97  unsigned RegNo,
98  uint64_t Address,
99  const void *Decoder);
100 
102  unsigned RegNo,
103  uint64_t Address,
104  const void *Decoder);
105 
107  unsigned RegNo,
108  uint64_t Address,
109  const void *Decoder);
110 
112  unsigned Insn,
113  uint64_t Address,
114  const void *Decoder);
115 
117  unsigned RegNo,
118  uint64_t Address,
119  const void *Decoder);
120 
122  unsigned RegNo,
123  uint64_t Address,
124  const void *Decoder);
125 
127  unsigned RegNo,
128  uint64_t Address,
129  const void *Decoder);
130 
132  unsigned RegNo,
133  uint64_t Address,
134  const void *Decoder);
135 
137  unsigned RegNo,
138  uint64_t Address,
139  const void *Decoder);
140 
141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
142  uint64_t Address,
143  const void *Decoder);
144 
146  unsigned Insn,
147  uint64_t Address,
148  const void *Decoder);
149 
151  unsigned RegNo,
152  uint64_t Address,
153  const void *Decoder);
154 
156  unsigned RegNo,
157  uint64_t Address,
158  const void *Decoder);
159 
161  unsigned RegNo,
162  uint64_t Address,
163  const void *Decoder);
164 
166  unsigned RegNo,
167  uint64_t Address,
168  const void *Decoder);
169 
171  unsigned RegNo,
172  uint64_t Address,
173  const void *Decoder);
174 
176  unsigned RegNo,
177  uint64_t Address,
178  const void *Decoder);
179 
181  unsigned RegNo,
182  uint64_t Address,
183  const void *Decoder);
184 
186  unsigned RegNo,
187  uint64_t Address,
188  const void *Decoder);
189 
191  unsigned RegNo,
192  uint64_t Address,
193  const void *Decoder);
194 
196  unsigned RegNo,
197  uint64_t Address,
198  const void *Decoder);
199 
201  unsigned RegNo,
202  uint64_t Address,
203  const void *Decoder);
204 
206  unsigned Offset,
207  uint64_t Address,
208  const void *Decoder);
209 
211  unsigned Offset,
212  uint64_t Address,
213  const void *Decoder);
214 
216  unsigned Insn,
217  uint64_t Address,
218  const void *Decoder);
219 
221  unsigned Offset,
222  uint64_t Address,
223  const void *Decoder);
224 
226  unsigned Offset,
227  uint64_t Address,
228  const void *Decoder);
229 
231  unsigned Offset,
232  uint64_t Address,
233  const void *Decoder);
234 
235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
236 // shifted left by 1 bit.
238  unsigned Offset,
239  uint64_t Address,
240  const void *Decoder);
241 
242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
243 // shifted left by 1 bit.
245  unsigned Offset,
246  uint64_t Address,
247  const void *Decoder);
248 
249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
250 // shifted left by 1 bit.
252  unsigned Offset,
253  uint64_t Address,
254  const void *Decoder);
255 
256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
257 // shifted left by 1 bit.
259  unsigned Offset,
260  uint64_t Address,
261  const void *Decoder);
262 
263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
264 // shifted left by 1 bit.
266  unsigned Insn,
267  uint64_t Address,
268  const void *Decoder);
269 
270 static DecodeStatus DecodeMem(MCInst &Inst,
271  unsigned Insn,
272  uint64_t Address,
273  const void *Decoder);
274 
275 static DecodeStatus DecodeMemEVA(MCInst &Inst,
276  unsigned Insn,
277  uint64_t Address,
278  const void *Decoder);
279 
281  unsigned Insn,
282  uint64_t Address,
283  const void *Decoder);
284 
285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
286  const void *Decoder);
287 
289  unsigned Insn,
290  uint64_t Address,
291  const void *Decoder);
292 
293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
294  unsigned Insn,
295  uint64_t Address,
296  const void *Decoder);
297 
298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
299  unsigned Insn,
300  uint64_t Address,
301  const void *Decoder);
302 
303 static DecodeStatus DecodeSyncI(MCInst &Inst,
304  unsigned Insn,
305  uint64_t Address,
306  const void *Decoder);
307 
308 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
309  unsigned Insn,
310  uint64_t Address,
311  const void *Decoder);
312 
313 static DecodeStatus DecodeSynciR6(MCInst &Inst,
314  unsigned Insn,
315  uint64_t Address,
316  const void *Decoder);
317 
318 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
319  uint64_t Address, const void *Decoder);
320 
321 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
322  unsigned Insn,
323  uint64_t Address,
324  const void *Decoder);
325 
327  unsigned Insn,
328  uint64_t Address,
329  const void *Decoder);
330 
332  unsigned Insn,
333  uint64_t Address,
334  const void *Decoder);
335 
337  unsigned Insn,
338  uint64_t Address,
339  const void *Decoder);
340 
341 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
342  unsigned Insn,
343  uint64_t Address,
344  const void *Decoder);
345 
347  unsigned Insn,
348  uint64_t Address,
349  const void *Decoder);
350 
352  unsigned Insn,
353  uint64_t Address,
354  const void *Decoder);
355 
356 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
357  uint64_t Address,
358  const void *Decoder);
359 
360 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
361  uint64_t Address,
362  const void *Decoder);
363 
364 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
365  const void *Decoder);
366 
367 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
368  const void *Decoder);
369 
370 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
371  uint64_t Address, const void *Decoder);
372 
373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
374  uint64_t Address,
375  const void *Decoder);
376 
378  unsigned Insn,
379  uint64_t Address,
380  const void *Decoder);
381 
383  unsigned Value,
384  uint64_t Address,
385  const void *Decoder);
386 
387 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
388  unsigned Value,
389  uint64_t Address,
390  const void *Decoder);
391 
393  unsigned Value,
394  uint64_t Address,
395  const void *Decoder);
396 
397 template <unsigned Bits, int Offset, int Scale>
398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
399  uint64_t Address,
400  const void *Decoder);
401 
402 template <unsigned Bits, int Offset>
403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
404  uint64_t Address,
405  const void *Decoder) {
406  return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
407  Decoder);
408 }
409 
410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
412  uint64_t Address,
413  const void *Decoder);
414 
415 static DecodeStatus DecodeInsSize(MCInst &Inst,
416  unsigned Insn,
417  uint64_t Address,
418  const void *Decoder);
419 
420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
421  uint64_t Address, const void *Decoder);
422 
423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
424  uint64_t Address, const void *Decoder);
425 
426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
427  uint64_t Address, const void *Decoder);
428 
429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
430  uint64_t Address, const void *Decoder);
431 
432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
433  uint64_t Address, const void *Decoder);
434 
435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
436 /// handle.
437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
439  const void *Decoder);
440 
441 template <typename InsnType>
442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
443  const void *Decoder);
444 
445 template <typename InsnType>
446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
447  const void *Decoder);
448 
449 template <typename InsnType>
450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
451  const void *Decoder);
452 
453 template <typename InsnType>
454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
455  const void *Decoder);
456 
457 template <typename InsnType>
458 static DecodeStatus
459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
460  const void *Decoder);
461 
462 template <typename InsnType>
463 static DecodeStatus
464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
465  const void *Decoder);
466 
467 template <typename InsnType>
468 static DecodeStatus
469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
470  const void *Decoder);
471 
472 template <typename InsnType>
473 static DecodeStatus
474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
475  const void *Decoder);
476 
477 template <typename InsnType>
478 static DecodeStatus
479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
480  const void *Decoder);
481 
482 template <typename InsnType>
483 static DecodeStatus
484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
485  const void *Decoder);
486 
487 template <typename InsnType>
488 static DecodeStatus
489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
490  const void *Decoder);
491 
492 template <typename InsnType>
493 static DecodeStatus
494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
495  const void *Decoder);
496 
497 template <typename InsnType>
498 static DecodeStatus
499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
500  const void *Decoder);
501 
502 template <typename InsnType>
503 static DecodeStatus
504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
505  const void *Decoder);
506 
507 template <typename InsnType>
508 static DecodeStatus
509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
510  const void *Decoder);
511 
512 template <typename InsnType>
513 static DecodeStatus
514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
515  const void *Decoder);
516 
517 template <typename InsnType>
518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
519  const void *Decoder);
520 
521 template <typename InsnType>
522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
523  const void *Decoder);
524 
525 template <typename InsnType>
526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
527  const void *Decoder);
528 
529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
530  uint64_t Address,
531  const void *Decoder);
532 
533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
534  uint64_t Address,
535  const void *Decoder);
536 
537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
538  uint64_t Address,
539  const void *Decoder);
540 
541 namespace llvm {
542 
547 
548 } // end namespace llvm
549 
551  const Target &T,
552  const MCSubtargetInfo &STI,
553  MCContext &Ctx) {
554  return new MipsDisassembler(STI, Ctx, true);
555 }
556 
558  const Target &T,
559  const MCSubtargetInfo &STI,
560  MCContext &Ctx) {
561  return new MipsDisassembler(STI, Ctx, false);
562 }
563 
565  // Register the disassembler.
574 }
575 
576 #include "MipsGenDisassemblerTables.inc"
577 
578 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
579  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
580  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
581  return *(RegInfo->getRegClass(RC).begin() + RegNo);
582 }
583 
584 template <typename InsnType>
585 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
586  const void *Decoder) {
587  using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
588 
589  // The size of the n field depends on the element size
590  // The register class also depends on this.
591  InsnType tmp = fieldFromInstruction(insn, 17, 5);
592  unsigned NSize = 0;
593  DecodeFN RegDecoder = nullptr;
594  if ((tmp & 0x18) == 0x00) { // INSVE_B
595  NSize = 4;
596  RegDecoder = DecodeMSA128BRegisterClass;
597  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
598  NSize = 3;
599  RegDecoder = DecodeMSA128HRegisterClass;
600  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
601  NSize = 2;
602  RegDecoder = DecodeMSA128WRegisterClass;
603  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
604  NSize = 1;
605  RegDecoder = DecodeMSA128DRegisterClass;
606  } else
607  llvm_unreachable("Invalid encoding");
608 
609  assert(NSize != 0 && RegDecoder != nullptr);
610 
611  // $wd
612  tmp = fieldFromInstruction(insn, 6, 5);
613  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
614  return MCDisassembler::Fail;
615  // $wd_in
616  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
617  return MCDisassembler::Fail;
618  // $n
619  tmp = fieldFromInstruction(insn, 16, NSize);
621  // $ws
622  tmp = fieldFromInstruction(insn, 11, 5);
623  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
624  return MCDisassembler::Fail;
625  // $n2
627 
629 }
630 
631 template <typename InsnType>
632 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
633  const void *Decoder) {
634  InsnType Rs = fieldFromInstruction(insn, 16, 5);
635  InsnType Imm = fieldFromInstruction(insn, 0, 16);
636  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
637  Rs)));
638  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
639  Rs)));
641 
643 }
644 
645 template <typename InsnType>
646 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
647  const void *Decoder) {
648  InsnType Rs = fieldFromInstruction(insn, 21, 5);
649  InsnType Imm = fieldFromInstruction(insn, 0, 16);
650  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
651  Rs)));
652  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
653  Rs)));
655 
657 }
658 
659 template <typename InsnType>
660 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
661  uint64_t Address,
662  const void *Decoder) {
663  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
664  // (otherwise we would have matched the ADDI instruction from the earlier
665  // ISA's instead).
666  //
667  // We have:
668  // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
669  // BOVC if rs >= rt
670  // BEQZALC if rs == 0 && rt != 0
671  // BEQC if rs < rt && rs != 0
672 
673  InsnType Rs = fieldFromInstruction(insn, 21, 5);
674  InsnType Rt = fieldFromInstruction(insn, 16, 5);
675  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
676  bool HasRs = false;
677 
678  if (Rs >= Rt) {
679  MI.setOpcode(Mips::BOVC);
680  HasRs = true;
681  } else if (Rs != 0 && Rs < Rt) {
682  MI.setOpcode(Mips::BEQC);
683  HasRs = true;
684  } else
685  MI.setOpcode(Mips::BEQZALC);
686 
687  if (HasRs)
688  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
689  Rs)));
690 
691  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
692  Rt)));
694 
696 }
697 
698 template <typename InsnType>
700  uint64_t Address,
701  const void *Decoder) {
702  InsnType Rt = fieldFromInstruction(insn, 21, 5);
703  InsnType Rs = fieldFromInstruction(insn, 16, 5);
704  int64_t Imm = 0;
705 
706  if (Rs >= Rt) {
707  MI.setOpcode(Mips::BOVC_MMR6);
708  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
709  Rt)));
710  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
711  Rs)));
712  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
713  } else if (Rs != 0 && Rs < Rt) {
714  MI.setOpcode(Mips::BEQC_MMR6);
715  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
716  Rs)));
717  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
718  Rt)));
719  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
720  } else {
721  MI.setOpcode(Mips::BEQZALC_MMR6);
722  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
723  Rt)));
724  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
725  }
726 
728 
730 }
731 
732 template <typename InsnType>
733 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
734  uint64_t Address,
735  const void *Decoder) {
736  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
737  // (otherwise we would have matched the ADDI instruction from the earlier
738  // ISA's instead).
739  //
740  // We have:
741  // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
742  // BNVC if rs >= rt
743  // BNEZALC if rs == 0 && rt != 0
744  // BNEC if rs < rt && rs != 0
745 
746  InsnType Rs = fieldFromInstruction(insn, 21, 5);
747  InsnType Rt = fieldFromInstruction(insn, 16, 5);
748  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
749  bool HasRs = false;
750 
751  if (Rs >= Rt) {
752  MI.setOpcode(Mips::BNVC);
753  HasRs = true;
754  } else if (Rs != 0 && Rs < Rt) {
755  MI.setOpcode(Mips::BNEC);
756  HasRs = true;
757  } else
758  MI.setOpcode(Mips::BNEZALC);
759 
760  if (HasRs)
761  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
762  Rs)));
763 
764  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
765  Rt)));
767 
769 }
770 
771 template <typename InsnType>
773  uint64_t Address,
774  const void *Decoder) {
775  InsnType Rt = fieldFromInstruction(insn, 21, 5);
776  InsnType Rs = fieldFromInstruction(insn, 16, 5);
777  int64_t Imm = 0;
778 
779  if (Rs >= Rt) {
780  MI.setOpcode(Mips::BNVC_MMR6);
781  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
782  Rt)));
783  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
784  Rs)));
785  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
786  } else if (Rs != 0 && Rs < Rt) {
787  MI.setOpcode(Mips::BNEC_MMR6);
788  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
789  Rs)));
790  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
791  Rt)));
792  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
793  } else {
794  MI.setOpcode(Mips::BNEZALC_MMR6);
795  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
796  Rt)));
797  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
798  }
799 
801 
803 }
804 
805 template <typename InsnType>
807  uint64_t Address,
808  const void *Decoder) {
809  // We have:
810  // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
811  // Invalid if rt == 0
812  // BGTZC_MMR6 if rs == 0 && rt != 0
813  // BLTZC_MMR6 if rs == rt && rt != 0
814  // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
815 
816  InsnType Rt = fieldFromInstruction(insn, 21, 5);
817  InsnType Rs = fieldFromInstruction(insn, 16, 5);
818  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
819  bool HasRs = false;
820 
821  if (Rt == 0)
822  return MCDisassembler::Fail;
823  else if (Rs == 0)
824  MI.setOpcode(Mips::BGTZC_MMR6);
825  else if (Rs == Rt)
826  MI.setOpcode(Mips::BLTZC_MMR6);
827  else {
828  MI.setOpcode(Mips::BLTC_MMR6);
829  HasRs = true;
830  }
831 
832  if (HasRs)
833  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
834  Rs)));
835 
836  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
837  Rt)));
838 
840 
842 }
843 
844 template <typename InsnType>
846  uint64_t Address,
847  const void *Decoder) {
848  // We have:
849  // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
850  // Invalid if rt == 0
851  // BLEZC_MMR6 if rs == 0 && rt != 0
852  // BGEZC_MMR6 if rs == rt && rt != 0
853  // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
854 
855  InsnType Rt = fieldFromInstruction(insn, 21, 5);
856  InsnType Rs = fieldFromInstruction(insn, 16, 5);
857  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
858  bool HasRs = false;
859 
860  if (Rt == 0)
861  return MCDisassembler::Fail;
862  else if (Rs == 0)
863  MI.setOpcode(Mips::BLEZC_MMR6);
864  else if (Rs == Rt)
865  MI.setOpcode(Mips::BGEZC_MMR6);
866  else {
867  HasRs = true;
868  MI.setOpcode(Mips::BGEC_MMR6);
869  }
870 
871  if (HasRs)
872  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
873  Rs)));
874 
875  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
876  Rt)));
877 
879 
881 }
882 
883 template <typename InsnType>
884 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
885  uint64_t Address,
886  const void *Decoder) {
887  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
888  // (otherwise we would have matched the BLEZL instruction from the earlier
889  // ISA's instead).
890  //
891  // We have:
892  // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
893  // Invalid if rs == 0
894  // BLEZC if rs == 0 && rt != 0
895  // BGEZC if rs == rt && rt != 0
896  // BGEC if rs != rt && rs != 0 && rt != 0
897 
898  InsnType Rs = fieldFromInstruction(insn, 21, 5);
899  InsnType Rt = fieldFromInstruction(insn, 16, 5);
900  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
901  bool HasRs = false;
902 
903  if (Rt == 0)
904  return MCDisassembler::Fail;
905  else if (Rs == 0)
906  MI.setOpcode(Mips::BLEZC);
907  else if (Rs == Rt)
908  MI.setOpcode(Mips::BGEZC);
909  else {
910  HasRs = true;
911  MI.setOpcode(Mips::BGEC);
912  }
913 
914  if (HasRs)
915  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
916  Rs)));
917 
918  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
919  Rt)));
920 
922 
924 }
925 
926 template <typename InsnType>
927 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
928  uint64_t Address,
929  const void *Decoder) {
930  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
931  // (otherwise we would have matched the BGTZL instruction from the earlier
932  // ISA's instead).
933  //
934  // We have:
935  // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
936  // Invalid if rs == 0
937  // BGTZC if rs == 0 && rt != 0
938  // BLTZC if rs == rt && rt != 0
939  // BLTC if rs != rt && rs != 0 && rt != 0
940 
941  bool HasRs = false;
942 
943  InsnType Rs = fieldFromInstruction(insn, 21, 5);
944  InsnType Rt = fieldFromInstruction(insn, 16, 5);
945  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
946 
947  if (Rt == 0)
948  return MCDisassembler::Fail;
949  else if (Rs == 0)
950  MI.setOpcode(Mips::BGTZC);
951  else if (Rs == Rt)
952  MI.setOpcode(Mips::BLTZC);
953  else {
954  MI.setOpcode(Mips::BLTC);
955  HasRs = true;
956  }
957 
958  if (HasRs)
959  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
960  Rs)));
961 
962  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
963  Rt)));
964 
966 
968 }
969 
970 template <typename InsnType>
971 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
972  uint64_t Address,
973  const void *Decoder) {
974  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
975  // (otherwise we would have matched the BGTZ instruction from the earlier
976  // ISA's instead).
977  //
978  // We have:
979  // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
980  // BGTZ if rt == 0
981  // BGTZALC if rs == 0 && rt != 0
982  // BLTZALC if rs != 0 && rs == rt
983  // BLTUC if rs != 0 && rs != rt
984 
985  InsnType Rs = fieldFromInstruction(insn, 21, 5);
986  InsnType Rt = fieldFromInstruction(insn, 16, 5);
987  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
988  bool HasRs = false;
989  bool HasRt = false;
990 
991  if (Rt == 0) {
992  MI.setOpcode(Mips::BGTZ);
993  HasRs = true;
994  } else if (Rs == 0) {
995  MI.setOpcode(Mips::BGTZALC);
996  HasRt = true;
997  } else if (Rs == Rt) {
998  MI.setOpcode(Mips::BLTZALC);
999  HasRs = true;
1000  } else {
1001  MI.setOpcode(Mips::BLTUC);
1002  HasRs = true;
1003  HasRt = true;
1004  }
1005 
1006  if (HasRs)
1007  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1008  Rs)));
1009 
1010  if (HasRt)
1011  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1012  Rt)));
1013 
1015 
1016  return MCDisassembler::Success;
1017 }
1018 
1019 template <typename InsnType>
1020 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1021  uint64_t Address,
1022  const void *Decoder) {
1023  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1024  // (otherwise we would have matched the BLEZL instruction from the earlier
1025  // ISA's instead).
1026  //
1027  // We have:
1028  // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1029  // Invalid if rs == 0
1030  // BLEZALC if rs == 0 && rt != 0
1031  // BGEZALC if rs == rt && rt != 0
1032  // BGEUC if rs != rt && rs != 0 && rt != 0
1033 
1034  InsnType Rs = fieldFromInstruction(insn, 21, 5);
1035  InsnType Rt = fieldFromInstruction(insn, 16, 5);
1036  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1037  bool HasRs = false;
1038 
1039  if (Rt == 0)
1040  return MCDisassembler::Fail;
1041  else if (Rs == 0)
1042  MI.setOpcode(Mips::BLEZALC);
1043  else if (Rs == Rt)
1044  MI.setOpcode(Mips::BGEZALC);
1045  else {
1046  HasRs = true;
1047  MI.setOpcode(Mips::BGEUC);
1048  }
1049 
1050  if (HasRs)
1051  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1052  Rs)));
1053  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1054  Rt)));
1055 
1057 
1058  return MCDisassembler::Success;
1059 }
1060 
1061 // Override the generated disassembler to produce DEXT all the time. This is
1062 // for feature / behaviour parity with binutils.
1063 template <typename InsnType>
1064 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1065  const void *Decoder) {
1066  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1067  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1068  unsigned Size = 0;
1069  unsigned Pos = 0;
1070 
1071  switch (MI.getOpcode()) {
1072  case Mips::DEXT:
1073  Pos = Lsb;
1074  Size = Msbd + 1;
1075  break;
1076  case Mips::DEXTM:
1077  Pos = Lsb;
1078  Size = Msbd + 1 + 32;
1079  break;
1080  case Mips::DEXTU:
1081  Pos = Lsb + 32;
1082  Size = Msbd + 1;
1083  break;
1084  default:
1085  llvm_unreachable("Unknown DEXT instruction!");
1086  }
1087 
1088  MI.setOpcode(Mips::DEXT);
1089 
1090  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1091  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1092 
1093  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1094  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1096  MI.addOperand(MCOperand::createImm(Size));
1097 
1098  return MCDisassembler::Success;
1099 }
1100 
1101 // Override the generated disassembler to produce DINS all the time. This is
1102 // for feature / behaviour parity with binutils.
1103 template <typename InsnType>
1104 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1105  const void *Decoder) {
1106  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1107  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1108  unsigned Size = 0;
1109  unsigned Pos = 0;
1110 
1111  switch (MI.getOpcode()) {
1112  case Mips::DINS:
1113  Pos = Lsb;
1114  Size = Msbd + 1 - Pos;
1115  break;
1116  case Mips::DINSM:
1117  Pos = Lsb;
1118  Size = Msbd + 33 - Pos;
1119  break;
1120  case Mips::DINSU:
1121  Pos = Lsb + 32;
1122  // mbsd = pos + size - 33
1123  // mbsd - pos + 33 = size
1124  Size = Msbd + 33 - Pos;
1125  break;
1126  default:
1127  llvm_unreachable("Unknown DINS instruction!");
1128  }
1129 
1130  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1131  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1132 
1133  MI.setOpcode(Mips::DINS);
1134  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1135  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1137  MI.addOperand(MCOperand::createImm(Size));
1138 
1139  return MCDisassembler::Success;
1140 }
1141 
1142 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1143 template <typename InsnType>
1144 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1145  const void *Decoder) {
1146  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1147  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1148  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1149  Rt)));
1150  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1151  Rs)));
1152  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1153  Rt)));
1154  return MCDisassembler::Success;
1155 }
1156 
1157 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1158 /// according to the given endianness.
1160  uint64_t &Size, uint32_t &Insn,
1161  bool IsBigEndian) {
1162  // We want to read exactly 2 Bytes of data.
1163  if (Bytes.size() < 2) {
1164  Size = 0;
1165  return MCDisassembler::Fail;
1166  }
1167 
1168  if (IsBigEndian) {
1169  Insn = (Bytes[0] << 8) | Bytes[1];
1170  } else {
1171  Insn = (Bytes[1] << 8) | Bytes[0];
1172  }
1173 
1174  return MCDisassembler::Success;
1175 }
1176 
1177 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1178 /// according to the given endianness.
1180  uint64_t &Size, uint32_t &Insn,
1181  bool IsBigEndian, bool IsMicroMips) {
1182  // We want to read exactly 4 Bytes of data.
1183  if (Bytes.size() < 4) {
1184  Size = 0;
1185  return MCDisassembler::Fail;
1186  }
1187 
1188  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1189  // always precede the low 16 bits in the instruction stream (that is, they
1190  // are placed at lower addresses in the instruction stream).
1191  //
1192  // microMIPS byte ordering:
1193  // Big-endian: 0 | 1 | 2 | 3
1194  // Little-endian: 1 | 0 | 3 | 2
1195 
1196  if (IsBigEndian) {
1197  // Encoded as a big-endian 32-bit word in the stream.
1198  Insn =
1199  (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1200  } else {
1201  if (IsMicroMips) {
1202  Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1203  (Bytes[1] << 24);
1204  } else {
1205  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1206  (Bytes[3] << 24);
1207  }
1208  }
1209 
1210  return MCDisassembler::Success;
1211 }
1212 
1213 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1214  ArrayRef<uint8_t> Bytes,
1215  uint64_t Address,
1216  raw_ostream &VStream,
1217  raw_ostream &CStream) const {
1218  uint32_t Insn;
1219  DecodeStatus Result;
1220  Size = 0;
1221 
1222  if (IsMicroMips) {
1223  Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1224  if (Result == MCDisassembler::Fail)
1225  return MCDisassembler::Fail;
1226 
1227  if (hasMips32r6()) {
1228  LLVM_DEBUG(
1229  dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1230  // Calling the auto-generated decoder function for microMIPS32R6
1231  // 16-bit instructions.
1232  Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1233  Address, this, STI);
1234  if (Result != MCDisassembler::Fail) {
1235  Size = 2;
1236  return Result;
1237  }
1238  }
1239 
1240  LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1241  // Calling the auto-generated decoder function for microMIPS 16-bit
1242  // instructions.
1243  Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1244  this, STI);
1245  if (Result != MCDisassembler::Fail) {
1246  Size = 2;
1247  return Result;
1248  }
1249 
1250  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1251  if (Result == MCDisassembler::Fail)
1252  return MCDisassembler::Fail;
1253 
1254  if (hasMips32r6()) {
1255  LLVM_DEBUG(
1256  dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1257  // Calling the auto-generated decoder function.
1258  Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1259  this, STI);
1260  if (Result != MCDisassembler::Fail) {
1261  Size = 4;
1262  return Result;
1263  }
1264  }
1265 
1266  LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1267  // Calling the auto-generated decoder function.
1268  Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1269  this, STI);
1270  if (Result != MCDisassembler::Fail) {
1271  Size = 4;
1272  return Result;
1273  }
1274 
1275  if (isFP64()) {
1276  LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1277  Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1278  Address, this, STI);
1279  if (Result != MCDisassembler::Fail) {
1280  Size = 4;
1281  return Result;
1282  }
1283  }
1284 
1285  // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1286  // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1287  // could form a valid instruction. The two bytes we rejected as an
1288  // instruction could have actually beeen an inline constant pool that is
1289  // unconditionally branched over.
1290  Size = 2;
1291  return MCDisassembler::Fail;
1292  }
1293 
1294  // Attempt to read the instruction so that we can attempt to decode it. If
1295  // the buffer is not 4 bytes long, let the higher level logic figure out
1296  // what to do with a size of zero and MCDisassembler::Fail.
1297  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1298  if (Result == MCDisassembler::Fail)
1299  return MCDisassembler::Fail;
1300 
1301  // The only instruction size for standard encoded MIPS.
1302  Size = 4;
1303 
1304  if (hasCOP3()) {
1305  LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1306  Result =
1307  decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1308  if (Result != MCDisassembler::Fail)
1309  return Result;
1310  }
1311 
1312  if (hasMips32r6() && isGP64()) {
1313  LLVM_DEBUG(
1314  dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1315  Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1316  Address, this, STI);
1317  if (Result != MCDisassembler::Fail)
1318  return Result;
1319  }
1320 
1321  if (hasMips32r6() && isPTR64()) {
1322  LLVM_DEBUG(
1323  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1324  Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1325  Address, this, STI);
1326  if (Result != MCDisassembler::Fail)
1327  return Result;
1328  }
1329 
1330  if (hasMips32r6()) {
1331  LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1332  Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1333  Address, this, STI);
1334  if (Result != MCDisassembler::Fail)
1335  return Result;
1336  }
1337 
1338  if (hasMips2() && isPTR64()) {
1339  LLVM_DEBUG(
1340  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1341  Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1342  Address, this, STI);
1343  if (Result != MCDisassembler::Fail)
1344  return Result;
1345  }
1346 
1347  if (hasCnMips()) {
1348  LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1349  Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1350  Address, this, STI);
1351  if (Result != MCDisassembler::Fail)
1352  return Result;
1353  }
1354 
1355  if (isGP64()) {
1356  LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1357  Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1358  Address, this, STI);
1359  if (Result != MCDisassembler::Fail)
1360  return Result;
1361  }
1362 
1363  if (isFP64()) {
1364  LLVM_DEBUG(
1365  dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1366  Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1367  Address, this, STI);
1368  if (Result != MCDisassembler::Fail)
1369  return Result;
1370  }
1371 
1372  LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1373  // Calling the auto-generated decoder function.
1374  Result =
1375  decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1376  if (Result != MCDisassembler::Fail)
1377  return Result;
1378 
1379  return MCDisassembler::Fail;
1380 }
1381 
1383  unsigned RegNo,
1384  uint64_t Address,
1385  const void *Decoder) {
1386  return MCDisassembler::Fail;
1387 }
1388 
1390  unsigned RegNo,
1391  uint64_t Address,
1392  const void *Decoder) {
1393  if (RegNo > 31)
1394  return MCDisassembler::Fail;
1395 
1396  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1397  Inst.addOperand(MCOperand::createReg(Reg));
1398  return MCDisassembler::Success;
1399 }
1400 
1402  unsigned RegNo,
1403  uint64_t Address,
1404  const void *Decoder) {
1405  if (RegNo > 7)
1406  return MCDisassembler::Fail;
1407  unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1408  Inst.addOperand(MCOperand::createReg(Reg));
1409  return MCDisassembler::Success;
1410 }
1411 
1413  unsigned RegNo,
1414  uint64_t Address,
1415  const void *Decoder) {
1416  if (RegNo > 7)
1417  return MCDisassembler::Fail;
1418  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1419  Inst.addOperand(MCOperand::createReg(Reg));
1420  return MCDisassembler::Success;
1421 }
1422 
1424  unsigned RegNo,
1425  uint64_t Address,
1426  const void *Decoder) {
1427  if (RegNo > 7)
1428  return MCDisassembler::Fail;
1429  unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1430  Inst.addOperand(MCOperand::createReg(Reg));
1431  return MCDisassembler::Success;
1432 }
1433 
1435  unsigned RegNo,
1436  uint64_t Address,
1437  const void *Decoder) {
1438  if (RegNo > 31)
1439  return MCDisassembler::Fail;
1440  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1441  Inst.addOperand(MCOperand::createReg(Reg));
1442  return MCDisassembler::Success;
1443 }
1444 
1446  unsigned RegNo,
1447  uint64_t Address,
1448  const void *Decoder) {
1449  if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1450  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1451 
1452  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1453 }
1454 
1456  unsigned RegNo,
1457  uint64_t Address,
1458  const void *Decoder) {
1459  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1460 }
1461 
1463  unsigned RegNo,
1464  uint64_t Address,
1465  const void *Decoder) {
1466  if (RegNo > 31)
1467  return MCDisassembler::Fail;
1468 
1469  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1470  Inst.addOperand(MCOperand::createReg(Reg));
1471  return MCDisassembler::Success;
1472 }
1473 
1475  unsigned RegNo,
1476  uint64_t Address,
1477  const void *Decoder) {
1478  if (RegNo > 31)
1479  return MCDisassembler::Fail;
1480 
1481  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1482  Inst.addOperand(MCOperand::createReg(Reg));
1483  return MCDisassembler::Success;
1484 }
1485 
1487  unsigned RegNo,
1488  uint64_t Address,
1489  const void *Decoder) {
1490  if (RegNo > 31)
1491  return MCDisassembler::Fail;
1492  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1493  Inst.addOperand(MCOperand::createReg(Reg));
1494  return MCDisassembler::Success;
1495 }
1496 
1498  unsigned RegNo,
1499  uint64_t Address,
1500  const void *Decoder) {
1501  if (RegNo > 7)
1502  return MCDisassembler::Fail;
1503  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1504  Inst.addOperand(MCOperand::createReg(Reg));
1505  return MCDisassembler::Success;
1506 }
1507 
1508 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1509  uint64_t Address,
1510  const void *Decoder) {
1511  if (RegNo > 31)
1512  return MCDisassembler::Fail;
1513 
1514  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1515  Inst.addOperand(MCOperand::createReg(Reg));
1516  return MCDisassembler::Success;
1517 }
1518 
1520  unsigned Insn,
1521  uint64_t Address,
1522  const void *Decoder) {
1523  int Offset = SignExtend32<16>(Insn & 0xffff);
1524  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1525  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1526 
1527  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1528  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1529 
1530  if (Inst.getOpcode() == Mips::SC ||
1531  Inst.getOpcode() == Mips::SCD)
1532  Inst.addOperand(MCOperand::createReg(Reg));
1533 
1534  Inst.addOperand(MCOperand::createReg(Reg));
1535  Inst.addOperand(MCOperand::createReg(Base));
1536  Inst.addOperand(MCOperand::createImm(Offset));
1537 
1538  return MCDisassembler::Success;
1539 }
1540 
1542  unsigned Insn,
1543  uint64_t Address,
1544  const void *Decoder) {
1545  int Offset = SignExtend32<9>(Insn >> 7);
1546  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1547  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1548 
1549  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1550  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1551 
1552  if (Inst.getOpcode() == Mips::SCE)
1553  Inst.addOperand(MCOperand::createReg(Reg));
1554 
1555  Inst.addOperand(MCOperand::createReg(Reg));
1556  Inst.addOperand(MCOperand::createReg(Base));
1557  Inst.addOperand(MCOperand::createImm(Offset));
1558 
1559  return MCDisassembler::Success;
1560 }
1561 
1563  unsigned Insn,
1564  uint64_t Address,
1565  const void *Decoder) {
1566  int Offset = SignExtend32<16>(Insn & 0xffff);
1567  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1568  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1569 
1570  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1571  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1572 
1573  Inst.addOperand(MCOperand::createReg(Reg));
1574  Inst.addOperand(MCOperand::createReg(Base));
1575  Inst.addOperand(MCOperand::createImm(Offset));
1576 
1577  return MCDisassembler::Success;
1578 }
1579 
1581  unsigned Insn,
1582  uint64_t Address,
1583  const void *Decoder) {
1584  int Offset = SignExtend32<16>(Insn & 0xffff);
1585  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1586  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1587 
1588  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1589 
1590  Inst.addOperand(MCOperand::createReg(Base));
1591  Inst.addOperand(MCOperand::createImm(Offset));
1592  Inst.addOperand(MCOperand::createImm(Hint));
1593 
1594  return MCDisassembler::Success;
1595 }
1596 
1598  unsigned Insn,
1599  uint64_t Address,
1600  const void *Decoder) {
1601  int Offset = SignExtend32<12>(Insn & 0xfff);
1602  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1603  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1604 
1605  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1606 
1607  Inst.addOperand(MCOperand::createReg(Base));
1608  Inst.addOperand(MCOperand::createImm(Offset));
1609  Inst.addOperand(MCOperand::createImm(Hint));
1610 
1611  return MCDisassembler::Success;
1612 }
1613 
1615  unsigned Insn,
1616  uint64_t Address,
1617  const void *Decoder) {
1618  int Offset = SignExtend32<9>(Insn & 0x1ff);
1619  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1620  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1621 
1622  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1623 
1624  Inst.addOperand(MCOperand::createReg(Base));
1625  Inst.addOperand(MCOperand::createImm(Offset));
1626  Inst.addOperand(MCOperand::createImm(Hint));
1627 
1628  return MCDisassembler::Success;
1629 }
1630 
1632  unsigned Insn,
1633  uint64_t Address,
1634  const void *Decoder) {
1635  int Offset = SignExtend32<9>(Insn >> 7);
1636  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1637  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1638 
1639  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1640 
1641  Inst.addOperand(MCOperand::createReg(Base));
1642  Inst.addOperand(MCOperand::createImm(Offset));
1643  Inst.addOperand(MCOperand::createImm(Hint));
1644 
1645  return MCDisassembler::Success;
1646 }
1647 
1649  unsigned Insn,
1650  uint64_t Address,
1651  const void *Decoder) {
1652  int Offset = SignExtend32<16>(Insn & 0xffff);
1653  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1654 
1655  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1656 
1657  Inst.addOperand(MCOperand::createReg(Base));
1658  Inst.addOperand(MCOperand::createImm(Offset));
1659 
1660  return MCDisassembler::Success;
1661 }
1662 
1663 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1664  uint64_t Address, const void *Decoder) {
1665  int Offset = SignExtend32<16>(Insn & 0xffff);
1666  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1667 
1668  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1669 
1670  Inst.addOperand(MCOperand::createReg(Base));
1671  Inst.addOperand(MCOperand::createImm(Offset));
1672 
1673  return MCDisassembler::Success;
1674 }
1675 
1677  unsigned Insn,
1678  uint64_t Address,
1679  const void *Decoder) {
1680  int Immediate = SignExtend32<16>(Insn & 0xffff);
1681  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1682 
1683  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1684 
1685  Inst.addOperand(MCOperand::createReg(Base));
1686  Inst.addOperand(MCOperand::createImm(Immediate));
1687 
1688  return MCDisassembler::Success;
1689 }
1690 
1691 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1692  uint64_t Address, const void *Decoder) {
1693  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1694  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1695  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1696 
1697  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1698  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1699 
1700  Inst.addOperand(MCOperand::createReg(Reg));
1701  Inst.addOperand(MCOperand::createReg(Base));
1702 
1703  // The immediate field of an LD/ST instruction is scaled which means it must
1704  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1705  // data format.
1706  // .b - 1 byte
1707  // .h - 2 bytes
1708  // .w - 4 bytes
1709  // .d - 8 bytes
1710  switch(Inst.getOpcode())
1711  {
1712  default:
1713  assert(false && "Unexpected instruction");
1714  return MCDisassembler::Fail;
1715  break;
1716  case Mips::LD_B:
1717  case Mips::ST_B:
1718  Inst.addOperand(MCOperand::createImm(Offset));
1719  break;
1720  case Mips::LD_H:
1721  case Mips::ST_H:
1722  Inst.addOperand(MCOperand::createImm(Offset * 2));
1723  break;
1724  case Mips::LD_W:
1725  case Mips::ST_W:
1726  Inst.addOperand(MCOperand::createImm(Offset * 4));
1727  break;
1728  case Mips::LD_D:
1729  case Mips::ST_D:
1730  Inst.addOperand(MCOperand::createImm(Offset * 8));
1731  break;
1732  }
1733 
1734  return MCDisassembler::Success;
1735 }
1736 
1738  unsigned Insn,
1739  uint64_t Address,
1740  const void *Decoder) {
1741  unsigned Offset = Insn & 0xf;
1742  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1743  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1744 
1745  switch (Inst.getOpcode()) {
1746  case Mips::LBU16_MM:
1747  case Mips::LHU16_MM:
1748  case Mips::LW16_MM:
1749  if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1751  return MCDisassembler::Fail;
1752  break;
1753  case Mips::SB16_MM:
1754  case Mips::SB16_MMR6:
1755  case Mips::SH16_MM:
1756  case Mips::SH16_MMR6:
1757  case Mips::SW16_MM:
1758  case Mips::SW16_MMR6:
1759  if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1761  return MCDisassembler::Fail;
1762  break;
1763  }
1764 
1765  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1767  return MCDisassembler::Fail;
1768 
1769  switch (Inst.getOpcode()) {
1770  case Mips::LBU16_MM:
1771  if (Offset == 0xf)
1772  Inst.addOperand(MCOperand::createImm(-1));
1773  else
1774  Inst.addOperand(MCOperand::createImm(Offset));
1775  break;
1776  case Mips::SB16_MM:
1777  case Mips::SB16_MMR6:
1778  Inst.addOperand(MCOperand::createImm(Offset));
1779  break;
1780  case Mips::LHU16_MM:
1781  case Mips::SH16_MM:
1782  case Mips::SH16_MMR6:
1783  Inst.addOperand(MCOperand::createImm(Offset << 1));
1784  break;
1785  case Mips::LW16_MM:
1786  case Mips::SW16_MM:
1787  case Mips::SW16_MMR6:
1788  Inst.addOperand(MCOperand::createImm(Offset << 2));
1789  break;
1790  }
1791 
1792  return MCDisassembler::Success;
1793 }
1794 
1796  unsigned Insn,
1797  uint64_t Address,
1798  const void *Decoder) {
1799  unsigned Offset = Insn & 0x1F;
1800  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1801 
1802  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1803 
1804  Inst.addOperand(MCOperand::createReg(Reg));
1805  Inst.addOperand(MCOperand::createReg(Mips::SP));
1806  Inst.addOperand(MCOperand::createImm(Offset << 2));
1807 
1808  return MCDisassembler::Success;
1809 }
1810 
1812  unsigned Insn,
1813  uint64_t Address,
1814  const void *Decoder) {
1815  unsigned Offset = Insn & 0x7F;
1816  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1817 
1818  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1819 
1820  Inst.addOperand(MCOperand::createReg(Reg));
1821  Inst.addOperand(MCOperand::createReg(Mips::GP));
1822  Inst.addOperand(MCOperand::createImm(Offset << 2));
1823 
1824  return MCDisassembler::Success;
1825 }
1826 
1828  unsigned Insn,
1829  uint64_t Address,
1830  const void *Decoder) {
1831  int Offset;
1832  switch (Inst.getOpcode()) {
1833  case Mips::LWM16_MMR6:
1834  case Mips::SWM16_MMR6:
1835  Offset = fieldFromInstruction(Insn, 4, 4);
1836  break;
1837  default:
1838  Offset = SignExtend32<4>(Insn & 0xf);
1839  break;
1840  }
1841 
1842  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1844  return MCDisassembler::Fail;
1845 
1846  Inst.addOperand(MCOperand::createReg(Mips::SP));
1847  Inst.addOperand(MCOperand::createImm(Offset << 2));
1848 
1849  return MCDisassembler::Success;
1850 }
1851 
1853  unsigned Insn,
1854  uint64_t Address,
1855  const void *Decoder) {
1856  int Offset = SignExtend32<9>(Insn & 0x1ff);
1857  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1858  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1859 
1860  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1861  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1862 
1863  if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1864  Inst.addOperand(MCOperand::createReg(Reg));
1865 
1866  Inst.addOperand(MCOperand::createReg(Reg));
1867  Inst.addOperand(MCOperand::createReg(Base));
1868  Inst.addOperand(MCOperand::createImm(Offset));
1869 
1870  return MCDisassembler::Success;
1871 }
1872 
1874  unsigned Insn,
1875  uint64_t Address,
1876  const void *Decoder) {
1877  int Offset = SignExtend32<12>(Insn & 0x0fff);
1878  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1879  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1880 
1881  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1882  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1883 
1884  switch (Inst.getOpcode()) {
1885  case Mips::SWM32_MM:
1886  case Mips::LWM32_MM:
1887  if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1889  return MCDisassembler::Fail;
1890  Inst.addOperand(MCOperand::createReg(Base));
1891  Inst.addOperand(MCOperand::createImm(Offset));
1892  break;
1893  case Mips::SC_MM:
1894  Inst.addOperand(MCOperand::createReg(Reg));
1896  default:
1897  Inst.addOperand(MCOperand::createReg(Reg));
1898  if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1899  Inst.addOperand(MCOperand::createReg(Reg+1));
1900 
1901  Inst.addOperand(MCOperand::createReg(Base));
1902  Inst.addOperand(MCOperand::createImm(Offset));
1903  }
1904 
1905  return MCDisassembler::Success;
1906 }
1907 
1909  unsigned Insn,
1910  uint64_t Address,
1911  const void *Decoder) {
1912  int Offset = SignExtend32<16>(Insn & 0xffff);
1913  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1914  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1915 
1916  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1917  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1918 
1919  Inst.addOperand(MCOperand::createReg(Reg));
1920  Inst.addOperand(MCOperand::createReg(Base));
1921  Inst.addOperand(MCOperand::createImm(Offset));
1922 
1923  return MCDisassembler::Success;
1924 }
1925 
1927  unsigned Insn,
1928  uint64_t Address,
1929  const void *Decoder) {
1930  int Offset = SignExtend32<16>(Insn & 0xffff);
1931  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1932  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1933 
1934  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1935  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1936 
1937  Inst.addOperand(MCOperand::createReg(Reg));
1938  Inst.addOperand(MCOperand::createReg(Base));
1939  Inst.addOperand(MCOperand::createImm(Offset));
1940 
1941  return MCDisassembler::Success;
1942 }
1943 
1944 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1945  uint64_t Address, const void *Decoder) {
1946  // This function is the same as DecodeFMem but with the Reg and Base fields
1947  // swapped according to microMIPS spec.
1948  int Offset = SignExtend32<16>(Insn & 0xffff);
1949  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1950  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1951 
1952  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1953  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1954 
1955  Inst.addOperand(MCOperand::createReg(Reg));
1956  Inst.addOperand(MCOperand::createReg(Base));
1957  Inst.addOperand(MCOperand::createImm(Offset));
1958 
1959  return MCDisassembler::Success;
1960 }
1961 
1963  unsigned Insn,
1964  uint64_t Address,
1965  const void *Decoder) {
1966  int Offset = SignExtend32<16>(Insn & 0xffff);
1967  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1968  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1969 
1970  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1971  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1972 
1973  Inst.addOperand(MCOperand::createReg(Reg));
1974  Inst.addOperand(MCOperand::createReg(Base));
1975  Inst.addOperand(MCOperand::createImm(Offset));
1976 
1977  return MCDisassembler::Success;
1978 }
1979 
1981  unsigned Insn,
1982  uint64_t Address,
1983  const void *Decoder) {
1984  int Offset = SignExtend32<16>(Insn & 0xffff);
1985  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1986  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1987 
1988  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1989  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1990 
1991  Inst.addOperand(MCOperand::createReg(Reg));
1992  Inst.addOperand(MCOperand::createReg(Base));
1993  Inst.addOperand(MCOperand::createImm(Offset));
1994 
1995  return MCDisassembler::Success;
1996 }
1997 
1999  unsigned Insn,
2000  uint64_t Address,
2001  const void *Decoder) {
2002  int Offset = SignExtend32<11>(Insn & 0x07ff);
2003  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2004  unsigned Base = fieldFromInstruction(Insn, 11, 5);
2005 
2006  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2007  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2008 
2009  Inst.addOperand(MCOperand::createReg(Reg));
2010  Inst.addOperand(MCOperand::createReg(Base));
2011  Inst.addOperand(MCOperand::createImm(Offset));
2012 
2013  return MCDisassembler::Success;
2014 }
2015 
2016 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2017  uint64_t Address, const void *Decoder) {
2018  int Offset = SignExtend32<11>(Insn & 0x07ff);
2019  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2020  unsigned Base = fieldFromInstruction(Insn, 16, 5);
2021 
2022  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2023  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2024 
2025  Inst.addOperand(MCOperand::createReg(Reg));
2026  Inst.addOperand(MCOperand::createReg(Base));
2027  Inst.addOperand(MCOperand::createImm(Offset));
2028 
2029  return MCDisassembler::Success;
2030 }
2031 
2033  unsigned Insn,
2034  uint64_t Address,
2035  const void *Decoder) {
2036  int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2037  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2038  unsigned Base = fieldFromInstruction(Insn, 21, 5);
2039 
2040  Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2041  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2042 
2043  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2044  Inst.addOperand(MCOperand::createReg(Rt));
2045  }
2046 
2047  Inst.addOperand(MCOperand::createReg(Rt));
2048  Inst.addOperand(MCOperand::createReg(Base));
2049  Inst.addOperand(MCOperand::createImm(Offset));
2050 
2051  return MCDisassembler::Success;
2052 }
2053 
2055  unsigned RegNo,
2056  uint64_t Address,
2057  const void *Decoder) {
2058  // Currently only hardware register 29 is supported.
2059  if (RegNo != 29)
2060  return MCDisassembler::Fail;
2061  Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2062  return MCDisassembler::Success;
2063 }
2064 
2066  unsigned RegNo,
2067  uint64_t Address,
2068  const void *Decoder) {
2069  if (RegNo > 30 || RegNo %2)
2070  return MCDisassembler::Fail;
2071 
2072  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2073  Inst.addOperand(MCOperand::createReg(Reg));
2074  return MCDisassembler::Success;
2075 }
2076 
2078  unsigned RegNo,
2079  uint64_t Address,
2080  const void *Decoder) {
2081  if (RegNo >= 4)
2082  return MCDisassembler::Fail;
2083 
2084  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2085  Inst.addOperand(MCOperand::createReg(Reg));
2086  return MCDisassembler::Success;
2087 }
2088 
2090  unsigned RegNo,
2091  uint64_t Address,
2092  const void *Decoder) {
2093  if (RegNo >= 4)
2094  return MCDisassembler::Fail;
2095 
2096  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2097  Inst.addOperand(MCOperand::createReg(Reg));
2098  return MCDisassembler::Success;
2099 }
2100 
2102  unsigned RegNo,
2103  uint64_t Address,
2104  const void *Decoder) {
2105  if (RegNo >= 4)
2106  return MCDisassembler::Fail;
2107 
2108  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2109  Inst.addOperand(MCOperand::createReg(Reg));
2110  return MCDisassembler::Success;
2111 }
2112 
2114  unsigned RegNo,
2115  uint64_t Address,
2116  const void *Decoder) {
2117  if (RegNo > 31)
2118  return MCDisassembler::Fail;
2119 
2120  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2121  Inst.addOperand(MCOperand::createReg(Reg));
2122  return MCDisassembler::Success;
2123 }
2124 
2126  unsigned RegNo,
2127  uint64_t Address,
2128  const void *Decoder) {
2129  if (RegNo > 31)
2130  return MCDisassembler::Fail;
2131 
2132  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2133  Inst.addOperand(MCOperand::createReg(Reg));
2134  return MCDisassembler::Success;
2135 }
2136 
2138  unsigned RegNo,
2139  uint64_t Address,
2140  const void *Decoder) {
2141  if (RegNo > 31)
2142  return MCDisassembler::Fail;
2143 
2144  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2145  Inst.addOperand(MCOperand::createReg(Reg));
2146  return MCDisassembler::Success;
2147 }
2148 
2150  unsigned RegNo,
2151  uint64_t Address,
2152  const void *Decoder) {
2153  if (RegNo > 31)
2154  return MCDisassembler::Fail;
2155 
2156  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2157  Inst.addOperand(MCOperand::createReg(Reg));
2158  return MCDisassembler::Success;
2159 }
2160 
2162  unsigned RegNo,
2163  uint64_t Address,
2164  const void *Decoder) {
2165  if (RegNo > 7)
2166  return MCDisassembler::Fail;
2167 
2168  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2169  Inst.addOperand(MCOperand::createReg(Reg));
2170  return MCDisassembler::Success;
2171 }
2172 
2174  unsigned RegNo,
2175  uint64_t Address,
2176  const void *Decoder) {
2177  if (RegNo > 31)
2178  return MCDisassembler::Fail;
2179 
2180  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2181  Inst.addOperand(MCOperand::createReg(Reg));
2182  return MCDisassembler::Success;
2183 }
2184 
2186  unsigned RegNo,
2187  uint64_t Address,
2188  const void *Decoder) {
2189  if (RegNo > 31)
2190  return MCDisassembler::Fail;
2191 
2192  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2193  Inst.addOperand(MCOperand::createReg(Reg));
2194  return MCDisassembler::Success;
2195 }
2196 
2198  unsigned Offset,
2199  uint64_t Address,
2200  const void *Decoder) {
2201  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2202  Inst.addOperand(MCOperand::createImm(BranchOffset));
2203  return MCDisassembler::Success;
2204 }
2205 
2207  unsigned Offset,
2208  uint64_t Address,
2209  const void *Decoder) {
2210  int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2211  Inst.addOperand(MCOperand::createImm(BranchOffset));
2212  return MCDisassembler::Success;
2213 }
2214 
2216  unsigned Insn,
2217  uint64_t Address,
2218  const void *Decoder) {
2219  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2220  Inst.addOperand(MCOperand::createImm(JumpOffset));
2221  return MCDisassembler::Success;
2222 }
2223 
2225  unsigned Offset,
2226  uint64_t Address,
2227  const void *Decoder) {
2228  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2229 
2230  Inst.addOperand(MCOperand::createImm(BranchOffset));
2231  return MCDisassembler::Success;
2232 }
2233 
2235  unsigned Offset,
2236  uint64_t Address,
2237  const void *Decoder) {
2238  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2239 
2240  Inst.addOperand(MCOperand::createImm(BranchOffset));
2241  return MCDisassembler::Success;
2242 }
2243 
2245  unsigned Offset,
2246  uint64_t Address,
2247  const void *Decoder) {
2248  int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2249 
2250  Inst.addOperand(MCOperand::createImm(BranchOffset));
2251  return MCDisassembler::Success;
2252 }
2253 
2255  unsigned Offset,
2256  uint64_t Address,
2257  const void *Decoder) {
2258  int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2259  Inst.addOperand(MCOperand::createImm(BranchOffset));
2260  return MCDisassembler::Success;
2261 }
2262 
2264  unsigned Offset,
2265  uint64_t Address,
2266  const void *Decoder) {
2267  int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2268  Inst.addOperand(MCOperand::createImm(BranchOffset));
2269  return MCDisassembler::Success;
2270 }
2271 
2273  unsigned Offset,
2274  uint64_t Address,
2275  const void *Decoder) {
2276  int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2277  Inst.addOperand(MCOperand::createImm(BranchOffset));
2278  return MCDisassembler::Success;
2279 }
2280 
2282  unsigned Offset,
2283  uint64_t Address,
2284  const void *Decoder) {
2285  int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2286 
2287  Inst.addOperand(MCOperand::createImm(BranchOffset));
2288  return MCDisassembler::Success;
2289 }
2290 
2292  unsigned Insn,
2293  uint64_t Address,
2294  const void *Decoder) {
2295  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2296  Inst.addOperand(MCOperand::createImm(JumpOffset));
2297  return MCDisassembler::Success;
2298 }
2299 
2301  unsigned Value,
2302  uint64_t Address,
2303  const void *Decoder) {
2304  if (Value == 0)
2306  else if (Value == 0x7)
2307  Inst.addOperand(MCOperand::createImm(-1));
2308  else
2309  Inst.addOperand(MCOperand::createImm(Value << 2));
2310  return MCDisassembler::Success;
2311 }
2312 
2314  unsigned Value,
2315  uint64_t Address,
2316  const void *Decoder) {
2317  if (Value == 0x7F)
2318  Inst.addOperand(MCOperand::createImm(-1));
2319  else
2320  Inst.addOperand(MCOperand::createImm(Value));
2321  return MCDisassembler::Success;
2322 }
2323 
2325  unsigned Value,
2326  uint64_t Address,
2327  const void *Decoder) {
2328  Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2329  return MCDisassembler::Success;
2330 }
2331 
2332 template <unsigned Bits, int Offset, int Scale>
2333 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2334  uint64_t Address,
2335  const void *Decoder) {
2336  Value &= ((1 << Bits) - 1);
2337  Value *= Scale;
2338  Inst.addOperand(MCOperand::createImm(Value + Offset));
2339  return MCDisassembler::Success;
2340 }
2341 
2342 template <unsigned Bits, int Offset, int ScaleBy>
2343 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2344  uint64_t Address,
2345  const void *Decoder) {
2346  int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2347  Inst.addOperand(MCOperand::createImm(Imm + Offset));
2348  return MCDisassembler::Success;
2349 }
2350 
2352  unsigned Insn,
2353  uint64_t Address,
2354  const void *Decoder) {
2355  // First we need to grab the pos(lsb) from MCInst.
2356  // This function only handles the 32 bit variants of ins, as dins
2357  // variants are handled differently.
2358  int Pos = Inst.getOperand(2).getImm();
2359  int Size = (int) Insn - Pos + 1;
2360  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2361  return MCDisassembler::Success;
2362 }
2363 
2364 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2365  uint64_t Address, const void *Decoder) {
2366  Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2367  return MCDisassembler::Success;
2368 }
2369 
2370 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2371  uint64_t Address, const void *Decoder) {
2372  Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2373  return MCDisassembler::Success;
2374 }
2375 
2376 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2377  uint64_t Address, const void *Decoder) {
2378  int32_t DecodedValue;
2379  switch (Insn) {
2380  case 0: DecodedValue = 256; break;
2381  case 1: DecodedValue = 257; break;
2382  case 510: DecodedValue = -258; break;
2383  case 511: DecodedValue = -257; break;
2384  default: DecodedValue = SignExtend32<9>(Insn); break;
2385  }
2386  Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2387  return MCDisassembler::Success;
2388 }
2389 
2390 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2391  uint64_t Address, const void *Decoder) {
2392  // Insn must be >= 0, since it is unsigned that condition is always true.
2393  assert(Insn < 16);
2394  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2395  255, 32768, 65535};
2396  Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2397  return MCDisassembler::Success;
2398 }
2399 
2401  unsigned Insn,
2402  uint64_t Address,
2403  const void *Decoder) {
2404  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2405  Mips::S6, Mips::S7, Mips::FP};
2406  unsigned RegNum;
2407 
2408  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2409 
2410  // Empty register lists are not allowed.
2411  if (RegLst == 0)
2412  return MCDisassembler::Fail;
2413 
2414  RegNum = RegLst & 0xf;
2415 
2416  // RegLst values 10-15, and 26-31 are reserved.
2417  if (RegNum > 9)
2418  return MCDisassembler::Fail;
2419 
2420  for (unsigned i = 0; i < RegNum; i++)
2421  Inst.addOperand(MCOperand::createReg(Regs[i]));
2422 
2423  if (RegLst & 0x10)
2425 
2426  return MCDisassembler::Success;
2427 }
2428 
2429 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2430  uint64_t Address,
2431  const void *Decoder) {
2432  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2433  unsigned RegLst;
2434  switch(Inst.getOpcode()) {
2435  default:
2436  RegLst = fieldFromInstruction(Insn, 4, 2);
2437  break;
2438  case Mips::LWM16_MMR6:
2439  case Mips::SWM16_MMR6:
2440  RegLst = fieldFromInstruction(Insn, 8, 2);
2441  break;
2442  }
2443  unsigned RegNum = RegLst & 0x3;
2444 
2445  for (unsigned i = 0; i <= RegNum; i++)
2446  Inst.addOperand(MCOperand::createReg(Regs[i]));
2447 
2449 
2450  return MCDisassembler::Success;
2451 }
2452 
2453 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2454  uint64_t Address, const void *Decoder) {
2455  switch (RegPair) {
2456  default:
2457  return MCDisassembler::Fail;
2458  case 0:
2459  Inst.addOperand(MCOperand::createReg(Mips::A1));
2460  Inst.addOperand(MCOperand::createReg(Mips::A2));
2461  break;
2462  case 1:
2463  Inst.addOperand(MCOperand::createReg(Mips::A1));
2464  Inst.addOperand(MCOperand::createReg(Mips::A3));
2465  break;
2466  case 2:
2467  Inst.addOperand(MCOperand::createReg(Mips::A2));
2468  Inst.addOperand(MCOperand::createReg(Mips::A3));
2469  break;
2470  case 3:
2471  Inst.addOperand(MCOperand::createReg(Mips::A0));
2472  Inst.addOperand(MCOperand::createReg(Mips::S5));
2473  break;
2474  case 4:
2475  Inst.addOperand(MCOperand::createReg(Mips::A0));
2476  Inst.addOperand(MCOperand::createReg(Mips::S6));
2477  break;
2478  case 5:
2479  Inst.addOperand(MCOperand::createReg(Mips::A0));
2480  Inst.addOperand(MCOperand::createReg(Mips::A1));
2481  break;
2482  case 6:
2483  Inst.addOperand(MCOperand::createReg(Mips::A0));
2484  Inst.addOperand(MCOperand::createReg(Mips::A2));
2485  break;
2486  case 7:
2487  Inst.addOperand(MCOperand::createReg(Mips::A0));
2488  Inst.addOperand(MCOperand::createReg(Mips::A3));
2489  break;
2490  }
2491 
2492  return MCDisassembler::Success;
2493 }
2494 
2495 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2496  uint64_t Address, const void *Decoder) {
2497  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2498  return MCDisassembler::Success;
2499 }
2500 
2501 template <typename InsnType>
2503  uint64_t Address,
2504  const void *Decoder) {
2505  // We have:
2506  // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2507  // Invalid if rt == 0
2508  // BGTZALC_MMR6 if rs == 0 && rt != 0
2509  // BLTZALC_MMR6 if rs != 0 && rs == rt
2510  // BLTUC_MMR6 if rs != 0 && rs != rt
2511 
2512  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2513  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2514  InsnType Imm = 0;
2515  bool HasRs = false;
2516  bool HasRt = false;
2517 
2518  if (Rt == 0)
2519  return MCDisassembler::Fail;
2520  else if (Rs == 0) {
2521  MI.setOpcode(Mips::BGTZALC_MMR6);
2522  HasRt = true;
2523  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2524  }
2525  else if (Rs == Rt) {
2526  MI.setOpcode(Mips::BLTZALC_MMR6);
2527  HasRs = true;
2528  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2529  }
2530  else {
2531  MI.setOpcode(Mips::BLTUC_MMR6);
2532  HasRs = true;
2533  HasRt = true;
2534  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2535  }
2536 
2537  if (HasRs)
2538  MI.addOperand(
2539  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2540 
2541  if (HasRt)
2542  MI.addOperand(
2543  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2544 
2546 
2547  return MCDisassembler::Success;
2548 }
2549 
2550 template <typename InsnType>
2552  uint64_t Address,
2553  const void *Decoder) {
2554  // We have:
2555  // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2556  // Invalid if rt == 0
2557  // BLEZALC_MMR6 if rs == 0 && rt != 0
2558  // BGEZALC_MMR6 if rs == rt && rt != 0
2559  // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2560 
2561  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2562  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2563  InsnType Imm = 0;
2564  bool HasRs = false;
2565 
2566  if (Rt == 0)
2567  return MCDisassembler::Fail;
2568  else if (Rs == 0) {
2569  MI.setOpcode(Mips::BLEZALC_MMR6);
2570  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2571  }
2572  else if (Rs == Rt) {
2573  MI.setOpcode(Mips::BGEZALC_MMR6);
2574  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2575  }
2576  else {
2577  HasRs = true;
2578  MI.setOpcode(Mips::BGEUC_MMR6);
2579  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2580  }
2581 
2582  if (HasRs)
2583  MI.addOperand(
2584  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2585  MI.addOperand(
2586  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2587 
2589 
2590  return MCDisassembler::Success;
2591 }
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn&#39;t handle.
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned Reg
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Target & getTheMipselTarget()
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
SI optimize exec mask operations pre RA
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
const FeatureBitset & getFeatureBits() const
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:63
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Target & getTheMips64Target()
const RegList & Regs
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int64_t getImm() const
Definition: MCInst.h:76
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Target & getTheMips64elTarget()
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
void setOpcode(unsigned Op)
Definition: MCInst.h:173
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness...
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheMipsTarget()
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Generic base class for all target subtargets.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:749
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:73
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:238
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Definition: MCInst.h:174
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_DEBUG(X)
Definition: Debug.h:119
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)