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MipsDisassembler.cpp
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1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Mips.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/Debug.h"
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mips-disassembler"
35 
37 
38 namespace {
39 
40 class MipsDisassembler : public MCDisassembler {
41  bool IsMicroMips;
42  bool IsBigEndian;
43 
44 public:
45  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46  : MCDisassembler(STI, Ctx),
47  IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
48  IsBigEndian(IsBigEndian) {}
49 
50  bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52  bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
53 
54  bool hasMips32r6() const {
55  return STI.getFeatureBits()[Mips::FeatureMips32r6];
56  }
57 
58  bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
59 
60  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
61 
62  bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
63 
64  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
65 
66  bool hasCOP3() const {
67  // Only present in MIPS-I and MIPS-II
68  return !hasMips32() && !hasMips3();
69  }
70 
71  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
72  ArrayRef<uint8_t> Bytes, uint64_t Address,
73  raw_ostream &VStream,
74  raw_ostream &CStream) const override;
75 };
76 
77 } // end anonymous namespace
78 
79 // Forward declare these because the autogenerated code will reference them.
80 // Definitions are further down.
82  unsigned RegNo,
83  uint64_t Address,
84  const void *Decoder);
85 
87  unsigned RegNo,
88  uint64_t Address,
89  const void *Decoder);
90 
92  unsigned RegNo,
93  uint64_t Address,
94  const void *Decoder);
95 
97  unsigned RegNo,
98  uint64_t Address,
99  const void *Decoder);
100 
102  unsigned RegNo,
103  uint64_t Address,
104  const void *Decoder);
105 
107  unsigned RegNo,
108  uint64_t Address,
109  const void *Decoder);
110 
112  unsigned Insn,
113  uint64_t Address,
114  const void *Decoder);
115 
117  unsigned RegNo,
118  uint64_t Address,
119  const void *Decoder);
120 
122  unsigned RegNo,
123  uint64_t Address,
124  const void *Decoder);
125 
127  unsigned RegNo,
128  uint64_t Address,
129  const void *Decoder);
130 
132  unsigned RegNo,
133  uint64_t Address,
134  const void *Decoder);
135 
137  unsigned RegNo,
138  uint64_t Address,
139  const void *Decoder);
140 
141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
142  uint64_t Address,
143  const void *Decoder);
144 
146  unsigned Insn,
147  uint64_t Address,
148  const void *Decoder);
149 
151  unsigned RegNo,
152  uint64_t Address,
153  const void *Decoder);
154 
156  unsigned RegNo,
157  uint64_t Address,
158  const void *Decoder);
159 
161  unsigned RegNo,
162  uint64_t Address,
163  const void *Decoder);
164 
166  unsigned RegNo,
167  uint64_t Address,
168  const void *Decoder);
169 
171  unsigned RegNo,
172  uint64_t Address,
173  const void *Decoder);
174 
176  unsigned RegNo,
177  uint64_t Address,
178  const void *Decoder);
179 
181  unsigned RegNo,
182  uint64_t Address,
183  const void *Decoder);
184 
186  unsigned RegNo,
187  uint64_t Address,
188  const void *Decoder);
189 
191  unsigned RegNo,
192  uint64_t Address,
193  const void *Decoder);
194 
196  unsigned RegNo,
197  uint64_t Address,
198  const void *Decoder);
199 
201  unsigned RegNo,
202  uint64_t Address,
203  const void *Decoder);
204 
206  unsigned Offset,
207  uint64_t Address,
208  const void *Decoder);
209 
211  unsigned Offset,
212  uint64_t Address,
213  const void *Decoder);
214 
216  unsigned Insn,
217  uint64_t Address,
218  const void *Decoder);
219 
221  unsigned Offset,
222  uint64_t Address,
223  const void *Decoder);
224 
226  unsigned Offset,
227  uint64_t Address,
228  const void *Decoder);
229 
231  unsigned Offset,
232  uint64_t Address,
233  const void *Decoder);
234 
235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
236 // shifted left by 1 bit.
238  unsigned Offset,
239  uint64_t Address,
240  const void *Decoder);
241 
242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
243 // shifted left by 1 bit.
245  unsigned Offset,
246  uint64_t Address,
247  const void *Decoder);
248 
249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
250 // shifted left by 1 bit.
252  unsigned Offset,
253  uint64_t Address,
254  const void *Decoder);
255 
256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
257 // shifted left by 1 bit.
259  unsigned Offset,
260  uint64_t Address,
261  const void *Decoder);
262 
263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
264 // shifted left by 1 bit.
266  unsigned Insn,
267  uint64_t Address,
268  const void *Decoder);
269 
270 static DecodeStatus DecodeMem(MCInst &Inst,
271  unsigned Insn,
272  uint64_t Address,
273  const void *Decoder);
274 
275 static DecodeStatus DecodeMemEVA(MCInst &Inst,
276  unsigned Insn,
277  uint64_t Address,
278  const void *Decoder);
279 
280 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
281  unsigned Insn,
282  uint64_t Address,
283  const void *Decoder);
284 
286  unsigned Insn,
287  uint64_t Address,
288  const void *Decoder);
289 
290 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
291  const void *Decoder);
292 
294  unsigned Insn,
295  uint64_t Address,
296  const void *Decoder);
297 
298 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
299  unsigned Insn,
300  uint64_t Address,
301  const void *Decoder);
302 
304  unsigned Insn,
305  uint64_t Address,
306  const void *Decoder);
307 
308 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
309  unsigned Insn,
310  uint64_t Address,
311  const void *Decoder);
312 
313 static DecodeStatus DecodeSyncI(MCInst &Inst,
314  unsigned Insn,
315  uint64_t Address,
316  const void *Decoder);
317 
318 static DecodeStatus DecodeSynciR6(MCInst &Inst,
319  unsigned Insn,
320  uint64_t Address,
321  const void *Decoder);
322 
323 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
324  uint64_t Address, const void *Decoder);
325 
326 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
327  unsigned Insn,
328  uint64_t Address,
329  const void *Decoder);
330 
332  unsigned Insn,
333  uint64_t Address,
334  const void *Decoder);
335 
337  unsigned Insn,
338  uint64_t Address,
339  const void *Decoder);
340 
342  unsigned Insn,
343  uint64_t Address,
344  const void *Decoder);
345 
346 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
347  unsigned Insn,
348  uint64_t Address,
349  const void *Decoder);
350 
352  unsigned Insn,
353  uint64_t Address,
354  const void *Decoder);
355 
357  unsigned Insn,
358  uint64_t Address,
359  const void *Decoder);
360 
361 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
362  uint64_t Address,
363  const void *Decoder);
364 
365 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
366  uint64_t Address,
367  const void *Decoder);
368 
369 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
370  const void *Decoder);
371 
372 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
373  const void *Decoder);
374 
375 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
376  uint64_t Address, const void *Decoder);
377 
378 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
379  uint64_t Address,
380  const void *Decoder);
381 
383  unsigned Insn,
384  uint64_t Address,
385  const void *Decoder);
386 
388  unsigned Value,
389  uint64_t Address,
390  const void *Decoder);
391 
392 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
393  unsigned Value,
394  uint64_t Address,
395  const void *Decoder);
396 
398  unsigned Value,
399  uint64_t Address,
400  const void *Decoder);
401 
402 template <unsigned Bits, int Offset, int Scale>
403 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
404  uint64_t Address,
405  const void *Decoder);
406 
407 template <unsigned Bits, int Offset>
408 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
409  uint64_t Address,
410  const void *Decoder) {
411  return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
412  Decoder);
413 }
414 
415 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
416 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
417  uint64_t Address,
418  const void *Decoder);
419 
420 static DecodeStatus DecodeInsSize(MCInst &Inst,
421  unsigned Insn,
422  uint64_t Address,
423  const void *Decoder);
424 
425 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
426  uint64_t Address, const void *Decoder);
427 
428 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
429  uint64_t Address, const void *Decoder);
430 
431 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
432  uint64_t Address, const void *Decoder);
433 
434 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
435  uint64_t Address, const void *Decoder);
436 
437 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
438  uint64_t Address, const void *Decoder);
439 
440 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
441 /// handle.
442 template <typename InsnType>
443 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
444  const void *Decoder);
445 
446 template <typename InsnType>
447 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
448  const void *Decoder);
449 
450 template <typename InsnType>
451 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
452  const void *Decoder);
453 
454 template <typename InsnType>
455 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
456  const void *Decoder);
457 
458 template <typename InsnType>
459 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
460  const void *Decoder);
461 
462 template <typename InsnType>
463 static DecodeStatus
464 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
465  const void *Decoder);
466 
467 template <typename InsnType>
468 static DecodeStatus
469 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
470  const void *Decoder);
471 
472 template <typename InsnType>
473 static DecodeStatus
474 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
475  const void *Decoder);
476 
477 template <typename InsnType>
478 static DecodeStatus
479 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
480  const void *Decoder);
481 
482 template <typename InsnType>
483 static DecodeStatus
484 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
485  const void *Decoder);
486 
487 template <typename InsnType>
488 static DecodeStatus
489 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
490  const void *Decoder);
491 
492 template <typename InsnType>
493 static DecodeStatus
494 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
495  const void *Decoder);
496 
497 template <typename InsnType>
498 static DecodeStatus
499 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
500  const void *Decoder);
501 
502 template <typename InsnType>
503 static DecodeStatus
504 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
505  const void *Decoder);
506 
507 template <typename InsnType>
508 static DecodeStatus
509 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
510  const void *Decoder);
511 
512 template <typename InsnType>
513 static DecodeStatus
514 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
515  const void *Decoder);
516 
517 template <typename InsnType>
518 static DecodeStatus
519 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
520  const void *Decoder);
521 
522 template <typename InsnType>
523 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
524  const void *Decoder);
525 
526 template <typename InsnType>
527 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
528  const void *Decoder);
529 
530 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
531  uint64_t Address,
532  const void *Decoder);
533 
534 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
535  uint64_t Address,
536  const void *Decoder);
537 
538 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
539  uint64_t Address,
540  const void *Decoder);
541 
542 namespace llvm {
543 
548 
549 } // end namespace llvm
550 
552  const Target &T,
553  const MCSubtargetInfo &STI,
554  MCContext &Ctx) {
555  return new MipsDisassembler(STI, Ctx, true);
556 }
557 
559  const Target &T,
560  const MCSubtargetInfo &STI,
561  MCContext &Ctx) {
562  return new MipsDisassembler(STI, Ctx, false);
563 }
564 
566  // Register the disassembler.
575 }
576 
577 #include "MipsGenDisassemblerTables.inc"
578 
579 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
580  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
581  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
582  return *(RegInfo->getRegClass(RC).begin() + RegNo);
583 }
584 
585 template <typename InsnType>
586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
587  const void *Decoder) {
588  using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
589 
590  // The size of the n field depends on the element size
591  // The register class also depends on this.
592  InsnType tmp = fieldFromInstruction(insn, 17, 5);
593  unsigned NSize = 0;
594  DecodeFN RegDecoder = nullptr;
595  if ((tmp & 0x18) == 0x00) { // INSVE_B
596  NSize = 4;
597  RegDecoder = DecodeMSA128BRegisterClass;
598  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
599  NSize = 3;
600  RegDecoder = DecodeMSA128HRegisterClass;
601  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
602  NSize = 2;
603  RegDecoder = DecodeMSA128WRegisterClass;
604  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
605  NSize = 1;
606  RegDecoder = DecodeMSA128DRegisterClass;
607  } else
608  llvm_unreachable("Invalid encoding");
609 
610  assert(NSize != 0 && RegDecoder != nullptr);
611 
612  // $wd
613  tmp = fieldFromInstruction(insn, 6, 5);
614  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
615  return MCDisassembler::Fail;
616  // $wd_in
617  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
618  return MCDisassembler::Fail;
619  // $n
620  tmp = fieldFromInstruction(insn, 16, NSize);
622  // $ws
623  tmp = fieldFromInstruction(insn, 11, 5);
624  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
625  return MCDisassembler::Fail;
626  // $n2
628 
630 }
631 
632 template <typename InsnType>
633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
634  const void *Decoder) {
635  InsnType Rs = fieldFromInstruction(insn, 16, 5);
636  InsnType Imm = fieldFromInstruction(insn, 0, 16);
637  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
638  Rs)));
639  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
640  Rs)));
642 
644 }
645 
646 template <typename InsnType>
647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
648  const void *Decoder) {
649  InsnType Rs = fieldFromInstruction(insn, 21, 5);
650  InsnType Imm = fieldFromInstruction(insn, 0, 16);
651  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
652  Rs)));
653  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
654  Rs)));
656 
658 }
659 
660 template <typename InsnType>
661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
662  uint64_t Address,
663  const void *Decoder) {
664  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
665  // (otherwise we would have matched the ADDI instruction from the earlier
666  // ISA's instead).
667  //
668  // We have:
669  // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
670  // BOVC if rs >= rt
671  // BEQZALC if rs == 0 && rt != 0
672  // BEQC if rs < rt && rs != 0
673 
674  InsnType Rs = fieldFromInstruction(insn, 21, 5);
675  InsnType Rt = fieldFromInstruction(insn, 16, 5);
676  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
677  bool HasRs = false;
678 
679  if (Rs >= Rt) {
680  MI.setOpcode(Mips::BOVC);
681  HasRs = true;
682  } else if (Rs != 0 && Rs < Rt) {
683  MI.setOpcode(Mips::BEQC);
684  HasRs = true;
685  } else
686  MI.setOpcode(Mips::BEQZALC);
687 
688  if (HasRs)
689  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
690  Rs)));
691 
692  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
693  Rt)));
695 
697 }
698 
699 template <typename InsnType>
701  uint64_t Address,
702  const void *Decoder) {
703  InsnType Rt = fieldFromInstruction(insn, 21, 5);
704  InsnType Rs = fieldFromInstruction(insn, 16, 5);
705  int64_t Imm = 0;
706 
707  if (Rs >= Rt) {
708  MI.setOpcode(Mips::BOVC_MMR6);
709  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
710  Rt)));
711  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
712  Rs)));
713  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
714  } else if (Rs != 0 && Rs < Rt) {
715  MI.setOpcode(Mips::BEQC_MMR6);
716  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
717  Rs)));
718  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
719  Rt)));
720  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
721  } else {
722  MI.setOpcode(Mips::BEQZALC_MMR6);
723  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
724  Rt)));
725  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
726  }
727 
729 
731 }
732 
733 template <typename InsnType>
734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
735  uint64_t Address,
736  const void *Decoder) {
737  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
738  // (otherwise we would have matched the ADDI instruction from the earlier
739  // ISA's instead).
740  //
741  // We have:
742  // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
743  // BNVC if rs >= rt
744  // BNEZALC if rs == 0 && rt != 0
745  // BNEC if rs < rt && rs != 0
746 
747  InsnType Rs = fieldFromInstruction(insn, 21, 5);
748  InsnType Rt = fieldFromInstruction(insn, 16, 5);
749  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
750  bool HasRs = false;
751 
752  if (Rs >= Rt) {
753  MI.setOpcode(Mips::BNVC);
754  HasRs = true;
755  } else if (Rs != 0 && Rs < Rt) {
756  MI.setOpcode(Mips::BNEC);
757  HasRs = true;
758  } else
759  MI.setOpcode(Mips::BNEZALC);
760 
761  if (HasRs)
762  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
763  Rs)));
764 
765  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
766  Rt)));
768 
770 }
771 
772 template <typename InsnType>
774  uint64_t Address,
775  const void *Decoder) {
776  InsnType Rt = fieldFromInstruction(insn, 21, 5);
777  InsnType Rs = fieldFromInstruction(insn, 16, 5);
778  int64_t Imm = 0;
779 
780  if (Rs >= Rt) {
781  MI.setOpcode(Mips::BNVC_MMR6);
782  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
783  Rt)));
784  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
785  Rs)));
786  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
787  } else if (Rs != 0 && Rs < Rt) {
788  MI.setOpcode(Mips::BNEC_MMR6);
789  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
790  Rs)));
791  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
792  Rt)));
793  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
794  } else {
795  MI.setOpcode(Mips::BNEZALC_MMR6);
796  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
797  Rt)));
798  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
799  }
800 
802 
804 }
805 
806 template <typename InsnType>
808  uint64_t Address,
809  const void *Decoder) {
810  // We have:
811  // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
812  // Invalid if rt == 0
813  // BGTZC_MMR6 if rs == 0 && rt != 0
814  // BLTZC_MMR6 if rs == rt && rt != 0
815  // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
816 
817  InsnType Rt = fieldFromInstruction(insn, 21, 5);
818  InsnType Rs = fieldFromInstruction(insn, 16, 5);
819  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
820  bool HasRs = false;
821 
822  if (Rt == 0)
823  return MCDisassembler::Fail;
824  else if (Rs == 0)
825  MI.setOpcode(Mips::BGTZC_MMR6);
826  else if (Rs == Rt)
827  MI.setOpcode(Mips::BLTZC_MMR6);
828  else {
829  MI.setOpcode(Mips::BLTC_MMR6);
830  HasRs = true;
831  }
832 
833  if (HasRs)
834  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
835  Rs)));
836 
837  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
838  Rt)));
839 
841 
843 }
844 
845 template <typename InsnType>
847  uint64_t Address,
848  const void *Decoder) {
849  // We have:
850  // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
851  // Invalid if rt == 0
852  // BLEZC_MMR6 if rs == 0 && rt != 0
853  // BGEZC_MMR6 if rs == rt && rt != 0
854  // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
855 
856  InsnType Rt = fieldFromInstruction(insn, 21, 5);
857  InsnType Rs = fieldFromInstruction(insn, 16, 5);
858  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
859  bool HasRs = false;
860 
861  if (Rt == 0)
862  return MCDisassembler::Fail;
863  else if (Rs == 0)
864  MI.setOpcode(Mips::BLEZC_MMR6);
865  else if (Rs == Rt)
866  MI.setOpcode(Mips::BGEZC_MMR6);
867  else {
868  HasRs = true;
869  MI.setOpcode(Mips::BGEC_MMR6);
870  }
871 
872  if (HasRs)
873  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
874  Rs)));
875 
876  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
877  Rt)));
878 
880 
882 }
883 
884 template <typename InsnType>
885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
886  uint64_t Address,
887  const void *Decoder) {
888  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
889  // (otherwise we would have matched the BLEZL instruction from the earlier
890  // ISA's instead).
891  //
892  // We have:
893  // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
894  // Invalid if rs == 0
895  // BLEZC if rs == 0 && rt != 0
896  // BGEZC if rs == rt && rt != 0
897  // BGEC if rs != rt && rs != 0 && rt != 0
898 
899  InsnType Rs = fieldFromInstruction(insn, 21, 5);
900  InsnType Rt = fieldFromInstruction(insn, 16, 5);
901  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
902  bool HasRs = false;
903 
904  if (Rt == 0)
905  return MCDisassembler::Fail;
906  else if (Rs == 0)
907  MI.setOpcode(Mips::BLEZC);
908  else if (Rs == Rt)
909  MI.setOpcode(Mips::BGEZC);
910  else {
911  HasRs = true;
912  MI.setOpcode(Mips::BGEC);
913  }
914 
915  if (HasRs)
916  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
917  Rs)));
918 
919  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
920  Rt)));
921 
923 
925 }
926 
927 template <typename InsnType>
928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
929  uint64_t Address,
930  const void *Decoder) {
931  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
932  // (otherwise we would have matched the BGTZL instruction from the earlier
933  // ISA's instead).
934  //
935  // We have:
936  // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
937  // Invalid if rs == 0
938  // BGTZC if rs == 0 && rt != 0
939  // BLTZC if rs == rt && rt != 0
940  // BLTC if rs != rt && rs != 0 && rt != 0
941 
942  bool HasRs = false;
943 
944  InsnType Rs = fieldFromInstruction(insn, 21, 5);
945  InsnType Rt = fieldFromInstruction(insn, 16, 5);
946  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
947 
948  if (Rt == 0)
949  return MCDisassembler::Fail;
950  else if (Rs == 0)
951  MI.setOpcode(Mips::BGTZC);
952  else if (Rs == Rt)
953  MI.setOpcode(Mips::BLTZC);
954  else {
955  MI.setOpcode(Mips::BLTC);
956  HasRs = true;
957  }
958 
959  if (HasRs)
960  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
961  Rs)));
962 
963  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
964  Rt)));
965 
967 
969 }
970 
971 template <typename InsnType>
972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
973  uint64_t Address,
974  const void *Decoder) {
975  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
976  // (otherwise we would have matched the BGTZ instruction from the earlier
977  // ISA's instead).
978  //
979  // We have:
980  // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
981  // BGTZ if rt == 0
982  // BGTZALC if rs == 0 && rt != 0
983  // BLTZALC if rs != 0 && rs == rt
984  // BLTUC if rs != 0 && rs != rt
985 
986  InsnType Rs = fieldFromInstruction(insn, 21, 5);
987  InsnType Rt = fieldFromInstruction(insn, 16, 5);
988  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
989  bool HasRs = false;
990  bool HasRt = false;
991 
992  if (Rt == 0) {
993  MI.setOpcode(Mips::BGTZ);
994  HasRs = true;
995  } else if (Rs == 0) {
996  MI.setOpcode(Mips::BGTZALC);
997  HasRt = true;
998  } else if (Rs == Rt) {
999  MI.setOpcode(Mips::BLTZALC);
1000  HasRs = true;
1001  } else {
1002  MI.setOpcode(Mips::BLTUC);
1003  HasRs = true;
1004  HasRt = true;
1005  }
1006 
1007  if (HasRs)
1008  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1009  Rs)));
1010 
1011  if (HasRt)
1012  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1013  Rt)));
1014 
1016 
1017  return MCDisassembler::Success;
1018 }
1019 
1020 template <typename InsnType>
1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1022  uint64_t Address,
1023  const void *Decoder) {
1024  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1025  // (otherwise we would have matched the BLEZL instruction from the earlier
1026  // ISA's instead).
1027  //
1028  // We have:
1029  // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1030  // Invalid if rs == 0
1031  // BLEZALC if rs == 0 && rt != 0
1032  // BGEZALC if rs == rt && rt != 0
1033  // BGEUC if rs != rt && rs != 0 && rt != 0
1034 
1035  InsnType Rs = fieldFromInstruction(insn, 21, 5);
1036  InsnType Rt = fieldFromInstruction(insn, 16, 5);
1037  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1038  bool HasRs = false;
1039 
1040  if (Rt == 0)
1041  return MCDisassembler::Fail;
1042  else if (Rs == 0)
1043  MI.setOpcode(Mips::BLEZALC);
1044  else if (Rs == Rt)
1045  MI.setOpcode(Mips::BGEZALC);
1046  else {
1047  HasRs = true;
1048  MI.setOpcode(Mips::BGEUC);
1049  }
1050 
1051  if (HasRs)
1052  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1053  Rs)));
1054  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1055  Rt)));
1056 
1058 
1059  return MCDisassembler::Success;
1060 }
1061 
1062 // Override the generated disassembler to produce DEXT all the time. This is
1063 // for feature / behaviour parity with binutils.
1064 template <typename InsnType>
1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1066  const void *Decoder) {
1067  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1068  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1069  unsigned Size = 0;
1070  unsigned Pos = 0;
1071  bool IsMicroMips = false;
1072 
1073  switch (MI.getOpcode()) {
1074  case Mips::DEXT_MM64R6:
1075  IsMicroMips = true;
1077  case Mips::DEXT:
1078  Pos = Lsb;
1079  Size = Msbd + 1;
1080  break;
1081  case Mips::DEXTM_MM64R6:
1082  IsMicroMips = true;
1084  case Mips::DEXTM:
1085  Pos = Lsb;
1086  Size = Msbd + 1 + 32;
1087  break;
1088  case Mips::DEXTU_MM64R6:
1089  IsMicroMips = true;
1091  case Mips::DEXTU:
1092  Pos = Lsb + 32;
1093  Size = Msbd + 1;
1094  break;
1095  default:
1096  llvm_unreachable("Unknown DEXT instruction!");
1097  }
1098 
1099  MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT);
1100 
1101  // Although the format of the instruction is similar, rs and rt are swapped
1102  // for microMIPS64R6.
1103  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1104  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1105  if (IsMicroMips)
1106  std::swap(Rs, Rt);
1107 
1108  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1109  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1111  MI.addOperand(MCOperand::createImm(Size));
1112 
1113  return MCDisassembler::Success;
1114 }
1115 
1116 // Override the generated disassembler to produce DINS all the time. This is
1117 // for feature / behaviour parity with binutils.
1118 template <typename InsnType>
1119 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1120  const void *Decoder) {
1121  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1122  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1123  unsigned Size = 0;
1124  unsigned Pos = 0;
1125  bool IsMicroMips = false;
1126 
1127  switch (MI.getOpcode()) {
1128  case Mips::DINS_MM64R6:
1129  IsMicroMips = true;
1131  case Mips::DINS:
1132  Pos = Lsb;
1133  Size = Msbd + 1 - Pos;
1134  break;
1135  case Mips::DINSM_MM64R6:
1136  IsMicroMips = true;
1138  case Mips::DINSM:
1139  Pos = Lsb;
1140  Size = Msbd + 33 - Pos;
1141  break;
1142  case Mips::DINSU_MM64R6:
1143  IsMicroMips = true;
1145  case Mips::DINSU:
1146  Pos = Lsb + 32;
1147  // mbsd = pos + size - 33
1148  // mbsd - pos + 33 = size
1149  Size = Msbd + 33 - Pos;
1150  break;
1151  default:
1152  llvm_unreachable("Unknown DINS instruction!");
1153  }
1154 
1155  // Although the format of the instruction is similar, rs and rt are swapped
1156  // for microMIPS64R6.
1157  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1158  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1159  if (IsMicroMips)
1160  std::swap(Rs, Rt);
1161 
1162  MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS);
1163  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1164  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1166  MI.addOperand(MCOperand::createImm(Size));
1167 
1168  return MCDisassembler::Success;
1169 }
1170 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1171 /// according to the given endianness.
1173  uint64_t &Size, uint32_t &Insn,
1174  bool IsBigEndian) {
1175  // We want to read exactly 2 Bytes of data.
1176  if (Bytes.size() < 2) {
1177  Size = 0;
1178  return MCDisassembler::Fail;
1179  }
1180 
1181  if (IsBigEndian) {
1182  Insn = (Bytes[0] << 8) | Bytes[1];
1183  } else {
1184  Insn = (Bytes[1] << 8) | Bytes[0];
1185  }
1186 
1187  return MCDisassembler::Success;
1188 }
1189 
1190 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1191 /// according to the given endianness.
1193  uint64_t &Size, uint32_t &Insn,
1194  bool IsBigEndian, bool IsMicroMips) {
1195  // We want to read exactly 4 Bytes of data.
1196  if (Bytes.size() < 4) {
1197  Size = 0;
1198  return MCDisassembler::Fail;
1199  }
1200 
1201  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1202  // always precede the low 16 bits in the instruction stream (that is, they
1203  // are placed at lower addresses in the instruction stream).
1204  //
1205  // microMIPS byte ordering:
1206  // Big-endian: 0 | 1 | 2 | 3
1207  // Little-endian: 1 | 0 | 3 | 2
1208 
1209  if (IsBigEndian) {
1210  // Encoded as a big-endian 32-bit word in the stream.
1211  Insn =
1212  (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1213  } else {
1214  if (IsMicroMips) {
1215  Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1216  (Bytes[1] << 24);
1217  } else {
1218  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1219  (Bytes[3] << 24);
1220  }
1221  }
1222 
1223  return MCDisassembler::Success;
1224 }
1225 
1226 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1227  ArrayRef<uint8_t> Bytes,
1228  uint64_t Address,
1229  raw_ostream &VStream,
1230  raw_ostream &CStream) const {
1231  uint32_t Insn;
1232  DecodeStatus Result;
1233  Size = 0;
1234 
1235  if (IsMicroMips) {
1236  Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1237  if (Result == MCDisassembler::Fail)
1238  return MCDisassembler::Fail;
1239 
1240  if (hasMips32r6()) {
1241  DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1242  // Calling the auto-generated decoder function for microMIPS32R6
1243  // (and microMIPS64R6) 16-bit instructions.
1244  Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1245  Address, this, STI);
1246  if (Result != MCDisassembler::Fail) {
1247  Size = 2;
1248  return Result;
1249  }
1250  }
1251 
1252  DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1253  // Calling the auto-generated decoder function for microMIPS 16-bit
1254  // instructions.
1255  Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1256  this, STI);
1257  if (Result != MCDisassembler::Fail) {
1258  Size = 2;
1259  return Result;
1260  }
1261 
1262  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1263  if (Result == MCDisassembler::Fail)
1264  return MCDisassembler::Fail;
1265 
1266  if (hasMips32r6()) {
1267  DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1268  // Calling the auto-generated decoder function.
1269  Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1270  this, STI);
1271  if (Result != MCDisassembler::Fail) {
1272  Size = 4;
1273  return Result;
1274  }
1275  }
1276 
1277  DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1278  // Calling the auto-generated decoder function.
1279  Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1280  this, STI);
1281  if (Result != MCDisassembler::Fail) {
1282  Size = 4;
1283  return Result;
1284  }
1285 
1286  if (hasMips32r6() && isFP64()) {
1287  DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
1288  Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
1289  Address, this, STI);
1290  if (Result != MCDisassembler::Fail) {
1291  Size = 4;
1292  return Result;
1293  }
1294  }
1295 
1296  // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1297  // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1298  // could form a valid instruction. The two bytes we rejected as an
1299  // instruction could have actually beeen an inline constant pool that is
1300  // unconditionally branched over.
1301  Size = 2;
1302  return MCDisassembler::Fail;
1303  }
1304 
1305  // Attempt to read the instruction so that we can attempt to decode it. If
1306  // the buffer is not 4 bytes long, let the higher level logic figure out
1307  // what to do with a size of zero and MCDisassembler::Fail.
1308  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1309  if (Result == MCDisassembler::Fail)
1310  return MCDisassembler::Fail;
1311 
1312  // The only instruction size for standard encoded MIPS.
1313  Size = 4;
1314 
1315  if (hasCOP3()) {
1316  DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1317  Result =
1318  decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1319  if (Result != MCDisassembler::Fail)
1320  return Result;
1321  }
1322 
1323  if (hasMips32r6() && isGP64()) {
1324  DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1325  Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1326  Address, this, STI);
1327  if (Result != MCDisassembler::Fail)
1328  return Result;
1329  }
1330 
1331  if (hasMips32r6() && isPTR64()) {
1332  DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1333  Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1334  Address, this, STI);
1335  if (Result != MCDisassembler::Fail)
1336  return Result;
1337  }
1338 
1339  if (hasMips32r6()) {
1340  DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1341  Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1342  Address, this, STI);
1343  if (Result != MCDisassembler::Fail)
1344  return Result;
1345  }
1346 
1347  if (hasMips2() && isPTR64()) {
1348  DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1349  Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1350  Address, this, STI);
1351  if (Result != MCDisassembler::Fail)
1352  return Result;
1353  }
1354 
1355  if (hasCnMips()) {
1356  DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1357  Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1358  Address, this, STI);
1359  if (Result != MCDisassembler::Fail)
1360  return Result;
1361  }
1362 
1363  if (isGP64()) {
1364  DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1365  Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1366  Address, this, STI);
1367  if (Result != MCDisassembler::Fail)
1368  return Result;
1369  }
1370 
1371  DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1372  // Calling the auto-generated decoder function.
1373  Result =
1374  decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1375  if (Result != MCDisassembler::Fail)
1376  return Result;
1377 
1378  return MCDisassembler::Fail;
1379 }
1380 
1382  unsigned RegNo,
1383  uint64_t Address,
1384  const void *Decoder) {
1385  return MCDisassembler::Fail;
1386 }
1387 
1389  unsigned RegNo,
1390  uint64_t Address,
1391  const void *Decoder) {
1392  if (RegNo > 31)
1393  return MCDisassembler::Fail;
1394 
1395  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1396  Inst.addOperand(MCOperand::createReg(Reg));
1397  return MCDisassembler::Success;
1398 }
1399 
1401  unsigned RegNo,
1402  uint64_t Address,
1403  const void *Decoder) {
1404  if (RegNo > 7)
1405  return MCDisassembler::Fail;
1406  unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1407  Inst.addOperand(MCOperand::createReg(Reg));
1408  return MCDisassembler::Success;
1409 }
1410 
1412  unsigned RegNo,
1413  uint64_t Address,
1414  const void *Decoder) {
1415  if (RegNo > 7)
1416  return MCDisassembler::Fail;
1417  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1418  Inst.addOperand(MCOperand::createReg(Reg));
1419  return MCDisassembler::Success;
1420 }
1421 
1423  unsigned RegNo,
1424  uint64_t Address,
1425  const void *Decoder) {
1426  if (RegNo > 7)
1427  return MCDisassembler::Fail;
1428  unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1429  Inst.addOperand(MCOperand::createReg(Reg));
1430  return MCDisassembler::Success;
1431 }
1432 
1434  unsigned RegNo,
1435  uint64_t Address,
1436  const void *Decoder) {
1437  if (RegNo > 31)
1438  return MCDisassembler::Fail;
1439  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1440  Inst.addOperand(MCOperand::createReg(Reg));
1441  return MCDisassembler::Success;
1442 }
1443 
1445  unsigned RegNo,
1446  uint64_t Address,
1447  const void *Decoder) {
1448  if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1449  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1450 
1451  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1452 }
1453 
1455  unsigned RegNo,
1456  uint64_t Address,
1457  const void *Decoder) {
1458  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1459 }
1460 
1462  unsigned RegNo,
1463  uint64_t Address,
1464  const void *Decoder) {
1465  if (RegNo > 31)
1466  return MCDisassembler::Fail;
1467 
1468  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1469  Inst.addOperand(MCOperand::createReg(Reg));
1470  return MCDisassembler::Success;
1471 }
1472 
1474  unsigned RegNo,
1475  uint64_t Address,
1476  const void *Decoder) {
1477  if (RegNo > 31)
1478  return MCDisassembler::Fail;
1479 
1480  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1481  Inst.addOperand(MCOperand::createReg(Reg));
1482  return MCDisassembler::Success;
1483 }
1484 
1486  unsigned RegNo,
1487  uint64_t Address,
1488  const void *Decoder) {
1489  if (RegNo > 31)
1490  return MCDisassembler::Fail;
1491  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1492  Inst.addOperand(MCOperand::createReg(Reg));
1493  return MCDisassembler::Success;
1494 }
1495 
1497  unsigned RegNo,
1498  uint64_t Address,
1499  const void *Decoder) {
1500  if (RegNo > 7)
1501  return MCDisassembler::Fail;
1502  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1503  Inst.addOperand(MCOperand::createReg(Reg));
1504  return MCDisassembler::Success;
1505 }
1506 
1507 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1508  uint64_t Address,
1509  const void *Decoder) {
1510  if (RegNo > 31)
1511  return MCDisassembler::Fail;
1512 
1513  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1514  Inst.addOperand(MCOperand::createReg(Reg));
1515  return MCDisassembler::Success;
1516 }
1517 
1519  unsigned Insn,
1520  uint64_t Address,
1521  const void *Decoder) {
1522  int Offset = SignExtend32<16>(Insn & 0xffff);
1523  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1524  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1525 
1526  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1527  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1528 
1529  if (Inst.getOpcode() == Mips::SC ||
1530  Inst.getOpcode() == Mips::SCD)
1531  Inst.addOperand(MCOperand::createReg(Reg));
1532 
1533  Inst.addOperand(MCOperand::createReg(Reg));
1534  Inst.addOperand(MCOperand::createReg(Base));
1535  Inst.addOperand(MCOperand::createImm(Offset));
1536 
1537  return MCDisassembler::Success;
1538 }
1539 
1541  unsigned Insn,
1542  uint64_t Address,
1543  const void *Decoder) {
1544  int Offset = SignExtend32<9>(Insn >> 7);
1545  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1546  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1547 
1548  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1549  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1550 
1551  if (Inst.getOpcode() == Mips::SCE)
1552  Inst.addOperand(MCOperand::createReg(Reg));
1553 
1554  Inst.addOperand(MCOperand::createReg(Reg));
1555  Inst.addOperand(MCOperand::createReg(Base));
1556  Inst.addOperand(MCOperand::createImm(Offset));
1557 
1558  return MCDisassembler::Success;
1559 }
1560 
1562  unsigned Insn,
1563  uint64_t Address,
1564  const void *Decoder) {
1565  int Offset = SignExtend32<9>(Insn & 0x1ff);
1566  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1567  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1568 
1569  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1570  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1571 
1572  Inst.addOperand(MCOperand::createReg(Reg));
1573  Inst.addOperand(MCOperand::createReg(Base));
1574  Inst.addOperand(MCOperand::createImm(Offset));
1575 
1576  return MCDisassembler::Success;
1577 }
1578 
1580  unsigned Insn,
1581  uint64_t Address,
1582  const void *Decoder) {
1583  int Offset = SignExtend32<16>(Insn & 0xffff);
1584  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1585  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1586 
1587  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1588  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1589 
1590  Inst.addOperand(MCOperand::createReg(Reg));
1591  Inst.addOperand(MCOperand::createReg(Base));
1592  Inst.addOperand(MCOperand::createImm(Offset));
1593 
1594  return MCDisassembler::Success;
1595 }
1596 
1598  unsigned Insn,
1599  uint64_t Address,
1600  const void *Decoder) {
1601  int Offset = SignExtend32<16>(Insn & 0xffff);
1602  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1603  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1604 
1605  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1606 
1607  Inst.addOperand(MCOperand::createReg(Base));
1608  Inst.addOperand(MCOperand::createImm(Offset));
1609  Inst.addOperand(MCOperand::createImm(Hint));
1610 
1611  return MCDisassembler::Success;
1612 }
1613 
1615  unsigned Insn,
1616  uint64_t Address,
1617  const void *Decoder) {
1618  int Offset = SignExtend32<12>(Insn & 0xfff);
1619  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1620  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1621 
1622  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1623 
1624  Inst.addOperand(MCOperand::createReg(Base));
1625  Inst.addOperand(MCOperand::createImm(Offset));
1626  Inst.addOperand(MCOperand::createImm(Hint));
1627 
1628  return MCDisassembler::Success;
1629 }
1630 
1632  unsigned Insn,
1633  uint64_t Address,
1634  const void *Decoder) {
1635  int Offset = SignExtend32<9>(Insn & 0x1ff);
1636  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1637  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1638 
1639  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1640 
1641  Inst.addOperand(MCOperand::createReg(Base));
1642  Inst.addOperand(MCOperand::createImm(Offset));
1643  Inst.addOperand(MCOperand::createImm(Hint));
1644 
1645  return MCDisassembler::Success;
1646 }
1647 
1649  unsigned Insn,
1650  uint64_t Address,
1651  const void *Decoder) {
1652  int Offset = SignExtend32<9>(Insn >> 7);
1653  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1654  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1655 
1656  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1657 
1658  Inst.addOperand(MCOperand::createReg(Base));
1659  Inst.addOperand(MCOperand::createImm(Offset));
1660  Inst.addOperand(MCOperand::createImm(Hint));
1661 
1662  return MCDisassembler::Success;
1663 }
1664 
1666  unsigned Insn,
1667  uint64_t Address,
1668  const void *Decoder) {
1669  int Offset = SignExtend32<9>(Insn & 0x1ff);
1670  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1671  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1672 
1673  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1674  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1675 
1676  Inst.addOperand(MCOperand::createReg(Reg));
1677  Inst.addOperand(MCOperand::createReg(Base));
1678  Inst.addOperand(MCOperand::createImm(Offset));
1679 
1680  return MCDisassembler::Success;
1681 }
1682 
1684  unsigned Insn,
1685  uint64_t Address,
1686  const void *Decoder) {
1687  int Offset = SignExtend32<16>(Insn & 0xffff);
1688  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1689 
1690  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1691 
1692  Inst.addOperand(MCOperand::createReg(Base));
1693  Inst.addOperand(MCOperand::createImm(Offset));
1694 
1695  return MCDisassembler::Success;
1696 }
1697 
1699  unsigned Insn,
1700  uint64_t Address,
1701  const void *Decoder) {
1702  int Immediate = SignExtend32<16>(Insn & 0xffff);
1703  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1704 
1705  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1706 
1707  Inst.addOperand(MCOperand::createReg(Base));
1708  Inst.addOperand(MCOperand::createImm(Immediate));
1709 
1710  return MCDisassembler::Success;
1711 }
1712 
1713 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1714  uint64_t Address, const void *Decoder) {
1715  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1716  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1717  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1718 
1719  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1720  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1721 
1722  Inst.addOperand(MCOperand::createReg(Reg));
1723  Inst.addOperand(MCOperand::createReg(Base));
1724 
1725  // The immediate field of an LD/ST instruction is scaled which means it must
1726  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1727  // data format.
1728  // .b - 1 byte
1729  // .h - 2 bytes
1730  // .w - 4 bytes
1731  // .d - 8 bytes
1732  switch(Inst.getOpcode())
1733  {
1734  default:
1735  assert(false && "Unexpected instruction");
1736  return MCDisassembler::Fail;
1737  break;
1738  case Mips::LD_B:
1739  case Mips::ST_B:
1740  Inst.addOperand(MCOperand::createImm(Offset));
1741  break;
1742  case Mips::LD_H:
1743  case Mips::ST_H:
1744  Inst.addOperand(MCOperand::createImm(Offset * 2));
1745  break;
1746  case Mips::LD_W:
1747  case Mips::ST_W:
1748  Inst.addOperand(MCOperand::createImm(Offset * 4));
1749  break;
1750  case Mips::LD_D:
1751  case Mips::ST_D:
1752  Inst.addOperand(MCOperand::createImm(Offset * 8));
1753  break;
1754  }
1755 
1756  return MCDisassembler::Success;
1757 }
1758 
1760  unsigned Insn,
1761  uint64_t Address,
1762  const void *Decoder) {
1763  unsigned Offset = Insn & 0xf;
1764  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1765  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1766 
1767  switch (Inst.getOpcode()) {
1768  case Mips::LBU16_MM:
1769  case Mips::LHU16_MM:
1770  case Mips::LW16_MM:
1771  if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1773  return MCDisassembler::Fail;
1774  break;
1775  case Mips::SB16_MM:
1776  case Mips::SB16_MMR6:
1777  case Mips::SH16_MM:
1778  case Mips::SH16_MMR6:
1779  case Mips::SW16_MM:
1780  case Mips::SW16_MMR6:
1781  if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1783  return MCDisassembler::Fail;
1784  break;
1785  }
1786 
1787  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1789  return MCDisassembler::Fail;
1790 
1791  switch (Inst.getOpcode()) {
1792  case Mips::LBU16_MM:
1793  if (Offset == 0xf)
1794  Inst.addOperand(MCOperand::createImm(-1));
1795  else
1796  Inst.addOperand(MCOperand::createImm(Offset));
1797  break;
1798  case Mips::SB16_MM:
1799  case Mips::SB16_MMR6:
1800  Inst.addOperand(MCOperand::createImm(Offset));
1801  break;
1802  case Mips::LHU16_MM:
1803  case Mips::SH16_MM:
1804  case Mips::SH16_MMR6:
1805  Inst.addOperand(MCOperand::createImm(Offset << 1));
1806  break;
1807  case Mips::LW16_MM:
1808  case Mips::SW16_MM:
1809  case Mips::SW16_MMR6:
1810  Inst.addOperand(MCOperand::createImm(Offset << 2));
1811  break;
1812  }
1813 
1814  return MCDisassembler::Success;
1815 }
1816 
1818  unsigned Insn,
1819  uint64_t Address,
1820  const void *Decoder) {
1821  unsigned Offset = Insn & 0x1F;
1822  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1823 
1824  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1825 
1826  Inst.addOperand(MCOperand::createReg(Reg));
1827  Inst.addOperand(MCOperand::createReg(Mips::SP));
1828  Inst.addOperand(MCOperand::createImm(Offset << 2));
1829 
1830  return MCDisassembler::Success;
1831 }
1832 
1834  unsigned Insn,
1835  uint64_t Address,
1836  const void *Decoder) {
1837  unsigned Offset = Insn & 0x7F;
1838  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1839 
1840  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1841 
1842  Inst.addOperand(MCOperand::createReg(Reg));
1843  Inst.addOperand(MCOperand::createReg(Mips::GP));
1844  Inst.addOperand(MCOperand::createImm(Offset << 2));
1845 
1846  return MCDisassembler::Success;
1847 }
1848 
1850  unsigned Insn,
1851  uint64_t Address,
1852  const void *Decoder) {
1853  int Offset;
1854  switch (Inst.getOpcode()) {
1855  case Mips::LWM16_MMR6:
1856  case Mips::SWM16_MMR6:
1857  Offset = fieldFromInstruction(Insn, 4, 4);
1858  break;
1859  default:
1860  Offset = SignExtend32<4>(Insn & 0xf);
1861  break;
1862  }
1863 
1864  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1866  return MCDisassembler::Fail;
1867 
1868  Inst.addOperand(MCOperand::createReg(Mips::SP));
1869  Inst.addOperand(MCOperand::createImm(Offset << 2));
1870 
1871  return MCDisassembler::Success;
1872 }
1873 
1875  unsigned Insn,
1876  uint64_t Address,
1877  const void *Decoder) {
1878  int Offset = SignExtend32<9>(Insn & 0x1ff);
1879  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1880  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1881 
1882  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1883  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1884 
1885  if (Inst.getOpcode() == Mips::SCE_MM)
1886  Inst.addOperand(MCOperand::createReg(Reg));
1887 
1888  Inst.addOperand(MCOperand::createReg(Reg));
1889  Inst.addOperand(MCOperand::createReg(Base));
1890  Inst.addOperand(MCOperand::createImm(Offset));
1891 
1892  return MCDisassembler::Success;
1893 }
1894 
1896  unsigned Insn,
1897  uint64_t Address,
1898  const void *Decoder) {
1899  int Offset = SignExtend32<12>(Insn & 0x0fff);
1900  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1901  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1902 
1903  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1904  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1905 
1906  switch (Inst.getOpcode()) {
1907  case Mips::SWM32_MM:
1908  case Mips::LWM32_MM:
1909  if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1911  return MCDisassembler::Fail;
1912  Inst.addOperand(MCOperand::createReg(Base));
1913  Inst.addOperand(MCOperand::createImm(Offset));
1914  break;
1915  case Mips::SC_MM:
1916  Inst.addOperand(MCOperand::createReg(Reg));
1918  default:
1919  Inst.addOperand(MCOperand::createReg(Reg));
1920  if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
1921  Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
1922  Inst.addOperand(MCOperand::createReg(Reg+1));
1923 
1924  Inst.addOperand(MCOperand::createReg(Base));
1925  Inst.addOperand(MCOperand::createImm(Offset));
1926  }
1927 
1928  return MCDisassembler::Success;
1929 }
1930 
1932  unsigned Insn,
1933  uint64_t Address,
1934  const void *Decoder) {
1935  int Offset = SignExtend32<16>(Insn & 0xffff);
1936  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1937  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1938 
1939  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1940  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1941 
1942  Inst.addOperand(MCOperand::createReg(Reg));
1943  Inst.addOperand(MCOperand::createReg(Base));
1944  Inst.addOperand(MCOperand::createImm(Offset));
1945 
1946  return MCDisassembler::Success;
1947 }
1948 
1950  unsigned Insn,
1951  uint64_t Address,
1952  const void *Decoder) {
1953  int Offset = SignExtend32<16>(Insn & 0xffff);
1954  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1955  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1956 
1957  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1958  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1959 
1960  Inst.addOperand(MCOperand::createReg(Reg));
1961  Inst.addOperand(MCOperand::createReg(Base));
1962  Inst.addOperand(MCOperand::createImm(Offset));
1963 
1964  return MCDisassembler::Success;
1965 }
1966 
1967 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1968  uint64_t Address, const void *Decoder) {
1969  // This function is the same as DecodeFMem but with the Reg and Base fields
1970  // swapped according to microMIPS spec.
1971  int Offset = SignExtend32<16>(Insn & 0xffff);
1972  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1973  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1974 
1975  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1976  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1977 
1978  Inst.addOperand(MCOperand::createReg(Reg));
1979  Inst.addOperand(MCOperand::createReg(Base));
1980  Inst.addOperand(MCOperand::createImm(Offset));
1981 
1982  return MCDisassembler::Success;
1983 }
1984 
1986  unsigned Insn,
1987  uint64_t Address,
1988  const void *Decoder) {
1989  int Offset = SignExtend32<16>(Insn & 0xffff);
1990  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1991  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1992 
1993  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1994  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1995 
1996  Inst.addOperand(MCOperand::createReg(Reg));
1997  Inst.addOperand(MCOperand::createReg(Base));
1998  Inst.addOperand(MCOperand::createImm(Offset));
1999 
2000  return MCDisassembler::Success;
2001 }
2002 
2004  unsigned Insn,
2005  uint64_t Address,
2006  const void *Decoder) {
2007  int Offset = SignExtend32<16>(Insn & 0xffff);
2008  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2009  unsigned Base = fieldFromInstruction(Insn, 21, 5);
2010 
2011  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
2012  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2013 
2014  Inst.addOperand(MCOperand::createReg(Reg));
2015  Inst.addOperand(MCOperand::createReg(Base));
2016  Inst.addOperand(MCOperand::createImm(Offset));
2017 
2018  return MCDisassembler::Success;
2019 }
2020 
2022  unsigned Insn,
2023  uint64_t Address,
2024  const void *Decoder) {
2025  int Offset = SignExtend32<11>(Insn & 0x07ff);
2026  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2027  unsigned Base = fieldFromInstruction(Insn, 11, 5);
2028 
2029  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2030  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2031 
2032  Inst.addOperand(MCOperand::createReg(Reg));
2033  Inst.addOperand(MCOperand::createReg(Base));
2034  Inst.addOperand(MCOperand::createImm(Offset));
2035 
2036  return MCDisassembler::Success;
2037 }
2038 
2039 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2040  uint64_t Address, const void *Decoder) {
2041  int Offset = SignExtend32<11>(Insn & 0x07ff);
2042  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2043  unsigned Base = fieldFromInstruction(Insn, 16, 5);
2044 
2045  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2046  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2047 
2048  Inst.addOperand(MCOperand::createReg(Reg));
2049  Inst.addOperand(MCOperand::createReg(Base));
2050  Inst.addOperand(MCOperand::createImm(Offset));
2051 
2052  return MCDisassembler::Success;
2053 }
2054 
2056  unsigned Insn,
2057  uint64_t Address,
2058  const void *Decoder) {
2059  int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2060  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2061  unsigned Base = fieldFromInstruction(Insn, 21, 5);
2062 
2063  Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2064  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2065 
2066  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2067  Inst.addOperand(MCOperand::createReg(Rt));
2068  }
2069 
2070  Inst.addOperand(MCOperand::createReg(Rt));
2071  Inst.addOperand(MCOperand::createReg(Base));
2072  Inst.addOperand(MCOperand::createImm(Offset));
2073 
2074  return MCDisassembler::Success;
2075 }
2076 
2078  unsigned RegNo,
2079  uint64_t Address,
2080  const void *Decoder) {
2081  // Currently only hardware register 29 is supported.
2082  if (RegNo != 29)
2083  return MCDisassembler::Fail;
2084  Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2085  return MCDisassembler::Success;
2086 }
2087 
2089  unsigned RegNo,
2090  uint64_t Address,
2091  const void *Decoder) {
2092  if (RegNo > 30 || RegNo %2)
2093  return MCDisassembler::Fail;
2094 
2095  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2096  Inst.addOperand(MCOperand::createReg(Reg));
2097  return MCDisassembler::Success;
2098 }
2099 
2101  unsigned RegNo,
2102  uint64_t Address,
2103  const void *Decoder) {
2104  if (RegNo >= 4)
2105  return MCDisassembler::Fail;
2106 
2107  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2108  Inst.addOperand(MCOperand::createReg(Reg));
2109  return MCDisassembler::Success;
2110 }
2111 
2113  unsigned RegNo,
2114  uint64_t Address,
2115  const void *Decoder) {
2116  if (RegNo >= 4)
2117  return MCDisassembler::Fail;
2118 
2119  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2120  Inst.addOperand(MCOperand::createReg(Reg));
2121  return MCDisassembler::Success;
2122 }
2123 
2125  unsigned RegNo,
2126  uint64_t Address,
2127  const void *Decoder) {
2128  if (RegNo >= 4)
2129  return MCDisassembler::Fail;
2130 
2131  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2132  Inst.addOperand(MCOperand::createReg(Reg));
2133  return MCDisassembler::Success;
2134 }
2135 
2137  unsigned RegNo,
2138  uint64_t Address,
2139  const void *Decoder) {
2140  if (RegNo > 31)
2141  return MCDisassembler::Fail;
2142 
2143  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2144  Inst.addOperand(MCOperand::createReg(Reg));
2145  return MCDisassembler::Success;
2146 }
2147 
2149  unsigned RegNo,
2150  uint64_t Address,
2151  const void *Decoder) {
2152  if (RegNo > 31)
2153  return MCDisassembler::Fail;
2154 
2155  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2156  Inst.addOperand(MCOperand::createReg(Reg));
2157  return MCDisassembler::Success;
2158 }
2159 
2161  unsigned RegNo,
2162  uint64_t Address,
2163  const void *Decoder) {
2164  if (RegNo > 31)
2165  return MCDisassembler::Fail;
2166 
2167  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2168  Inst.addOperand(MCOperand::createReg(Reg));
2169  return MCDisassembler::Success;
2170 }
2171 
2173  unsigned RegNo,
2174  uint64_t Address,
2175  const void *Decoder) {
2176  if (RegNo > 31)
2177  return MCDisassembler::Fail;
2178 
2179  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2180  Inst.addOperand(MCOperand::createReg(Reg));
2181  return MCDisassembler::Success;
2182 }
2183 
2185  unsigned RegNo,
2186  uint64_t Address,
2187  const void *Decoder) {
2188  if (RegNo > 7)
2189  return MCDisassembler::Fail;
2190 
2191  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2192  Inst.addOperand(MCOperand::createReg(Reg));
2193  return MCDisassembler::Success;
2194 }
2195 
2197  unsigned RegNo,
2198  uint64_t Address,
2199  const void *Decoder) {
2200  if (RegNo > 31)
2201  return MCDisassembler::Fail;
2202 
2203  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2204  Inst.addOperand(MCOperand::createReg(Reg));
2205  return MCDisassembler::Success;
2206 }
2207 
2209  unsigned RegNo,
2210  uint64_t Address,
2211  const void *Decoder) {
2212  if (RegNo > 31)
2213  return MCDisassembler::Fail;
2214 
2215  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2216  Inst.addOperand(MCOperand::createReg(Reg));
2217  return MCDisassembler::Success;
2218 }
2219 
2221  unsigned Offset,
2222  uint64_t Address,
2223  const void *Decoder) {
2224  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2225  Inst.addOperand(MCOperand::createImm(BranchOffset));
2226  return MCDisassembler::Success;
2227 }
2228 
2230  unsigned Offset,
2231  uint64_t Address,
2232  const void *Decoder) {
2233  int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2234  Inst.addOperand(MCOperand::createImm(BranchOffset));
2235  return MCDisassembler::Success;
2236 }
2237 
2239  unsigned Insn,
2240  uint64_t Address,
2241  const void *Decoder) {
2242  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2243  Inst.addOperand(MCOperand::createImm(JumpOffset));
2244  return MCDisassembler::Success;
2245 }
2246 
2248  unsigned Offset,
2249  uint64_t Address,
2250  const void *Decoder) {
2251  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2252 
2253  Inst.addOperand(MCOperand::createImm(BranchOffset));
2254  return MCDisassembler::Success;
2255 }
2256 
2258  unsigned Offset,
2259  uint64_t Address,
2260  const void *Decoder) {
2261  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2262 
2263  Inst.addOperand(MCOperand::createImm(BranchOffset));
2264  return MCDisassembler::Success;
2265 }
2266 
2268  unsigned Offset,
2269  uint64_t Address,
2270  const void *Decoder) {
2271  int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2272 
2273  Inst.addOperand(MCOperand::createImm(BranchOffset));
2274  return MCDisassembler::Success;
2275 }
2276 
2278  unsigned Offset,
2279  uint64_t Address,
2280  const void *Decoder) {
2281  int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2282  Inst.addOperand(MCOperand::createImm(BranchOffset));
2283  return MCDisassembler::Success;
2284 }
2285 
2287  unsigned Offset,
2288  uint64_t Address,
2289  const void *Decoder) {
2290  int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2291  Inst.addOperand(MCOperand::createImm(BranchOffset));
2292  return MCDisassembler::Success;
2293 }
2294 
2296  unsigned Offset,
2297  uint64_t Address,
2298  const void *Decoder) {
2299  int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2300  Inst.addOperand(MCOperand::createImm(BranchOffset));
2301  return MCDisassembler::Success;
2302 }
2303 
2305  unsigned Offset,
2306  uint64_t Address,
2307  const void *Decoder) {
2308  int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2309 
2310  Inst.addOperand(MCOperand::createImm(BranchOffset));
2311  return MCDisassembler::Success;
2312 }
2313 
2315  unsigned Insn,
2316  uint64_t Address,
2317  const void *Decoder) {
2318  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2319  Inst.addOperand(MCOperand::createImm(JumpOffset));
2320  return MCDisassembler::Success;
2321 }
2322 
2324  unsigned Value,
2325  uint64_t Address,
2326  const void *Decoder) {
2327  if (Value == 0)
2329  else if (Value == 0x7)
2330  Inst.addOperand(MCOperand::createImm(-1));
2331  else
2332  Inst.addOperand(MCOperand::createImm(Value << 2));
2333  return MCDisassembler::Success;
2334 }
2335 
2337  unsigned Value,
2338  uint64_t Address,
2339  const void *Decoder) {
2340  if (Value == 0x7F)
2341  Inst.addOperand(MCOperand::createImm(-1));
2342  else
2343  Inst.addOperand(MCOperand::createImm(Value));
2344  return MCDisassembler::Success;
2345 }
2346 
2348  unsigned Value,
2349  uint64_t Address,
2350  const void *Decoder) {
2351  Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2352  return MCDisassembler::Success;
2353 }
2354 
2355 template <unsigned Bits, int Offset, int Scale>
2356 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2357  uint64_t Address,
2358  const void *Decoder) {
2359  Value &= ((1 << Bits) - 1);
2360  Value *= Scale;
2361  Inst.addOperand(MCOperand::createImm(Value + Offset));
2362  return MCDisassembler::Success;
2363 }
2364 
2365 template <unsigned Bits, int Offset, int ScaleBy>
2366 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2367  uint64_t Address,
2368  const void *Decoder) {
2369  int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2370  Inst.addOperand(MCOperand::createImm(Imm + Offset));
2371  return MCDisassembler::Success;
2372 }
2373 
2375  unsigned Insn,
2376  uint64_t Address,
2377  const void *Decoder) {
2378  // First we need to grab the pos(lsb) from MCInst.
2379  // This function only handles the 32 bit variants of ins, as dins
2380  // variants are handled differently.
2381  int Pos = Inst.getOperand(2).getImm();
2382  int Size = (int) Insn - Pos + 1;
2383  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2384  return MCDisassembler::Success;
2385 }
2386 
2387 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2388  uint64_t Address, const void *Decoder) {
2389  Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2390  return MCDisassembler::Success;
2391 }
2392 
2393 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2394  uint64_t Address, const void *Decoder) {
2395  Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2396  return MCDisassembler::Success;
2397 }
2398 
2399 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2400  uint64_t Address, const void *Decoder) {
2401  int32_t DecodedValue;
2402  switch (Insn) {
2403  case 0: DecodedValue = 256; break;
2404  case 1: DecodedValue = 257; break;
2405  case 510: DecodedValue = -258; break;
2406  case 511: DecodedValue = -257; break;
2407  default: DecodedValue = SignExtend32<9>(Insn); break;
2408  }
2409  Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2410  return MCDisassembler::Success;
2411 }
2412 
2413 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2414  uint64_t Address, const void *Decoder) {
2415  // Insn must be >= 0, since it is unsigned that condition is always true.
2416  assert(Insn < 16);
2417  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2418  255, 32768, 65535};
2419  Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2420  return MCDisassembler::Success;
2421 }
2422 
2424  unsigned Insn,
2425  uint64_t Address,
2426  const void *Decoder) {
2427  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2428  Mips::S6, Mips::S7, Mips::FP};
2429  unsigned RegNum;
2430 
2431  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2432 
2433  // Empty register lists are not allowed.
2434  if (RegLst == 0)
2435  return MCDisassembler::Fail;
2436 
2437  RegNum = RegLst & 0xf;
2438 
2439  // RegLst values 10-15, and 26-31 are reserved.
2440  if (RegNum > 9)
2441  return MCDisassembler::Fail;
2442 
2443  for (unsigned i = 0; i < RegNum; i++)
2444  Inst.addOperand(MCOperand::createReg(Regs[i]));
2445 
2446  if (RegLst & 0x10)
2448 
2449  return MCDisassembler::Success;
2450 }
2451 
2452 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2453  uint64_t Address,
2454  const void *Decoder) {
2455  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2456  unsigned RegLst;
2457  switch(Inst.getOpcode()) {
2458  default:
2459  RegLst = fieldFromInstruction(Insn, 4, 2);
2460  break;
2461  case Mips::LWM16_MMR6:
2462  case Mips::SWM16_MMR6:
2463  RegLst = fieldFromInstruction(Insn, 8, 2);
2464  break;
2465  }
2466  unsigned RegNum = RegLst & 0x3;
2467 
2468  for (unsigned i = 0; i <= RegNum; i++)
2469  Inst.addOperand(MCOperand::createReg(Regs[i]));
2470 
2472 
2473  return MCDisassembler::Success;
2474 }
2475 
2476 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2477  uint64_t Address, const void *Decoder) {
2478  unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2479 
2480  switch (RegPair) {
2481  default:
2482  return MCDisassembler::Fail;
2483  case 0:
2484  Inst.addOperand(MCOperand::createReg(Mips::A1));
2485  Inst.addOperand(MCOperand::createReg(Mips::A2));
2486  break;
2487  case 1:
2488  Inst.addOperand(MCOperand::createReg(Mips::A1));
2489  Inst.addOperand(MCOperand::createReg(Mips::A3));
2490  break;
2491  case 2:
2492  Inst.addOperand(MCOperand::createReg(Mips::A2));
2493  Inst.addOperand(MCOperand::createReg(Mips::A3));
2494  break;
2495  case 3:
2496  Inst.addOperand(MCOperand::createReg(Mips::A0));
2497  Inst.addOperand(MCOperand::createReg(Mips::S5));
2498  break;
2499  case 4:
2500  Inst.addOperand(MCOperand::createReg(Mips::A0));
2501  Inst.addOperand(MCOperand::createReg(Mips::S6));
2502  break;
2503  case 5:
2504  Inst.addOperand(MCOperand::createReg(Mips::A0));
2505  Inst.addOperand(MCOperand::createReg(Mips::A1));
2506  break;
2507  case 6:
2508  Inst.addOperand(MCOperand::createReg(Mips::A0));
2509  Inst.addOperand(MCOperand::createReg(Mips::A2));
2510  break;
2511  case 7:
2512  Inst.addOperand(MCOperand::createReg(Mips::A0));
2513  Inst.addOperand(MCOperand::createReg(Mips::A3));
2514  break;
2515  }
2516 
2517  return MCDisassembler::Success;
2518 }
2519 
2520 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2521  uint64_t Address, const void *Decoder) {
2522  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2523  return MCDisassembler::Success;
2524 }
2525 
2526 template <typename InsnType>
2528  uint64_t Address,
2529  const void *Decoder) {
2530  // We have:
2531  // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2532  // Invalid if rt == 0
2533  // BGTZALC_MMR6 if rs == 0 && rt != 0
2534  // BLTZALC_MMR6 if rs != 0 && rs == rt
2535  // BLTUC_MMR6 if rs != 0 && rs != rt
2536 
2537  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2538  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2539  InsnType Imm = 0;
2540  bool HasRs = false;
2541  bool HasRt = false;
2542 
2543  if (Rt == 0)
2544  return MCDisassembler::Fail;
2545  else if (Rs == 0) {
2546  MI.setOpcode(Mips::BGTZALC_MMR6);
2547  HasRt = true;
2548  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2549  }
2550  else if (Rs == Rt) {
2551  MI.setOpcode(Mips::BLTZALC_MMR6);
2552  HasRs = true;
2553  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2554  }
2555  else {
2556  MI.setOpcode(Mips::BLTUC_MMR6);
2557  HasRs = true;
2558  HasRt = true;
2559  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2560  }
2561 
2562  if (HasRs)
2563  MI.addOperand(
2564  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2565 
2566  if (HasRt)
2567  MI.addOperand(
2568  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2569 
2571 
2572  return MCDisassembler::Success;
2573 }
2574 
2575 template <typename InsnType>
2577  uint64_t Address,
2578  const void *Decoder) {
2579  // We have:
2580  // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2581  // Invalid if rt == 0
2582  // BLEZALC_MMR6 if rs == 0 && rt != 0
2583  // BGEZALC_MMR6 if rs == rt && rt != 0
2584  // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2585 
2586  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2587  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2588  InsnType Imm = 0;
2589  bool HasRs = false;
2590 
2591  if (Rt == 0)
2592  return MCDisassembler::Fail;
2593  else if (Rs == 0) {
2594  MI.setOpcode(Mips::BLEZALC_MMR6);
2595  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2596  }
2597  else if (Rs == Rt) {
2598  MI.setOpcode(Mips::BGEZALC_MMR6);
2599  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2600  }
2601  else {
2602  HasRs = true;
2603  MI.setOpcode(Mips::BGEUC_MMR6);
2604  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2605  }
2606 
2607  if (HasRs)
2608  MI.addOperand(
2609  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2610  MI.addOperand(
2611  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2612 
2614 
2615  return MCDisassembler::Success;
2616 }
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn&#39;t handle.
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Target & getTheMipselTarget()
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
SI optimize exec mask operations pre RA
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:59
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Target & getTheMips64Target()
const RegList & Regs
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int64_t getImm() const
Definition: MCInst.h:76
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Target & getTheMips64elTarget()
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
void setOpcode(unsigned Op)
Definition: MCInst.h:167
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness...
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:173
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheMipsTarget()
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:741
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:73
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:177
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Definition: MCInst.h:168
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)