LLVM  9.0.0svn
MipsISelDAGToDAG.cpp
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1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the MIPS target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsISelDAGToDAG.h"
15 #include "Mips.h"
16 #include "Mips16ISelDAGToDAG.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSEISelDAGToDAG.h"
27 #include "llvm/IR/CFG.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips-isel"
39 
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
43 
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
48 
50  // There are multiple MipsDAGToDAGISel instances added to the pass pipeline.
51  // We need to preserve StackProtector for the next one.
54 }
55 
57  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
59 
60  processFunctionAfterISel(MF);
61 
62  return Ret;
63 }
64 
65 /// getGlobalBaseReg - Output the instructions required to put the
66 /// GOT address into a register.
69  return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy(
71  .getNode();
72 }
73 
74 /// ComplexPattern used on MipsInstrInfo
75 /// Used on Mips Load/Store instructions
76 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
77  SDValue &Offset) const {
78  llvm_unreachable("Unimplemented function.");
79  return false;
80 }
81 
82 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
83  SDValue &Offset) const {
84  llvm_unreachable("Unimplemented function.");
85  return false;
86 }
87 
88 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
89  SDValue &Offset) const {
90  llvm_unreachable("Unimplemented function.");
91  return false;
92 }
93 
94 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
95  SDValue &Offset) const {
96  llvm_unreachable("Unimplemented function.");
97  return false;
98 }
99 
100 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
101  SDValue &Offset) const {
102  llvm_unreachable("Unimplemented function.");
103  return false;
104 }
105 
106 bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
107  SDValue &Offset) const {
108  llvm_unreachable("Unimplemented function.");
109  return false;
110 }
111 
112 bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
113  SDValue &Offset) const {
114  llvm_unreachable("Unimplemented function.");
115  return false;
116 }
117 
118 bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
119  SDValue &Offset) const {
120  llvm_unreachable("Unimplemented function.");
121  return false;
122 }
123 
124 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
125  SDValue &Offset) const {
126  llvm_unreachable("Unimplemented function.");
127  return false;
128 }
129 
130 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
131  SDValue &Offset) const {
132  llvm_unreachable("Unimplemented function.");
133  return false;
134 }
135 
136 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
137  SDValue &Offset) const {
138  llvm_unreachable("Unimplemented function.");
139  return false;
140 }
141 
142 bool MipsDAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base,
143  SDValue &Offset) {
144  llvm_unreachable("Unimplemented function.");
145  return false;
146 }
147 
148 bool MipsDAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base,
149  SDValue &Offset) {
150  llvm_unreachable("Unimplemented function.");
151  return false;
152 }
153 
154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
155  unsigned MinSizeInBits) const {
156  llvm_unreachable("Unimplemented function.");
157  return false;
158 }
159 
160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
161  llvm_unreachable("Unimplemented function.");
162  return false;
163 }
164 
165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
166  llvm_unreachable("Unimplemented function.");
167  return false;
168 }
169 
170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
171  llvm_unreachable("Unimplemented function.");
172  return false;
173 }
174 
175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
176  llvm_unreachable("Unimplemented function.");
177  return false;
178 }
179 
180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
181  llvm_unreachable("Unimplemented function.");
182  return false;
183 }
184 
185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
186  llvm_unreachable("Unimplemented function.");
187  return false;
188 }
189 
190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
191  llvm_unreachable("Unimplemented function.");
192  return false;
193 }
194 
195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
196  llvm_unreachable("Unimplemented function.");
197  return false;
198 }
199 
200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
201  llvm_unreachable("Unimplemented function.");
202  return false;
203 }
204 
205 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const {
206  llvm_unreachable("Unimplemented function.");
207  return false;
208 }
209 
210 bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
211  llvm_unreachable("Unimplemented function.");
212  return false;
213 }
214 
215 bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
216  llvm_unreachable("Unimplemented function.");
217  return false;
218 }
219 
220 /// Select instructions not customized! Used for
221 /// expanded, promoted and normal instructions
222 void MipsDAGToDAGISel::Select(SDNode *Node) {
223  unsigned Opcode = Node->getOpcode();
224 
225  // If we have a custom node, we already have selected!
226  if (Node->isMachineOpcode()) {
227  LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
228  Node->setNodeId(-1);
229  return;
230  }
231 
232  // See if subclasses can handle this node.
233  if (trySelect(Node))
234  return;
235 
236  switch(Opcode) {
237  default: break;
238 
239  // Get target GOT address.
241  ReplaceNode(Node, getGlobalBaseReg());
242  return;
243 
244 #ifndef NDEBUG
245  case ISD::LOAD:
246  case ISD::STORE:
248  cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
249  cast<MemSDNode>(Node)->getAlignment()) &&
250  "Unexpected unaligned loads/stores.");
251  break;
252 #endif
253  }
254 
255  // Select the default instruction
256  SelectCode(Node);
257 }
258 
259 bool MipsDAGToDAGISel::
260 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
261  std::vector<SDValue> &OutOps) {
262  // All memory constraints can at least accept raw pointers.
263  switch(ConstraintID) {
264  default:
265  llvm_unreachable("Unexpected asm memory constraint");
270  OutOps.push_back(Op);
271  return false;
272  }
273  return true;
274 }
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void setNodeId(int Id)
Set unique node id.
SDNode * getNode() const
get the SDNode which holds the desired result
The address of the GOT.
Definition: ISDOpcodes.h:65
MachineFunction * MF
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
static uint32_t getAlignment(const MCSectionCOFF &Sec)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Represent the analysis usage information of a pass.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void dump() const
Dump this node, for debugging.
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
SDNode * getGlobalBaseReg()
getGlobalBaseReg - Output the instructions required to put the GOT address into a register...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:615
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
const TargetLowering * getTargetLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getRegister(unsigned Reg, EVT VT)
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...