LLVM  9.0.0svn
MipsOptionRecord.cpp
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1 //===- MipsOptionRecord.cpp - Abstraction for storing information ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MipsOptionRecord.h"
10 #include "MipsABIInfo.h"
11 #include "MipsELFStreamer.h"
12 #include "MipsTargetStreamer.h"
13 #include "llvm/BinaryFormat/ELF.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSectionELF.h"
18 #include <cassert>
19 
20 using namespace llvm;
21 
23  MCAssembler &MCA = Streamer->getAssembler();
24  MipsTargetStreamer *MTS =
25  static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer());
26 
27  Streamer->PushSection();
28 
29  // We need to distinguish between N64 and the rest because at the moment
30  // we don't emit .Mips.options for other ELFs other than N64.
31  // Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
32  // we can use the same abstraction (MipsRegInfoRecord class) to handle both.
33  if (MTS->getABI().IsN64()) {
34  // The EntrySize value of 1 seems strange since the records are neither
35  // 1-byte long nor fixed length but it matches the value GAS emits.
36  MCSectionELF *Sec =
37  Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
39  MCA.registerSection(*Sec);
40  Sec->setAlignment(8);
41  Streamer->SwitchSection(Sec);
42 
43  Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind
44  Streamer->EmitIntValue(40, 1); // size
45  Streamer->EmitIntValue(0, 2); // section
46  Streamer->EmitIntValue(0, 4); // info
47  Streamer->EmitIntValue(ri_gprmask, 4);
48  Streamer->EmitIntValue(0, 4); // pad
49  Streamer->EmitIntValue(ri_cprmask[0], 4);
50  Streamer->EmitIntValue(ri_cprmask[1], 4);
51  Streamer->EmitIntValue(ri_cprmask[2], 4);
52  Streamer->EmitIntValue(ri_cprmask[3], 4);
53  Streamer->EmitIntValue(ri_gp_value, 8);
54  } else {
55  MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO,
56  ELF::SHF_ALLOC, 24, "");
57  MCA.registerSection(*Sec);
58  Sec->setAlignment(MTS->getABI().IsN32() ? 8 : 4);
59  Streamer->SwitchSection(Sec);
60 
61  Streamer->EmitIntValue(ri_gprmask, 4);
62  Streamer->EmitIntValue(ri_cprmask[0], 4);
63  Streamer->EmitIntValue(ri_cprmask[1], 4);
64  Streamer->EmitIntValue(ri_cprmask[2], 4);
65  Streamer->EmitIntValue(ri_cprmask[3], 4);
66  assert((ri_gp_value & 0xffffffff) == ri_gp_value);
67  Streamer->EmitIntValue(ri_gp_value, 4);
68  }
69 
70  Streamer->PopSection();
71 }
72 
74  const MCRegisterInfo *MCRegInfo) {
75  unsigned Value = 0;
76 
77  for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
78  ++SubRegIt) {
79  unsigned CurrentSubReg = *SubRegIt;
80 
81  unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg);
82  Value |= 1 << EncVal;
83 
84  if (GPR32RegClass->contains(CurrentSubReg) ||
85  GPR64RegClass->contains(CurrentSubReg))
86  ri_gprmask |= Value;
87  else if (COP0RegClass->contains(CurrentSubReg))
88  ri_cprmask[0] |= Value;
89  // MIPS COP1 is the FPU.
90  else if (FGR32RegClass->contains(CurrentSubReg) ||
91  FGR64RegClass->contains(CurrentSubReg) ||
92  AFGR64RegClass->contains(CurrentSubReg) ||
93  MSA128BRegClass->contains(CurrentSubReg))
94  ri_cprmask[1] |= Value;
95  else if (COP2RegClass->contains(CurrentSubReg))
96  ri_cprmask[2] |= Value;
97  else if (COP3RegClass->contains(CurrentSubReg))
98  ri_cprmask[3] |= Value;
99  }
100 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
void setAlignment(unsigned Value)
Definition: MCSection.h:121
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:367
const MipsABIInfo & getABI() const
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
bool registerSection(MCSection &Section)
bool IsN32() const
Definition: MipsABIInfo.h:42
void EmitMipsOptionRecord() override
bool IsN64() const
Definition: MipsABIInfo.h:43
void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:257
MCAssembler & getAssembler()
void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr) override
Overriding this function allows us to dismiss all labels that are candidates for marking as microMIPS...
MCSubRegIterator enumerates all sub-registers of Reg.
void EmitIntValue(uint64_t Value, unsigned Size) override
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:376
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:388
LLVM Value Representation.
Definition: Value.h:72