LLVM  9.0.0svn
MipsOptionRecord.h
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1 //===- MipsOptionRecord.h - Abstraction for storing information -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // MipsOptionRecord - Abstraction for storing arbitrary information in
10 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
11 // specific ELF sections like .Mips.options. Specific records should subclass
12 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
13 // basically just dumps the information into an ELF section. More information
14 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
15 // specification.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
20 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
21 
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include <cstdint>
26 
27 namespace llvm {
28 
29 class MipsELFStreamer;
30 
32 public:
33  virtual ~MipsOptionRecord() = default;
34 
35  virtual void EmitMipsOptionRecord() = 0;
36 };
37 
39 public:
41  : Streamer(S), Context(Context) {
42  ri_gprmask = 0;
43  ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
44  ri_gp_value = 0;
45 
46  const MCRegisterInfo *TRI = Context.getRegisterInfo();
47  GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48  GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49  FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50  FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51  AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52  MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53  COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
54  COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
55  COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
56  }
57 
58  ~MipsRegInfoRecord() override = default;
59 
60  void EmitMipsOptionRecord() override;
61  void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
62 
63 private:
64  MipsELFStreamer *Streamer;
66  const MCRegisterClass *GPR32RegClass;
67  const MCRegisterClass *GPR64RegClass;
68  const MCRegisterClass *FGR32RegClass;
69  const MCRegisterClass *FGR64RegClass;
70  const MCRegisterClass *AFGR64RegClass;
71  const MCRegisterClass *MSA128BRegClass;
72  const MCRegisterClass *COP0RegClass;
73  const MCRegisterClass *COP2RegClass;
74  const MCRegisterClass *COP3RegClass;
75  uint32_t ri_gprmask;
76  uint32_t ri_cprmask[4];
77  int64_t ri_gp_value;
78 };
79 
80 } // end namespace llvm
81 
82 #endif // LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
unsigned const TargetRegisterInfo * TRI
Context object for machine code objects.
Definition: MCContext.h:62
virtual void EmitMipsOptionRecord()=0
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
virtual ~MipsOptionRecord()=default
MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.