LLVM  7.0.0svn
MipsSEISelLowering.cpp
Go to the documentation of this file.
1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsTargetLowering specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEISelLowering.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Triple.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/IR/Intrinsics.h"
39 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Debug.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <iterator>
49 #include <utility>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "mips-isel"
54 
55 static cl::opt<bool>
56 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
57  cl::desc("MIPS: permit tail calls."), cl::init(false));
58 
59 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
60  cl::desc("Expand double precision loads and "
61  "stores to their single precision "
62  "counterparts"));
63 
65  const MipsSubtarget &STI)
66  : MipsTargetLowering(TM, STI) {
67  // Set up the register classes
68  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
69 
70  if (Subtarget.isGP64bit())
71  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
72 
73  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
74  // Expand all truncating stores and extending loads.
75  for (MVT VT0 : MVT::vector_valuetypes()) {
76  for (MVT VT1 : MVT::vector_valuetypes()) {
77  setTruncStoreAction(VT0, VT1, Expand);
81  }
82  }
83  }
84 
85  if (Subtarget.hasDSP()) {
87 
88  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
89  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
90 
91  // Expand all builtin opcodes.
92  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
93  setOperationAction(Opc, VecTys[i], Expand);
94 
95  setOperationAction(ISD::ADD, VecTys[i], Legal);
96  setOperationAction(ISD::SUB, VecTys[i], Legal);
97  setOperationAction(ISD::LOAD, VecTys[i], Legal);
98  setOperationAction(ISD::STORE, VecTys[i], Legal);
100  }
101 
107  }
108 
109  if (Subtarget.hasDSPR2())
111 
112  if (Subtarget.hasMSA()) {
113  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
114  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
115  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
116  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
117  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
118  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
119  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
120 
121  // f16 is a storage-only type, always promote it to f32.
122  addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
158 
164  }
165 
166  if (!Subtarget.useSoftFloat()) {
167  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
168 
169  // When dealing with single precision only, use libcalls
170  if (!Subtarget.isSingleFloat()) {
171  if (Subtarget.isFP64bit())
172  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
173  else
174  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
175  }
176  }
177 
182 
183  if (Subtarget.hasCnMips())
185  else if (Subtarget.isGP64bit())
187 
188  if (Subtarget.isGP64bit()) {
195  }
196 
199 
205 
207 
211 
212  if (NoDPLoadStore) {
215  }
216 
217  if (Subtarget.hasMips32r6()) {
218  // MIPS32r6 replaces the accumulator-based multiplies with a three register
219  // instruction
225 
226  // MIPS32r6 replaces the accumulator-based division/remainder with separate
227  // three register division and remainder instructions.
234 
235  // MIPS32r6 replaces conditional moves with an equivalent that removes the
236  // need for three GPR read ports.
240 
244 
245  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
249 
251 
252  // Floating point > and >= are supported via < and <=
257 
262  }
263 
264  if (Subtarget.hasMips64r6()) {
265  // MIPS64r6 replaces the accumulator-based multiplies with a three register
266  // instruction
272 
273  // MIPS32r6 replaces the accumulator-based division/remainder with separate
274  // three register division and remainder instructions.
281 
282  // MIPS64r6 replaces conditional moves with an equivalent that removes the
283  // need for three GPR read ports.
287  }
288 
290 }
291 
292 const MipsTargetLowering *
294  const MipsSubtarget &STI) {
295  return new MipsSETargetLowering(TM, STI);
296 }
297 
298 const TargetRegisterClass *
300  if (VT == MVT::Untyped)
301  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
302 
304 }
305 
306 // Enable MSA support for the given integer type and Register class.
309  addRegisterClass(Ty, RC);
310 
311  // Expand all builtin opcodes.
312  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
313  setOperationAction(Opc, Ty, Expand);
314 
321 
343 
344  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
349  }
350 
357 }
358 
359 // Enable MSA support for the given floating-point type and Register class.
362  addRegisterClass(Ty, RC);
363 
364  // Expand all builtin opcodes.
365  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
366  setOperationAction(Opc, Ty, Expand);
367 
374 
375  if (Ty != MVT::v8f16) {
387 
395  }
396 }
397 
398 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
399  if(!Subtarget.hasMips32r6())
400  return MipsTargetLowering::LowerOperation(Op, DAG);
401 
402  EVT ResTy = Op->getValueType(0);
403  SDLoc DL(Op);
404 
405  // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
406  // floating point register are undefined. Not really an issue as sel.d, which
407  // is produced from an FSELECT node, only looks at bit 0.
408  SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
409  return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
410  Op->getOperand(2));
411 }
412 
413 bool
415  unsigned,
416  unsigned,
417  bool *Fast) const {
419 
421  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
422  // implementation defined whether this is handled by hardware, software, or
423  // a hybrid of the two but it's expected that most implementations will
424  // handle the majority of cases in hardware.
425  if (Fast)
426  *Fast = true;
427  return true;
428  }
429 
430  switch (SVT) {
431  case MVT::i64:
432  case MVT::i32:
433  if (Fast)
434  *Fast = true;
435  return true;
436  default:
437  return false;
438  }
439 }
440 
442  SelectionDAG &DAG) const {
443  switch(Op.getOpcode()) {
444  case ISD::LOAD: return lowerLOAD(Op, DAG);
445  case ISD::STORE: return lowerSTORE(Op, DAG);
446  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
447  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
448  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
449  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
450  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
451  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
452  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
453  DAG);
454  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
455  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
456  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
457  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
458  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
459  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
460  case ISD::SELECT: return lowerSELECT(Op, DAG);
461  }
462 
463  return MipsTargetLowering::LowerOperation(Op, DAG);
464 }
465 
466 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
467 //
468 // Performs the following transformations:
469 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
470 // sign/zero-extension is completely overwritten by the new one performed by
471 // the ISD::AND.
472 // - Removes redundant zero extensions performed by an ISD::AND.
475  const MipsSubtarget &Subtarget) {
476  if (!Subtarget.hasMSA())
477  return SDValue();
478 
479  SDValue Op0 = N->getOperand(0);
480  SDValue Op1 = N->getOperand(1);
481  unsigned Op0Opcode = Op0->getOpcode();
482 
483  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
484  // where $d + 1 == 2^n and n == 32
485  // or $d + 1 == 2^n and n <= 32 and ZExt
486  // -> (MipsVExtractZExt $a, $b, $c)
487  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
488  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
490 
491  if (!Mask)
492  return SDValue();
493 
494  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
495 
496  if (Log2IfPositive <= 0)
497  return SDValue(); // Mask+1 is not a power of 2
498 
499  SDValue Op0Op2 = Op0->getOperand(2);
500  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
501  unsigned ExtendTySize = ExtendTy.getSizeInBits();
502  unsigned Log2 = Log2IfPositive;
503 
504  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
505  Log2 == ExtendTySize) {
506  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
507  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
508  Op0->getVTList(),
509  makeArrayRef(Ops, Op0->getNumOperands()));
510  }
511  }
512 
513  return SDValue();
514 }
515 
516 // Determine if the specified node is a constant vector splat.
517 //
518 // Returns true and sets Imm if:
519 // * N is a ISD::BUILD_VECTOR representing a constant splat
520 //
521 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
522 // differences are that it assumes the MSA has already been checked and the
523 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
524 // must not be in order for binsri.d to be selectable).
525 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
527 
528  if (!Node)
529  return false;
530 
531  APInt SplatValue, SplatUndef;
532  unsigned SplatBitSize;
533  bool HasAnyUndefs;
534 
535  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
536  8, !IsLittleEndian))
537  return false;
538 
539  Imm = SplatValue;
540 
541  return true;
542 }
543 
544 // Test whether the given node is an all-ones build_vector.
545 static bool isVectorAllOnes(SDValue N) {
546  // Look through bitcasts. Endianness doesn't matter because we are looking
547  // for an all-ones value.
548  if (N->getOpcode() == ISD::BITCAST)
549  N = N->getOperand(0);
550 
552 
553  if (!BVN)
554  return false;
555 
556  APInt SplatValue, SplatUndef;
557  unsigned SplatBitSize;
558  bool HasAnyUndefs;
559 
560  // Endianness doesn't matter in this context because we are looking for
561  // an all-ones value.
562  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
563  return SplatValue.isAllOnesValue();
564 
565  return false;
566 }
567 
568 // Test whether N is the bitwise inverse of OfNode.
569 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
570  if (N->getOpcode() != ISD::XOR)
571  return false;
572 
573  if (isVectorAllOnes(N->getOperand(0)))
574  return N->getOperand(1) == OfNode;
575 
576  if (isVectorAllOnes(N->getOperand(1)))
577  return N->getOperand(0) == OfNode;
578 
579  return false;
580 }
581 
582 // Perform combines where ISD::OR is the root node.
583 //
584 // Performs the following transformations:
585 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
586 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
587 // vector type.
590  const MipsSubtarget &Subtarget) {
591  if (!Subtarget.hasMSA())
592  return SDValue();
593 
594  EVT Ty = N->getValueType(0);
595 
596  if (!Ty.is128BitVector())
597  return SDValue();
598 
599  SDValue Op0 = N->getOperand(0);
600  SDValue Op1 = N->getOperand(1);
601 
602  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
603  SDValue Op0Op0 = Op0->getOperand(0);
604  SDValue Op0Op1 = Op0->getOperand(1);
605  SDValue Op1Op0 = Op1->getOperand(0);
606  SDValue Op1Op1 = Op1->getOperand(1);
607  bool IsLittleEndian = !Subtarget.isLittle();
608 
609  SDValue IfSet, IfClr, Cond;
610  bool IsConstantMask = false;
611  APInt Mask, InvMask;
612 
613  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
614  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
615  // looking.
616  // IfClr will be set if we find a valid match.
617  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
618  Cond = Op0Op0;
619  IfSet = Op0Op1;
620 
621  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
622  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
623  IfClr = Op1Op1;
624  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
625  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
626  IfClr = Op1Op0;
627 
628  IsConstantMask = true;
629  }
630 
631  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
632  // thing again using this mask.
633  // IfClr will be set if we find a valid match.
634  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
635  Cond = Op0Op1;
636  IfSet = Op0Op0;
637 
638  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
639  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
640  IfClr = Op1Op1;
641  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
642  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
643  IfClr = Op1Op0;
644 
645  IsConstantMask = true;
646  }
647 
648  // If IfClr is not yet set, try looking for a non-constant match.
649  // IfClr will be set if we find a valid match amongst the eight
650  // possibilities.
651  if (!IfClr.getNode()) {
652  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
653  Cond = Op1Op0;
654  IfSet = Op1Op1;
655  IfClr = Op0Op1;
656  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
657  Cond = Op1Op0;
658  IfSet = Op1Op1;
659  IfClr = Op0Op0;
660  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
661  Cond = Op1Op1;
662  IfSet = Op1Op0;
663  IfClr = Op0Op1;
664  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
665  Cond = Op1Op1;
666  IfSet = Op1Op0;
667  IfClr = Op0Op0;
668  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
669  Cond = Op0Op0;
670  IfSet = Op0Op1;
671  IfClr = Op1Op1;
672  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
673  Cond = Op0Op0;
674  IfSet = Op0Op1;
675  IfClr = Op1Op0;
676  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
677  Cond = Op0Op1;
678  IfSet = Op0Op0;
679  IfClr = Op1Op1;
680  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
681  Cond = Op0Op1;
682  IfSet = Op0Op0;
683  IfClr = Op1Op0;
684  }
685  }
686 
687  // At this point, IfClr will be set if we have a valid match.
688  if (!IfClr.getNode())
689  return SDValue();
690 
691  assert(Cond.getNode() && IfSet.getNode());
692 
693  // Fold degenerate cases.
694  if (IsConstantMask) {
695  if (Mask.isAllOnesValue())
696  return IfSet;
697  else if (Mask == 0)
698  return IfClr;
699  }
700 
701  // Transform the DAG into an equivalent VSELECT.
702  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
703  }
704 
705  return SDValue();
706 }
707 
708 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
709  EVT ShiftTy, SelectionDAG &DAG) {
710  // Return 0.
711  if (C == 0)
712  return DAG.getConstant(0, DL, VT);
713 
714  // Return x.
715  if (C == 1)
716  return X;
717 
718  // If c is power of 2, return (shl x, log2(c)).
719  if (C.isPowerOf2())
720  return DAG.getNode(ISD::SHL, DL, VT, X,
721  DAG.getConstant(C.logBase2(), DL, ShiftTy));
722 
723  unsigned BitWidth = C.getBitWidth();
724  APInt Floor = APInt(BitWidth, 1) << C.logBase2();
725  APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
726  APInt(BitWidth, 1) << C.ceilLogBase2();
727 
728  // If |c - floor_c| <= |c - ceil_c|,
729  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
730  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
731  if ((C - Floor).ule(Ceil - C)) {
732  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
733  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
734  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
735  }
736 
737  // If |c - floor_c| > |c - ceil_c|,
738  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
739  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
740  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
741  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
742 }
743 
746  const MipsSETargetLowering *TL) {
747  EVT VT = N->getValueType(0);
748 
749  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
750  if (!VT.isVector())
751  return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
752  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
753  DAG);
754 
755  return SDValue(N, 0);
756 }
757 
758 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
759  SelectionDAG &DAG,
760  const MipsSubtarget &Subtarget) {
761  // See if this is a vector splat immediate node.
762  APInt SplatValue, SplatUndef;
763  unsigned SplatBitSize;
764  bool HasAnyUndefs;
765  unsigned EltSize = Ty.getScalarSizeInBits();
767 
768  if (!Subtarget.hasDSP())
769  return SDValue();
770 
771  if (!BV ||
772  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
773  EltSize, !Subtarget.isLittle()) ||
774  (SplatBitSize != EltSize) ||
775  (SplatValue.getZExtValue() >= EltSize))
776  return SDValue();
777 
778  SDLoc DL(N);
779  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
780  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
781 }
782 
785  const MipsSubtarget &Subtarget) {
786  EVT Ty = N->getValueType(0);
787 
788  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
789  return SDValue();
790 
791  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
792 }
793 
794 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
795 // constant splats into MipsISD::SHRA_DSP for DSPr2.
796 //
797 // Performs the following transformations:
798 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
799 // sign/zero-extension is completely overwritten by the new one performed by
800 // the ISD::SRA and ISD::SHL nodes.
801 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
802 // sequence.
803 //
804 // See performDSPShiftCombine for more information about the transformation
805 // used for DSPr2.
808  const MipsSubtarget &Subtarget) {
809  EVT Ty = N->getValueType(0);
810 
811  if (Subtarget.hasMSA()) {
812  SDValue Op0 = N->getOperand(0);
813  SDValue Op1 = N->getOperand(1);
814 
815  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
816  // where $d + sizeof($c) == 32
817  // or $d + sizeof($c) <= 32 and SExt
818  // -> (MipsVExtractSExt $a, $b, $c)
819  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
820  SDValue Op0Op0 = Op0->getOperand(0);
821  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
822 
823  if (!ShAmount)
824  return SDValue();
825 
826  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
828  return SDValue();
829 
830  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
831  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
832 
833  if (TotalBits == 32 ||
834  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
835  TotalBits <= 32)) {
836  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
837  Op0Op0->getOperand(2) };
838  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
839  Op0Op0->getVTList(),
840  makeArrayRef(Ops, Op0Op0->getNumOperands()));
841  }
842  }
843  }
844 
845  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
846  return SDValue();
847 
848  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
849 }
850 
851 
854  const MipsSubtarget &Subtarget) {
855  EVT Ty = N->getValueType(0);
856 
857  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
858  return SDValue();
859 
860  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
861 }
862 
863 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
864  bool IsV216 = (Ty == MVT::v2i16);
865 
866  switch (CC) {
867  case ISD::SETEQ:
868  case ISD::SETNE: return true;
869  case ISD::SETLT:
870  case ISD::SETLE:
871  case ISD::SETGT:
872  case ISD::SETGE: return IsV216;
873  case ISD::SETULT:
874  case ISD::SETULE:
875  case ISD::SETUGT:
876  case ISD::SETUGE: return !IsV216;
877  default: return false;
878  }
879 }
880 
882  EVT Ty = N->getValueType(0);
883 
884  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
885  return SDValue();
886 
887  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
888  return SDValue();
889 
890  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
891  N->getOperand(1), N->getOperand(2));
892 }
893 
895  EVT Ty = N->getValueType(0);
896 
897  if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
898  SDValue SetCC = N->getOperand(0);
899 
900  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
901  return SDValue();
902 
903  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
904  SetCC.getOperand(0), SetCC.getOperand(1),
905  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
906  }
907 
908  return SDValue();
909 }
910 
912  const MipsSubtarget &Subtarget) {
913  EVT Ty = N->getValueType(0);
914 
915  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
916  // Try the following combines:
917  // (xor (or $a, $b), (build_vector allones))
918  // (xor (or $a, $b), (bitcast (build_vector allones)))
919  SDValue Op0 = N->getOperand(0);
920  SDValue Op1 = N->getOperand(1);
921  SDValue NotOp;
922 
924  NotOp = Op1;
925  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
926  NotOp = Op0;
927  else
928  return SDValue();
929 
930  if (NotOp->getOpcode() == ISD::OR)
931  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
932  NotOp->getOperand(1));
933  }
934 
935  return SDValue();
936 }
937 
938 SDValue
940  SelectionDAG &DAG = DCI.DAG;
941  SDValue Val;
942 
943  switch (N->getOpcode()) {
944  case ISD::AND:
945  Val = performANDCombine(N, DAG, DCI, Subtarget);
946  break;
947  case ISD::OR:
948  Val = performORCombine(N, DAG, DCI, Subtarget);
949  break;
950  case ISD::MUL:
951  return performMULCombine(N, DAG, DCI, this);
952  case ISD::SHL:
953  Val = performSHLCombine(N, DAG, DCI, Subtarget);
954  break;
955  case ISD::SRA:
956  return performSRACombine(N, DAG, DCI, Subtarget);
957  case ISD::SRL:
958  return performSRLCombine(N, DAG, DCI, Subtarget);
959  case ISD::VSELECT:
960  return performVSELECTCombine(N, DAG);
961  case ISD::XOR:
962  Val = performXORCombine(N, DAG, Subtarget);
963  break;
964  case ISD::SETCC:
965  Val = performSETCCCombine(N, DAG);
966  break;
967  }
968 
969  if (Val.getNode()) {
970  DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
971  N->printrWithDepth(dbgs(), &DAG);
972  dbgs() << "\n=> \n";
973  Val.getNode()->printrWithDepth(dbgs(), &DAG);
974  dbgs() << "\n");
975  return Val;
976  }
977 
979 }
980 
983  MachineBasicBlock *BB) const {
984  switch (MI.getOpcode()) {
985  default:
987  case Mips::BPOSGE32_PSEUDO:
988  return emitBPOSGE32(MI, BB);
989  case Mips::SNZ_B_PSEUDO:
990  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
991  case Mips::SNZ_H_PSEUDO:
992  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
993  case Mips::SNZ_W_PSEUDO:
994  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
995  case Mips::SNZ_D_PSEUDO:
996  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
997  case Mips::SNZ_V_PSEUDO:
998  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
999  case Mips::SZ_B_PSEUDO:
1000  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1001  case Mips::SZ_H_PSEUDO:
1002  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1003  case Mips::SZ_W_PSEUDO:
1004  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1005  case Mips::SZ_D_PSEUDO:
1006  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1007  case Mips::SZ_V_PSEUDO:
1008  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1009  case Mips::COPY_FW_PSEUDO:
1010  return emitCOPY_FW(MI, BB);
1011  case Mips::COPY_FD_PSEUDO:
1012  return emitCOPY_FD(MI, BB);
1013  case Mips::INSERT_FW_PSEUDO:
1014  return emitINSERT_FW(MI, BB);
1015  case Mips::INSERT_FD_PSEUDO:
1016  return emitINSERT_FD(MI, BB);
1017  case Mips::INSERT_B_VIDX_PSEUDO:
1018  case Mips::INSERT_B_VIDX64_PSEUDO:
1019  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1020  case Mips::INSERT_H_VIDX_PSEUDO:
1021  case Mips::INSERT_H_VIDX64_PSEUDO:
1022  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1023  case Mips::INSERT_W_VIDX_PSEUDO:
1024  case Mips::INSERT_W_VIDX64_PSEUDO:
1025  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1026  case Mips::INSERT_D_VIDX_PSEUDO:
1027  case Mips::INSERT_D_VIDX64_PSEUDO:
1028  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1029  case Mips::INSERT_FW_VIDX_PSEUDO:
1030  case Mips::INSERT_FW_VIDX64_PSEUDO:
1031  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1032  case Mips::INSERT_FD_VIDX_PSEUDO:
1033  case Mips::INSERT_FD_VIDX64_PSEUDO:
1034  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1035  case Mips::FILL_FW_PSEUDO:
1036  return emitFILL_FW(MI, BB);
1037  case Mips::FILL_FD_PSEUDO:
1038  return emitFILL_FD(MI, BB);
1039  case Mips::FEXP2_W_1_PSEUDO:
1040  return emitFEXP2_W_1(MI, BB);
1041  case Mips::FEXP2_D_1_PSEUDO:
1042  return emitFEXP2_D_1(MI, BB);
1043  case Mips::ST_F16:
1044  return emitST_F16_PSEUDO(MI, BB);
1045  case Mips::LD_F16:
1046  return emitLD_F16_PSEUDO(MI, BB);
1047  case Mips::MSA_FP_EXTEND_W_PSEUDO:
1048  return emitFPEXTEND_PSEUDO(MI, BB, false);
1049  case Mips::MSA_FP_ROUND_W_PSEUDO:
1050  return emitFPROUND_PSEUDO(MI, BB, false);
1051  case Mips::MSA_FP_EXTEND_D_PSEUDO:
1052  return emitFPEXTEND_PSEUDO(MI, BB, true);
1053  case Mips::MSA_FP_ROUND_D_PSEUDO:
1054  return emitFPROUND_PSEUDO(MI, BB, true);
1055  }
1056 }
1057 
1058 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1059  const CCState &CCInfo, unsigned NextStackOffset,
1060  const MipsFunctionInfo &FI) const {
1061  if (!UseMipsTailCalls)
1062  return false;
1063 
1064  // Exception has to be cleared with eret.
1065  if (FI.isISR())
1066  return false;
1067 
1068  // Return false if either the callee or caller has a byval argument.
1069  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1070  return false;
1071 
1072  // Return true if the callee's argument area is no larger than the
1073  // caller's.
1074  return NextStackOffset <= FI.getIncomingArgSize();
1075 }
1076 
1077 void MipsSETargetLowering::
1078 getOpndList(SmallVectorImpl<SDValue> &Ops,
1079  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1080  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1081  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1082  SDValue Chain) const {
1083  Ops.push_back(Callee);
1084  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1085  InternalLinkage, IsCallReloc, CLI, Callee,
1086  Chain);
1087 }
1088 
1089 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1090  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1091 
1092  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1093  return MipsTargetLowering::lowerLOAD(Op, DAG);
1094 
1095  // Replace a double precision load with two i32 loads and a buildpair64.
1096  SDLoc DL(Op);
1097  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1098  EVT PtrVT = Ptr.getValueType();
1099 
1100  // i32 load from lower address.
1101  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1102  Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1103 
1104  // i32 load from higher address.
1105  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1106  SDValue Hi = DAG.getLoad(
1107  MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1108  std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1109 
1110  if (!Subtarget.isLittle())
1111  std::swap(Lo, Hi);
1112 
1113  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1114  SDValue Ops[2] = {BP, Hi.getValue(1)};
1115  return DAG.getMergeValues(Ops, DL);
1116 }
1117 
1118 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1119  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1120 
1121  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1122  return MipsTargetLowering::lowerSTORE(Op, DAG);
1123 
1124  // Replace a double precision store with two extractelement64s and i32 stores.
1125  SDLoc DL(Op);
1126  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1127  EVT PtrVT = Ptr.getValueType();
1129  Val, DAG.getConstant(0, DL, MVT::i32));
1131  Val, DAG.getConstant(1, DL, MVT::i32));
1132 
1133  if (!Subtarget.isLittle())
1134  std::swap(Lo, Hi);
1135 
1136  // i32 store to lower address.
1137  Chain =
1138  DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1139  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1140 
1141  // i32 store to higher address.
1142  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1143  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1144  std::min(Nd.getAlignment(), 4U),
1145  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1146 }
1147 
1148 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1149  bool HasLo, bool HasHi,
1150  SelectionDAG &DAG) const {
1151  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1153 
1154  EVT Ty = Op.getOperand(0).getValueType();
1155  SDLoc DL(Op);
1156  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1157  Op.getOperand(0), Op.getOperand(1));
1158  SDValue Lo, Hi;
1159 
1160  if (HasLo)
1161  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1162  if (HasHi)
1163  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1164 
1165  if (!HasLo || !HasHi)
1166  return HasLo ? Lo : Hi;
1167 
1168  SDValue Vals[] = { Lo, Hi };
1169  return DAG.getMergeValues(Vals, DL);
1170 }
1171 
1173  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1174  DAG.getConstant(0, DL, MVT::i32));
1175  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1176  DAG.getConstant(1, DL, MVT::i32));
1177  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1178 }
1179 
1180 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1181  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1182  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1183  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1184 }
1185 
1186 // This function expands mips intrinsic nodes which have 64-bit input operands
1187 // or output values.
1188 //
1189 // out64 = intrinsic-node in64
1190 // =>
1191 // lo = copy (extract-element (in64, 0))
1192 // hi = copy (extract-element (in64, 1))
1193 // mips-specific-node
1194 // v0 = copy lo
1195 // v1 = copy hi
1196 // out64 = merge-values (v0, v1)
1197 //
1198 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1199  SDLoc DL(Op);
1200  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1202  unsigned OpNo = 0;
1203 
1204  // See if Op has a chain input.
1205  if (HasChainIn)
1206  Ops.push_back(Op->getOperand(OpNo++));
1207 
1208  // The next operand is the intrinsic opcode.
1210 
1211  // See if the next operand has type i64.
1212  SDValue Opnd = Op->getOperand(++OpNo), In64;
1213 
1214  if (Opnd.getValueType() == MVT::i64)
1215  In64 = initAccumulator(Opnd, DL, DAG);
1216  else
1217  Ops.push_back(Opnd);
1218 
1219  // Push the remaining operands.
1220  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1221  Ops.push_back(Op->getOperand(OpNo));
1222 
1223  // Add In64 to the end of the list.
1224  if (In64.getNode())
1225  Ops.push_back(In64);
1226 
1227  // Scan output.
1228  SmallVector<EVT, 2> ResTys;
1229 
1230  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1231  I != E; ++I)
1232  ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1233 
1234  // Create node.
1235  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1236  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1237 
1238  if (!HasChainIn)
1239  return Out;
1240 
1241  assert(Val->getValueType(1) == MVT::Other);
1242  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1243  return DAG.getMergeValues(Vals, DL);
1244 }
1245 
1246 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1247 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1248  SDLoc DL(Op);
1249  SDValue Vec = Op->getOperand(1);
1250  SDValue Idx = Op->getOperand(2);
1251  EVT ResTy = Op->getValueType(0);
1252  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1253 
1254  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1255  DAG.getValueType(EltTy));
1256 
1257  return Result;
1258 }
1259 
1260 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1261  EVT ResVecTy = Op->getValueType(0);
1262  EVT ViaVecTy = ResVecTy;
1263  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1264  SDLoc DL(Op);
1265 
1266  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1267  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1268  // lanes.
1269  SDValue LaneA = Op->getOperand(OpNr);
1270  SDValue LaneB;
1271 
1272  if (ResVecTy == MVT::v2i64) {
1273  LaneB = DAG.getConstant(0, DL, MVT::i32);
1274  ViaVecTy = MVT::v4i32;
1275  if(BigEndian)
1276  std::swap(LaneA, LaneB);
1277  } else
1278  LaneB = LaneA;
1279 
1280  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1281  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1282 
1283  SDValue Result = DAG.getBuildVector(
1284  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1285 
1286  if (ViaVecTy != ResVecTy) {
1287  SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1288  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1289  DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1290  }
1291 
1292  return Result;
1293 }
1294 
1295 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1296  bool IsSigned = false) {
1297  return DAG.getConstant(
1299  Op->getConstantOperandVal(ImmOp), IsSigned),
1300  SDLoc(Op), Op->getValueType(0));
1301 }
1302 
1303 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1304  bool BigEndian, SelectionDAG &DAG) {
1305  EVT ViaVecTy = VecTy;
1306  SDValue SplatValueA = SplatValue;
1307  SDValue SplatValueB = SplatValue;
1308  SDLoc DL(SplatValue);
1309 
1310  if (VecTy == MVT::v2i64) {
1311  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1312  ViaVecTy = MVT::v4i32;
1313 
1314  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1315  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1316  DAG.getConstant(32, DL, MVT::i32));
1317  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1318  }
1319 
1320  // We currently hold the parts in little endian order. Swap them if
1321  // necessary.
1322  if (BigEndian)
1323  std::swap(SplatValueA, SplatValueB);
1324 
1325  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1326  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1327  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1328  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1329 
1330  SDValue Result = DAG.getBuildVector(
1331  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1332 
1333  if (VecTy != ViaVecTy)
1334  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1335 
1336  return Result;
1337 }
1338 
1340  unsigned Opc, SDValue Imm,
1341  bool BigEndian) {
1342  EVT VecTy = Op->getValueType(0);
1343  SDValue Exp2Imm;
1344  SDLoc DL(Op);
1345 
1346  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1347  // here for now.
1348  if (VecTy == MVT::v2i64) {
1349  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1350  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1351 
1352  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1353  MVT::i32);
1354  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1355 
1356  if (BigEndian)
1357  std::swap(BitImmLoOp, BitImmHiOp);
1358 
1359  Exp2Imm = DAG.getNode(
1360  ISD::BITCAST, DL, MVT::v2i64,
1361  DAG.getBuildVector(MVT::v4i32, DL,
1362  {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1363  }
1364  }
1365 
1366  if (!Exp2Imm.getNode()) {
1367  // We couldnt constant fold, do a vector shift instead
1368 
1369  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1370  // only values 0-63 are valid.
1371  if (VecTy == MVT::v2i64)
1372  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1373 
1374  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1375 
1376  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1377  Exp2Imm);
1378  }
1379 
1380  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1381 }
1382 
1384  SDLoc DL(Op);
1385  EVT ResTy = Op->getValueType(0);
1386  SDValue Vec = Op->getOperand(2);
1387  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1388  MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1389  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1390  DL, ResEltTy);
1391  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1392 
1393  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1394 }
1395 
1397  EVT ResTy = Op->getValueType(0);
1398  SDLoc DL(Op);
1399  SDValue One = DAG.getConstant(1, DL, ResTy);
1400  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1401 
1402  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1403  DAG.getNOT(DL, Bit, ResTy));
1404 }
1405 
1407  SDLoc DL(Op);
1408  EVT ResTy = Op->getValueType(0);
1409  APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1410  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1411  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1412 
1413  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1414 }
1415 
1416 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1417  SelectionDAG &DAG) const {
1418  SDLoc DL(Op);
1419  unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1420  switch (Intrinsic) {
1421  default:
1422  return SDValue();
1423  case Intrinsic::mips_shilo:
1424  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1425  case Intrinsic::mips_dpau_h_qbl:
1426  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1427  case Intrinsic::mips_dpau_h_qbr:
1428  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1429  case Intrinsic::mips_dpsu_h_qbl:
1430  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1431  case Intrinsic::mips_dpsu_h_qbr:
1432  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1433  case Intrinsic::mips_dpa_w_ph:
1434  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1435  case Intrinsic::mips_dps_w_ph:
1436  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1437  case Intrinsic::mips_dpax_w_ph:
1438  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1439  case Intrinsic::mips_dpsx_w_ph:
1440  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1441  case Intrinsic::mips_mulsa_w_ph:
1442  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1443  case Intrinsic::mips_mult:
1444  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1445  case Intrinsic::mips_multu:
1446  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1447  case Intrinsic::mips_madd:
1448  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1449  case Intrinsic::mips_maddu:
1450  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1451  case Intrinsic::mips_msub:
1452  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1453  case Intrinsic::mips_msubu:
1454  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1455  case Intrinsic::mips_addv_b:
1456  case Intrinsic::mips_addv_h:
1457  case Intrinsic::mips_addv_w:
1458  case Intrinsic::mips_addv_d:
1459  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1460  Op->getOperand(2));
1461  case Intrinsic::mips_addvi_b:
1462  case Intrinsic::mips_addvi_h:
1463  case Intrinsic::mips_addvi_w:
1464  case Intrinsic::mips_addvi_d:
1465  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1466  lowerMSASplatImm(Op, 2, DAG));
1467  case Intrinsic::mips_and_v:
1468  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1469  Op->getOperand(2));
1470  case Intrinsic::mips_andi_b:
1471  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1472  lowerMSASplatImm(Op, 2, DAG));
1473  case Intrinsic::mips_bclr_b:
1474  case Intrinsic::mips_bclr_h:
1475  case Intrinsic::mips_bclr_w:
1476  case Intrinsic::mips_bclr_d:
1477  return lowerMSABitClear(Op, DAG);
1478  case Intrinsic::mips_bclri_b:
1479  case Intrinsic::mips_bclri_h:
1480  case Intrinsic::mips_bclri_w:
1481  case Intrinsic::mips_bclri_d:
1482  return lowerMSABitClearImm(Op, DAG);
1483  case Intrinsic::mips_binsli_b:
1484  case Intrinsic::mips_binsli_h:
1485  case Intrinsic::mips_binsli_w:
1486  case Intrinsic::mips_binsli_d: {
1487  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1488  EVT VecTy = Op->getValueType(0);
1489  EVT EltTy = VecTy.getVectorElementType();
1490  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1491  report_fatal_error("Immediate out of range");
1493  Op->getConstantOperandVal(3) + 1);
1494  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1495  DAG.getConstant(Mask, DL, VecTy, true),
1496  Op->getOperand(2), Op->getOperand(1));
1497  }
1498  case Intrinsic::mips_binsri_b:
1499  case Intrinsic::mips_binsri_h:
1500  case Intrinsic::mips_binsri_w:
1501  case Intrinsic::mips_binsri_d: {
1502  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1503  EVT VecTy = Op->getValueType(0);
1504  EVT EltTy = VecTy.getVectorElementType();
1505  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1506  report_fatal_error("Immediate out of range");
1508  Op->getConstantOperandVal(3) + 1);
1509  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1510  DAG.getConstant(Mask, DL, VecTy, true),
1511  Op->getOperand(2), Op->getOperand(1));
1512  }
1513  case Intrinsic::mips_bmnz_v:
1514  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1515  Op->getOperand(2), Op->getOperand(1));
1516  case Intrinsic::mips_bmnzi_b:
1517  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1518  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1519  Op->getOperand(1));
1520  case Intrinsic::mips_bmz_v:
1521  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1522  Op->getOperand(1), Op->getOperand(2));
1523  case Intrinsic::mips_bmzi_b:
1524  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1525  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1526  Op->getOperand(2));
1527  case Intrinsic::mips_bneg_b:
1528  case Intrinsic::mips_bneg_h:
1529  case Intrinsic::mips_bneg_w:
1530  case Intrinsic::mips_bneg_d: {
1531  EVT VecTy = Op->getValueType(0);
1532  SDValue One = DAG.getConstant(1, DL, VecTy);
1533 
1534  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1535  DAG.getNode(ISD::SHL, DL, VecTy, One,
1536  truncateVecElts(Op, DAG)));
1537  }
1538  case Intrinsic::mips_bnegi_b:
1539  case Intrinsic::mips_bnegi_h:
1540  case Intrinsic::mips_bnegi_w:
1541  case Intrinsic::mips_bnegi_d:
1542  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1543  !Subtarget.isLittle());
1544  case Intrinsic::mips_bnz_b:
1545  case Intrinsic::mips_bnz_h:
1546  case Intrinsic::mips_bnz_w:
1547  case Intrinsic::mips_bnz_d:
1548  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1549  Op->getOperand(1));
1550  case Intrinsic::mips_bnz_v:
1551  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1552  Op->getOperand(1));
1553  case Intrinsic::mips_bsel_v:
1554  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1555  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1556  Op->getOperand(1), Op->getOperand(3),
1557  Op->getOperand(2));
1558  case Intrinsic::mips_bseli_b:
1559  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1560  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1561  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1562  Op->getOperand(2));
1563  case Intrinsic::mips_bset_b:
1564  case Intrinsic::mips_bset_h:
1565  case Intrinsic::mips_bset_w:
1566  case Intrinsic::mips_bset_d: {
1567  EVT VecTy = Op->getValueType(0);
1568  SDValue One = DAG.getConstant(1, DL, VecTy);
1569 
1570  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1571  DAG.getNode(ISD::SHL, DL, VecTy, One,
1572  truncateVecElts(Op, DAG)));
1573  }
1574  case Intrinsic::mips_bseti_b:
1575  case Intrinsic::mips_bseti_h:
1576  case Intrinsic::mips_bseti_w:
1577  case Intrinsic::mips_bseti_d:
1578  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1579  !Subtarget.isLittle());
1580  case Intrinsic::mips_bz_b:
1581  case Intrinsic::mips_bz_h:
1582  case Intrinsic::mips_bz_w:
1583  case Intrinsic::mips_bz_d:
1584  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1585  Op->getOperand(1));
1586  case Intrinsic::mips_bz_v:
1587  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1588  Op->getOperand(1));
1589  case Intrinsic::mips_ceq_b:
1590  case Intrinsic::mips_ceq_h:
1591  case Intrinsic::mips_ceq_w:
1592  case Intrinsic::mips_ceq_d:
1593  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1594  Op->getOperand(2), ISD::SETEQ);
1595  case Intrinsic::mips_ceqi_b:
1596  case Intrinsic::mips_ceqi_h:
1597  case Intrinsic::mips_ceqi_w:
1598  case Intrinsic::mips_ceqi_d:
1599  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1600  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1601  case Intrinsic::mips_cle_s_b:
1602  case Intrinsic::mips_cle_s_h:
1603  case Intrinsic::mips_cle_s_w:
1604  case Intrinsic::mips_cle_s_d:
1605  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1606  Op->getOperand(2), ISD::SETLE);
1607  case Intrinsic::mips_clei_s_b:
1608  case Intrinsic::mips_clei_s_h:
1609  case Intrinsic::mips_clei_s_w:
1610  case Intrinsic::mips_clei_s_d:
1611  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1612  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1613  case Intrinsic::mips_cle_u_b:
1614  case Intrinsic::mips_cle_u_h:
1615  case Intrinsic::mips_cle_u_w:
1616  case Intrinsic::mips_cle_u_d:
1617  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1618  Op->getOperand(2), ISD::SETULE);
1619  case Intrinsic::mips_clei_u_b:
1620  case Intrinsic::mips_clei_u_h:
1621  case Intrinsic::mips_clei_u_w:
1622  case Intrinsic::mips_clei_u_d:
1623  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1624  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1625  case Intrinsic::mips_clt_s_b:
1626  case Intrinsic::mips_clt_s_h:
1627  case Intrinsic::mips_clt_s_w:
1628  case Intrinsic::mips_clt_s_d:
1629  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1630  Op->getOperand(2), ISD::SETLT);
1631  case Intrinsic::mips_clti_s_b:
1632  case Intrinsic::mips_clti_s_h:
1633  case Intrinsic::mips_clti_s_w:
1634  case Intrinsic::mips_clti_s_d:
1635  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1636  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1637  case Intrinsic::mips_clt_u_b:
1638  case Intrinsic::mips_clt_u_h:
1639  case Intrinsic::mips_clt_u_w:
1640  case Intrinsic::mips_clt_u_d:
1641  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1642  Op->getOperand(2), ISD::SETULT);
1643  case Intrinsic::mips_clti_u_b:
1644  case Intrinsic::mips_clti_u_h:
1645  case Intrinsic::mips_clti_u_w:
1646  case Intrinsic::mips_clti_u_d:
1647  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1648  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1649  case Intrinsic::mips_copy_s_b:
1650  case Intrinsic::mips_copy_s_h:
1651  case Intrinsic::mips_copy_s_w:
1653  case Intrinsic::mips_copy_s_d:
1654  if (Subtarget.hasMips64())
1655  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1657  else {
1658  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1659  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1660  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1661  Op->getValueType(0), Op->getOperand(1),
1662  Op->getOperand(2));
1663  }
1664  case Intrinsic::mips_copy_u_b:
1665  case Intrinsic::mips_copy_u_h:
1666  case Intrinsic::mips_copy_u_w:
1668  case Intrinsic::mips_copy_u_d:
1669  if (Subtarget.hasMips64())
1670  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1672  else {
1673  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1674  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1675  // Note: When i64 is illegal, this results in copy_s.w instructions
1676  // instead of copy_u.w instructions. This makes no difference to the
1677  // behaviour since i64 is only illegal when the register file is 32-bit.
1678  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1679  Op->getValueType(0), Op->getOperand(1),
1680  Op->getOperand(2));
1681  }
1682  case Intrinsic::mips_div_s_b:
1683  case Intrinsic::mips_div_s_h:
1684  case Intrinsic::mips_div_s_w:
1685  case Intrinsic::mips_div_s_d:
1686  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1687  Op->getOperand(2));
1688  case Intrinsic::mips_div_u_b:
1689  case Intrinsic::mips_div_u_h:
1690  case Intrinsic::mips_div_u_w:
1691  case Intrinsic::mips_div_u_d:
1692  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1693  Op->getOperand(2));
1694  case Intrinsic::mips_fadd_w:
1695  case Intrinsic::mips_fadd_d:
1696  // TODO: If intrinsics have fast-math-flags, propagate them.
1697  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1698  Op->getOperand(2));
1699  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1700  case Intrinsic::mips_fceq_w:
1701  case Intrinsic::mips_fceq_d:
1702  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1703  Op->getOperand(2), ISD::SETOEQ);
1704  case Intrinsic::mips_fcle_w:
1705  case Intrinsic::mips_fcle_d:
1706  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1707  Op->getOperand(2), ISD::SETOLE);
1708  case Intrinsic::mips_fclt_w:
1709  case Intrinsic::mips_fclt_d:
1710  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1711  Op->getOperand(2), ISD::SETOLT);
1712  case Intrinsic::mips_fcne_w:
1713  case Intrinsic::mips_fcne_d:
1714  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1715  Op->getOperand(2), ISD::SETONE);
1716  case Intrinsic::mips_fcor_w:
1717  case Intrinsic::mips_fcor_d:
1718  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1719  Op->getOperand(2), ISD::SETO);
1720  case Intrinsic::mips_fcueq_w:
1721  case Intrinsic::mips_fcueq_d:
1722  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1723  Op->getOperand(2), ISD::SETUEQ);
1724  case Intrinsic::mips_fcule_w:
1725  case Intrinsic::mips_fcule_d:
1726  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1727  Op->getOperand(2), ISD::SETULE);
1728  case Intrinsic::mips_fcult_w:
1729  case Intrinsic::mips_fcult_d:
1730  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1731  Op->getOperand(2), ISD::SETULT);
1732  case Intrinsic::mips_fcun_w:
1733  case Intrinsic::mips_fcun_d:
1734  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1735  Op->getOperand(2), ISD::SETUO);
1736  case Intrinsic::mips_fcune_w:
1737  case Intrinsic::mips_fcune_d:
1738  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1739  Op->getOperand(2), ISD::SETUNE);
1740  case Intrinsic::mips_fdiv_w:
1741  case Intrinsic::mips_fdiv_d:
1742  // TODO: If intrinsics have fast-math-flags, propagate them.
1743  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1744  Op->getOperand(2));
1745  case Intrinsic::mips_ffint_u_w:
1746  case Intrinsic::mips_ffint_u_d:
1747  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1748  Op->getOperand(1));
1749  case Intrinsic::mips_ffint_s_w:
1750  case Intrinsic::mips_ffint_s_d:
1751  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1752  Op->getOperand(1));
1753  case Intrinsic::mips_fill_b:
1754  case Intrinsic::mips_fill_h:
1755  case Intrinsic::mips_fill_w:
1756  case Intrinsic::mips_fill_d: {
1757  EVT ResTy = Op->getValueType(0);
1759  Op->getOperand(1));
1760 
1761  // If ResTy is v2i64 then the type legalizer will break this node down into
1762  // an equivalent v4i32.
1763  return DAG.getBuildVector(ResTy, DL, Ops);
1764  }
1765  case Intrinsic::mips_fexp2_w:
1766  case Intrinsic::mips_fexp2_d: {
1767  // TODO: If intrinsics have fast-math-flags, propagate them.
1768  EVT ResTy = Op->getValueType(0);
1769  return DAG.getNode(
1770  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1771  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1772  }
1773  case Intrinsic::mips_flog2_w:
1774  case Intrinsic::mips_flog2_d:
1775  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1776  case Intrinsic::mips_fmadd_w:
1777  case Intrinsic::mips_fmadd_d:
1778  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1779  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1780  case Intrinsic::mips_fmul_w:
1781  case Intrinsic::mips_fmul_d:
1782  // TODO: If intrinsics have fast-math-flags, propagate them.
1783  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1784  Op->getOperand(2));
1785  case Intrinsic::mips_fmsub_w:
1786  case Intrinsic::mips_fmsub_d: {
1787  // TODO: If intrinsics have fast-math-flags, propagate them.
1788  EVT ResTy = Op->getValueType(0);
1789  return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1790  DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1791  Op->getOperand(2), Op->getOperand(3)));
1792  }
1793  case Intrinsic::mips_frint_w:
1794  case Intrinsic::mips_frint_d:
1795  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1796  case Intrinsic::mips_fsqrt_w:
1797  case Intrinsic::mips_fsqrt_d:
1798  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1799  case Intrinsic::mips_fsub_w:
1800  case Intrinsic::mips_fsub_d:
1801  // TODO: If intrinsics have fast-math-flags, propagate them.
1802  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1803  Op->getOperand(2));
1804  case Intrinsic::mips_ftrunc_u_w:
1805  case Intrinsic::mips_ftrunc_u_d:
1806  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1807  Op->getOperand(1));
1808  case Intrinsic::mips_ftrunc_s_w:
1809  case Intrinsic::mips_ftrunc_s_d:
1810  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1811  Op->getOperand(1));
1812  case Intrinsic::mips_ilvev_b:
1813  case Intrinsic::mips_ilvev_h:
1814  case Intrinsic::mips_ilvev_w:
1815  case Intrinsic::mips_ilvev_d:
1816  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1817  Op->getOperand(1), Op->getOperand(2));
1818  case Intrinsic::mips_ilvl_b:
1819  case Intrinsic::mips_ilvl_h:
1820  case Intrinsic::mips_ilvl_w:
1821  case Intrinsic::mips_ilvl_d:
1822  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1823  Op->getOperand(1), Op->getOperand(2));
1824  case Intrinsic::mips_ilvod_b:
1825  case Intrinsic::mips_ilvod_h:
1826  case Intrinsic::mips_ilvod_w:
1827  case Intrinsic::mips_ilvod_d:
1828  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1829  Op->getOperand(1), Op->getOperand(2));
1830  case Intrinsic::mips_ilvr_b:
1831  case Intrinsic::mips_ilvr_h:
1832  case Intrinsic::mips_ilvr_w:
1833  case Intrinsic::mips_ilvr_d:
1834  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1835  Op->getOperand(1), Op->getOperand(2));
1836  case Intrinsic::mips_insert_b:
1837  case Intrinsic::mips_insert_h:
1838  case Intrinsic::mips_insert_w:
1839  case Intrinsic::mips_insert_d:
1840  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1841  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1842  case Intrinsic::mips_insve_b:
1843  case Intrinsic::mips_insve_h:
1844  case Intrinsic::mips_insve_w:
1845  case Intrinsic::mips_insve_d: {
1846  // Report an error for out of range values.
1847  int64_t Max;
1848  switch (Intrinsic) {
1849  case Intrinsic::mips_insve_b: Max = 15; break;
1850  case Intrinsic::mips_insve_h: Max = 7; break;
1851  case Intrinsic::mips_insve_w: Max = 3; break;
1852  case Intrinsic::mips_insve_d: Max = 1; break;
1853  default: llvm_unreachable("Unmatched intrinsic");
1854  }
1855  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1856  if (Value < 0 || Value > Max)
1857  report_fatal_error("Immediate out of range");
1858  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1859  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1860  DAG.getConstant(0, DL, MVT::i32));
1861  }
1862  case Intrinsic::mips_ldi_b:
1863  case Intrinsic::mips_ldi_h:
1864  case Intrinsic::mips_ldi_w:
1865  case Intrinsic::mips_ldi_d:
1866  return lowerMSASplatImm(Op, 1, DAG, true);
1867  case Intrinsic::mips_lsa:
1868  case Intrinsic::mips_dlsa: {
1869  EVT ResTy = Op->getValueType(0);
1870  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1871  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1872  Op->getOperand(2), Op->getOperand(3)));
1873  }
1874  case Intrinsic::mips_maddv_b:
1875  case Intrinsic::mips_maddv_h:
1876  case Intrinsic::mips_maddv_w:
1877  case Intrinsic::mips_maddv_d: {
1878  EVT ResTy = Op->getValueType(0);
1879  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1880  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1881  Op->getOperand(2), Op->getOperand(3)));
1882  }
1883  case Intrinsic::mips_max_s_b:
1884  case Intrinsic::mips_max_s_h:
1885  case Intrinsic::mips_max_s_w:
1886  case Intrinsic::mips_max_s_d:
1887  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
1888  Op->getOperand(1), Op->getOperand(2));
1889  case Intrinsic::mips_max_u_b:
1890  case Intrinsic::mips_max_u_h:
1891  case Intrinsic::mips_max_u_w:
1892  case Intrinsic::mips_max_u_d:
1893  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
1894  Op->getOperand(1), Op->getOperand(2));
1895  case Intrinsic::mips_maxi_s_b:
1896  case Intrinsic::mips_maxi_s_h:
1897  case Intrinsic::mips_maxi_s_w:
1898  case Intrinsic::mips_maxi_s_d:
1899  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
1900  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
1901  case Intrinsic::mips_maxi_u_b:
1902  case Intrinsic::mips_maxi_u_h:
1903  case Intrinsic::mips_maxi_u_w:
1904  case Intrinsic::mips_maxi_u_d:
1905  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
1906  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1907  case Intrinsic::mips_min_s_b:
1908  case Intrinsic::mips_min_s_h:
1909  case Intrinsic::mips_min_s_w:
1910  case Intrinsic::mips_min_s_d:
1911  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
1912  Op->getOperand(1), Op->getOperand(2));
1913  case Intrinsic::mips_min_u_b:
1914  case Intrinsic::mips_min_u_h:
1915  case Intrinsic::mips_min_u_w:
1916  case Intrinsic::mips_min_u_d:
1917  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
1918  Op->getOperand(1), Op->getOperand(2));
1919  case Intrinsic::mips_mini_s_b:
1920  case Intrinsic::mips_mini_s_h:
1921  case Intrinsic::mips_mini_s_w:
1922  case Intrinsic::mips_mini_s_d:
1923  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
1924  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
1925  case Intrinsic::mips_mini_u_b:
1926  case Intrinsic::mips_mini_u_h:
1927  case Intrinsic::mips_mini_u_w:
1928  case Intrinsic::mips_mini_u_d:
1929  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
1930  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1931  case Intrinsic::mips_mod_s_b:
1932  case Intrinsic::mips_mod_s_h:
1933  case Intrinsic::mips_mod_s_w:
1934  case Intrinsic::mips_mod_s_d:
1935  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1936  Op->getOperand(2));
1937  case Intrinsic::mips_mod_u_b:
1938  case Intrinsic::mips_mod_u_h:
1939  case Intrinsic::mips_mod_u_w:
1940  case Intrinsic::mips_mod_u_d:
1941  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1942  Op->getOperand(2));
1943  case Intrinsic::mips_mulv_b:
1944  case Intrinsic::mips_mulv_h:
1945  case Intrinsic::mips_mulv_w:
1946  case Intrinsic::mips_mulv_d:
1947  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1948  Op->getOperand(2));
1949  case Intrinsic::mips_msubv_b:
1950  case Intrinsic::mips_msubv_h:
1951  case Intrinsic::mips_msubv_w:
1952  case Intrinsic::mips_msubv_d: {
1953  EVT ResTy = Op->getValueType(0);
1954  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1955  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1956  Op->getOperand(2), Op->getOperand(3)));
1957  }
1958  case Intrinsic::mips_nlzc_b:
1959  case Intrinsic::mips_nlzc_h:
1960  case Intrinsic::mips_nlzc_w:
1961  case Intrinsic::mips_nlzc_d:
1962  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1963  case Intrinsic::mips_nor_v: {
1964  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1965  Op->getOperand(1), Op->getOperand(2));
1966  return DAG.getNOT(DL, Res, Res->getValueType(0));
1967  }
1968  case Intrinsic::mips_nori_b: {
1969  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1970  Op->getOperand(1),
1971  lowerMSASplatImm(Op, 2, DAG));
1972  return DAG.getNOT(DL, Res, Res->getValueType(0));
1973  }
1974  case Intrinsic::mips_or_v:
1975  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1976  Op->getOperand(2));
1977  case Intrinsic::mips_ori_b:
1978  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1979  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1980  case Intrinsic::mips_pckev_b:
1981  case Intrinsic::mips_pckev_h:
1982  case Intrinsic::mips_pckev_w:
1983  case Intrinsic::mips_pckev_d:
1984  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1985  Op->getOperand(1), Op->getOperand(2));
1986  case Intrinsic::mips_pckod_b:
1987  case Intrinsic::mips_pckod_h:
1988  case Intrinsic::mips_pckod_w:
1989  case Intrinsic::mips_pckod_d:
1990  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1991  Op->getOperand(1), Op->getOperand(2));
1992  case Intrinsic::mips_pcnt_b:
1993  case Intrinsic::mips_pcnt_h:
1994  case Intrinsic::mips_pcnt_w:
1995  case Intrinsic::mips_pcnt_d:
1996  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1997  case Intrinsic::mips_sat_s_b:
1998  case Intrinsic::mips_sat_s_h:
1999  case Intrinsic::mips_sat_s_w:
2000  case Intrinsic::mips_sat_s_d:
2001  case Intrinsic::mips_sat_u_b:
2002  case Intrinsic::mips_sat_u_h:
2003  case Intrinsic::mips_sat_u_w:
2004  case Intrinsic::mips_sat_u_d: {
2005  // Report an error for out of range values.
2006  int64_t Max;
2007  switch (Intrinsic) {
2008  case Intrinsic::mips_sat_s_b:
2009  case Intrinsic::mips_sat_u_b: Max = 7; break;
2010  case Intrinsic::mips_sat_s_h:
2011  case Intrinsic::mips_sat_u_h: Max = 15; break;
2012  case Intrinsic::mips_sat_s_w:
2013  case Intrinsic::mips_sat_u_w: Max = 31; break;
2014  case Intrinsic::mips_sat_s_d:
2015  case Intrinsic::mips_sat_u_d: Max = 63; break;
2016  default: llvm_unreachable("Unmatched intrinsic");
2017  }
2018  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2019  if (Value < 0 || Value > Max)
2020  report_fatal_error("Immediate out of range");
2021  return SDValue();
2022  }
2023  case Intrinsic::mips_shf_b:
2024  case Intrinsic::mips_shf_h:
2025  case Intrinsic::mips_shf_w: {
2026  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2027  if (Value < 0 || Value > 255)
2028  report_fatal_error("Immediate out of range");
2029  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2030  Op->getOperand(2), Op->getOperand(1));
2031  }
2032  case Intrinsic::mips_sldi_b:
2033  case Intrinsic::mips_sldi_h:
2034  case Intrinsic::mips_sldi_w:
2035  case Intrinsic::mips_sldi_d: {
2036  // Report an error for out of range values.
2037  int64_t Max;
2038  switch (Intrinsic) {
2039  case Intrinsic::mips_sldi_b: Max = 15; break;
2040  case Intrinsic::mips_sldi_h: Max = 7; break;
2041  case Intrinsic::mips_sldi_w: Max = 3; break;
2042  case Intrinsic::mips_sldi_d: Max = 1; break;
2043  default: llvm_unreachable("Unmatched intrinsic");
2044  }
2045  int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2046  if (Value < 0 || Value > Max)
2047  report_fatal_error("Immediate out of range");
2048  return SDValue();
2049  }
2050  case Intrinsic::mips_sll_b:
2051  case Intrinsic::mips_sll_h:
2052  case Intrinsic::mips_sll_w:
2053  case Intrinsic::mips_sll_d:
2054  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2055  truncateVecElts(Op, DAG));
2056  case Intrinsic::mips_slli_b:
2057  case Intrinsic::mips_slli_h:
2058  case Intrinsic::mips_slli_w:
2059  case Intrinsic::mips_slli_d:
2060  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2061  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2062  case Intrinsic::mips_splat_b:
2063  case Intrinsic::mips_splat_h:
2064  case Intrinsic::mips_splat_w:
2065  case Intrinsic::mips_splat_d:
2066  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2067  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2068  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2069  // Instead we lower to MipsISD::VSHF and match from there.
2070  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2071  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2072  Op->getOperand(1));
2073  case Intrinsic::mips_splati_b:
2074  case Intrinsic::mips_splati_h:
2075  case Intrinsic::mips_splati_w:
2076  case Intrinsic::mips_splati_d:
2077  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2078  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2079  Op->getOperand(1));
2080  case Intrinsic::mips_sra_b:
2081  case Intrinsic::mips_sra_h:
2082  case Intrinsic::mips_sra_w:
2083  case Intrinsic::mips_sra_d:
2084  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2085  truncateVecElts(Op, DAG));
2086  case Intrinsic::mips_srai_b:
2087  case Intrinsic::mips_srai_h:
2088  case Intrinsic::mips_srai_w:
2089  case Intrinsic::mips_srai_d:
2090  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2091  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2092  case Intrinsic::mips_srari_b:
2093  case Intrinsic::mips_srari_h:
2094  case Intrinsic::mips_srari_w:
2095  case Intrinsic::mips_srari_d: {
2096  // Report an error for out of range values.
2097  int64_t Max;
2098  switch (Intrinsic) {
2099  case Intrinsic::mips_srari_b: Max = 7; break;
2100  case Intrinsic::mips_srari_h: Max = 15; break;
2101  case Intrinsic::mips_srari_w: Max = 31; break;
2102  case Intrinsic::mips_srari_d: Max = 63; break;
2103  default: llvm_unreachable("Unmatched intrinsic");
2104  }
2105  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2106  if (Value < 0 || Value > Max)
2107  report_fatal_error("Immediate out of range");
2108  return SDValue();
2109  }
2110  case Intrinsic::mips_srl_b:
2111  case Intrinsic::mips_srl_h:
2112  case Intrinsic::mips_srl_w:
2113  case Intrinsic::mips_srl_d:
2114  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2115  truncateVecElts(Op, DAG));
2116  case Intrinsic::mips_srli_b:
2117  case Intrinsic::mips_srli_h:
2118  case Intrinsic::mips_srli_w:
2119  case Intrinsic::mips_srli_d:
2120  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2121  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2122  case Intrinsic::mips_srlri_b:
2123  case Intrinsic::mips_srlri_h:
2124  case Intrinsic::mips_srlri_w:
2125  case Intrinsic::mips_srlri_d: {
2126  // Report an error for out of range values.
2127  int64_t Max;
2128  switch (Intrinsic) {
2129  case Intrinsic::mips_srlri_b: Max = 7; break;
2130  case Intrinsic::mips_srlri_h: Max = 15; break;
2131  case Intrinsic::mips_srlri_w: Max = 31; break;
2132  case Intrinsic::mips_srlri_d: Max = 63; break;
2133  default: llvm_unreachable("Unmatched intrinsic");
2134  }
2135  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2136  if (Value < 0 || Value > Max)
2137  report_fatal_error("Immediate out of range");
2138  return SDValue();
2139  }
2140  case Intrinsic::mips_subv_b:
2141  case Intrinsic::mips_subv_h:
2142  case Intrinsic::mips_subv_w:
2143  case Intrinsic::mips_subv_d:
2144  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2145  Op->getOperand(2));
2146  case Intrinsic::mips_subvi_b:
2147  case Intrinsic::mips_subvi_h:
2148  case Intrinsic::mips_subvi_w:
2149  case Intrinsic::mips_subvi_d:
2150  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2151  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2152  case Intrinsic::mips_vshf_b:
2153  case Intrinsic::mips_vshf_h:
2154  case Intrinsic::mips_vshf_w:
2155  case Intrinsic::mips_vshf_d:
2156  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2157  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2158  case Intrinsic::mips_xor_v:
2159  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2160  Op->getOperand(2));
2161  case Intrinsic::mips_xori_b:
2162  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2163  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2164  case Intrinsic::thread_pointer: {
2165  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2166  return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2167  }
2168  }
2169 }
2170 
2171 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2172  const MipsSubtarget &Subtarget) {
2173  SDLoc DL(Op);
2174  SDValue ChainIn = Op->getOperand(0);
2175  SDValue Address = Op->getOperand(2);
2176  SDValue Offset = Op->getOperand(3);
2177  EVT ResTy = Op->getValueType(0);
2178  EVT PtrTy = Address->getValueType(0);
2179 
2180  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2181  // however takes an i32 signed constant offset. The actual type of the
2182  // intrinsic is a scaled signed i10.
2183  if (Subtarget.isABI_N64())
2184  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2185 
2186  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2187  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2188  /* Alignment = */ 16);
2189 }
2190 
2191 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2192  SelectionDAG &DAG) const {
2193  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2194  switch (Intr) {
2195  default:
2196  return SDValue();
2197  case Intrinsic::mips_extp:
2198  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2199  case Intrinsic::mips_extpdp:
2200  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2201  case Intrinsic::mips_extr_w:
2202  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2203  case Intrinsic::mips_extr_r_w:
2204  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2205  case Intrinsic::mips_extr_rs_w:
2206  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2207  case Intrinsic::mips_extr_s_h:
2208  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2209  case Intrinsic::mips_mthlip:
2210  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2211  case Intrinsic::mips_mulsaq_s_w_ph:
2212  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2213  case Intrinsic::mips_maq_s_w_phl:
2214  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2215  case Intrinsic::mips_maq_s_w_phr:
2216  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2217  case Intrinsic::mips_maq_sa_w_phl:
2218  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2219  case Intrinsic::mips_maq_sa_w_phr:
2220  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2221  case Intrinsic::mips_dpaq_s_w_ph:
2222  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2223  case Intrinsic::mips_dpsq_s_w_ph:
2224  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2225  case Intrinsic::mips_dpaq_sa_l_w:
2226  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2227  case Intrinsic::mips_dpsq_sa_l_w:
2228  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2229  case Intrinsic::mips_dpaqx_s_w_ph:
2230  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2231  case Intrinsic::mips_dpaqx_sa_w_ph:
2232  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2233  case Intrinsic::mips_dpsqx_s_w_ph:
2234  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2235  case Intrinsic::mips_dpsqx_sa_w_ph:
2236  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2237  case Intrinsic::mips_ld_b:
2238  case Intrinsic::mips_ld_h:
2239  case Intrinsic::mips_ld_w:
2240  case Intrinsic::mips_ld_d:
2241  return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2242  }
2243 }
2244 
2245 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2246  const MipsSubtarget &Subtarget) {
2247  SDLoc DL(Op);
2248  SDValue ChainIn = Op->getOperand(0);
2249  SDValue Value = Op->getOperand(2);
2250  SDValue Address = Op->getOperand(3);
2251  SDValue Offset = Op->getOperand(4);
2252  EVT PtrTy = Address->getValueType(0);
2253 
2254  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2255  // however takes an i32 signed constant offset. The actual type of the
2256  // intrinsic is a scaled signed i10.
2257  if (Subtarget.isABI_N64())
2258  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2259 
2260  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2261 
2262  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2263  /* Alignment = */ 16);
2264 }
2265 
2266 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2267  SelectionDAG &DAG) const {
2268  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2269  switch (Intr) {
2270  default:
2271  return SDValue();
2272  case Intrinsic::mips_st_b:
2273  case Intrinsic::mips_st_h:
2274  case Intrinsic::mips_st_w:
2275  case Intrinsic::mips_st_d:
2276  return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2277  }
2278 }
2279 
2280 /// \brief Check if the given BuildVectorSDNode is a splat.
2281 /// This method currently relies on DAG nodes being reused when equivalent,
2282 /// so it's possible for this to return false even when isConstantSplat returns
2283 /// true.
2284 static bool isSplatVector(const BuildVectorSDNode *N) {
2285  unsigned int nOps = N->getNumOperands();
2286  assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2287 
2288  SDValue Operand0 = N->getOperand(0);
2289 
2290  for (unsigned int i = 1; i < nOps; ++i) {
2291  if (N->getOperand(i) != Operand0)
2292  return false;
2293  }
2294 
2295  return true;
2296 }
2297 
2298 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2299 //
2300 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2301 // choose to sign-extend but we could have equally chosen zero-extend. The
2302 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2303 // result into this node later (possibly changing it to a zero-extend in the
2304 // process).
2305 SDValue MipsSETargetLowering::
2306 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2307  SDLoc DL(Op);
2308  EVT ResTy = Op->getValueType(0);
2309  SDValue Op0 = Op->getOperand(0);
2310  EVT VecTy = Op0->getValueType(0);
2311 
2312  if (!VecTy.is128BitVector())
2313  return SDValue();
2314 
2315  if (ResTy.isInteger()) {
2316  SDValue Op1 = Op->getOperand(1);
2317  EVT EltTy = VecTy.getVectorElementType();
2318  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2319  DAG.getValueType(EltTy));
2320  }
2321 
2322  return Op;
2323 }
2324 
2325 static bool isConstantOrUndef(const SDValue Op) {
2326  if (Op->isUndef())
2327  return true;
2328  if (isa<ConstantSDNode>(Op))
2329  return true;
2330  if (isa<ConstantFPSDNode>(Op))
2331  return true;
2332  return false;
2333 }
2334 
2336  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2337  if (isConstantOrUndef(Op->getOperand(i)))
2338  return true;
2339  return false;
2340 }
2341 
2342 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2343 // backend.
2344 //
2345 // Lowers according to the following rules:
2346 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2347 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2348 // immediate
2349 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2350 // is a power of 2 less than or equal to 64 and the value does not fit into a
2351 // signed 10-bit immediate
2352 // - Non-constant splats are legal as-is.
2353 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2354 // - All others are illegal and must be expanded.
2355 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2356  SelectionDAG &DAG) const {
2357  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2358  EVT ResTy = Op->getValueType(0);
2359  SDLoc DL(Op);
2360  APInt SplatValue, SplatUndef;
2361  unsigned SplatBitSize;
2362  bool HasAnyUndefs;
2363 
2364  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2365  return SDValue();
2366 
2367  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2368  HasAnyUndefs, 8,
2369  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2370  // We can only cope with 8, 16, 32, or 64-bit elements
2371  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2372  SplatBitSize != 64)
2373  return SDValue();
2374 
2375  // If the value isn't an integer type we will have to bitcast
2376  // from an integer type first. Also, if there are any undefs, we must
2377  // lower them to defined values first.
2378  if (ResTy.isInteger() && !HasAnyUndefs)
2379  return Op;
2380 
2381  EVT ViaVecTy;
2382 
2383  switch (SplatBitSize) {
2384  default:
2385  return SDValue();
2386  case 8:
2387  ViaVecTy = MVT::v16i8;
2388  break;
2389  case 16:
2390  ViaVecTy = MVT::v8i16;
2391  break;
2392  case 32:
2393  ViaVecTy = MVT::v4i32;
2394  break;
2395  case 64:
2396  // There's no fill.d to fall back on for 64-bit values
2397  return SDValue();
2398  }
2399 
2400  // SelectionDAG::getConstant will promote SplatValue appropriately.
2401  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2402 
2403  // Bitcast to the type we originally wanted
2404  if (ViaVecTy != ResTy)
2405  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2406 
2407  return Result;
2408  } else if (isSplatVector(Node))
2409  return Op;
2410  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2411  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2412  // The resulting code is the same length as the expansion, but it doesn't
2413  // use memory operations
2414  EVT ResTy = Node->getValueType(0);
2415 
2416  assert(ResTy.isVector());
2417 
2418  unsigned NumElts = ResTy.getVectorNumElements();
2419  SDValue Vector = DAG.getUNDEF(ResTy);
2420  for (unsigned i = 0; i < NumElts; ++i) {
2421  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2422  Node->getOperand(i),
2423  DAG.getConstant(i, DL, MVT::i32));
2424  }
2425  return Vector;
2426  }
2427 
2428  return SDValue();
2429 }
2430 
2431 // Lower VECTOR_SHUFFLE into SHF (if possible).
2432 //
2433 // SHF splits the vector into blocks of four elements, then shuffles these
2434 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2435 //
2436 // It is therefore possible to lower into SHF when the mask takes the form:
2437 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2438 // When undef's appear they are treated as if they were whatever value is
2439 // necessary in order to fit the above forms.
2440 //
2441 // For example:
2442 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2443 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2444 // i32 7, i32 6, i32 5, i32 4>
2445 // is lowered to:
2446 // (SHF_H $w0, $w1, 27)
2447 // where the 27 comes from:
2448 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2450  SmallVector<int, 16> Indices,
2451  SelectionDAG &DAG) {
2452  int SHFIndices[4] = { -1, -1, -1, -1 };
2453 
2454  if (Indices.size() < 4)
2455  return SDValue();
2456 
2457  for (unsigned i = 0; i < 4; ++i) {
2458  for (unsigned j = i; j < Indices.size(); j += 4) {
2459  int Idx = Indices[j];
2460 
2461  // Convert from vector index to 4-element subvector index
2462  // If an index refers to an element outside of the subvector then give up
2463  if (Idx != -1) {
2464  Idx -= 4 * (j / 4);
2465  if (Idx < 0 || Idx >= 4)
2466  return SDValue();
2467  }
2468 
2469  // If the mask has an undef, replace it with the current index.
2470  // Note that it might still be undef if the current index is also undef
2471  if (SHFIndices[i] == -1)
2472  SHFIndices[i] = Idx;
2473 
2474  // Check that non-undef values are the same as in the mask. If they
2475  // aren't then give up
2476  if (!(Idx == -1 || Idx == SHFIndices[i]))
2477  return SDValue();
2478  }
2479  }
2480 
2481  // Calculate the immediate. Replace any remaining undefs with zero
2482  APInt Imm(32, 0);
2483  for (int i = 3; i >= 0; --i) {
2484  int Idx = SHFIndices[i];
2485 
2486  if (Idx == -1)
2487  Idx = 0;
2488 
2489  Imm <<= 2;
2490  Imm |= Idx & 0x3;
2491  }
2492 
2493  SDLoc DL(Op);
2494  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2495  DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2496 }
2497 
2498 /// Determine whether a range fits a regular pattern of values.
2499 /// This function accounts for the possibility of jumping over the End iterator.
2500 template <typename ValType>
2501 static bool
2503  unsigned CheckStride,
2505  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2506  auto &I = Begin;
2507 
2508  while (I != End) {
2509  if (*I != -1 && *I != ExpectedIndex)
2510  return false;
2511  ExpectedIndex += ExpectedIndexStride;
2512 
2513  // Incrementing past End is undefined behaviour so we must increment one
2514  // step at a time and check for End at each step.
2515  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2516  ; // Empty loop body.
2517  }
2518  return true;
2519 }
2520 
2521 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2522 //
2523 // It is a SPLATI when the mask is:
2524 // <x, x, x, ...>
2525 // where x is any valid index.
2526 //
2527 // When undef's appear in the mask they are treated as if they were whatever
2528 // value is necessary in order to fit the above form.
2529 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2530  SmallVector<int, 16> Indices,
2531  SelectionDAG &DAG) {
2532  assert((Indices.size() % 2) == 0);
2533 
2534  int SplatIndex = -1;
2535  for (const auto &V : Indices) {
2536  if (V != -1) {
2537  SplatIndex = V;
2538  break;
2539  }
2540  }
2541 
2542  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2543  0);
2544 }
2545 
2546 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2547 //
2548 // ILVEV interleaves the even elements from each vector.
2549 //
2550 // It is possible to lower into ILVEV when the mask consists of two of the
2551 // following forms interleaved:
2552 // <0, 2, 4, ...>
2553 // <n, n+2, n+4, ...>
2554 // where n is the number of elements in the vector.
2555 // For example:
2556 // <0, 0, 2, 2, 4, 4, ...>
2557 // <0, n, 2, n+2, 4, n+4, ...>
2558 //
2559 // When undef's appear in the mask they are treated as if they were whatever
2560 // value is necessary in order to fit the above forms.
2562  SmallVector<int, 16> Indices,
2563  SelectionDAG &DAG) {
2564  assert((Indices.size() % 2) == 0);
2565 
2566  SDValue Wt;
2567  SDValue Ws;
2568  const auto &Begin = Indices.begin();
2569  const auto &End = Indices.end();
2570 
2571  // Check even elements are taken from the even elements of one half or the
2572  // other and pick an operand accordingly.
2573  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2574  Wt = Op->getOperand(0);
2575  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2576  Wt = Op->getOperand(1);
2577  else
2578  return SDValue();
2579 
2580  // Check odd elements are taken from the even elements of one half or the
2581  // other and pick an operand accordingly.
2582  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2583  Ws = Op->getOperand(0);
2584  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2585  Ws = Op->getOperand(1);
2586  else
2587  return SDValue();
2588 
2589  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2590 }
2591 
2592 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2593 //
2594 // ILVOD interleaves the odd elements from each vector.
2595 //
2596 // It is possible to lower into ILVOD when the mask consists of two of the
2597 // following forms interleaved:
2598 // <1, 3, 5, ...>
2599 // <n+1, n+3, n+5, ...>
2600 // where n is the number of elements in the vector.
2601 // For example:
2602 // <1, 1, 3, 3, 5, 5, ...>
2603 // <1, n+1, 3, n+3, 5, n+5, ...>
2604 //
2605 // When undef's appear in the mask they are treated as if they were whatever
2606 // value is necessary in order to fit the above forms.
2608  SmallVector<int, 16> Indices,
2609  SelectionDAG &DAG) {
2610  assert((Indices.size() % 2) == 0);
2611 
2612  SDValue Wt;
2613  SDValue Ws;
2614  const auto &Begin = Indices.begin();
2615  const auto &End = Indices.end();
2616 
2617  // Check even elements are taken from the odd elements of one half or the
2618  // other and pick an operand accordingly.
2619  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2620  Wt = Op->getOperand(0);
2621  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2622  Wt = Op->getOperand(1);
2623  else
2624  return SDValue();
2625 
2626  // Check odd elements are taken from the odd elements of one half or the
2627  // other and pick an operand accordingly.
2628  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2629  Ws = Op->getOperand(0);
2630  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2631  Ws = Op->getOperand(1);
2632  else
2633  return SDValue();
2634 
2635  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2636 }
2637 
2638 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2639 //
2640 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2641 // each vector.
2642 //
2643 // It is possible to lower into ILVR when the mask consists of two of the
2644 // following forms interleaved:
2645 // <0, 1, 2, ...>
2646 // <n, n+1, n+2, ...>
2647 // where n is the number of elements in the vector.
2648 // For example:
2649 // <0, 0, 1, 1, 2, 2, ...>
2650 // <0, n, 1, n+1, 2, n+2, ...>
2651 //
2652 // When undef's appear in the mask they are treated as if they were whatever
2653 // value is necessary in order to fit the above forms.
2655  SmallVector<int, 16> Indices,
2656  SelectionDAG &DAG) {
2657  assert((Indices.size() % 2) == 0);
2658 
2659  SDValue Wt;
2660  SDValue Ws;
2661  const auto &Begin = Indices.begin();
2662  const auto &End = Indices.end();
2663 
2664  // Check even elements are taken from the right (lowest-indexed) elements of
2665  // one half or the other and pick an operand accordingly.
2666  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2667  Wt = Op->getOperand(0);
2668  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2669  Wt = Op->getOperand(1);
2670  else
2671  return SDValue();
2672 
2673  // Check odd elements are taken from the right (lowest-indexed) elements of
2674  // one half or the other and pick an operand accordingly.
2675  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2676  Ws = Op->getOperand(0);
2677  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2678  Ws = Op->getOperand(1);
2679  else
2680  return SDValue();
2681 
2682  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2683 }
2684 
2685 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2686 //
2687 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2688 // of each vector.
2689 //
2690 // It is possible to lower into ILVL when the mask consists of two of the
2691 // following forms interleaved:
2692 // <x, x+1, x+2, ...>
2693 // <n+x, n+x+1, n+x+2, ...>
2694 // where n is the number of elements in the vector and x is half n.
2695 // For example:
2696 // <x, x, x+1, x+1, x+2, x+2, ...>
2697 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2698 //
2699 // When undef's appear in the mask they are treated as if they were whatever
2700 // value is necessary in order to fit the above forms.
2702  SmallVector<int, 16> Indices,
2703  SelectionDAG &DAG) {
2704  assert((Indices.size() % 2) == 0);
2705 
2706  unsigned HalfSize = Indices.size() / 2;
2707  SDValue Wt;
2708  SDValue Ws;
2709  const auto &Begin = Indices.begin();
2710  const auto &End = Indices.end();
2711 
2712  // Check even elements are taken from the left (highest-indexed) elements of
2713  // one half or the other and pick an operand accordingly.
2714  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2715  Wt = Op->getOperand(0);
2716  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2717  Wt = Op->getOperand(1);
2718  else
2719  return SDValue();
2720 
2721  // Check odd elements are taken from the left (highest-indexed) elements of
2722  // one half or the other and pick an operand accordingly.
2723  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2724  Ws = Op->getOperand(0);
2725  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2726  1))
2727  Ws = Op->getOperand(1);
2728  else
2729  return SDValue();
2730 
2731  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2732 }
2733 
2734 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2735 //
2736 // PCKEV copies the even elements of each vector into the result vector.
2737 //
2738 // It is possible to lower into PCKEV when the mask consists of two of the
2739 // following forms concatenated:
2740 // <0, 2, 4, ...>
2741 // <n, n+2, n+4, ...>
2742 // where n is the number of elements in the vector.
2743 // For example:
2744 // <0, 2, 4, ..., 0, 2, 4, ...>
2745 // <0, 2, 4, ..., n, n+2, n+4, ...>
2746 //
2747 // When undef's appear in the mask they are treated as if they were whatever
2748 // value is necessary in order to fit the above forms.
2750  SmallVector<int, 16> Indices,
2751  SelectionDAG &DAG) {
2752  assert((Indices.size() % 2) == 0);
2753 
2754  SDValue Wt;
2755  SDValue Ws;
2756  const auto &Begin = Indices.begin();
2757  const auto &Mid = Indices.begin() + Indices.size() / 2;
2758  const auto &End = Indices.end();
2759 
2760  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2761  Wt = Op->getOperand(0);
2762  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2763  Wt = Op->getOperand(1);
2764  else
2765  return SDValue();
2766 
2767  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2768  Ws = Op->getOperand(0);
2769  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2770  Ws = Op->getOperand(1);
2771  else
2772  return SDValue();
2773 
2774  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2775 }
2776 
2777 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2778 //
2779 // PCKOD copies the odd elements of each vector into the result vector.
2780 //
2781 // It is possible to lower into PCKOD when the mask consists of two of the
2782 // following forms concatenated:
2783 // <1, 3, 5, ...>
2784 // <n+1, n+3, n+5, ...>
2785 // where n is the number of elements in the vector.
2786 // For example:
2787 // <1, 3, 5, ..., 1, 3, 5, ...>
2788 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2789 //
2790 // When undef's appear in the mask they are treated as if they were whatever
2791 // value is necessary in order to fit the above forms.
2793  SmallVector<int, 16> Indices,
2794  SelectionDAG &DAG) {
2795  assert((Indices.size() % 2) == 0);
2796 
2797  SDValue Wt;
2798  SDValue Ws;
2799  const auto &Begin = Indices.begin();
2800  const auto &Mid = Indices.begin() + Indices.size() / 2;
2801  const auto &End = Indices.end();
2802 
2803  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2804  Wt = Op->getOperand(0);
2805  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2806  Wt = Op->getOperand(1);
2807  else
2808  return SDValue();
2809 
2810  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2811  Ws = Op->getOperand(0);
2812  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2813  Ws = Op->getOperand(1);
2814  else
2815  return SDValue();
2816 
2817  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2818 }
2819 
2820 // Lower VECTOR_SHUFFLE into VSHF.
2821 //
2822 // This mostly consists of converting the shuffle indices in Indices into a
2823 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2824 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2825 // if the type is v8i16 and all the indices are less than 8 then the second
2826 // operand is unused and can be replaced with anything. We choose to replace it
2827 // with the used operand since this reduces the number of instructions overall.
2829  SmallVector<int, 16> Indices,
2830  SelectionDAG &DAG) {
2832  SDValue Op0;
2833  SDValue Op1;
2834  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2835  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2836  bool Using1stVec = false;
2837  bool Using2ndVec = false;
2838  SDLoc DL(Op);
2839  int ResTyNumElts = ResTy.getVectorNumElements();
2840 
2841  for (int i = 0; i < ResTyNumElts; ++i) {
2842  // Idx == -1 means UNDEF
2843  int Idx = Indices[i];
2844 
2845  if (0 <= Idx && Idx < ResTyNumElts)
2846  Using1stVec = true;
2847  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2848  Using2ndVec = true;
2849  }
2850 
2851  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2852  ++I)
2853  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2854 
2855  SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2856 
2857  if (Using1stVec && Using2ndVec) {
2858  Op0 = Op->getOperand(0);
2859  Op1 = Op->getOperand(1);
2860  } else if (Using1stVec)
2861  Op0 = Op1 = Op->getOperand(0);
2862  else if (Using2ndVec)
2863  Op0 = Op1 = Op->getOperand(1);
2864  else
2865  llvm_unreachable("shuffle vector mask references neither vector operand?");
2866 
2867  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2868  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2869  // VSHF concatenates the vectors in a bitwise fashion:
2870  // <0b00, 0b01> + <0b10, 0b11> ->
2871  // 0b0100 + 0b1110 -> 0b01001110
2872  // <0b10, 0b11, 0b00, 0b01>
2873  // We must therefore swap the operands to get the correct result.
2874  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2875 }
2876 
2877 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2878 // indices in the shuffle.
2879 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2880  SelectionDAG &DAG) const {
2881  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2882  EVT ResTy = Op->getValueType(0);
2883 
2884  if (!ResTy.is128BitVector())
2885  return SDValue();
2886 
2887  int ResTyNumElts = ResTy.getVectorNumElements();
2888  SmallVector<int, 16> Indices;
2889 
2890  for (int i = 0; i < ResTyNumElts; ++i)
2891  Indices.push_back(Node->getMaskElt(i));
2892 
2893  // splati.[bhwd] is preferable to the others but is matched from
2894  // MipsISD::VSHF.
2895  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2896  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2897  SDValue Result;
2898  if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
2899  return Result;
2900  if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
2901  return Result;
2902  if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
2903  return Result;
2904  if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
2905  return Result;
2906  if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
2907  return Result;
2908  if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
2909  return Result;
2910  if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
2911  return Result;
2912  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2913 }
2914 
2916 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
2917  MachineBasicBlock *BB) const {
2918  // $bb:
2919  // bposge32_pseudo $vr0
2920  // =>
2921  // $bb:
2922  // bposge32 $tbb
2923  // $fbb:
2924  // li $vr2, 0
2925  // b $sink
2926  // $tbb:
2927  // li $vr1, 1
2928  // $sink:
2929  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2930 
2931  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2933  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2934  DebugLoc DL = MI.getDebugLoc();
2935  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2937  MachineFunction *F = BB->getParent();
2938  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2939  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2941  F->insert(It, FBB);
2942  F->insert(It, TBB);
2943  F->insert(It, Sink);
2944 
2945  // Transfer the remainder of BB and its successor edges to Sink.
2946  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2947  BB->end());
2949 
2950  // Add successors.
2951  BB->addSuccessor(FBB);
2952  BB->addSuccessor(TBB);
2953  FBB->addSuccessor(Sink);
2954  TBB->addSuccessor(Sink);
2955 
2956  // Insert the real bposge32 instruction to $BB.
2957  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2958  // Insert the real bposge32c instruction to $BB.
2959  BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
2960 
2961  // Fill $FBB.
2962  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2963  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2964  .addReg(Mips::ZERO).addImm(0);
2965  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2966 
2967  // Fill $TBB.
2968  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2969  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2970  .addReg(Mips::ZERO).addImm(1);
2971 
2972  // Insert phi function to $Sink.
2973  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2974  MI.getOperand(0).getReg())
2975  .addReg(VR2)
2976  .addMBB(FBB)
2977  .addReg(VR1)
2978  .addMBB(TBB);
2979 
2980  MI.eraseFromParent(); // The pseudo instruction is gone now.
2981  return Sink;
2982 }
2983 
2984 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
2985  MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
2986  // $bb:
2987  // vany_nonzero $rd, $ws
2988  // =>
2989  // $bb:
2990  // bnz.b $ws, $tbb
2991  // b $fbb
2992  // $fbb:
2993  // li $rd1, 0
2994  // b $sink
2995  // $tbb:
2996  // li $rd2, 1
2997  // $sink:
2998  // $rd = phi($rd1, $fbb, $rd2, $tbb)
2999 
3000  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3002  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3003  DebugLoc DL = MI.getDebugLoc();
3004  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3006  MachineFunction *F = BB->getParent();
3007  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3008  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3010  F->insert(It, FBB);
3011  F->insert(It, TBB);
3012  F->insert(It, Sink);
3013 
3014  // Transfer the remainder of BB and its successor edges to Sink.
3015  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3016  BB->end());
3018 
3019  // Add successors.
3020  BB->addSuccessor(FBB);
3021  BB->addSuccessor(TBB);
3022  FBB->addSuccessor(Sink);
3023  TBB->addSuccessor(Sink);
3024 
3025  // Insert the real bnz.b instruction to $BB.
3026  BuildMI(BB, DL, TII->get(BranchOp))
3027  .addReg(MI.getOperand(1).getReg())
3028  .addMBB(TBB);
3029 
3030  // Fill $FBB.
3031  unsigned RD1 = RegInfo.createVirtualRegister(RC);
3032  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3033  .addReg(Mips::ZERO).addImm(0);
3034  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3035 
3036  // Fill $TBB.
3037  unsigned RD2 = RegInfo.createVirtualRegister(RC);
3038  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3039  .addReg(Mips::ZERO).addImm(1);
3040 
3041  // Insert phi function to $Sink.
3042  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3043  MI.getOperand(0).getReg())
3044  .addReg(RD1)
3045  .addMBB(FBB)
3046  .addReg(RD2)
3047  .addMBB(TBB);
3048 
3049  MI.eraseFromParent(); // The pseudo instruction is gone now.
3050  return Sink;
3051 }
3052 
3053 // Emit the COPY_FW pseudo instruction.
3054 //
3055 // copy_fw_pseudo $fd, $ws, n
3056 // =>
3057 // copy_u_w $rt, $ws, $n
3058 // mtc1 $rt, $fd
3059 //
3060 // When n is zero, the equivalent operation can be performed with (potentially)
3061 // zero instructions due to register overlaps. This optimization is never valid
3062 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3064 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3065  MachineBasicBlock *BB) const {
3067  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3068  DebugLoc DL = MI.getDebugLoc();
3069  unsigned Fd = MI.getOperand(0).getReg();
3070  unsigned Ws = MI.getOperand(1).getReg();
3071  unsigned Lane = MI.getOperand(2).getImm();
3072 
3073  if (Lane == 0) {
3074  unsigned Wt = Ws;
3075  if (!Subtarget.useOddSPReg()) {
3076  // We must copy to an even-numbered MSA register so that the
3077  // single-precision sub-register is also guaranteed to be even-numbered.
3078  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3079 
3080  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3081  }
3082 
3083  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3084  } else {
3085  unsigned Wt = RegInfo.createVirtualRegister(
3086  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3087  &Mips::MSA128WEvensRegClass);
3088 
3089  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3090  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3091  }
3092 
3093  MI.eraseFromParent(); // The pseudo instruction is gone now.
3094  return BB;
3095 }
3096 
3097 // Emit the COPY_FD pseudo instruction.
3098 //
3099 // copy_fd_pseudo $fd, $ws, n
3100 // =>
3101 // splati.d $wt, $ws, $n
3102 // copy $fd, $wt:sub_64
3103 //
3104 // When n is zero, the equivalent operation can be performed with (potentially)
3105 // zero instructions due to register overlaps. This optimization is always
3106 // valid because FR=1 mode which is the only supported mode in MSA.
3108 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3109  MachineBasicBlock *BB) const {
3111 
3113  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3114  unsigned Fd = MI.getOperand(0).getReg();
3115  unsigned Ws = MI.getOperand(1).getReg();
3116  unsigned Lane = MI.getOperand(2).getImm() * 2;
3117  DebugLoc DL = MI.getDebugLoc();
3118 
3119  if (Lane == 0)
3120  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3121  else {
3122  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3123 
3124  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3125  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3126  }
3127 
3128  MI.eraseFromParent(); // The pseudo instruction is gone now.
3129  return BB;
3130 }
3131 
3132 // Emit the INSERT_FW pseudo instruction.
3133 //
3134 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3135 // =>
3136 // subreg_to_reg $wt:sub_lo, $fs
3137 // insve_w $wd[$n], $wd_in, $wt[0]
3139 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3140  MachineBasicBlock *BB) const {
3142  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3143  DebugLoc DL = MI.getDebugLoc();
3144  unsigned Wd = MI.getOperand(0).getReg();
3145  unsigned Wd_in = MI.getOperand(1).getReg();
3146  unsigned Lane = MI.getOperand(2).getImm();
3147  unsigned Fs = MI.getOperand(3).getReg();
3148  unsigned Wt = RegInfo.createVirtualRegister(
3149  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3150  &Mips::MSA128WEvensRegClass);
3151 
3152  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3153  .addImm(0)
3154  .addReg(Fs)
3155  .addImm(Mips::sub_lo);
3156  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3157  .addReg(Wd_in)
3158  .addImm(Lane)
3159  .addReg(Wt)
3160  .addImm(0);
3161 
3162  MI.eraseFromParent(); // The pseudo instruction is gone now.
3163  return BB;
3164 }
3165 
3166 // Emit the INSERT_FD pseudo instruction.
3167 //
3168 // insert_fd_pseudo $wd, $fs, n
3169 // =>
3170 // subreg_to_reg $wt:sub_64, $fs
3171 // insve_d $wd[$n], $wd_in, $wt[0]
3173 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3174  MachineBasicBlock *BB) const {
3176 
3178  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3179  DebugLoc DL = MI.getDebugLoc();
3180  unsigned Wd = MI.getOperand(0).getReg();
3181  unsigned Wd_in = MI.getOperand(1).getReg();
3182  unsigned Lane = MI.getOperand(2).getImm();
3183  unsigned Fs = MI.getOperand(3).getReg();
3184  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3185 
3186  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3187  .addImm(0)
3188  .addReg(Fs)
3189  .addImm(Mips::sub_64);
3190  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3191  .addReg(Wd_in)
3192  .addImm(Lane)
3193  .addReg(Wt)
3194  .addImm(0);
3195 
3196  MI.eraseFromParent(); // The pseudo instruction is gone now.
3197  return BB;
3198 }
3199 
3200 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3201 //
3202 // For integer:
3203 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3204 // =>
3205 // (SLL $lanetmp1, $lane, <log2size)
3206 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3207 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3208 // (NEG $lanetmp2, $lanetmp1)
3209 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3210 //
3211 // For floating point:
3212 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3213 // =>
3214 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3215 // (SLL $lanetmp1, $lane, <log2size)
3216 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3217 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3218 // (NEG $lanetmp2, $lanetmp1)
3219 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3220 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3221  MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3222  bool IsFP) const {
3224  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3225  DebugLoc DL = MI.getDebugLoc();
3226  unsigned Wd = MI.getOperand(0).getReg();
3227  unsigned SrcVecReg = MI.getOperand(1).getReg();
3228  unsigned LaneReg = MI.getOperand(2).getReg();
3229  unsigned SrcValReg = MI.getOperand(3).getReg();
3230 
3231  const TargetRegisterClass *VecRC = nullptr;
3232  // FIXME: This should be true for N32 too.
3233  const TargetRegisterClass *GPRRC =
3234  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3235  unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3236  unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3237  unsigned EltLog2Size;
3238  unsigned InsertOp = 0;
3239  unsigned InsveOp = 0;
3240  switch (EltSizeInBytes) {
3241  default:
3242  llvm_unreachable("Unexpected size");
3243  case 1:
3244  EltLog2Size = 0;
3245  InsertOp = Mips::INSERT_B;
3246  InsveOp = Mips::INSVE_B;
3247  VecRC = &Mips::MSA128BRegClass;
3248  break;
3249  case 2:
3250  EltLog2Size = 1;
3251  InsertOp = Mips::INSERT_H;
3252  InsveOp = Mips::INSVE_H;
3253  VecRC = &Mips::MSA128HRegClass;
3254  break;
3255  case 4:
3256  EltLog2Size = 2;
3257  InsertOp = Mips::INSERT_W;
3258  InsveOp = Mips::INSVE_W;
3259  VecRC = &Mips::MSA128WRegClass;
3260  break;
3261  case 8:
3262  EltLog2Size = 3;
3263  InsertOp = Mips::INSERT_D;
3264  InsveOp = Mips::INSVE_D;
3265  VecRC = &Mips::MSA128DRegClass;
3266  break;
3267  }
3268 
3269  if (IsFP) {
3270  unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3271  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3272  .addImm(0)
3273  .addReg(SrcValReg)
3274  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3275  SrcValReg = Wt;
3276  }
3277 
3278  // Convert the lane index into a byte index
3279  if (EltSizeInBytes != 1) {
3280  unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3281  BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3282  .addReg(LaneReg)
3283  .addImm(EltLog2Size);
3284  LaneReg = LaneTmp1;
3285  }
3286 
3287  // Rotate bytes around so that the desired lane is element zero
3288  unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3289  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3290  .addReg(SrcVecReg)
3291  .addReg(SrcVecReg)
3292  .addReg(LaneReg, 0, SubRegIdx);
3293 
3294  unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3295  if (IsFP) {
3296  // Use insve.df to insert to element zero
3297  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3298  .addReg(WdTmp1)
3299  .addImm(0)
3300  .addReg(SrcValReg)
3301  .addImm(0);
3302  } else {
3303  // Use insert.df to insert to element zero
3304  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3305  .addReg(WdTmp1)
3306  .addReg(SrcValReg)
3307  .addImm(0);
3308  }
3309 
3310  // Rotate elements the rest of the way for a full rotation.
3311  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3312  // the lane index to do this.
3313  unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3314  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3315  LaneTmp2)
3316  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3317  .addReg(LaneReg);
3318  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3319  .addReg(WdTmp2)
3320  .addReg(WdTmp2)
3321  .addReg(LaneTmp2, 0, SubRegIdx);
3322 
3323  MI.eraseFromParent(); // The pseudo instruction is gone now.
3324  return BB;
3325 }
3326 
3327 // Emit the FILL_FW pseudo instruction.
3328 //
3329 // fill_fw_pseudo $wd, $fs
3330 // =>
3331 // implicit_def $wt1
3332 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3333 // splati.w $wd, $wt2[0]
3335 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3336  MachineBasicBlock *BB) const {
3338  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3339  DebugLoc DL = MI.getDebugLoc();
3340  unsigned Wd = MI.getOperand(0).getReg();
3341  unsigned Fs = MI.getOperand(1).getReg();
3342  unsigned Wt1 = RegInfo.createVirtualRegister(
3343  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3344  : &Mips::MSA128WEvensRegClass);
3345  unsigned Wt2 = RegInfo.createVirtualRegister(
3346  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3347  : &Mips::MSA128WEvensRegClass);
3348 
3349  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3350  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3351  .addReg(Wt1)
3352  .addReg(Fs)
3353  .addImm(Mips::sub_lo);
3354  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3355 
3356  MI.eraseFromParent(); // The pseudo instruction is gone now.
3357  return BB;
3358 }
3359 
3360 // Emit the FILL_FD pseudo instruction.
3361 //
3362 // fill_fd_pseudo $wd, $fs
3363 // =>
3364 // implicit_def $wt1
3365 // insert_subreg $wt2:subreg_64, $wt1, $fs
3366 // splati.d $wd, $wt2[0]
3368 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3369  MachineBasicBlock *BB) const {
3371 
3373  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3374  DebugLoc DL = MI.getDebugLoc();
3375  unsigned Wd = MI.getOperand(0).getReg();
3376  unsigned Fs = MI.getOperand(1).getReg();
3377  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3378  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3379 
3380  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3381  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3382  .addReg(Wt1)
3383  .addReg(Fs)
3384  .addImm(Mips::sub_64);
3385  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3386 
3387  MI.eraseFromParent(); // The pseudo instruction is gone now.
3388  return BB;
3389 }
3390 
3391 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3392 // register.
3393 //
3394 // STF16 MSA128F16:$wd, mem_simm10:$addr
3395 // =>
3396 // copy_u.h $rtemp,$wd[0]
3397 // sh $rtemp, $addr
3398 //
3399 // Safety: We can't use st.h & co as they would over write the memory after
3400 // the destination. It would require half floats be allocated 16 bytes(!) of
3401 // space.
3403 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3404  MachineBasicBlock *BB) const {
3405 
3407  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3408  DebugLoc DL = MI.getDebugLoc();
3409  unsigned Ws = MI.getOperand(0).getReg();
3410  unsigned Rt = MI.getOperand(1).getReg();
3411  const MachineMemOperand &MMO = **MI.memoperands_begin();
3412  unsigned Imm = MMO.getOffset();
3413 
3414  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3415  // spill and reload can expand as a GPR64 operand. Examine the
3416  // operand in detail and default to ABI.
3417  const TargetRegisterClass *RC =
3418  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3419  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3420  : &Mips::GPR64RegClass);
3421  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3422  unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3423 
3424  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3425  if(!UsingMips32) {
3426  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3427  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3428  .addImm(0)
3429  .addReg(Rs)
3430  .addImm(Mips::sub_32);
3431  Rs = Tmp;
3432  }
3433  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3434  .addReg(Rs)
3435  .addReg(Rt)
3436  .addImm(Imm)
3438  &MMO, MMO.getOffset(), MMO.getSize()));
3439 
3440  MI.eraseFromParent();
3441  return BB;
3442 }
3443 
3444 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3445 //
3446 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3447 // =>
3448 // lh $rtemp, $addr
3449 // fill.h $wd, $rtemp
3450 //
3451 // Safety: We can't use ld.h & co as they over-read from the source.
3452 // Additionally, if the address is not modulo 16, 2 cases can occur:
3453 // a) Segmentation fault as the load instruction reads from a memory page
3454 // memory it's not supposed to.
3455 // b) The load crosses an implementation specific boundary, requiring OS
3456 // intervention.
3458 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3459  MachineBasicBlock *BB) const {
3460 
3462  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3463  DebugLoc DL = MI.getDebugLoc();
3464  unsigned Wd = MI.getOperand(0).getReg();
3465 
3466  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3467  // spill and reload can expand as a GPR64 operand. Examine the
3468  // operand in detail and default to ABI.
3469  const TargetRegisterClass *RC =
3470  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3471  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3472  : &Mips::GPR64RegClass);
3473 
3474  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3475  unsigned Rt = RegInfo.createVirtualRegister(RC);
3476 
3477  MachineInstrBuilder MIB =
3478  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3479  for (unsigned i = 1; i < MI.getNumOperands(); i++)
3480  MIB.add(MI.getOperand(i));
3481 
3482  if(!UsingMips32) {
3483  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3484  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3485  Rt = Tmp;
3486  }
3487 
3488  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3489 
3490  MI.eraseFromParent();
3491  return BB;
3492 }
3493 
3494 // Emit the FPROUND_PSEUDO instruction.
3495 //
3496 // Round an FGR64Opnd, FGR32Opnd to an f16.
3497 //
3498 // Safety: Cycle the operand through the GPRs so the result always ends up
3499 // the correct MSA register.
3500 //
3501 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3502 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3503 // (which they can be, as the MSA registers are defined to alias the
3504 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3505 // the correct register class. That requires operands be tie-able across
3506 // register classes which have a sub/super register class relationship.
3507 //
3508 // For FPG32Opnd:
3509 //
3510 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3511 // =>
3512 // mfc1 $rtemp, $fs
3513 // fill.w $rtemp, $wtemp
3514 // fexdo.w $wd, $wtemp, $wtemp
3515 //
3516 // For FPG64Opnd on mips32r2+:
3517 //
3518 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3519 // =>
3520 // mfc1 $rtemp, $fs
3521 // fill.w $rtemp, $wtemp
3522 // mfhc1 $rtemp2, $fs
3523 // insert.w $wtemp[1], $rtemp2
3524 // insert.w $wtemp[3], $rtemp2
3525 // fexdo.w $wtemp2, $wtemp, $wtemp
3526 // fexdo.h $wd, $temp2, $temp2
3527 //
3528 // For FGR64Opnd on mips64r2+:
3529 //
3530 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3531 // =>
3532 // dmfc1 $rtemp, $fs
3533 // fill.d $rtemp, $wtemp
3534 // fexdo.w $wtemp2, $wtemp, $wtemp
3535 // fexdo.h $wd, $wtemp2, $wtemp2
3536 //
3537 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3538 // undef bits are "just right" and the exception enable bits are
3539 // set. By using fill.w to replicate $fs into all elements over
3540 // insert.w for one element, we avoid that potiential case. If
3541 // fexdo.[hw] causes an exception in, the exception is valid and it
3542 // occurs for all elements.
3544 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3545  MachineBasicBlock *BB,
3546  bool IsFGR64) const {
3547 
3548  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3549  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3550  // it.
3552 
3553  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3554  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3555 
3557  DebugLoc DL = MI.getDebugLoc();
3558  unsigned Wd = MI.getOperand(0).getReg();
3559  unsigned Fs = MI.getOperand(1).getReg();
3560 
3561  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3562  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3563  const TargetRegisterClass *GPRRC =
3564  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3565  unsigned MFC1Opc = IsFGR64onMips64
3566  ? Mips::DMFC1
3567  : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3568  unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3569 
3570  // Perform the register class copy as mentioned above.
3571  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3572  BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3573  BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3574  unsigned WPHI = Wtemp;
3575 
3576  if (IsFGR64onMips32) {
3577  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3578  BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3579  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3580  unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3581  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3582  .addReg(Wtemp)
3583  .addReg(Rtemp2)
3584  .addImm(1);
3585  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3586  .addReg(Wtemp2)
3587  .addReg(Rtemp2)
3588  .addImm(3);
3589  WPHI = Wtemp3;
3590  }
3591 
3592  if (IsFGR64) {
3593  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3594  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3595  .addReg(WPHI)
3596  .addReg(WPHI);
3597  WPHI = Wtemp2;
3598  }
3599 
3600  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3601 
3602  MI.eraseFromParent();
3603  return BB;
3604 }
3605 
3606 // Emit the FPEXTEND_PSEUDO instruction.
3607 //
3608 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3609 //
3610 // Safety: Cycle the result through the GPRs so the result always ends up
3611 // the correct floating point register.
3612 //
3613 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3614 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3615 // (which they can be, as the MSA registers are defined to alias the
3616 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3617 // the correct register class. That requires operands be tie-able across
3618 // register classes which have a sub/super register class relationship. I
3619 // haven't checked.
3620 //
3621 // For FGR32Opnd:
3622 //
3623 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3624 // =>
3625 // fexupr.w $wtemp, $ws
3626 // copy_s.w $rtemp, $ws[0]
3627 // mtc1 $rtemp, $fd
3628 //
3629 // For FGR64Opnd on Mips64:
3630 //
3631 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3632 // =>
3633 // fexupr.w $wtemp, $ws
3634 // fexupr.d $wtemp2, $wtemp
3635 // copy_s.d $rtemp, $wtemp2s[0]
3636 // dmtc1 $rtemp, $fd
3637 //
3638 // For FGR64Opnd on Mips32:
3639 //
3640 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3641 // =>
3642 // fexupr.w $wtemp, $ws
3643 // fexupr.d $wtemp2, $wtemp
3644 // copy_s.w $rtemp, $wtemp2[0]
3645 // mtc1 $rtemp, $ftemp
3646 // copy_s.w $rtemp2, $wtemp2[1]
3647 // $fd = mthc1 $rtemp2, $ftemp
3649 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3650  MachineBasicBlock *BB,
3651  bool IsFGR64) const {
3652 
3653  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3654  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3655  // it.
3657 
3658  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3659  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3660 
3662  DebugLoc DL = MI.getDebugLoc();
3663  unsigned Fd = MI.getOperand(0).getReg();
3664  unsigned Ws = MI.getOperand(1).getReg();
3665 
3666  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3667  const TargetRegisterClass *GPRRC =
3668  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3669  unsigned MTC1Opc = IsFGR64onMips64
3670  ? Mips::DMTC1
3671  : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3672  unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3673 
3674  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3675  unsigned WPHI = Wtemp;
3676 
3677  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3678  if (IsFGR64) {
3679  WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3680  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3681  }
3682 
3683  // Perform the safety regclass copy mentioned above.
3684  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3685  unsigned FPRPHI = IsFGR64onMips32
3686  ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3687  : Fd;
3688  BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3689  BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3690 
3691  if (IsFGR64onMips32) {
3692  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3693  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3694  .addReg(WPHI)
3695  .addImm(1);
3696  BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3697  .addReg(FPRPHI)
3698  .addReg(Rtemp2);
3699  }
3700 
3701  MI.eraseFromParent();
3702  return BB;
3703 }
3704 
3705 // Emit the FEXP2_W_1 pseudo instructions.
3706 //
3707 // fexp2_w_1_pseudo $wd, $wt
3708 // =>
3709 // ldi.w $ws, 1
3710 // fexp2.w $wd, $ws, $wt
3712 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3713  MachineBasicBlock *BB) const {
3715  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3716  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3717  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3718  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3719  DebugLoc DL = MI.getDebugLoc();
3720 
3721  // Splat 1.0 into a vector
3722  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3723  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3724 
3725  // Emit 1.0 * fexp2(Wt)
3726  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3727  .addReg(Ws2)
3728  .addReg(MI.getOperand(1).getReg());
3729 
3730  MI.eraseFromParent(); // The pseudo instruction is gone now.
3731  return BB;
3732 }
3733 
3734 // Emit the FEXP2_D_1 pseudo instructions.
3735 //
3736 // fexp2_d_1_pseudo $wd, $wt
3737 // =>
3738 // ldi.d $ws, 1
3739 // fexp2.d $wd, $ws, $wt
3741 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3742  MachineBasicBlock *BB) const {
3744  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3745  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3746  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3747  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3748  DebugLoc DL = MI.getDebugLoc();
3749 
3750  // Splat 1.0 into a vector
3751  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3752  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3753 
3754  // Emit 1.0 * fexp2(Wt)
3755  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3756  .addReg(Ws2)
3757  .addReg(MI.getOperand(1).getReg());
3758 
3759  MI.eraseFromParent(); // The pseudo instruction is gone now.
3760  return BB;
3761 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:546
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
const MachineInstrBuilder & add(const MachineOperand &MO) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:570
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:923
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:329
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MipsSubtarget & Subtarget
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:618
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
value_iterator value_end() const
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:343
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned getReg() const
getReg - Returns the register number.
const SDValue & getValue() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDVTList getVTList() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:641
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
const MipsInstrInfo * getInstrInfo() const override
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isABI_O32() const
unsigned getAlignment() const
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:819
A debug info location.
Definition: DebugLoc.h:34
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:360
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:749
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1488
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasMips64() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
bool hasDSPR2() const
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
Shift and rotation operations.
Definition: ISDOpcodes.h:380
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:191
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getScalarValueSizeInBits() const
bool isGP64bit() const
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
bool hasMips32r6() const
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:390
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This file implements a class to represent arbitrary precision integral constant values and operations...
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:456
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:399
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
static bool isConstantOrUndef(const SDValue Op)
unsigned getIncomingArgSize() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:855
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:125
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:561
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
amdgpu Simplify well known AMD library false Value * Callee
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:499
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:303
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:629
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1164
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:357
const SDValue & getBasePtr() const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:389
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Machine Value Type.
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1472
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
const SDValue & getOperand(unsigned Num) const
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:308
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static const unsigned End
const APInt & getAPIntValue() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:531
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Extended Value Type.
Definition: ValueTypes.h:34
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
bool isSingleFloat() const
unsigned ceilLogBase2() const
Definition: APInt.h:1730
This structure contains all information that is necessary for lowering calls.
bool hasMips64r6() const
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:959
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isLittle() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:392
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:315
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL)
double Log2(double Value)
Return the log base 2 of the specified value.
Definition: MathExtras.h:520
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
value_iterator value_begin() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
Definition: SelectionDAG.h:719
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:721
bool hasCnMips() const
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:96
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:612
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
int64_t getImm() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasDSP() const
unsigned logBase2() const
Definition: APInt.h:1727
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
static bool isSplatVector(const BuildVectorSDNode *N)
Check if the given BuildVectorSDNode is a splat.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
bool isPowerOf2() const
Check if this APInt&#39;s value is a power of two greater than zero.
Definition: APInt.h:457
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:446
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:288
int getMaskElt(unsigned Idx) const
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:573
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:182
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:582
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the &#39;representative&#39; register class for the specified value type.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:392
Flags getFlags() const
Return the raw flags of the source value,.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
bool useOddSPReg() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:576
SDValue getValue(unsigned R) const
unsigned getInRegsParamsCount() const
bool hasMips32r2() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isABI_N64() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:278
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool isUndef() const
Return true if the type of the node type undefined.
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
bool useSoftFloat() const
#define DEBUG(X)
Definition: Debug.h:118
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
IRTranslator LLVM IR MI
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:413
Conversion operators.
Definition: ISDOpcodes.h:443
const SDValue & getOperand(unsigned i) const
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
Definition: MipsSEISelLower