LLVM  9.0.0svn
MipsSEISelLowering.cpp
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1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Triple.h"
35 #include "llvm/IR/DebugLoc.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Debug.h"
44 #include <algorithm>
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "mips-isel"
53 
54 static cl::opt<bool>
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
56  cl::desc("MIPS: permit tail calls."), cl::init(false));
57 
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
59  cl::desc("Expand double precision loads and "
60  "stores to their single precision "
61  "counterparts"));
62 
64  const MipsSubtarget &STI)
65  : MipsTargetLowering(TM, STI) {
66  // Set up the register classes
67  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
68 
69  if (Subtarget.isGP64bit())
70  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
71 
72  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
73  // Expand all truncating stores and extending loads.
74  for (MVT VT0 : MVT::vector_valuetypes()) {
75  for (MVT VT1 : MVT::vector_valuetypes()) {
76  setTruncStoreAction(VT0, VT1, Expand);
80  }
81  }
82  }
83 
84  if (Subtarget.hasDSP()) {
86 
87  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
88  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
89 
90  // Expand all builtin opcodes.
91  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
92  setOperationAction(Opc, VecTys[i], Expand);
93 
94  setOperationAction(ISD::ADD, VecTys[i], Legal);
95  setOperationAction(ISD::SUB, VecTys[i], Legal);
96  setOperationAction(ISD::LOAD, VecTys[i], Legal);
97  setOperationAction(ISD::STORE, VecTys[i], Legal);
99  }
100 
106 
107  if (Subtarget.hasMips32r2()) {
110  }
111  }
112 
113  if (Subtarget.hasDSPR2())
115 
116  if (Subtarget.hasMSA()) {
117  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
118  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
119  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
120  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
121  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
122  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
123  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
124 
125  // f16 is a storage-only type, always promote it to f32.
126  addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
162 
168  }
169 
170  if (!Subtarget.useSoftFloat()) {
171  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
172 
173  // When dealing with single precision only, use libcalls
174  if (!Subtarget.isSingleFloat()) {
175  if (Subtarget.isFP64bit())
176  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
177  else
178  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
179  }
180  }
181 
186 
187  if (Subtarget.hasCnMips())
189  else if (Subtarget.isGP64bit())
191 
192  if (Subtarget.isGP64bit()) {
199  }
200 
203 
209 
211 
215 
216  if (NoDPLoadStore) {
219  }
220 
221  if (Subtarget.hasMips32r6()) {
222  // MIPS32r6 replaces the accumulator-based multiplies with a three register
223  // instruction
229 
230  // MIPS32r6 replaces the accumulator-based division/remainder with separate
231  // three register division and remainder instructions.
238 
239  // MIPS32r6 replaces conditional moves with an equivalent that removes the
240  // need for three GPR read ports.
244 
248 
249  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
253 
255 
256  // Floating point > and >= are supported via < and <=
261 
266  }
267 
268  if (Subtarget.hasMips64r6()) {
269  // MIPS64r6 replaces the accumulator-based multiplies with a three register
270  // instruction
276 
277  // MIPS32r6 replaces the accumulator-based division/remainder with separate
278  // three register division and remainder instructions.
285 
286  // MIPS64r6 replaces conditional moves with an equivalent that removes the
287  // need for three GPR read ports.
291  }
292 
294 }
295 
296 const MipsTargetLowering *
298  const MipsSubtarget &STI) {
299  return new MipsSETargetLowering(TM, STI);
300 }
301 
302 const TargetRegisterClass *
304  if (VT == MVT::Untyped)
305  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
306 
308 }
309 
310 // Enable MSA support for the given integer type and Register class.
313  addRegisterClass(Ty, RC);
314 
315  // Expand all builtin opcodes.
316  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
317  setOperationAction(Opc, Ty, Expand);
318 
325 
347 
348  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
353  }
354 
361 }
362 
363 // Enable MSA support for the given floating-point type and Register class.
366  addRegisterClass(Ty, RC);
367 
368  // Expand all builtin opcodes.
369  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
370  setOperationAction(Opc, Ty, Expand);
371 
378 
379  if (Ty != MVT::v8f16) {
391 
399  }
400 }
401 
402 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
403  if(!Subtarget.hasMips32r6())
404  return MipsTargetLowering::LowerOperation(Op, DAG);
405 
406  EVT ResTy = Op->getValueType(0);
407  SDLoc DL(Op);
408 
409  // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
410  // floating point register are undefined. Not really an issue as sel.d, which
411  // is produced from an FSELECT node, only looks at bit 0.
412  SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
413  return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
414  Op->getOperand(2));
415 }
416 
417 bool
419  unsigned,
420  unsigned,
421  bool *Fast) const {
423 
425  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
426  // implementation defined whether this is handled by hardware, software, or
427  // a hybrid of the two but it's expected that most implementations will
428  // handle the majority of cases in hardware.
429  if (Fast)
430  *Fast = true;
431  return true;
432  }
433 
434  switch (SVT) {
435  case MVT::i64:
436  case MVT::i32:
437  if (Fast)
438  *Fast = true;
439  return true;
440  default:
441  return false;
442  }
443 }
444 
446  SelectionDAG &DAG) const {
447  switch(Op.getOpcode()) {
448  case ISD::LOAD: return lowerLOAD(Op, DAG);
449  case ISD::STORE: return lowerSTORE(Op, DAG);
450  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
451  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
452  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
453  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
454  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
455  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
456  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
457  DAG);
458  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
459  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
460  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
461  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
462  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
463  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
464  case ISD::SELECT: return lowerSELECT(Op, DAG);
465  }
466 
467  return MipsTargetLowering::LowerOperation(Op, DAG);
468 }
469 
470 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
471 //
472 // Performs the following transformations:
473 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
474 // sign/zero-extension is completely overwritten by the new one performed by
475 // the ISD::AND.
476 // - Removes redundant zero extensions performed by an ISD::AND.
479  const MipsSubtarget &Subtarget) {
480  if (!Subtarget.hasMSA())
481  return SDValue();
482 
483  SDValue Op0 = N->getOperand(0);
484  SDValue Op1 = N->getOperand(1);
485  unsigned Op0Opcode = Op0->getOpcode();
486 
487  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
488  // where $d + 1 == 2^n and n == 32
489  // or $d + 1 == 2^n and n <= 32 and ZExt
490  // -> (MipsVExtractZExt $a, $b, $c)
491  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
492  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
494 
495  if (!Mask)
496  return SDValue();
497 
498  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
499 
500  if (Log2IfPositive <= 0)
501  return SDValue(); // Mask+1 is not a power of 2
502 
503  SDValue Op0Op2 = Op0->getOperand(2);
504  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
505  unsigned ExtendTySize = ExtendTy.getSizeInBits();
506  unsigned Log2 = Log2IfPositive;
507 
508  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
509  Log2 == ExtendTySize) {
510  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
511  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
512  Op0->getVTList(),
513  makeArrayRef(Ops, Op0->getNumOperands()));
514  }
515  }
516 
517  return SDValue();
518 }
519 
520 // Determine if the specified node is a constant vector splat.
521 //
522 // Returns true and sets Imm if:
523 // * N is a ISD::BUILD_VECTOR representing a constant splat
524 //
525 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
526 // differences are that it assumes the MSA has already been checked and the
527 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
528 // must not be in order for binsri.d to be selectable).
529 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
531 
532  if (!Node)
533  return false;
534 
535  APInt SplatValue, SplatUndef;
536  unsigned SplatBitSize;
537  bool HasAnyUndefs;
538 
539  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
540  8, !IsLittleEndian))
541  return false;
542 
543  Imm = SplatValue;
544 
545  return true;
546 }
547 
548 // Test whether the given node is an all-ones build_vector.
549 static bool isVectorAllOnes(SDValue N) {
550  // Look through bitcasts. Endianness doesn't matter because we are looking
551  // for an all-ones value.
552  if (N->getOpcode() == ISD::BITCAST)
553  N = N->getOperand(0);
554 
556 
557  if (!BVN)
558  return false;
559 
560  APInt SplatValue, SplatUndef;
561  unsigned SplatBitSize;
562  bool HasAnyUndefs;
563 
564  // Endianness doesn't matter in this context because we are looking for
565  // an all-ones value.
566  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
567  return SplatValue.isAllOnesValue();
568 
569  return false;
570 }
571 
572 // Test whether N is the bitwise inverse of OfNode.
573 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
574  if (N->getOpcode() != ISD::XOR)
575  return false;
576 
577  if (isVectorAllOnes(N->getOperand(0)))
578  return N->getOperand(1) == OfNode;
579 
580  if (isVectorAllOnes(N->getOperand(1)))
581  return N->getOperand(0) == OfNode;
582 
583  return false;
584 }
585 
586 // Perform combines where ISD::OR is the root node.
587 //
588 // Performs the following transformations:
589 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
590 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
591 // vector type.
594  const MipsSubtarget &Subtarget) {
595  if (!Subtarget.hasMSA())
596  return SDValue();
597 
598  EVT Ty = N->getValueType(0);
599 
600  if (!Ty.is128BitVector())
601  return SDValue();
602 
603  SDValue Op0 = N->getOperand(0);
604  SDValue Op1 = N->getOperand(1);
605 
606  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
607  SDValue Op0Op0 = Op0->getOperand(0);
608  SDValue Op0Op1 = Op0->getOperand(1);
609  SDValue Op1Op0 = Op1->getOperand(0);
610  SDValue Op1Op1 = Op1->getOperand(1);
611  bool IsLittleEndian = !Subtarget.isLittle();
612 
613  SDValue IfSet, IfClr, Cond;
614  bool IsConstantMask = false;
615  APInt Mask, InvMask;
616 
617  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
618  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
619  // looking.
620  // IfClr will be set if we find a valid match.
621  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
622  Cond = Op0Op0;
623  IfSet = Op0Op1;
624 
625  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
626  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
627  IfClr = Op1Op1;
628  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
629  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
630  IfClr = Op1Op0;
631 
632  IsConstantMask = true;
633  }
634 
635  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
636  // thing again using this mask.
637  // IfClr will be set if we find a valid match.
638  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
639  Cond = Op0Op1;
640  IfSet = Op0Op0;
641 
642  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
643  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
644  IfClr = Op1Op1;
645  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
646  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
647  IfClr = Op1Op0;
648 
649  IsConstantMask = true;
650  }
651 
652  // If IfClr is not yet set, try looking for a non-constant match.
653  // IfClr will be set if we find a valid match amongst the eight
654  // possibilities.
655  if (!IfClr.getNode()) {
656  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
657  Cond = Op1Op0;
658  IfSet = Op1Op1;
659  IfClr = Op0Op1;
660  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
661  Cond = Op1Op0;
662  IfSet = Op1Op1;
663  IfClr = Op0Op0;
664  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
665  Cond = Op1Op1;
666  IfSet = Op1Op0;
667  IfClr = Op0Op1;
668  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
669  Cond = Op1Op1;
670  IfSet = Op1Op0;
671  IfClr = Op0Op0;
672  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
673  Cond = Op0Op0;
674  IfSet = Op0Op1;
675  IfClr = Op1Op1;
676  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
677  Cond = Op0Op0;
678  IfSet = Op0Op1;
679  IfClr = Op1Op0;
680  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
681  Cond = Op0Op1;
682  IfSet = Op0Op0;
683  IfClr = Op1Op1;
684  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
685  Cond = Op0Op1;
686  IfSet = Op0Op0;
687  IfClr = Op1Op0;
688  }
689  }
690 
691  // At this point, IfClr will be set if we have a valid match.
692  if (!IfClr.getNode())
693  return SDValue();
694 
695  assert(Cond.getNode() && IfSet.getNode());
696 
697  // Fold degenerate cases.
698  if (IsConstantMask) {
699  if (Mask.isAllOnesValue())
700  return IfSet;
701  else if (Mask == 0)
702  return IfClr;
703  }
704 
705  // Transform the DAG into an equivalent VSELECT.
706  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
707  }
708 
709  return SDValue();
710 }
711 
713  SelectionDAG &DAG,
714  const MipsSubtarget &Subtarget) {
715  // Estimate the number of operations the below transform will turn a
716  // constant multiply into. The number is approximately how many powers
717  // of two summed together that the constant can be broken down into.
718 
719  SmallVector<APInt, 16> WorkStack(1, C);
720  unsigned Steps = 0;
721  unsigned BitWidth = C.getBitWidth();
722 
723  while (!WorkStack.empty()) {
724  APInt Val = WorkStack.pop_back_val();
725 
726  if (Val == 0 || Val == 1)
727  continue;
728 
729  if (Val.isPowerOf2()) {
730  ++Steps;
731  continue;
732  }
733 
734  APInt Floor = APInt(BitWidth, 1) << Val.logBase2();
735  APInt Ceil = Val.isNegative() ? APInt(BitWidth, 0)
736  : APInt(BitWidth, 1) << C.ceilLogBase2();
737 
738  if ((Val - Floor).ule(Ceil - Val)) {
739  WorkStack.push_back(Floor);
740  WorkStack.push_back(Val - Floor);
741  ++Steps;
742  continue;
743  }
744 
745  WorkStack.push_back(Ceil);
746  WorkStack.push_back(Ceil - Val);
747  ++Steps;
748 
749  // If we have taken more than 12[1] / 8[2] steps to attempt the
750  // optimization for a native sized value, it is more than likely that this
751  // optimization will make things worse.
752  //
753  // [1] MIPS64 requires 6 instructions at most to materialize any constant,
754  // multiplication requires at least 4 cycles, but another cycle (or two)
755  // to retrieve the result from the HI/LO registers.
756  //
757  // [2] For MIPS32, more than 8 steps is expensive as the constant could be
758  // materialized in 2 instructions, multiplication requires at least 4
759  // cycles, but another cycle (or two) to retrieve the result from the
760  // HI/LO registers.
761 
762  if (Steps > 12 && (Subtarget.isABI_N32() || Subtarget.isABI_N64()))
763  return false;
764 
765  if (Steps > 8 && Subtarget.isABI_O32())
766  return false;
767  }
768 
769  // If the value being multiplied is not supported natively, we have to pay
770  // an additional legalization cost, conservatively assume an increase in the
771  // cost of 3 instructions per step. This values for this heuristic were
772  // determined experimentally.
773  unsigned RegisterSize = DAG.getTargetLoweringInfo()
774  .getRegisterType(*DAG.getContext(), VT)
775  .getSizeInBits();
776  Steps *= (VT.getSizeInBits() != RegisterSize) * 3;
777  if (Steps > 27)
778  return false;
779 
780  return true;
781 }
782 
783 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
784  EVT ShiftTy, SelectionDAG &DAG) {
785  // Return 0.
786  if (C == 0)
787  return DAG.getConstant(0, DL, VT);
788 
789  // Return x.
790  if (C == 1)
791  return X;
792 
793  // If c is power of 2, return (shl x, log2(c)).
794  if (C.isPowerOf2())
795  return DAG.getNode(ISD::SHL, DL, VT, X,
796  DAG.getConstant(C.logBase2(), DL, ShiftTy));
797 
798  unsigned BitWidth = C.getBitWidth();
799  APInt Floor = APInt(BitWidth, 1) << C.logBase2();
800  APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
801  APInt(BitWidth, 1) << C.ceilLogBase2();
802 
803  // If |c - floor_c| <= |c - ceil_c|,
804  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
805  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
806  if ((C - Floor).ule(Ceil - C)) {
807  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
808  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
809  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
810  }
811 
812  // If |c - floor_c| > |c - ceil_c|,
813  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
814  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
815  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
816  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
817 }
818 
821  const MipsSETargetLowering *TL,
822  const MipsSubtarget &Subtarget) {
823  EVT VT = N->getValueType(0);
824 
825  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
827  C->getAPIntValue(), VT, DAG, Subtarget))
828  return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
829  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
830  DAG);
831 
832  return SDValue(N, 0);
833 }
834 
835 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
836  SelectionDAG &DAG,
837  const MipsSubtarget &Subtarget) {
838  // See if this is a vector splat immediate node.
839  APInt SplatValue, SplatUndef;
840  unsigned SplatBitSize;
841  bool HasAnyUndefs;
842  unsigned EltSize = Ty.getScalarSizeInBits();
844 
845  if (!Subtarget.hasDSP())
846  return SDValue();
847 
848  if (!BV ||
849  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
850  EltSize, !Subtarget.isLittle()) ||
851  (SplatBitSize != EltSize) ||
852  (SplatValue.getZExtValue() >= EltSize))
853  return SDValue();
854 
855  SDLoc DL(N);
856  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
857  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
858 }
859 
862  const MipsSubtarget &Subtarget) {
863  EVT Ty = N->getValueType(0);
864 
865  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
866  return SDValue();
867 
868  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
869 }
870 
871 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
872 // constant splats into MipsISD::SHRA_DSP for DSPr2.
873 //
874 // Performs the following transformations:
875 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
876 // sign/zero-extension is completely overwritten by the new one performed by
877 // the ISD::SRA and ISD::SHL nodes.
878 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
879 // sequence.
880 //
881 // See performDSPShiftCombine for more information about the transformation
882 // used for DSPr2.
885  const MipsSubtarget &Subtarget) {
886  EVT Ty = N->getValueType(0);
887 
888  if (Subtarget.hasMSA()) {
889  SDValue Op0 = N->getOperand(0);
890  SDValue Op1 = N->getOperand(1);
891 
892  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
893  // where $d + sizeof($c) == 32
894  // or $d + sizeof($c) <= 32 and SExt
895  // -> (MipsVExtractSExt $a, $b, $c)
896  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
897  SDValue Op0Op0 = Op0->getOperand(0);
898  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
899 
900  if (!ShAmount)
901  return SDValue();
902 
903  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
905  return SDValue();
906 
907  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
908  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
909 
910  if (TotalBits == 32 ||
911  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
912  TotalBits <= 32)) {
913  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
914  Op0Op0->getOperand(2) };
915  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
916  Op0Op0->getVTList(),
917  makeArrayRef(Ops, Op0Op0->getNumOperands()));
918  }
919  }
920  }
921 
922  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
923  return SDValue();
924 
925  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
926 }
927 
928 
931  const MipsSubtarget &Subtarget) {
932  EVT Ty = N->getValueType(0);
933 
934  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
935  return SDValue();
936 
937  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
938 }
939 
940 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
941  bool IsV216 = (Ty == MVT::v2i16);
942 
943  switch (CC) {
944  case ISD::SETEQ:
945  case ISD::SETNE: return true;
946  case ISD::SETLT:
947  case ISD::SETLE:
948  case ISD::SETGT:
949  case ISD::SETGE: return IsV216;
950  case ISD::SETULT:
951  case ISD::SETULE:
952  case ISD::SETUGT:
953  case ISD::SETUGE: return !IsV216;
954  default: return false;
955  }
956 }
957 
959  EVT Ty = N->getValueType(0);
960 
961  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
962  return SDValue();
963 
964  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
965  return SDValue();
966 
967  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
968  N->getOperand(1), N->getOperand(2));
969 }
970 
972  EVT Ty = N->getValueType(0);
973 
974  if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
975  SDValue SetCC = N->getOperand(0);
976 
977  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
978  return SDValue();
979 
980  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
981  SetCC.getOperand(0), SetCC.getOperand(1),
982  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
983  }
984 
985  return SDValue();
986 }
987 
989  const MipsSubtarget &Subtarget) {
990  EVT Ty = N->getValueType(0);
991 
992  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
993  // Try the following combines:
994  // (xor (or $a, $b), (build_vector allones))
995  // (xor (or $a, $b), (bitcast (build_vector allones)))
996  SDValue Op0 = N->getOperand(0);
997  SDValue Op1 = N->getOperand(1);
998  SDValue NotOp;
999 
1001  NotOp = Op1;
1002  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1003  NotOp = Op0;
1004  else
1005  return SDValue();
1006 
1007  if (NotOp->getOpcode() == ISD::OR)
1008  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1009  NotOp->getOperand(1));
1010  }
1011 
1012  return SDValue();
1013 }
1014 
1015 SDValue
1017  SelectionDAG &DAG = DCI.DAG;
1018  SDValue Val;
1019 
1020  switch (N->getOpcode()) {
1021  case ISD::AND:
1022  Val = performANDCombine(N, DAG, DCI, Subtarget);
1023  break;
1024  case ISD::OR:
1025  Val = performORCombine(N, DAG, DCI, Subtarget);
1026  break;
1027  case ISD::MUL:
1028  return performMULCombine(N, DAG, DCI, this, Subtarget);
1029  case ISD::SHL:
1030  Val = performSHLCombine(N, DAG, DCI, Subtarget);
1031  break;
1032  case ISD::SRA:
1033  return performSRACombine(N, DAG, DCI, Subtarget);
1034  case ISD::SRL:
1035  return performSRLCombine(N, DAG, DCI, Subtarget);
1036  case ISD::VSELECT:
1037  return performVSELECTCombine(N, DAG);
1038  case ISD::XOR:
1039  Val = performXORCombine(N, DAG, Subtarget);
1040  break;
1041  case ISD::SETCC:
1042  Val = performSETCCCombine(N, DAG);
1043  break;
1044  }
1045 
1046  if (Val.getNode()) {
1047  LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1048  N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";
1049  Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n");
1050  return Val;
1051  }
1052 
1054 }
1055 
1058  MachineBasicBlock *BB) const {
1059  switch (MI.getOpcode()) {
1060  default:
1062  case Mips::BPOSGE32_PSEUDO:
1063  return emitBPOSGE32(MI, BB);
1064  case Mips::SNZ_B_PSEUDO:
1065  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1066  case Mips::SNZ_H_PSEUDO:
1067  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1068  case Mips::SNZ_W_PSEUDO:
1069  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1070  case Mips::SNZ_D_PSEUDO:
1071  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1072  case Mips::SNZ_V_PSEUDO:
1073  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1074  case Mips::SZ_B_PSEUDO:
1075  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1076  case Mips::SZ_H_PSEUDO:
1077  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1078  case Mips::SZ_W_PSEUDO:
1079  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1080  case Mips::SZ_D_PSEUDO:
1081  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1082  case Mips::SZ_V_PSEUDO:
1083  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1084  case Mips::COPY_FW_PSEUDO:
1085  return emitCOPY_FW(MI, BB);
1086  case Mips::COPY_FD_PSEUDO:
1087  return emitCOPY_FD(MI, BB);
1088  case Mips::INSERT_FW_PSEUDO:
1089  return emitINSERT_FW(MI, BB);
1090  case Mips::INSERT_FD_PSEUDO:
1091  return emitINSERT_FD(MI, BB);
1092  case Mips::INSERT_B_VIDX_PSEUDO:
1093  case Mips::INSERT_B_VIDX64_PSEUDO:
1094  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1095  case Mips::INSERT_H_VIDX_PSEUDO:
1096  case Mips::INSERT_H_VIDX64_PSEUDO:
1097  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1098  case Mips::INSERT_W_VIDX_PSEUDO:
1099  case Mips::INSERT_W_VIDX64_PSEUDO:
1100  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1101  case Mips::INSERT_D_VIDX_PSEUDO:
1102  case Mips::INSERT_D_VIDX64_PSEUDO:
1103  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1104  case Mips::INSERT_FW_VIDX_PSEUDO:
1105  case Mips::INSERT_FW_VIDX64_PSEUDO:
1106  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1107  case Mips::INSERT_FD_VIDX_PSEUDO:
1108  case Mips::INSERT_FD_VIDX64_PSEUDO:
1109  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1110  case Mips::FILL_FW_PSEUDO:
1111  return emitFILL_FW(MI, BB);
1112  case Mips::FILL_FD_PSEUDO:
1113  return emitFILL_FD(MI, BB);
1114  case Mips::FEXP2_W_1_PSEUDO:
1115  return emitFEXP2_W_1(MI, BB);
1116  case Mips::FEXP2_D_1_PSEUDO:
1117  return emitFEXP2_D_1(MI, BB);
1118  case Mips::ST_F16:
1119  return emitST_F16_PSEUDO(MI, BB);
1120  case Mips::LD_F16:
1121  return emitLD_F16_PSEUDO(MI, BB);
1122  case Mips::MSA_FP_EXTEND_W_PSEUDO:
1123  return emitFPEXTEND_PSEUDO(MI, BB, false);
1124  case Mips::MSA_FP_ROUND_W_PSEUDO:
1125  return emitFPROUND_PSEUDO(MI, BB, false);
1126  case Mips::MSA_FP_EXTEND_D_PSEUDO:
1127  return emitFPEXTEND_PSEUDO(MI, BB, true);
1128  case Mips::MSA_FP_ROUND_D_PSEUDO:
1129  return emitFPROUND_PSEUDO(MI, BB, true);
1130  }
1131 }
1132 
1133 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1134  const CCState &CCInfo, unsigned NextStackOffset,
1135  const MipsFunctionInfo &FI) const {
1136  if (!UseMipsTailCalls)
1137  return false;
1138 
1139  // Exception has to be cleared with eret.
1140  if (FI.isISR())
1141  return false;
1142 
1143  // Return false if either the callee or caller has a byval argument.
1144  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1145  return false;
1146 
1147  // Return true if the callee's argument area is no larger than the
1148  // caller's.
1149  return NextStackOffset <= FI.getIncomingArgSize();
1150 }
1151 
1152 void MipsSETargetLowering::
1153 getOpndList(SmallVectorImpl<SDValue> &Ops,
1154  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1155  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1156  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1157  SDValue Chain) const {
1158  Ops.push_back(Callee);
1159  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1160  InternalLinkage, IsCallReloc, CLI, Callee,
1161  Chain);
1162 }
1163 
1164 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1165  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1166 
1167  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1168  return MipsTargetLowering::lowerLOAD(Op, DAG);
1169 
1170  // Replace a double precision load with two i32 loads and a buildpair64.
1171  SDLoc DL(Op);
1172  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1173  EVT PtrVT = Ptr.getValueType();
1174 
1175  // i32 load from lower address.
1176  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1177  Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1178 
1179  // i32 load from higher address.
1180  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1181  SDValue Hi = DAG.getLoad(
1182  MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1183  std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1184 
1185  if (!Subtarget.isLittle())
1186  std::swap(Lo, Hi);
1187 
1188  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1189  SDValue Ops[2] = {BP, Hi.getValue(1)};
1190  return DAG.getMergeValues(Ops, DL);
1191 }
1192 
1193 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1194  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1195 
1196  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1197  return MipsTargetLowering::lowerSTORE(Op, DAG);
1198 
1199  // Replace a double precision store with two extractelement64s and i32 stores.
1200  SDLoc DL(Op);
1201  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1202  EVT PtrVT = Ptr.getValueType();
1204  Val, DAG.getConstant(0, DL, MVT::i32));
1206  Val, DAG.getConstant(1, DL, MVT::i32));
1207 
1208  if (!Subtarget.isLittle())
1209  std::swap(Lo, Hi);
1210 
1211  // i32 store to lower address.
1212  Chain =
1213  DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1214  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1215 
1216  // i32 store to higher address.
1217  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1218  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1219  std::min(Nd.getAlignment(), 4U),
1220  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1221 }
1222 
1223 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1224  bool HasLo, bool HasHi,
1225  SelectionDAG &DAG) const {
1226  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1228 
1229  EVT Ty = Op.getOperand(0).getValueType();
1230  SDLoc DL(Op);
1231  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1232  Op.getOperand(0), Op.getOperand(1));
1233  SDValue Lo, Hi;
1234 
1235  if (HasLo)
1236  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1237  if (HasHi)
1238  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1239 
1240  if (!HasLo || !HasHi)
1241  return HasLo ? Lo : Hi;
1242 
1243  SDValue Vals[] = { Lo, Hi };
1244  return DAG.getMergeValues(Vals, DL);
1245 }
1246 
1248  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1249  DAG.getConstant(0, DL, MVT::i32));
1250  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1251  DAG.getConstant(1, DL, MVT::i32));
1252  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1253 }
1254 
1255 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1256  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1257  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1258  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1259 }
1260 
1261 // This function expands mips intrinsic nodes which have 64-bit input operands
1262 // or output values.
1263 //
1264 // out64 = intrinsic-node in64
1265 // =>
1266 // lo = copy (extract-element (in64, 0))
1267 // hi = copy (extract-element (in64, 1))
1268 // mips-specific-node
1269 // v0 = copy lo
1270 // v1 = copy hi
1271 // out64 = merge-values (v0, v1)
1272 //
1273 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1274  SDLoc DL(Op);
1275  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1277  unsigned OpNo = 0;
1278 
1279  // See if Op has a chain input.
1280  if (HasChainIn)
1281  Ops.push_back(Op->getOperand(OpNo++));
1282 
1283  // The next operand is the intrinsic opcode.
1285 
1286  // See if the next operand has type i64.
1287  SDValue Opnd = Op->getOperand(++OpNo), In64;
1288 
1289  if (Opnd.getValueType() == MVT::i64)
1290  In64 = initAccumulator(Opnd, DL, DAG);
1291  else
1292  Ops.push_back(Opnd);
1293 
1294  // Push the remaining operands.
1295  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1296  Ops.push_back(Op->getOperand(OpNo));
1297 
1298  // Add In64 to the end of the list.
1299  if (In64.getNode())
1300  Ops.push_back(In64);
1301 
1302  // Scan output.
1303  SmallVector<EVT, 2> ResTys;
1304 
1305  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1306  I != E; ++I)
1307  ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1308 
1309  // Create node.
1310  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1311  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1312 
1313  if (!HasChainIn)
1314  return Out;
1315 
1316  assert(Val->getValueType(1) == MVT::Other);
1317  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1318  return DAG.getMergeValues(Vals, DL);
1319 }
1320 
1321 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1322 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1323  SDLoc DL(Op);
1324  SDValue Vec = Op->getOperand(1);
1325  SDValue Idx = Op->getOperand(2);
1326  EVT ResTy = Op->getValueType(0);
1327  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1328 
1329  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1330  DAG.getValueType(EltTy));
1331 
1332  return Result;
1333 }
1334 
1335 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1336  EVT ResVecTy = Op->getValueType(0);
1337  EVT ViaVecTy = ResVecTy;
1338  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1339  SDLoc DL(Op);
1340 
1341  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1342  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1343  // lanes.
1344  SDValue LaneA = Op->getOperand(OpNr);
1345  SDValue LaneB;
1346 
1347  if (ResVecTy == MVT::v2i64) {
1348  // In case of the index being passed as an immediate value, set the upper
1349  // lane to 0 so that the splati.d instruction can be matched.
1350  if (isa<ConstantSDNode>(LaneA))
1351  LaneB = DAG.getConstant(0, DL, MVT::i32);
1352  // Having the index passed in a register, set the upper lane to the same
1353  // value as the lower - this results in the BUILD_VECTOR node not being
1354  // expanded through stack. This way we are able to pattern match the set of
1355  // nodes created here to splat.d.
1356  else
1357  LaneB = LaneA;
1358  ViaVecTy = MVT::v4i32;
1359  if(BigEndian)
1360  std::swap(LaneA, LaneB);
1361  } else
1362  LaneB = LaneA;
1363 
1364  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1365  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1366 
1367  SDValue Result = DAG.getBuildVector(
1368  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1369 
1370  if (ViaVecTy != ResVecTy) {
1371  SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1372  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1373  DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1374  }
1375 
1376  return Result;
1377 }
1378 
1379 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1380  bool IsSigned = false) {
1381  return DAG.getConstant(
1383  Op->getConstantOperandVal(ImmOp), IsSigned),
1384  SDLoc(Op), Op->getValueType(0));
1385 }
1386 
1387 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1388  bool BigEndian, SelectionDAG &DAG) {
1389  EVT ViaVecTy = VecTy;
1390  SDValue SplatValueA = SplatValue;
1391  SDValue SplatValueB = SplatValue;
1392  SDLoc DL(SplatValue);
1393 
1394  if (VecTy == MVT::v2i64) {
1395  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1396  ViaVecTy = MVT::v4i32;
1397 
1398  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1399  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1400  DAG.getConstant(32, DL, MVT::i32));
1401  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1402  }
1403 
1404  // We currently hold the parts in little endian order. Swap them if
1405  // necessary.
1406  if (BigEndian)
1407  std::swap(SplatValueA, SplatValueB);
1408 
1409  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1410  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1411  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1412  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1413 
1414  SDValue Result = DAG.getBuildVector(
1415  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1416 
1417  if (VecTy != ViaVecTy)
1418  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1419 
1420  return Result;
1421 }
1422 
1424  unsigned Opc, SDValue Imm,
1425  bool BigEndian) {
1426  EVT VecTy = Op->getValueType(0);
1427  SDValue Exp2Imm;
1428  SDLoc DL(Op);
1429 
1430  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1431  // here for now.
1432  if (VecTy == MVT::v2i64) {
1433  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1434  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1435 
1436  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1437  MVT::i32);
1438  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1439 
1440  if (BigEndian)
1441  std::swap(BitImmLoOp, BitImmHiOp);
1442 
1443  Exp2Imm = DAG.getNode(
1444  ISD::BITCAST, DL, MVT::v2i64,
1445  DAG.getBuildVector(MVT::v4i32, DL,
1446  {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1447  }
1448  }
1449 
1450  if (!Exp2Imm.getNode()) {
1451  // We couldnt constant fold, do a vector shift instead
1452 
1453  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1454  // only values 0-63 are valid.
1455  if (VecTy == MVT::v2i64)
1456  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1457 
1458  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1459 
1460  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1461  Exp2Imm);
1462  }
1463 
1464  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1465 }
1466 
1468  SDLoc DL(Op);
1469  EVT ResTy = Op->getValueType(0);
1470  SDValue Vec = Op->getOperand(2);
1471  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1472  MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1473  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1474  DL, ResEltTy);
1475  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1476 
1477  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1478 }
1479 
1481  EVT ResTy = Op->getValueType(0);
1482  SDLoc DL(Op);
1483  SDValue One = DAG.getConstant(1, DL, ResTy);
1484  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1485 
1486  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1487  DAG.getNOT(DL, Bit, ResTy));
1488 }
1489 
1491  SDLoc DL(Op);
1492  EVT ResTy = Op->getValueType(0);
1493  APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1494  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1495  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1496 
1497  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1498 }
1499 
1500 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1501  SelectionDAG &DAG) const {
1502  SDLoc DL(Op);
1503  unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1504  switch (Intrinsic) {
1505  default:
1506  return SDValue();
1507  case Intrinsic::mips_shilo:
1508  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1509  case Intrinsic::mips_dpau_h_qbl:
1510  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1511  case Intrinsic::mips_dpau_h_qbr:
1512  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1513  case Intrinsic::mips_dpsu_h_qbl:
1514  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1515  case Intrinsic::mips_dpsu_h_qbr:
1516  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1517  case Intrinsic::mips_dpa_w_ph:
1518  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1519  case Intrinsic::mips_dps_w_ph:
1520  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1521  case Intrinsic::mips_dpax_w_ph:
1522  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1523  case Intrinsic::mips_dpsx_w_ph:
1524  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1525  case Intrinsic::mips_mulsa_w_ph:
1526  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1527  case Intrinsic::mips_mult:
1528  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1529  case Intrinsic::mips_multu:
1530  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1531  case Intrinsic::mips_madd:
1532  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1533  case Intrinsic::mips_maddu:
1534  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1535  case Intrinsic::mips_msub:
1536  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1537  case Intrinsic::mips_msubu:
1538  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1539  case Intrinsic::mips_addv_b:
1540  case Intrinsic::mips_addv_h:
1541  case Intrinsic::mips_addv_w:
1542  case Intrinsic::mips_addv_d:
1543  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1544  Op->getOperand(2));
1545  case Intrinsic::mips_addvi_b:
1546  case Intrinsic::mips_addvi_h:
1547  case Intrinsic::mips_addvi_w:
1548  case Intrinsic::mips_addvi_d:
1549  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1550  lowerMSASplatImm(Op, 2, DAG));
1551  case Intrinsic::mips_and_v:
1552  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1553  Op->getOperand(2));
1554  case Intrinsic::mips_andi_b:
1555  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1556  lowerMSASplatImm(Op, 2, DAG));
1557  case Intrinsic::mips_bclr_b:
1558  case Intrinsic::mips_bclr_h:
1559  case Intrinsic::mips_bclr_w:
1560  case Intrinsic::mips_bclr_d:
1561  return lowerMSABitClear(Op, DAG);
1562  case Intrinsic::mips_bclri_b:
1563  case Intrinsic::mips_bclri_h:
1564  case Intrinsic::mips_bclri_w:
1565  case Intrinsic::mips_bclri_d:
1566  return lowerMSABitClearImm(Op, DAG);
1567  case Intrinsic::mips_binsli_b:
1568  case Intrinsic::mips_binsli_h:
1569  case Intrinsic::mips_binsli_w:
1570  case Intrinsic::mips_binsli_d: {
1571  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1572  EVT VecTy = Op->getValueType(0);
1573  EVT EltTy = VecTy.getVectorElementType();
1574  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1575  report_fatal_error("Immediate out of range");
1577  Op->getConstantOperandVal(3) + 1);
1578  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1579  DAG.getConstant(Mask, DL, VecTy, true),
1580  Op->getOperand(2), Op->getOperand(1));
1581  }
1582  case Intrinsic::mips_binsri_b:
1583  case Intrinsic::mips_binsri_h:
1584  case Intrinsic::mips_binsri_w:
1585  case Intrinsic::mips_binsri_d: {
1586  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1587  EVT VecTy = Op->getValueType(0);
1588  EVT EltTy = VecTy.getVectorElementType();
1589  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1590  report_fatal_error("Immediate out of range");
1592  Op->getConstantOperandVal(3) + 1);
1593  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1594  DAG.getConstant(Mask, DL, VecTy, true),
1595  Op->getOperand(2), Op->getOperand(1));
1596  }
1597  case Intrinsic::mips_bmnz_v:
1598  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1599  Op->getOperand(2), Op->getOperand(1));
1600  case Intrinsic::mips_bmnzi_b:
1601  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1602  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1603  Op->getOperand(1));
1604  case Intrinsic::mips_bmz_v:
1605  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1606  Op->getOperand(1), Op->getOperand(2));
1607  case Intrinsic::mips_bmzi_b:
1608  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1609  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1610  Op->getOperand(2));
1611  case Intrinsic::mips_bneg_b:
1612  case Intrinsic::mips_bneg_h:
1613  case Intrinsic::mips_bneg_w:
1614  case Intrinsic::mips_bneg_d: {
1615  EVT VecTy = Op->getValueType(0);
1616  SDValue One = DAG.getConstant(1, DL, VecTy);
1617 
1618  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1619  DAG.getNode(ISD::SHL, DL, VecTy, One,
1620  truncateVecElts(Op, DAG)));
1621  }
1622  case Intrinsic::mips_bnegi_b:
1623  case Intrinsic::mips_bnegi_h:
1624  case Intrinsic::mips_bnegi_w:
1625  case Intrinsic::mips_bnegi_d:
1626  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1627  !Subtarget.isLittle());
1628  case Intrinsic::mips_bnz_b:
1629  case Intrinsic::mips_bnz_h:
1630  case Intrinsic::mips_bnz_w:
1631  case Intrinsic::mips_bnz_d:
1632  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1633  Op->getOperand(1));
1634  case Intrinsic::mips_bnz_v:
1635  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1636  Op->getOperand(1));
1637  case Intrinsic::mips_bsel_v:
1638  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1639  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1640  Op->getOperand(1), Op->getOperand(3),
1641  Op->getOperand(2));
1642  case Intrinsic::mips_bseli_b:
1643  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1644  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1645  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1646  Op->getOperand(2));
1647  case Intrinsic::mips_bset_b:
1648  case Intrinsic::mips_bset_h:
1649  case Intrinsic::mips_bset_w:
1650  case Intrinsic::mips_bset_d: {
1651  EVT VecTy = Op->getValueType(0);
1652  SDValue One = DAG.getConstant(1, DL, VecTy);
1653 
1654  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1655  DAG.getNode(ISD::SHL, DL, VecTy, One,
1656  truncateVecElts(Op, DAG)));
1657  }
1658  case Intrinsic::mips_bseti_b:
1659  case Intrinsic::mips_bseti_h:
1660  case Intrinsic::mips_bseti_w:
1661  case Intrinsic::mips_bseti_d:
1662  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1663  !Subtarget.isLittle());
1664  case Intrinsic::mips_bz_b:
1665  case Intrinsic::mips_bz_h:
1666  case Intrinsic::mips_bz_w:
1667  case Intrinsic::mips_bz_d:
1668  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1669  Op->getOperand(1));
1670  case Intrinsic::mips_bz_v:
1671  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1672  Op->getOperand(1));
1673  case Intrinsic::mips_ceq_b:
1674  case Intrinsic::mips_ceq_h:
1675  case Intrinsic::mips_ceq_w:
1676  case Intrinsic::mips_ceq_d:
1677  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1678  Op->getOperand(2), ISD::SETEQ);
1679  case Intrinsic::mips_ceqi_b:
1680  case Intrinsic::mips_ceqi_h:
1681  case Intrinsic::mips_ceqi_w:
1682  case Intrinsic::mips_ceqi_d:
1683  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1684  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1685  case Intrinsic::mips_cle_s_b:
1686  case Intrinsic::mips_cle_s_h:
1687  case Intrinsic::mips_cle_s_w:
1688  case Intrinsic::mips_cle_s_d:
1689  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1690  Op->getOperand(2), ISD::SETLE);
1691  case Intrinsic::mips_clei_s_b:
1692  case Intrinsic::mips_clei_s_h:
1693  case Intrinsic::mips_clei_s_w:
1694  case Intrinsic::mips_clei_s_d:
1695  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1696  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1697  case Intrinsic::mips_cle_u_b:
1698  case Intrinsic::mips_cle_u_h:
1699  case Intrinsic::mips_cle_u_w:
1700  case Intrinsic::mips_cle_u_d:
1701  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1702  Op->getOperand(2), ISD::SETULE);
1703  case Intrinsic::mips_clei_u_b:
1704  case Intrinsic::mips_clei_u_h:
1705  case Intrinsic::mips_clei_u_w:
1706  case Intrinsic::mips_clei_u_d:
1707  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1708  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1709  case Intrinsic::mips_clt_s_b:
1710  case Intrinsic::mips_clt_s_h:
1711  case Intrinsic::mips_clt_s_w:
1712  case Intrinsic::mips_clt_s_d:
1713  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1714  Op->getOperand(2), ISD::SETLT);
1715  case Intrinsic::mips_clti_s_b:
1716  case Intrinsic::mips_clti_s_h:
1717  case Intrinsic::mips_clti_s_w:
1718  case Intrinsic::mips_clti_s_d:
1719  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1720  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1721  case Intrinsic::mips_clt_u_b:
1722  case Intrinsic::mips_clt_u_h:
1723  case Intrinsic::mips_clt_u_w:
1724  case Intrinsic::mips_clt_u_d:
1725  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1726  Op->getOperand(2), ISD::SETULT);
1727  case Intrinsic::mips_clti_u_b:
1728  case Intrinsic::mips_clti_u_h:
1729  case Intrinsic::mips_clti_u_w:
1730  case Intrinsic::mips_clti_u_d:
1731  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1732  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1733  case Intrinsic::mips_copy_s_b:
1734  case Intrinsic::mips_copy_s_h:
1735  case Intrinsic::mips_copy_s_w:
1737  case Intrinsic::mips_copy_s_d:
1738  if (Subtarget.hasMips64())
1739  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1741  else {
1742  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1743  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1744  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1745  Op->getValueType(0), Op->getOperand(1),
1746  Op->getOperand(2));
1747  }
1748  case Intrinsic::mips_copy_u_b:
1749  case Intrinsic::mips_copy_u_h:
1750  case Intrinsic::mips_copy_u_w:
1752  case Intrinsic::mips_copy_u_d:
1753  if (Subtarget.hasMips64())
1754  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1756  else {
1757  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1758  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1759  // Note: When i64 is illegal, this results in copy_s.w instructions
1760  // instead of copy_u.w instructions. This makes no difference to the
1761  // behaviour since i64 is only illegal when the register file is 32-bit.
1762  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1763  Op->getValueType(0), Op->getOperand(1),
1764  Op->getOperand(2));
1765  }
1766  case Intrinsic::mips_div_s_b:
1767  case Intrinsic::mips_div_s_h:
1768  case Intrinsic::mips_div_s_w:
1769  case Intrinsic::mips_div_s_d:
1770  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1771  Op->getOperand(2));
1772  case Intrinsic::mips_div_u_b:
1773  case Intrinsic::mips_div_u_h:
1774  case Intrinsic::mips_div_u_w:
1775  case Intrinsic::mips_div_u_d:
1776  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1777  Op->getOperand(2));
1778  case Intrinsic::mips_fadd_w:
1779  case Intrinsic::mips_fadd_d:
1780  // TODO: If intrinsics have fast-math-flags, propagate them.
1781  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1782  Op->getOperand(2));
1783  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1784  case Intrinsic::mips_fceq_w:
1785  case Intrinsic::mips_fceq_d:
1786  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1787  Op->getOperand(2), ISD::SETOEQ);
1788  case Intrinsic::mips_fcle_w:
1789  case Intrinsic::mips_fcle_d:
1790  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1791  Op->getOperand(2), ISD::SETOLE);
1792  case Intrinsic::mips_fclt_w:
1793  case Intrinsic::mips_fclt_d:
1794  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1795  Op->getOperand(2), ISD::SETOLT);
1796  case Intrinsic::mips_fcne_w:
1797  case Intrinsic::mips_fcne_d:
1798  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1799  Op->getOperand(2), ISD::SETONE);
1800  case Intrinsic::mips_fcor_w:
1801  case Intrinsic::mips_fcor_d:
1802  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1803  Op->getOperand(2), ISD::SETO);
1804  case Intrinsic::mips_fcueq_w:
1805  case Intrinsic::mips_fcueq_d:
1806  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1807  Op->getOperand(2), ISD::SETUEQ);
1808  case Intrinsic::mips_fcule_w:
1809  case Intrinsic::mips_fcule_d:
1810  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1811  Op->getOperand(2), ISD::SETULE);
1812  case Intrinsic::mips_fcult_w:
1813  case Intrinsic::mips_fcult_d:
1814  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1815  Op->getOperand(2), ISD::SETULT);
1816  case Intrinsic::mips_fcun_w:
1817  case Intrinsic::mips_fcun_d:
1818  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1819  Op->getOperand(2), ISD::SETUO);
1820  case Intrinsic::mips_fcune_w:
1821  case Intrinsic::mips_fcune_d:
1822  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1823  Op->getOperand(2), ISD::SETUNE);
1824  case Intrinsic::mips_fdiv_w:
1825  case Intrinsic::mips_fdiv_d:
1826  // TODO: If intrinsics have fast-math-flags, propagate them.
1827  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1828  Op->getOperand(2));
1829  case Intrinsic::mips_ffint_u_w:
1830  case Intrinsic::mips_ffint_u_d:
1831  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1832  Op->getOperand(1));
1833  case Intrinsic::mips_ffint_s_w:
1834  case Intrinsic::mips_ffint_s_d:
1835  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1836  Op->getOperand(1));
1837  case Intrinsic::mips_fill_b:
1838  case Intrinsic::mips_fill_h:
1839  case Intrinsic::mips_fill_w:
1840  case Intrinsic::mips_fill_d: {
1841  EVT ResTy = Op->getValueType(0);
1843  Op->getOperand(1));
1844 
1845  // If ResTy is v2i64 then the type legalizer will break this node down into
1846  // an equivalent v4i32.
1847  return DAG.getBuildVector(ResTy, DL, Ops);
1848  }
1849  case Intrinsic::mips_fexp2_w:
1850  case Intrinsic::mips_fexp2_d: {
1851  // TODO: If intrinsics have fast-math-flags, propagate them.
1852  EVT ResTy = Op->getValueType(0);
1853  return DAG.getNode(
1854  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1855  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1856  }
1857  case Intrinsic::mips_flog2_w:
1858  case Intrinsic::mips_flog2_d:
1859  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1860  case Intrinsic::mips_fmadd_w:
1861  case Intrinsic::mips_fmadd_d:
1862  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1863  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1864  case Intrinsic::mips_fmul_w:
1865  case Intrinsic::mips_fmul_d:
1866  // TODO: If intrinsics have fast-math-flags, propagate them.
1867  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1868  Op->getOperand(2));
1869  case Intrinsic::mips_fmsub_w:
1870  case Intrinsic::mips_fmsub_d: {
1871  // TODO: If intrinsics have fast-math-flags, propagate them.
1872  return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
1873  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1874  }
1875  case Intrinsic::mips_frint_w:
1876  case Intrinsic::mips_frint_d:
1877  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1878  case Intrinsic::mips_fsqrt_w:
1879  case Intrinsic::mips_fsqrt_d:
1880  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1881  case Intrinsic::mips_fsub_w:
1882  case Intrinsic::mips_fsub_d:
1883  // TODO: If intrinsics have fast-math-flags, propagate them.
1884  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1885  Op->getOperand(2));
1886  case Intrinsic::mips_ftrunc_u_w:
1887  case Intrinsic::mips_ftrunc_u_d:
1888  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1889  Op->getOperand(1));
1890  case Intrinsic::mips_ftrunc_s_w:
1891  case Intrinsic::mips_ftrunc_s_d:
1892  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1893  Op->getOperand(1));
1894  case Intrinsic::mips_ilvev_b:
1895  case Intrinsic::mips_ilvev_h:
1896  case Intrinsic::mips_ilvev_w:
1897  case Intrinsic::mips_ilvev_d:
1898  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1899  Op->getOperand(1), Op->getOperand(2));
1900  case Intrinsic::mips_ilvl_b:
1901  case Intrinsic::mips_ilvl_h:
1902  case Intrinsic::mips_ilvl_w:
1903  case Intrinsic::mips_ilvl_d:
1904  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1905  Op->getOperand(1), Op->getOperand(2));
1906  case Intrinsic::mips_ilvod_b:
1907  case Intrinsic::mips_ilvod_h:
1908  case Intrinsic::mips_ilvod_w:
1909  case Intrinsic::mips_ilvod_d:
1910  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1911  Op->getOperand(1), Op->getOperand(2));
1912  case Intrinsic::mips_ilvr_b:
1913  case Intrinsic::mips_ilvr_h:
1914  case Intrinsic::mips_ilvr_w:
1915  case Intrinsic::mips_ilvr_d:
1916  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1917  Op->getOperand(1), Op->getOperand(2));
1918  case Intrinsic::mips_insert_b:
1919  case Intrinsic::mips_insert_h:
1920  case Intrinsic::mips_insert_w:
1921  case Intrinsic::mips_insert_d:
1922  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1923  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1924  case Intrinsic::mips_insve_b:
1925  case Intrinsic::mips_insve_h:
1926  case Intrinsic::mips_insve_w:
1927  case Intrinsic::mips_insve_d: {
1928  // Report an error for out of range values.
1929  int64_t Max;
1930  switch (Intrinsic) {
1931  case Intrinsic::mips_insve_b: Max = 15; break;
1932  case Intrinsic::mips_insve_h: Max = 7; break;
1933  case Intrinsic::mips_insve_w: Max = 3; break;
1934  case Intrinsic::mips_insve_d: Max = 1; break;
1935  default: llvm_unreachable("Unmatched intrinsic");
1936  }
1937  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1938  if (Value < 0 || Value > Max)
1939  report_fatal_error("Immediate out of range");
1940  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1941  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1942  DAG.getConstant(0, DL, MVT::i32));
1943  }
1944  case Intrinsic::mips_ldi_b:
1945  case Intrinsic::mips_ldi_h:
1946  case Intrinsic::mips_ldi_w:
1947  case Intrinsic::mips_ldi_d:
1948  return lowerMSASplatImm(Op, 1, DAG, true);
1949  case Intrinsic::mips_lsa:
1950  case Intrinsic::mips_dlsa: {
1951  EVT ResTy = Op->getValueType(0);
1952  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1953  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1954  Op->getOperand(2), Op->getOperand(3)));
1955  }
1956  case Intrinsic::mips_maddv_b:
1957  case Intrinsic::mips_maddv_h:
1958  case Intrinsic::mips_maddv_w:
1959  case Intrinsic::mips_maddv_d: {
1960  EVT ResTy = Op->getValueType(0);
1961  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1962  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1963  Op->getOperand(2), Op->getOperand(3)));
1964  }
1965  case Intrinsic::mips_max_s_b:
1966  case Intrinsic::mips_max_s_h:
1967  case Intrinsic::mips_max_s_w:
1968  case Intrinsic::mips_max_s_d:
1969  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
1970  Op->getOperand(1), Op->getOperand(2));
1971  case Intrinsic::mips_max_u_b:
1972  case Intrinsic::mips_max_u_h:
1973  case Intrinsic::mips_max_u_w:
1974  case Intrinsic::mips_max_u_d:
1975  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
1976  Op->getOperand(1), Op->getOperand(2));
1977  case Intrinsic::mips_maxi_s_b:
1978  case Intrinsic::mips_maxi_s_h:
1979  case Intrinsic::mips_maxi_s_w:
1980  case Intrinsic::mips_maxi_s_d:
1981  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
1982  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
1983  case Intrinsic::mips_maxi_u_b:
1984  case Intrinsic::mips_maxi_u_h:
1985  case Intrinsic::mips_maxi_u_w:
1986  case Intrinsic::mips_maxi_u_d:
1987  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
1988  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1989  case Intrinsic::mips_min_s_b:
1990  case Intrinsic::mips_min_s_h:
1991  case Intrinsic::mips_min_s_w:
1992  case Intrinsic::mips_min_s_d:
1993  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
1994  Op->getOperand(1), Op->getOperand(2));
1995  case Intrinsic::mips_min_u_b:
1996  case Intrinsic::mips_min_u_h:
1997  case Intrinsic::mips_min_u_w:
1998  case Intrinsic::mips_min_u_d:
1999  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2000  Op->getOperand(1), Op->getOperand(2));
2001  case Intrinsic::mips_mini_s_b:
2002  case Intrinsic::mips_mini_s_h:
2003  case Intrinsic::mips_mini_s_w:
2004  case Intrinsic::mips_mini_s_d:
2005  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2006  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2007  case Intrinsic::mips_mini_u_b:
2008  case Intrinsic::mips_mini_u_h:
2009  case Intrinsic::mips_mini_u_w:
2010  case Intrinsic::mips_mini_u_d:
2011  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2012  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2013  case Intrinsic::mips_mod_s_b:
2014  case Intrinsic::mips_mod_s_h:
2015  case Intrinsic::mips_mod_s_w:
2016  case Intrinsic::mips_mod_s_d:
2017  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2018  Op->getOperand(2));
2019  case Intrinsic::mips_mod_u_b:
2020  case Intrinsic::mips_mod_u_h:
2021  case Intrinsic::mips_mod_u_w:
2022  case Intrinsic::mips_mod_u_d:
2023  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2024  Op->getOperand(2));
2025  case Intrinsic::mips_mulv_b:
2026  case Intrinsic::mips_mulv_h:
2027  case Intrinsic::mips_mulv_w:
2028  case Intrinsic::mips_mulv_d:
2029  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2030  Op->getOperand(2));
2031  case Intrinsic::mips_msubv_b:
2032  case Intrinsic::mips_msubv_h:
2033  case Intrinsic::mips_msubv_w:
2034  case Intrinsic::mips_msubv_d: {
2035  EVT ResTy = Op->getValueType(0);
2036  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2037  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2038  Op->getOperand(2), Op->getOperand(3)));
2039  }
2040  case Intrinsic::mips_nlzc_b:
2041  case Intrinsic::mips_nlzc_h:
2042  case Intrinsic::mips_nlzc_w:
2043  case Intrinsic::mips_nlzc_d:
2044  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2045  case Intrinsic::mips_nor_v: {
2046  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2047  Op->getOperand(1), Op->getOperand(2));
2048  return DAG.getNOT(DL, Res, Res->getValueType(0));
2049  }
2050  case Intrinsic::mips_nori_b: {
2051  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2052  Op->getOperand(1),
2053  lowerMSASplatImm(Op, 2, DAG));
2054  return DAG.getNOT(DL, Res, Res->getValueType(0));
2055  }
2056  case Intrinsic::mips_or_v:
2057  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2058  Op->getOperand(2));
2059  case Intrinsic::mips_ori_b:
2060  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2061  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2062  case Intrinsic::mips_pckev_b:
2063  case Intrinsic::mips_pckev_h:
2064  case Intrinsic::mips_pckev_w:
2065  case Intrinsic::mips_pckev_d:
2066  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2067  Op->getOperand(1), Op->getOperand(2));
2068  case Intrinsic::mips_pckod_b:
2069  case Intrinsic::mips_pckod_h:
2070  case Intrinsic::mips_pckod_w:
2071  case Intrinsic::mips_pckod_d:
2072  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2073  Op->getOperand(1), Op->getOperand(2));
2074  case Intrinsic::mips_pcnt_b:
2075  case Intrinsic::mips_pcnt_h:
2076  case Intrinsic::mips_pcnt_w:
2077  case Intrinsic::mips_pcnt_d:
2078  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2079  case Intrinsic::mips_sat_s_b:
2080  case Intrinsic::mips_sat_s_h:
2081  case Intrinsic::mips_sat_s_w:
2082  case Intrinsic::mips_sat_s_d:
2083  case Intrinsic::mips_sat_u_b:
2084  case Intrinsic::mips_sat_u_h:
2085  case Intrinsic::mips_sat_u_w:
2086  case Intrinsic::mips_sat_u_d: {
2087  // Report an error for out of range values.
2088  int64_t Max;
2089  switch (Intrinsic) {
2090  case Intrinsic::mips_sat_s_b:
2091  case Intrinsic::mips_sat_u_b: Max = 7; break;
2092  case Intrinsic::mips_sat_s_h:
2093  case Intrinsic::mips_sat_u_h: Max = 15; break;
2094  case Intrinsic::mips_sat_s_w:
2095  case Intrinsic::mips_sat_u_w: Max = 31; break;
2096  case Intrinsic::mips_sat_s_d:
2097  case Intrinsic::mips_sat_u_d: Max = 63; break;
2098  default: llvm_unreachable("Unmatched intrinsic");
2099  }
2100  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2101  if (Value < 0 || Value > Max)
2102  report_fatal_error("Immediate out of range");
2103  return SDValue();
2104  }
2105  case Intrinsic::mips_shf_b:
2106  case Intrinsic::mips_shf_h:
2107  case Intrinsic::mips_shf_w: {
2108  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2109  if (Value < 0 || Value > 255)
2110  report_fatal_error("Immediate out of range");
2111  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2112  Op->getOperand(2), Op->getOperand(1));
2113  }
2114  case Intrinsic::mips_sldi_b:
2115  case Intrinsic::mips_sldi_h:
2116  case Intrinsic::mips_sldi_w:
2117  case Intrinsic::mips_sldi_d: {
2118  // Report an error for out of range values.
2119  int64_t Max;
2120  switch (Intrinsic) {
2121  case Intrinsic::mips_sldi_b: Max = 15; break;
2122  case Intrinsic::mips_sldi_h: Max = 7; break;
2123  case Intrinsic::mips_sldi_w: Max = 3; break;
2124  case Intrinsic::mips_sldi_d: Max = 1; break;
2125  default: llvm_unreachable("Unmatched intrinsic");
2126  }
2127  int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2128  if (Value < 0 || Value > Max)
2129  report_fatal_error("Immediate out of range");
2130  return SDValue();
2131  }
2132  case Intrinsic::mips_sll_b:
2133  case Intrinsic::mips_sll_h:
2134  case Intrinsic::mips_sll_w:
2135  case Intrinsic::mips_sll_d:
2136  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2137  truncateVecElts(Op, DAG));
2138  case Intrinsic::mips_slli_b:
2139  case Intrinsic::mips_slli_h:
2140  case Intrinsic::mips_slli_w:
2141  case Intrinsic::mips_slli_d:
2142  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2143  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2144  case Intrinsic::mips_splat_b:
2145  case Intrinsic::mips_splat_h:
2146  case Intrinsic::mips_splat_w:
2147  case Intrinsic::mips_splat_d:
2148  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2149  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2150  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2151  // Instead we lower to MipsISD::VSHF and match from there.
2152  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2153  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2154  Op->getOperand(1));
2155  case Intrinsic::mips_splati_b:
2156  case Intrinsic::mips_splati_h:
2157  case Intrinsic::mips_splati_w:
2158  case Intrinsic::mips_splati_d:
2159  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2160  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2161  Op->getOperand(1));
2162  case Intrinsic::mips_sra_b:
2163  case Intrinsic::mips_sra_h:
2164  case Intrinsic::mips_sra_w:
2165  case Intrinsic::mips_sra_d:
2166  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2167  truncateVecElts(Op, DAG));
2168  case Intrinsic::mips_srai_b:
2169  case Intrinsic::mips_srai_h:
2170  case Intrinsic::mips_srai_w:
2171  case Intrinsic::mips_srai_d:
2172  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2173  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2174  case Intrinsic::mips_srari_b:
2175  case Intrinsic::mips_srari_h:
2176  case Intrinsic::mips_srari_w:
2177  case Intrinsic::mips_srari_d: {
2178  // Report an error for out of range values.
2179  int64_t Max;
2180  switch (Intrinsic) {
2181  case Intrinsic::mips_srari_b: Max = 7; break;
2182  case Intrinsic::mips_srari_h: Max = 15; break;
2183  case Intrinsic::mips_srari_w: Max = 31; break;
2184  case Intrinsic::mips_srari_d: Max = 63; break;
2185  default: llvm_unreachable("Unmatched intrinsic");
2186  }
2187  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2188  if (Value < 0 || Value > Max)
2189  report_fatal_error("Immediate out of range");
2190  return SDValue();
2191  }
2192  case Intrinsic::mips_srl_b:
2193  case Intrinsic::mips_srl_h:
2194  case Intrinsic::mips_srl_w:
2195  case Intrinsic::mips_srl_d:
2196  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2197  truncateVecElts(Op, DAG));
2198  case Intrinsic::mips_srli_b:
2199  case Intrinsic::mips_srli_h:
2200  case Intrinsic::mips_srli_w:
2201  case Intrinsic::mips_srli_d:
2202  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2203  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2204  case Intrinsic::mips_srlri_b:
2205  case Intrinsic::mips_srlri_h:
2206  case Intrinsic::mips_srlri_w:
2207  case Intrinsic::mips_srlri_d: {
2208  // Report an error for out of range values.
2209  int64_t Max;
2210  switch (Intrinsic) {
2211  case Intrinsic::mips_srlri_b: Max = 7; break;
2212  case Intrinsic::mips_srlri_h: Max = 15; break;
2213  case Intrinsic::mips_srlri_w: Max = 31; break;
2214  case Intrinsic::mips_srlri_d: Max = 63; break;
2215  default: llvm_unreachable("Unmatched intrinsic");
2216  }
2217  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2218  if (Value < 0 || Value > Max)
2219  report_fatal_error("Immediate out of range");
2220  return SDValue();
2221  }
2222  case Intrinsic::mips_subv_b:
2223  case Intrinsic::mips_subv_h:
2224  case Intrinsic::mips_subv_w:
2225  case Intrinsic::mips_subv_d:
2226  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2227  Op->getOperand(2));
2228  case Intrinsic::mips_subvi_b:
2229  case Intrinsic::mips_subvi_h:
2230  case Intrinsic::mips_subvi_w:
2231  case Intrinsic::mips_subvi_d:
2232  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2233  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2234  case Intrinsic::mips_vshf_b:
2235  case Intrinsic::mips_vshf_h:
2236  case Intrinsic::mips_vshf_w:
2237  case Intrinsic::mips_vshf_d:
2238  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2239  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2240  case Intrinsic::mips_xor_v:
2241  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2242  Op->getOperand(2));
2243  case Intrinsic::mips_xori_b:
2244  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2245  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2246  case Intrinsic::thread_pointer: {
2247  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2248  return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2249  }
2250  }
2251 }
2252 
2254  const MipsSubtarget &Subtarget) {
2255  SDLoc DL(Op);
2256  SDValue ChainIn = Op->getOperand(0);
2257  SDValue Address = Op->getOperand(2);
2258  SDValue Offset = Op->getOperand(3);
2259  EVT ResTy = Op->getValueType(0);
2260  EVT PtrTy = Address->getValueType(0);
2261 
2262  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2263  // however takes an i32 signed constant offset. The actual type of the
2264  // intrinsic is a scaled signed i10.
2265  if (Subtarget.isABI_N64())
2266  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2267 
2268  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2269  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2270  /* Alignment = */ 16);
2271 }
2272 
2273 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2274  SelectionDAG &DAG) const {
2275  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2276  switch (Intr) {
2277  default:
2278  return SDValue();
2279  case Intrinsic::mips_extp:
2280  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2281  case Intrinsic::mips_extpdp:
2282  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2283  case Intrinsic::mips_extr_w:
2284  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2285  case Intrinsic::mips_extr_r_w:
2286  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2287  case Intrinsic::mips_extr_rs_w:
2288  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2289  case Intrinsic::mips_extr_s_h:
2290  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2291  case Intrinsic::mips_mthlip:
2292  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2293  case Intrinsic::mips_mulsaq_s_w_ph:
2294  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2295  case Intrinsic::mips_maq_s_w_phl:
2296  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2297  case Intrinsic::mips_maq_s_w_phr:
2298  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2299  case Intrinsic::mips_maq_sa_w_phl:
2300  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2301  case Intrinsic::mips_maq_sa_w_phr:
2302  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2303  case Intrinsic::mips_dpaq_s_w_ph:
2304  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2305  case Intrinsic::mips_dpsq_s_w_ph:
2306  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2307  case Intrinsic::mips_dpaq_sa_l_w:
2308  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2309  case Intrinsic::mips_dpsq_sa_l_w:
2310  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2311  case Intrinsic::mips_dpaqx_s_w_ph:
2312  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2313  case Intrinsic::mips_dpaqx_sa_w_ph:
2314  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2315  case Intrinsic::mips_dpsqx_s_w_ph:
2316  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2317  case Intrinsic::mips_dpsqx_sa_w_ph:
2318  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2319  case Intrinsic::mips_ld_b:
2320  case Intrinsic::mips_ld_h:
2321  case Intrinsic::mips_ld_w:
2322  case Intrinsic::mips_ld_d:
2323  return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2324  }
2325 }
2326 
2328  const MipsSubtarget &Subtarget) {
2329  SDLoc DL(Op);
2330  SDValue ChainIn = Op->getOperand(0);
2331  SDValue Value = Op->getOperand(2);
2332  SDValue Address = Op->getOperand(3);
2333  SDValue Offset = Op->getOperand(4);
2334  EVT PtrTy = Address->getValueType(0);
2335 
2336  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2337  // however takes an i32 signed constant offset. The actual type of the
2338  // intrinsic is a scaled signed i10.
2339  if (Subtarget.isABI_N64())
2340  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2341 
2342  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2343 
2344  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2345  /* Alignment = */ 16);
2346 }
2347 
2348 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2349  SelectionDAG &DAG) const {
2350  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2351  switch (Intr) {
2352  default:
2353  return SDValue();
2354  case Intrinsic::mips_st_b:
2355  case Intrinsic::mips_st_h:
2356  case Intrinsic::mips_st_w:
2357  case Intrinsic::mips_st_d:
2358  return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2359  }
2360 }
2361 
2362 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2363 //
2364 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2365 // choose to sign-extend but we could have equally chosen zero-extend. The
2366 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2367 // result into this node later (possibly changing it to a zero-extend in the
2368 // process).
2369 SDValue MipsSETargetLowering::
2370 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2371  SDLoc DL(Op);
2372  EVT ResTy = Op->getValueType(0);
2373  SDValue Op0 = Op->getOperand(0);
2374  EVT VecTy = Op0->getValueType(0);
2375 
2376  if (!VecTy.is128BitVector())
2377  return SDValue();
2378 
2379  if (ResTy.isInteger()) {
2380  SDValue Op1 = Op->getOperand(1);
2381  EVT EltTy = VecTy.getVectorElementType();
2382  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2383  DAG.getValueType(EltTy));
2384  }
2385 
2386  return Op;
2387 }
2388 
2389 static bool isConstantOrUndef(const SDValue Op) {
2390  if (Op->isUndef())
2391  return true;
2392  if (isa<ConstantSDNode>(Op))
2393  return true;
2394  if (isa<ConstantFPSDNode>(Op))
2395  return true;
2396  return false;
2397 }
2398 
2400  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2401  if (isConstantOrUndef(Op->getOperand(i)))
2402  return true;
2403  return false;
2404 }
2405 
2406 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2407 // backend.
2408 //
2409 // Lowers according to the following rules:
2410 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2411 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2412 // immediate
2413 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2414 // is a power of 2 less than or equal to 64 and the value does not fit into a
2415 // signed 10-bit immediate
2416 // - Non-constant splats are legal as-is.
2417 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2418 // - All others are illegal and must be expanded.
2419 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2420  SelectionDAG &DAG) const {
2421  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2422  EVT ResTy = Op->getValueType(0);
2423  SDLoc DL(Op);
2424  APInt SplatValue, SplatUndef;
2425  unsigned SplatBitSize;
2426  bool HasAnyUndefs;
2427 
2428  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2429  return SDValue();
2430 
2431  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2432  HasAnyUndefs, 8,
2433  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2434  // We can only cope with 8, 16, 32, or 64-bit elements
2435  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2436  SplatBitSize != 64)
2437  return SDValue();
2438 
2439  // If the value isn't an integer type we will have to bitcast
2440  // from an integer type first. Also, if there are any undefs, we must
2441  // lower them to defined values first.
2442  if (ResTy.isInteger() && !HasAnyUndefs)
2443  return Op;
2444 
2445  EVT ViaVecTy;
2446 
2447  switch (SplatBitSize) {
2448  default:
2449  return SDValue();
2450  case 8:
2451  ViaVecTy = MVT::v16i8;
2452  break;
2453  case 16:
2454  ViaVecTy = MVT::v8i16;
2455  break;
2456  case 32:
2457  ViaVecTy = MVT::v4i32;
2458  break;
2459  case 64:
2460  // There's no fill.d to fall back on for 64-bit values
2461  return SDValue();
2462  }
2463 
2464  // SelectionDAG::getConstant will promote SplatValue appropriately.
2465  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2466 
2467  // Bitcast to the type we originally wanted
2468  if (ViaVecTy != ResTy)
2469  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2470 
2471  return Result;
2472  } else if (DAG.isSplatValue(Op, /* AllowUndefs */ false))
2473  return Op;
2474  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2475  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2476  // The resulting code is the same length as the expansion, but it doesn't
2477  // use memory operations
2478  EVT ResTy = Node->getValueType(0);
2479 
2480  assert(ResTy.isVector());
2481 
2482  unsigned NumElts = ResTy.getVectorNumElements();
2483  SDValue Vector = DAG.getUNDEF(ResTy);
2484  for (unsigned i = 0; i < NumElts; ++i) {
2485  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2486  Node->getOperand(i),
2487  DAG.getConstant(i, DL, MVT::i32));
2488  }
2489  return Vector;
2490  }
2491 
2492  return SDValue();
2493 }
2494 
2495 // Lower VECTOR_SHUFFLE into SHF (if possible).
2496 //
2497 // SHF splits the vector into blocks of four elements, then shuffles these
2498 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2499 //
2500 // It is therefore possible to lower into SHF when the mask takes the form:
2501 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2502 // When undef's appear they are treated as if they were whatever value is
2503 // necessary in order to fit the above forms.
2504 //
2505 // For example:
2506 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2507 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2508 // i32 7, i32 6, i32 5, i32 4>
2509 // is lowered to:
2510 // (SHF_H $w0, $w1, 27)
2511 // where the 27 comes from:
2512 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2514  SmallVector<int, 16> Indices,
2515  SelectionDAG &DAG) {
2516  int SHFIndices[4] = { -1, -1, -1, -1 };
2517 
2518  if (Indices.size() < 4)
2519  return SDValue();
2520 
2521  for (unsigned i = 0; i < 4; ++i) {
2522  for (unsigned j = i; j < Indices.size(); j += 4) {
2523  int Idx = Indices[j];
2524 
2525  // Convert from vector index to 4-element subvector index
2526  // If an index refers to an element outside of the subvector then give up
2527  if (Idx != -1) {
2528  Idx -= 4 * (j / 4);
2529  if (Idx < 0 || Idx >= 4)
2530  return SDValue();
2531  }
2532 
2533  // If the mask has an undef, replace it with the current index.
2534  // Note that it might still be undef if the current index is also undef
2535  if (SHFIndices[i] == -1)
2536  SHFIndices[i] = Idx;
2537 
2538  // Check that non-undef values are the same as in the mask. If they
2539  // aren't then give up
2540  if (!(Idx == -1 || Idx == SHFIndices[i]))
2541  return SDValue();
2542  }
2543  }
2544 
2545  // Calculate the immediate. Replace any remaining undefs with zero
2546  APInt Imm(32, 0);
2547  for (int i = 3; i >= 0; --i) {
2548  int Idx = SHFIndices[i];
2549 
2550  if (Idx == -1)
2551  Idx = 0;
2552 
2553  Imm <<= 2;
2554  Imm |= Idx & 0x3;
2555  }
2556 
2557  SDLoc DL(Op);
2558  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2559  DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2560 }
2561 
2562 /// Determine whether a range fits a regular pattern of values.
2563 /// This function accounts for the possibility of jumping over the End iterator.
2564 template <typename ValType>
2565 static bool
2567  unsigned CheckStride,
2569  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2570  auto &I = Begin;
2571 
2572  while (I != End) {
2573  if (*I != -1 && *I != ExpectedIndex)
2574  return false;
2575  ExpectedIndex += ExpectedIndexStride;
2576 
2577  // Incrementing past End is undefined behaviour so we must increment one
2578  // step at a time and check for End at each step.
2579  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2580  ; // Empty loop body.
2581  }
2582  return true;
2583 }
2584 
2585 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2586 //
2587 // It is a SPLATI when the mask is:
2588 // <x, x, x, ...>
2589 // where x is any valid index.
2590 //
2591 // When undef's appear in the mask they are treated as if they were whatever
2592 // value is necessary in order to fit the above form.
2593 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2594  SmallVector<int, 16> Indices,
2595  SelectionDAG &DAG) {
2596  assert((Indices.size() % 2) == 0);
2597 
2598  int SplatIndex = -1;
2599  for (const auto &V : Indices) {
2600  if (V != -1) {
2601  SplatIndex = V;
2602  break;
2603  }
2604  }
2605 
2606  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2607  0);
2608 }
2609 
2610 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2611 //
2612 // ILVEV interleaves the even elements from each vector.
2613 //
2614 // It is possible to lower into ILVEV when the mask consists of two of the
2615 // following forms interleaved:
2616 // <0, 2, 4, ...>
2617 // <n, n+2, n+4, ...>
2618 // where n is the number of elements in the vector.
2619 // For example:
2620 // <0, 0, 2, 2, 4, 4, ...>
2621 // <0, n, 2, n+2, 4, n+4, ...>
2622 //
2623 // When undef's appear in the mask they are treated as if they were whatever
2624 // value is necessary in order to fit the above forms.
2626  SmallVector<int, 16> Indices,
2627  SelectionDAG &DAG) {
2628  assert((Indices.size() % 2) == 0);
2629 
2630  SDValue Wt;
2631  SDValue Ws;
2632  const auto &Begin = Indices.begin();
2633  const auto &End = Indices.end();
2634 
2635  // Check even elements are taken from the even elements of one half or the
2636  // other and pick an operand accordingly.
2637  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2638  Wt = Op->getOperand(0);
2639  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2640  Wt = Op->getOperand(1);
2641  else
2642  return SDValue();
2643 
2644  // Check odd elements are taken from the even elements of one half or the
2645  // other and pick an operand accordingly.
2646  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2647  Ws = Op->getOperand(0);
2648  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2649  Ws = Op->getOperand(1);
2650  else
2651  return SDValue();
2652 
2653  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2654 }
2655 
2656 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2657 //
2658 // ILVOD interleaves the odd elements from each vector.
2659 //
2660 // It is possible to lower into ILVOD when the mask consists of two of the
2661 // following forms interleaved:
2662 // <1, 3, 5, ...>
2663 // <n+1, n+3, n+5, ...>
2664 // where n is the number of elements in the vector.
2665 // For example:
2666 // <1, 1, 3, 3, 5, 5, ...>
2667 // <1, n+1, 3, n+3, 5, n+5, ...>
2668 //
2669 // When undef's appear in the mask they are treated as if they were whatever
2670 // value is necessary in order to fit the above forms.
2672  SmallVector<int, 16> Indices,
2673  SelectionDAG &DAG) {
2674  assert((Indices.size() % 2) == 0);
2675 
2676  SDValue Wt;
2677  SDValue Ws;
2678  const auto &Begin = Indices.begin();
2679  const auto &End = Indices.end();
2680 
2681  // Check even elements are taken from the odd elements of one half or the
2682  // other and pick an operand accordingly.
2683  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2684  Wt = Op->getOperand(0);
2685  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2686  Wt = Op->getOperand(1);
2687  else
2688  return SDValue();
2689 
2690  // Check odd elements are taken from the odd elements of one half or the
2691  // other and pick an operand accordingly.
2692  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2693  Ws = Op->getOperand(0);
2694  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2695  Ws = Op->getOperand(1);
2696  else
2697  return SDValue();
2698 
2699  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2700 }
2701 
2702 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2703 //
2704 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2705 // each vector.
2706 //
2707 // It is possible to lower into ILVR when the mask consists of two of the
2708 // following forms interleaved:
2709 // <0, 1, 2, ...>
2710 // <n, n+1, n+2, ...>
2711 // where n is the number of elements in the vector.
2712 // For example:
2713 // <0, 0, 1, 1, 2, 2, ...>
2714 // <0, n, 1, n+1, 2, n+2, ...>
2715 //
2716 // When undef's appear in the mask they are treated as if they were whatever
2717 // value is necessary in order to fit the above forms.
2719  SmallVector<int, 16> Indices,
2720  SelectionDAG &DAG) {
2721  assert((Indices.size() % 2) == 0);
2722 
2723  SDValue Wt;
2724  SDValue Ws;
2725  const auto &Begin = Indices.begin();
2726  const auto &End = Indices.end();
2727 
2728  // Check even elements are taken from the right (lowest-indexed) elements of
2729  // one half or the other and pick an operand accordingly.
2730  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2731  Wt = Op->getOperand(0);
2732  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2733  Wt = Op->getOperand(1);
2734  else
2735  return SDValue();
2736 
2737  // Check odd elements are taken from the right (lowest-indexed) elements of
2738  // one half or the other and pick an operand accordingly.
2739  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2740  Ws = Op->getOperand(0);
2741  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2742  Ws = Op->getOperand(1);
2743  else
2744  return SDValue();
2745 
2746  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2747 }
2748 
2749 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2750 //
2751 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2752 // of each vector.
2753 //
2754 // It is possible to lower into ILVL when the mask consists of two of the
2755 // following forms interleaved:
2756 // <x, x+1, x+2, ...>
2757 // <n+x, n+x+1, n+x+2, ...>
2758 // where n is the number of elements in the vector and x is half n.
2759 // For example:
2760 // <x, x, x+1, x+1, x+2, x+2, ...>
2761 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2762 //
2763 // When undef's appear in the mask they are treated as if they were whatever
2764 // value is necessary in order to fit the above forms.
2766  SmallVector<int, 16> Indices,
2767  SelectionDAG &DAG) {
2768  assert((Indices.size() % 2) == 0);
2769 
2770  unsigned HalfSize = Indices.size() / 2;
2771  SDValue Wt;
2772  SDValue Ws;
2773  const auto &Begin = Indices.begin();
2774  const auto &End = Indices.end();
2775 
2776  // Check even elements are taken from the left (highest-indexed) elements of
2777  // one half or the other and pick an operand accordingly.
2778  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2779  Wt = Op->getOperand(0);
2780  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2781  Wt = Op->getOperand(1);
2782  else
2783  return SDValue();
2784 
2785  // Check odd elements are taken from the left (highest-indexed) elements of
2786  // one half or the other and pick an operand accordingly.
2787  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2788  Ws = Op->getOperand(0);
2789  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2790  1))
2791  Ws = Op->getOperand(1);
2792  else
2793  return SDValue();
2794 
2795  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2796 }
2797 
2798 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2799 //
2800 // PCKEV copies the even elements of each vector into the result vector.
2801 //
2802 // It is possible to lower into PCKEV when the mask consists of two of the
2803 // following forms concatenated:
2804 // <0, 2, 4, ...>
2805 // <n, n+2, n+4, ...>
2806 // where n is the number of elements in the vector.
2807 // For example:
2808 // <0, 2, 4, ..., 0, 2, 4, ...>
2809 // <0, 2, 4, ..., n, n+2, n+4, ...>
2810 //
2811 // When undef's appear in the mask they are treated as if they were whatever
2812 // value is necessary in order to fit the above forms.
2814  SmallVector<int, 16> Indices,
2815  SelectionDAG &DAG) {
2816  assert((Indices.size() % 2) == 0);
2817 
2818  SDValue Wt;
2819  SDValue Ws;
2820  const auto &Begin = Indices.begin();
2821  const auto &Mid = Indices.begin() + Indices.size() / 2;
2822  const auto &End = Indices.end();
2823 
2824  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2825  Wt = Op->getOperand(0);
2826  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2827  Wt = Op->getOperand(1);
2828  else
2829  return SDValue();
2830 
2831  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2832  Ws = Op->getOperand(0);
2833  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2834  Ws = Op->getOperand(1);
2835  else
2836  return SDValue();
2837 
2838  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2839 }
2840 
2841 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2842 //
2843 // PCKOD copies the odd elements of each vector into the result vector.
2844 //
2845 // It is possible to lower into PCKOD when the mask consists of two of the
2846 // following forms concatenated:
2847 // <1, 3, 5, ...>
2848 // <n+1, n+3, n+5, ...>
2849 // where n is the number of elements in the vector.
2850 // For example:
2851 // <1, 3, 5, ..., 1, 3, 5, ...>
2852 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2853 //
2854 // When undef's appear in the mask they are treated as if they were whatever
2855 // value is necessary in order to fit the above forms.
2857  SmallVector<int, 16> Indices,
2858  SelectionDAG &DAG) {
2859  assert((Indices.size() % 2) == 0);
2860 
2861  SDValue Wt;
2862  SDValue Ws;
2863  const auto &Begin = Indices.begin();
2864  const auto &Mid = Indices.begin() + Indices.size() / 2;
2865  const auto &End = Indices.end();
2866 
2867  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2868  Wt = Op->getOperand(0);
2869  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2870  Wt = Op->getOperand(1);
2871  else
2872  return SDValue();
2873 
2874  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2875  Ws = Op->getOperand(0);
2876  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2877  Ws = Op->getOperand(1);
2878  else
2879  return SDValue();
2880 
2881  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2882 }
2883 
2884 // Lower VECTOR_SHUFFLE into VSHF.
2885 //
2886 // This mostly consists of converting the shuffle indices in Indices into a
2887 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2888 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2889 // if the type is v8i16 and all the indices are less than 8 then the second
2890 // operand is unused and can be replaced with anything. We choose to replace it
2891 // with the used operand since this reduces the number of instructions overall.
2893  SmallVector<int, 16> Indices,
2894  SelectionDAG &DAG) {
2896  SDValue Op0;
2897  SDValue Op1;
2898  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2899  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2900  bool Using1stVec = false;
2901  bool Using2ndVec = false;
2902  SDLoc DL(Op);
2903  int ResTyNumElts = ResTy.getVectorNumElements();
2904 
2905  for (int i = 0; i < ResTyNumElts; ++i) {
2906  // Idx == -1 means UNDEF
2907  int Idx = Indices[i];
2908 
2909  if (0 <= Idx && Idx < ResTyNumElts)
2910  Using1stVec = true;
2911  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2912  Using2ndVec = true;
2913  }
2914 
2915  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2916  ++I)
2917  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2918 
2919  SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2920 
2921  if (Using1stVec && Using2ndVec) {
2922  Op0 = Op->getOperand(0);
2923  Op1 = Op->getOperand(1);
2924  } else if (Using1stVec)
2925  Op0 = Op1 = Op->getOperand(0);
2926  else if (Using2ndVec)
2927  Op0 = Op1 = Op->getOperand(1);
2928  else
2929  llvm_unreachable("shuffle vector mask references neither vector operand?");
2930 
2931  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2932  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2933  // VSHF concatenates the vectors in a bitwise fashion:
2934  // <0b00, 0b01> + <0b10, 0b11> ->
2935  // 0b0100 + 0b1110 -> 0b01001110
2936  // <0b10, 0b11, 0b00, 0b01>
2937  // We must therefore swap the operands to get the correct result.
2938  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2939 }
2940 
2941 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2942 // indices in the shuffle.
2943 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2944  SelectionDAG &DAG) const {
2945  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2946  EVT ResTy = Op->getValueType(0);
2947 
2948  if (!ResTy.is128BitVector())
2949  return SDValue();
2950 
2951  int ResTyNumElts = ResTy.getVectorNumElements();
2952  SmallVector<int, 16> Indices;
2953 
2954  for (int i = 0; i < ResTyNumElts; ++i)
2955  Indices.push_back(Node->getMaskElt(i));
2956 
2957  // splati.[bhwd] is preferable to the others but is matched from
2958  // MipsISD::VSHF.
2959  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2960  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2961  SDValue Result;
2962  if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
2963  return Result;
2964  if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
2965  return Result;
2966  if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
2967  return Result;
2968  if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
2969  return Result;
2970  if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
2971  return Result;
2972  if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
2973  return Result;
2974  if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
2975  return Result;
2976  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2977 }
2978 
2980 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
2981  MachineBasicBlock *BB) const {
2982  // $bb:
2983  // bposge32_pseudo $vr0
2984  // =>
2985  // $bb:
2986  // bposge32 $tbb
2987  // $fbb:
2988  // li $vr2, 0
2989  // b $sink
2990  // $tbb:
2991  // li $vr1, 1
2992  // $sink:
2993  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2994 
2995  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2997  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2998  DebugLoc DL = MI.getDebugLoc();
2999  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3001  MachineFunction *F = BB->getParent();
3002  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3003  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3005  F->insert(It, FBB);
3006  F->insert(It, TBB);
3007  F->insert(It, Sink);
3008 
3009  // Transfer the remainder of BB and its successor edges to Sink.
3010  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3011  BB->end());
3013 
3014  // Add successors.
3015  BB->addSuccessor(FBB);
3016  BB->addSuccessor(TBB);
3017  FBB->addSuccessor(Sink);
3018  TBB->addSuccessor(Sink);
3019 
3020  // Insert the real bposge32 instruction to $BB.
3021  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3022  // Insert the real bposge32c instruction to $BB.
3023  BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3024 
3025  // Fill $FBB.
3026  unsigned VR2 = RegInfo.createVirtualRegister(RC);
3027  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3028  .addReg(Mips::ZERO).addImm(0);
3029  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3030 
3031  // Fill $TBB.
3032  unsigned VR1 = RegInfo.createVirtualRegister(RC);
3033  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3034  .addReg(Mips::ZERO).addImm(1);
3035 
3036  // Insert phi function to $Sink.
3037  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3038  MI.getOperand(0).getReg())
3039  .addReg(VR2)
3040  .addMBB(FBB)
3041  .addReg(VR1)
3042  .addMBB(TBB);
3043 
3044  MI.eraseFromParent(); // The pseudo instruction is gone now.
3045  return Sink;
3046 }
3047 
3048 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3049  MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3050  // $bb:
3051  // vany_nonzero $rd, $ws
3052  // =>
3053  // $bb:
3054  // bnz.b $ws, $tbb
3055  // b $fbb
3056  // $fbb:
3057  // li $rd1, 0
3058  // b $sink
3059  // $tbb:
3060  // li $rd2, 1
3061  // $sink:
3062  // $rd = phi($rd1, $fbb, $rd2, $tbb)
3063 
3064  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3066  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3067  DebugLoc DL = MI.getDebugLoc();
3068  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3070  MachineFunction *F = BB->getParent();
3071  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3072  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3074  F->insert(It, FBB);
3075  F->insert(It, TBB);
3076  F->insert(It, Sink);
3077 
3078  // Transfer the remainder of BB and its successor edges to Sink.
3079  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3080  BB->end());
3082 
3083  // Add successors.
3084  BB->addSuccessor(FBB);
3085  BB->addSuccessor(TBB);
3086  FBB->addSuccessor(Sink);
3087  TBB->addSuccessor(Sink);
3088 
3089  // Insert the real bnz.b instruction to $BB.
3090  BuildMI(BB, DL, TII->get(BranchOp))
3091  .addReg(MI.getOperand(1).getReg())
3092  .addMBB(TBB);
3093 
3094  // Fill $FBB.
3095  unsigned RD1 = RegInfo.createVirtualRegister(RC);
3096  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3097  .addReg(Mips::ZERO).addImm(0);
3098  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3099 
3100  // Fill $TBB.
3101  unsigned RD2 = RegInfo.createVirtualRegister(RC);
3102  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3103  .addReg(Mips::ZERO).addImm(1);
3104 
3105  // Insert phi function to $Sink.
3106  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3107  MI.getOperand(0).getReg())
3108  .addReg(RD1)
3109  .addMBB(FBB)
3110  .addReg(RD2)
3111  .addMBB(TBB);
3112 
3113  MI.eraseFromParent(); // The pseudo instruction is gone now.
3114  return Sink;
3115 }
3116 
3117 // Emit the COPY_FW pseudo instruction.
3118 //
3119 // copy_fw_pseudo $fd, $ws, n
3120 // =>
3121 // copy_u_w $rt, $ws, $n
3122 // mtc1 $rt, $fd
3123 //
3124 // When n is zero, the equivalent operation can be performed with (potentially)
3125 // zero instructions due to register overlaps. This optimization is never valid
3126 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3128 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3129  MachineBasicBlock *BB) const {
3131  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3132  DebugLoc DL = MI.getDebugLoc();
3133  unsigned Fd = MI.getOperand(0).getReg();
3134  unsigned Ws = MI.getOperand(1).getReg();
3135  unsigned Lane = MI.getOperand(2).getImm();
3136 
3137  if (Lane == 0) {
3138  unsigned Wt = Ws;
3139  if (!Subtarget.useOddSPReg()) {
3140  // We must copy to an even-numbered MSA register so that the
3141  // single-precision sub-register is also guaranteed to be even-numbered.
3142  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3143 
3144  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3145  }
3146 
3147  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3148  } else {
3149  unsigned Wt = RegInfo.createVirtualRegister(
3150  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3151  &Mips::MSA128WEvensRegClass);
3152 
3153  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3154  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3155  }
3156 
3157  MI.eraseFromParent(); // The pseudo instruction is gone now.
3158  return BB;
3159 }
3160 
3161 // Emit the COPY_FD pseudo instruction.
3162 //
3163 // copy_fd_pseudo $fd, $ws, n
3164 // =>
3165 // splati.d $wt, $ws, $n
3166 // copy $fd, $wt:sub_64
3167 //
3168 // When n is zero, the equivalent operation can be performed with (potentially)
3169 // zero instructions due to register overlaps. This optimization is always
3170 // valid because FR=1 mode which is the only supported mode in MSA.
3172 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3173  MachineBasicBlock *BB) const {
3175 
3177  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3178  unsigned Fd = MI.getOperand(0).getReg();
3179  unsigned Ws = MI.getOperand(1).getReg();
3180  unsigned Lane = MI.getOperand(2).getImm() * 2;
3181  DebugLoc DL = MI.getDebugLoc();
3182 
3183  if (Lane == 0)
3184  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3185  else {
3186  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3187 
3188  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3189  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3190  }
3191 
3192  MI.eraseFromParent(); // The pseudo instruction is gone now.
3193  return BB;
3194 }
3195 
3196 // Emit the INSERT_FW pseudo instruction.
3197 //
3198 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3199 // =>
3200 // subreg_to_reg $wt:sub_lo, $fs
3201 // insve_w $wd[$n], $wd_in, $wt[0]
3203 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3204  MachineBasicBlock *BB) const {
3206  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3207  DebugLoc DL = MI.getDebugLoc();
3208  unsigned Wd = MI.getOperand(0).getReg();
3209  unsigned Wd_in = MI.getOperand(1).getReg();
3210  unsigned Lane = MI.getOperand(2).getImm();
3211  unsigned Fs = MI.getOperand(3).getReg();
3212  unsigned Wt = RegInfo.createVirtualRegister(
3213  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3214  &Mips::MSA128WEvensRegClass);
3215 
3216  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3217  .addImm(0)
3218  .addReg(Fs)
3219  .addImm(Mips::sub_lo);
3220  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3221  .addReg(Wd_in)
3222  .addImm(Lane)
3223  .addReg(Wt)
3224  .addImm(0);
3225 
3226  MI.eraseFromParent(); // The pseudo instruction is gone now.
3227  return BB;
3228 }
3229 
3230 // Emit the INSERT_FD pseudo instruction.
3231 //
3232 // insert_fd_pseudo $wd, $fs, n
3233 // =>
3234 // subreg_to_reg $wt:sub_64, $fs
3235 // insve_d $wd[$n], $wd_in, $wt[0]
3237 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3238  MachineBasicBlock *BB) const {
3240 
3242  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3243  DebugLoc DL = MI.getDebugLoc();
3244  unsigned Wd = MI.getOperand(0).getReg();
3245  unsigned Wd_in = MI.getOperand(1).getReg();
3246  unsigned Lane = MI.getOperand(2).getImm();
3247  unsigned Fs = MI.getOperand(3).getReg();
3248  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3249 
3250  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3251  .addImm(0)
3252  .addReg(Fs)
3253  .addImm(Mips::sub_64);
3254  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3255  .addReg(Wd_in)
3256  .addImm(Lane)
3257  .addReg(Wt)
3258  .addImm(0);
3259 
3260  MI.eraseFromParent(); // The pseudo instruction is gone now.
3261  return BB;
3262 }
3263 
3264 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3265 //
3266 // For integer:
3267 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3268 // =>
3269 // (SLL $lanetmp1, $lane, <log2size)
3270 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3271 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3272 // (NEG $lanetmp2, $lanetmp1)
3273 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3274 //
3275 // For floating point:
3276 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3277 // =>
3278 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3279 // (SLL $lanetmp1, $lane, <log2size)
3280 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3281 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3282 // (NEG $lanetmp2, $lanetmp1)
3283 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3284 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3285  MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3286  bool IsFP) const {
3288  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3289  DebugLoc DL = MI.getDebugLoc();
3290  unsigned Wd = MI.getOperand(0).getReg();
3291  unsigned SrcVecReg = MI.getOperand(1).getReg();
3292  unsigned LaneReg = MI.getOperand(2).getReg();
3293  unsigned SrcValReg = MI.getOperand(3).getReg();
3294 
3295  const TargetRegisterClass *VecRC = nullptr;
3296  // FIXME: This should be true for N32 too.
3297  const TargetRegisterClass *GPRRC =
3298  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3299  unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3300  unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3301  unsigned EltLog2Size;
3302  unsigned InsertOp = 0;
3303  unsigned InsveOp = 0;
3304  switch (EltSizeInBytes) {
3305  default:
3306  llvm_unreachable("Unexpected size");
3307  case 1:
3308  EltLog2Size = 0;
3309  InsertOp = Mips::INSERT_B;
3310  InsveOp = Mips::INSVE_B;
3311  VecRC = &Mips::MSA128BRegClass;
3312  break;
3313  case 2:
3314  EltLog2Size = 1;
3315  InsertOp = Mips::INSERT_H;
3316  InsveOp = Mips::INSVE_H;
3317  VecRC = &Mips::MSA128HRegClass;
3318  break;
3319  case 4:
3320  EltLog2Size = 2;
3321  InsertOp = Mips::INSERT_W;
3322  InsveOp = Mips::INSVE_W;
3323  VecRC = &Mips::MSA128WRegClass;
3324  break;
3325  case 8:
3326  EltLog2Size = 3;
3327  InsertOp = Mips::INSERT_D;
3328  InsveOp = Mips::INSVE_D;
3329  VecRC = &Mips::MSA128DRegClass;
3330  break;
3331  }
3332 
3333  if (IsFP) {
3334  unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3335  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3336  .addImm(0)
3337  .addReg(SrcValReg)
3338  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3339  SrcValReg = Wt;
3340  }
3341 
3342  // Convert the lane index into a byte index
3343  if (EltSizeInBytes != 1) {
3344  unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3345  BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3346  .addReg(LaneReg)
3347  .addImm(EltLog2Size);
3348  LaneReg = LaneTmp1;
3349  }
3350 
3351  // Rotate bytes around so that the desired lane is element zero
3352  unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3353  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3354  .addReg(SrcVecReg)
3355  .addReg(SrcVecReg)
3356  .addReg(LaneReg, 0, SubRegIdx);
3357 
3358  unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3359  if (IsFP) {
3360  // Use insve.df to insert to element zero
3361  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3362  .addReg(WdTmp1)
3363  .addImm(0)
3364  .addReg(SrcValReg)
3365  .addImm(0);
3366  } else {
3367  // Use insert.df to insert to element zero
3368  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3369  .addReg(WdTmp1)
3370  .addReg(SrcValReg)
3371  .addImm(0);
3372  }
3373 
3374  // Rotate elements the rest of the way for a full rotation.
3375  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3376  // the lane index to do this.
3377  unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3378  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3379  LaneTmp2)
3380  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3381  .addReg(LaneReg);
3382  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3383  .addReg(WdTmp2)
3384  .addReg(WdTmp2)
3385  .addReg(LaneTmp2, 0, SubRegIdx);
3386 
3387  MI.eraseFromParent(); // The pseudo instruction is gone now.
3388  return BB;
3389 }
3390 
3391 // Emit the FILL_FW pseudo instruction.
3392 //
3393 // fill_fw_pseudo $wd, $fs
3394 // =>
3395 // implicit_def $wt1
3396 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3397 // splati.w $wd, $wt2[0]
3399 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3400  MachineBasicBlock *BB) const {
3402  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3403  DebugLoc DL = MI.getDebugLoc();
3404  unsigned Wd = MI.getOperand(0).getReg();
3405  unsigned Fs = MI.getOperand(1).getReg();
3406  unsigned Wt1 = RegInfo.createVirtualRegister(
3407  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3408  : &Mips::MSA128WEvensRegClass);
3409  unsigned Wt2 = RegInfo.createVirtualRegister(
3410  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3411  : &Mips::MSA128WEvensRegClass);
3412 
3413  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3414  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3415  .addReg(Wt1)
3416  .addReg(Fs)
3417  .addImm(Mips::sub_lo);
3418  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3419 
3420  MI.eraseFromParent(); // The pseudo instruction is gone now.
3421  return BB;
3422 }
3423 
3424 // Emit the FILL_FD pseudo instruction.
3425 //
3426 // fill_fd_pseudo $wd, $fs
3427 // =>
3428 // implicit_def $wt1
3429 // insert_subreg $wt2:subreg_64, $wt1, $fs
3430 // splati.d $wd, $wt2[0]
3432 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3433  MachineBasicBlock *BB) const {
3435 
3437  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3438  DebugLoc DL = MI.getDebugLoc();
3439  unsigned Wd = MI.getOperand(0).getReg();
3440  unsigned Fs = MI.getOperand(1).getReg();
3441  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3442  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3443 
3444  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3445  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3446  .addReg(Wt1)
3447  .addReg(Fs)
3448  .addImm(Mips::sub_64);
3449  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3450 
3451  MI.eraseFromParent(); // The pseudo instruction is gone now.
3452  return BB;
3453 }
3454 
3455 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3456 // register.
3457 //
3458 // STF16 MSA128F16:$wd, mem_simm10:$addr
3459 // =>
3460 // copy_u.h $rtemp,$wd[0]
3461 // sh $rtemp, $addr
3462 //
3463 // Safety: We can't use st.h & co as they would over write the memory after
3464 // the destination. It would require half floats be allocated 16 bytes(!) of
3465 // space.
3467 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3468  MachineBasicBlock *BB) const {
3469 
3471  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3472  DebugLoc DL = MI.getDebugLoc();
3473  unsigned Ws = MI.getOperand(0).getReg();
3474  unsigned Rt = MI.getOperand(1).getReg();
3475  const MachineMemOperand &MMO = **MI.memoperands_begin();
3476  unsigned Imm = MMO.getOffset();
3477 
3478  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3479  // spill and reload can expand as a GPR64 operand. Examine the
3480  // operand in detail and default to ABI.
3481  const TargetRegisterClass *RC =
3482  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3483  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3484  : &Mips::GPR64RegClass);
3485  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3486  unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3487 
3488  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3489  if(!UsingMips32) {
3490  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3491  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3492  .addImm(0)
3493  .addReg(Rs)
3494  .addImm(Mips::sub_32);
3495  Rs = Tmp;
3496  }
3497  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3498  .addReg(Rs)
3499  .addReg(Rt)
3500  .addImm(Imm)
3502  &MMO, MMO.getOffset(), MMO.getSize()));
3503 
3504  MI.eraseFromParent();
3505  return BB;
3506 }
3507 
3508 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3509 //
3510 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3511 // =>
3512 // lh $rtemp, $addr
3513 // fill.h $wd, $rtemp
3514 //
3515 // Safety: We can't use ld.h & co as they over-read from the source.
3516 // Additionally, if the address is not modulo 16, 2 cases can occur:
3517 // a) Segmentation fault as the load instruction reads from a memory page
3518 // memory it's not supposed to.
3519 // b) The load crosses an implementation specific boundary, requiring OS
3520 // intervention.
3522 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3523  MachineBasicBlock *BB) const {
3524 
3526  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3527  DebugLoc DL = MI.getDebugLoc();
3528  unsigned Wd = MI.getOperand(0).getReg();
3529 
3530  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3531  // spill and reload can expand as a GPR64 operand. Examine the
3532  // operand in detail and default to ABI.
3533  const TargetRegisterClass *RC =
3534  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3535  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3536  : &Mips::GPR64RegClass);
3537 
3538  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3539  unsigned Rt = RegInfo.createVirtualRegister(RC);
3540 
3541  MachineInstrBuilder MIB =
3542  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3543  for (unsigned i = 1; i < MI.getNumOperands(); i++)
3544  MIB.add(MI.getOperand(i));
3545 
3546  if(!UsingMips32) {
3547  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3548  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3549  Rt = Tmp;
3550  }
3551 
3552  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3553 
3554  MI.eraseFromParent();
3555  return BB;
3556 }
3557 
3558 // Emit the FPROUND_PSEUDO instruction.
3559 //
3560 // Round an FGR64Opnd, FGR32Opnd to an f16.
3561 //
3562 // Safety: Cycle the operand through the GPRs so the result always ends up
3563 // the correct MSA register.
3564 //
3565 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3566 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3567 // (which they can be, as the MSA registers are defined to alias the
3568 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3569 // the correct register class. That requires operands be tie-able across
3570 // register classes which have a sub/super register class relationship.
3571 //
3572 // For FPG32Opnd:
3573 //
3574 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3575 // =>
3576 // mfc1 $rtemp, $fs
3577 // fill.w $rtemp, $wtemp
3578 // fexdo.w $wd, $wtemp, $wtemp
3579 //
3580 // For FPG64Opnd on mips32r2+:
3581 //
3582 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3583 // =>
3584 // mfc1 $rtemp, $fs
3585 // fill.w $rtemp, $wtemp
3586 // mfhc1 $rtemp2, $fs
3587 // insert.w $wtemp[1], $rtemp2
3588 // insert.w $wtemp[3], $rtemp2
3589 // fexdo.w $wtemp2, $wtemp, $wtemp
3590 // fexdo.h $wd, $temp2, $temp2
3591 //
3592 // For FGR64Opnd on mips64r2+:
3593 //
3594 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3595 // =>
3596 // dmfc1 $rtemp, $fs
3597 // fill.d $rtemp, $wtemp
3598 // fexdo.w $wtemp2, $wtemp, $wtemp
3599 // fexdo.h $wd, $wtemp2, $wtemp2
3600 //
3601 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3602 // undef bits are "just right" and the exception enable bits are
3603 // set. By using fill.w to replicate $fs into all elements over
3604 // insert.w for one element, we avoid that potiential case. If
3605 // fexdo.[hw] causes an exception in, the exception is valid and it
3606 // occurs for all elements.
3608 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3609  MachineBasicBlock *BB,
3610  bool IsFGR64) const {
3611 
3612  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3613  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3614  // it.
3616 
3617  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3618  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3619 
3621  DebugLoc DL = MI.getDebugLoc();
3622  unsigned Wd = MI.getOperand(0).getReg();
3623  unsigned Fs = MI.getOperand(1).getReg();
3624 
3625  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3626  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3627  const TargetRegisterClass *GPRRC =
3628  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3629  unsigned MFC1Opc = IsFGR64onMips64
3630  ? Mips::DMFC1
3631  : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3632  unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3633 
3634  // Perform the register class copy as mentioned above.
3635  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3636  BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3637  BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3638  unsigned WPHI = Wtemp;
3639 
3640  if (IsFGR64onMips32) {
3641  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3642  BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3643  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3644  unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3645  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3646  .addReg(Wtemp)
3647  .addReg(Rtemp2)
3648  .addImm(1);
3649  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3650  .addReg(Wtemp2)
3651  .addReg(Rtemp2)
3652  .addImm(3);
3653  WPHI = Wtemp3;
3654  }
3655 
3656  if (IsFGR64) {
3657  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3658  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3659  .addReg(WPHI)
3660  .addReg(WPHI);
3661  WPHI = Wtemp2;
3662  }
3663 
3664  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3665 
3666  MI.eraseFromParent();
3667  return BB;
3668 }
3669 
3670 // Emit the FPEXTEND_PSEUDO instruction.
3671 //
3672 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3673 //
3674 // Safety: Cycle the result through the GPRs so the result always ends up
3675 // the correct floating point register.
3676 //
3677 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3678 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3679 // (which they can be, as the MSA registers are defined to alias the
3680 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3681 // the correct register class. That requires operands be tie-able across
3682 // register classes which have a sub/super register class relationship. I
3683 // haven't checked.
3684 //
3685 // For FGR32Opnd:
3686 //
3687 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3688 // =>
3689 // fexupr.w $wtemp, $ws
3690 // copy_s.w $rtemp, $ws[0]
3691 // mtc1 $rtemp, $fd
3692 //
3693 // For FGR64Opnd on Mips64:
3694 //
3695 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3696 // =>
3697 // fexupr.w $wtemp, $ws
3698 // fexupr.d $wtemp2, $wtemp
3699 // copy_s.d $rtemp, $wtemp2s[0]
3700 // dmtc1 $rtemp, $fd
3701 //
3702 // For FGR64Opnd on Mips32:
3703 //
3704 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3705 // =>
3706 // fexupr.w $wtemp, $ws
3707 // fexupr.d $wtemp2, $wtemp
3708 // copy_s.w $rtemp, $wtemp2[0]
3709 // mtc1 $rtemp, $ftemp
3710 // copy_s.w $rtemp2, $wtemp2[1]
3711 // $fd = mthc1 $rtemp2, $ftemp
3713 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3714  MachineBasicBlock *BB,
3715  bool IsFGR64) const {
3716 
3717  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3718  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3719  // it.
3721 
3722  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3723  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3724 
3726  DebugLoc DL = MI.getDebugLoc();
3727  unsigned Fd = MI.getOperand(0).getReg();
3728  unsigned Ws = MI.getOperand(1).getReg();
3729 
3730  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3731  const TargetRegisterClass *GPRRC =
3732  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3733  unsigned MTC1Opc = IsFGR64onMips64
3734  ? Mips::DMTC1
3735  : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3736  unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3737 
3738  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3739  unsigned WPHI = Wtemp;
3740 
3741  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3742  if (IsFGR64) {
3743  WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3744  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3745  }
3746 
3747  // Perform the safety regclass copy mentioned above.
3748  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3749  unsigned FPRPHI = IsFGR64onMips32
3750  ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3751  : Fd;
3752  BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3753  BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3754 
3755  if (IsFGR64onMips32) {
3756  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3757  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3758  .addReg(WPHI)
3759  .addImm(1);
3760  BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3761  .addReg(FPRPHI)
3762  .addReg(Rtemp2);
3763  }
3764 
3765  MI.eraseFromParent();
3766  return BB;
3767 }
3768 
3769 // Emit the FEXP2_W_1 pseudo instructions.
3770 //
3771 // fexp2_w_1_pseudo $wd, $wt
3772 // =>
3773 // ldi.w $ws, 1
3774 // fexp2.w $wd, $ws, $wt
3776 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3777  MachineBasicBlock *BB) const {
3779  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3780  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3781  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3782  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3783  DebugLoc DL = MI.getDebugLoc();
3784 
3785  // Splat 1.0 into a vector
3786  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3787  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3788 
3789  // Emit 1.0 * fexp2(Wt)
3790  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3791  .addReg(Ws2)
3792  .addReg(MI.getOperand(1).getReg());
3793 
3794  MI.eraseFromParent(); // The pseudo instruction is gone now.
3795  return BB;
3796 }
3797 
3798 // Emit the FEXP2_D_1 pseudo instructions.
3799 //
3800 // fexp2_d_1_pseudo $wd, $wt
3801 // =>
3802 // ldi.d $ws, 1
3803 // fexp2.d $wd, $ws, $wt
3805 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3806  MachineBasicBlock *BB) const {
3808  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3809  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3810  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3811  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3812  DebugLoc DL = MI.getDebugLoc();
3813 
3814  // Splat 1.0 into a vector
3815  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3816  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3817 
3818  // Emit 1.0 * fexp2(Wt)
3819  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3820  .addReg(Ws2)
3821  .addReg(MI.getOperand(1).getReg());
3822 
3823  MI.eraseFromParent(); // The pseudo instruction is gone now.
3824  return BB;
3825 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
const MachineInstrBuilder & add(const MachineOperand &MO) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:886
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:939
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MipsSubtarget & Subtarget
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:651
This class represents lattice values for constants.
Definition: AllocatorList.h:23
value_iterator value_end() const
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:606
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:366
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const SDValue & getBasePtr() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned getReg() const
getReg - Returns the register number.
const SDValue & getValue() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDVTList getVTList() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
const MipsInstrInfo * getInstrInfo() const override
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isABI_O32() const
unsigned getAlignment() const
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:785
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
const Triple & getTargetTriple() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasMips64() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool hasDSPR2() const
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
Shift and rotation operations.
Definition: ISDOpcodes.h:409
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getScalarValueSizeInBits() const
bool isGP64bit() const
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
bool hasMips32r6() const
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
unsigned Intr
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This file implements a class to represent arbitrary precision integral constant values and operations...
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:428
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
static bool isConstantOrUndef(const SDValue Op)
unsigned getIncomingArgSize() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:854
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:968
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:578
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:635
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1165
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
const SDValue & getBasePtr() const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Machine Value Type.
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1498
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:331
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const APInt & getAPIntValue() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:555
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
bool isSingleFloat() const
unsigned ceilLogBase2() const
Definition: APInt.h:1750
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
bool hasMips64r6() const
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isABI_N32() const
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:403
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isLittle() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:338
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
double Log2(double Value)
Return the log base 2 of the specified value.
Definition: MathExtras.h:527
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
value_iterator value_begin() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
Definition: SelectionDAG.h:736
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
bool hasCnMips() const
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:645
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
int64_t getImm() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasDSP() const
unsigned logBase2() const
Definition: APInt.h:1747
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
bool isPowerOf2() const
Check if this APInt&#39;s value is a power of two greater than zero.
Definition: APInt.h:463
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:311
int getMaskElt(unsigned Idx) const
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:615
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the &#39;representative&#39; register class for the specified value type.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:402
Flags getFlags() const
Return the raw flags of the source value,.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
bool useOddSPReg() const
static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:609
SDValue getValue(unsigned R) const
unsigned getInRegsParamsCount() const
bool hasMips32r2() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isABI_N64() const
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts)
Test whether V has a splatted value for all the demanded elements.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:72
uint64_t getConstantOperandVal(unsi