LLVM  6.0.0svn
MipsSEInstrInfo.cpp
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1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
25 
26 using namespace llvm;
27 
29  : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
30  RI() {}
31 
33  return RI;
34 }
35 
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
42  int &FrameIndex) const {
43  unsigned Opc = MI.getOpcode();
44 
45  if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46  (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
47  if ((MI.getOperand(1).isFI()) && // is a stack slot
48  (MI.getOperand(2).isImm()) && // the imm is zero
49  (isZeroImm(MI.getOperand(2)))) {
50  FrameIndex = MI.getOperand(1).getIndex();
51  return MI.getOperand(0).getReg();
52  }
53  }
54 
55  return 0;
56 }
57 
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
64  int &FrameIndex) const {
65  unsigned Opc = MI.getOpcode();
66 
67  if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68  (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
69  if ((MI.getOperand(1).isFI()) && // is a stack slot
70  (MI.getOperand(2).isImm()) && // the imm is zero
71  (isZeroImm(MI.getOperand(2)))) {
72  FrameIndex = MI.getOperand(1).getIndex();
73  return MI.getOperand(0).getReg();
74  }
75  }
76  return 0;
77 }
78 
81  const DebugLoc &DL, unsigned DestReg,
82  unsigned SrcReg, bool KillSrc) const {
83  unsigned Opc = 0, ZeroReg = 0;
84  bool isMicroMips = Subtarget.inMicroMipsMode();
85 
86  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
87  if (Mips::GPR32RegClass.contains(SrcReg)) {
88  if (isMicroMips)
89  Opc = Mips::MOVE16_MM;
90  else
91  Opc = Mips::OR, ZeroReg = Mips::ZERO;
92  } else if (Mips::CCRRegClass.contains(SrcReg))
93  Opc = Mips::CFC1;
94  else if (Mips::FGR32RegClass.contains(SrcReg))
95  Opc = Mips::MFC1;
96  else if (Mips::HI32RegClass.contains(SrcReg)) {
97  Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
98  SrcReg = 0;
99  } else if (Mips::LO32RegClass.contains(SrcReg)) {
100  Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
101  SrcReg = 0;
102  } else if (Mips::HI32DSPRegClass.contains(SrcReg))
103  Opc = Mips::MFHI_DSP;
104  else if (Mips::LO32DSPRegClass.contains(SrcReg))
105  Opc = Mips::MFLO_DSP;
106  else if (Mips::DSPCCRegClass.contains(SrcReg)) {
107  BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
108  .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
109  return;
110  }
111  else if (Mips::MSACtrlRegClass.contains(SrcReg))
112  Opc = Mips::CFCMSA;
113  }
114  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115  if (Mips::CCRRegClass.contains(DestReg))
116  Opc = Mips::CTC1;
117  else if (Mips::FGR32RegClass.contains(DestReg))
118  Opc = Mips::MTC1;
119  else if (Mips::HI32RegClass.contains(DestReg))
120  Opc = Mips::MTHI, DestReg = 0;
121  else if (Mips::LO32RegClass.contains(DestReg))
122  Opc = Mips::MTLO, DestReg = 0;
123  else if (Mips::HI32DSPRegClass.contains(DestReg))
124  Opc = Mips::MTHI_DSP;
125  else if (Mips::LO32DSPRegClass.contains(DestReg))
126  Opc = Mips::MTLO_DSP;
127  else if (Mips::DSPCCRegClass.contains(DestReg)) {
128  BuildMI(MBB, I, DL, get(Mips::WRDSP))
129  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130  .addReg(DestReg, RegState::ImplicitDefine);
131  return;
132  } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
133  BuildMI(MBB, I, DL, get(Mips::CTCMSA))
134  .addReg(DestReg)
135  .addReg(SrcReg, getKillRegState(KillSrc));
136  return;
137  }
138  }
139  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140  Opc = Mips::FMOV_S;
141  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142  Opc = Mips::FMOV_D32;
143  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144  Opc = Mips::FMOV_D64;
145  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146  if (Mips::GPR64RegClass.contains(SrcReg))
147  Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
148  else if (Mips::HI64RegClass.contains(SrcReg))
149  Opc = Mips::MFHI64, SrcReg = 0;
150  else if (Mips::LO64RegClass.contains(SrcReg))
151  Opc = Mips::MFLO64, SrcReg = 0;
152  else if (Mips::FGR64RegClass.contains(SrcReg))
153  Opc = Mips::DMFC1;
154  }
155  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156  if (Mips::HI64RegClass.contains(DestReg))
157  Opc = Mips::MTHI64, DestReg = 0;
158  else if (Mips::LO64RegClass.contains(DestReg))
159  Opc = Mips::MTLO64, DestReg = 0;
160  else if (Mips::FGR64RegClass.contains(DestReg))
161  Opc = Mips::DMTC1;
162  }
163  else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164  if (Mips::MSA128BRegClass.contains(SrcReg))
165  Opc = Mips::MOVE_V;
166  }
167 
168  assert(Opc && "Cannot copy registers");
169 
170  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
171 
172  if (DestReg)
173  MIB.addReg(DestReg, RegState::Define);
174 
175  if (SrcReg)
176  MIB.addReg(SrcReg, getKillRegState(KillSrc));
177 
178  if (ZeroReg)
179  MIB.addReg(ZeroReg);
180 }
181 
184  unsigned SrcReg, bool isKill, int FI,
185  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186  int64_t Offset) const {
187  DebugLoc DL;
189 
190  unsigned Opc = 0;
191 
192  if (Mips::GPR32RegClass.hasSubClassEq(RC))
193  Opc = Mips::SW;
194  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
195  Opc = Mips::SD;
196  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197  Opc = Mips::STORE_ACC64;
198  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199  Opc = Mips::STORE_ACC64DSP;
200  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201  Opc = Mips::STORE_ACC128;
202  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203  Opc = Mips::STORE_CCOND_DSP;
204  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
205  Opc = Mips::SWC1;
206  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
207  Opc = Mips::SDC1;
208  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
209  Opc = Mips::SDC164;
210  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
211  Opc = Mips::ST_B;
212  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
213  TRI->isTypeLegalForClass(*RC, MVT::v8f16))
214  Opc = Mips::ST_H;
215  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
216  TRI->isTypeLegalForClass(*RC, MVT::v4f32))
217  Opc = Mips::ST_W;
218  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
219  TRI->isTypeLegalForClass(*RC, MVT::v2f64))
220  Opc = Mips::ST_D;
221  else if (Mips::LO32RegClass.hasSubClassEq(RC))
222  Opc = Mips::SW;
223  else if (Mips::LO64RegClass.hasSubClassEq(RC))
224  Opc = Mips::SD;
225  else if (Mips::HI32RegClass.hasSubClassEq(RC))
226  Opc = Mips::SW;
227  else if (Mips::HI64RegClass.hasSubClassEq(RC))
228  Opc = Mips::SD;
229  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
230  Opc = Mips::SWDSP;
231 
232  // Hi, Lo are normally caller save but they are callee save
233  // for interrupt handling.
234  const Function *Func = MBB.getParent()->getFunction();
235  if (Func->hasFnAttribute("interrupt")) {
236  if (Mips::HI32RegClass.hasSubClassEq(RC)) {
237  BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
238  SrcReg = Mips::K0;
239  } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
240  BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
241  SrcReg = Mips::K0_64;
242  } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
243  BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
244  SrcReg = Mips::K0;
245  } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
246  BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
247  SrcReg = Mips::K0_64;
248  }
249  }
250 
251  assert(Opc && "Register class not handled!");
252  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
253  .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
254 }
255 
258  unsigned DestReg, int FI, const TargetRegisterClass *RC,
259  const TargetRegisterInfo *TRI, int64_t Offset) const {
260  DebugLoc DL;
261  if (I != MBB.end()) DL = I->getDebugLoc();
263  unsigned Opc = 0;
264 
265  const Function *Func = MBB.getParent()->getFunction();
266  bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
267  (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
268  DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
269 
270  if (Mips::GPR32RegClass.hasSubClassEq(RC))
271  Opc = Mips::LW;
272  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
273  Opc = Mips::LD;
274  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
275  Opc = Mips::LOAD_ACC64;
276  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
277  Opc = Mips::LOAD_ACC64DSP;
278  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
279  Opc = Mips::LOAD_ACC128;
280  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
281  Opc = Mips::LOAD_CCOND_DSP;
282  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
283  Opc = Mips::LWC1;
284  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
285  Opc = Mips::LDC1;
286  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
287  Opc = Mips::LDC164;
288  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
289  Opc = Mips::LD_B;
290  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
291  TRI->isTypeLegalForClass(*RC, MVT::v8f16))
292  Opc = Mips::LD_H;
293  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
294  TRI->isTypeLegalForClass(*RC, MVT::v4f32))
295  Opc = Mips::LD_W;
296  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
297  TRI->isTypeLegalForClass(*RC, MVT::v2f64))
298  Opc = Mips::LD_D;
299  else if (Mips::HI32RegClass.hasSubClassEq(RC))
300  Opc = Mips::LW;
301  else if (Mips::HI64RegClass.hasSubClassEq(RC))
302  Opc = Mips::LD;
303  else if (Mips::LO32RegClass.hasSubClassEq(RC))
304  Opc = Mips::LW;
305  else if (Mips::LO64RegClass.hasSubClassEq(RC))
306  Opc = Mips::LD;
307  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
308  Opc = Mips::LWDSP;
309 
310  assert(Opc && "Register class not handled!");
311 
312  if (!ReqIndirectLoad)
313  BuildMI(MBB, I, DL, get(Opc), DestReg)
314  .addFrameIndex(FI)
315  .addImm(Offset)
316  .addMemOperand(MMO);
317  else {
318  // Load HI/LO through K0. Notably the DestReg is encoded into the
319  // instruction itself.
320  unsigned Reg = Mips::K0;
321  unsigned LdOp = Mips::MTLO;
322  if (DestReg == Mips::HI0)
323  LdOp = Mips::MTHI;
324 
325  if (Subtarget.getABI().ArePtrs64bit()) {
326  Reg = Mips::K0_64;
327  if (DestReg == Mips::HI0_64)
328  LdOp = Mips::MTHI64;
329  else
330  LdOp = Mips::MTLO64;
331  }
332 
333  BuildMI(MBB, I, DL, get(Opc), Reg)
334  .addFrameIndex(FI)
335  .addImm(Offset)
336  .addMemOperand(MMO);
337  BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
338  }
339 }
340 
342  MachineBasicBlock &MBB = *MI.getParent();
343  bool isMicroMips = Subtarget.inMicroMipsMode();
344  unsigned Opc;
345 
346  switch (MI.getDesc().getOpcode()) {
347  default:
348  return false;
349  case Mips::RetRA:
350  expandRetRA(MBB, MI);
351  break;
352  case Mips::ERet:
353  expandERet(MBB, MI);
354  break;
355  case Mips::PseudoMFHI:
356  Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
357  expandPseudoMFHiLo(MBB, MI, Opc);
358  break;
359  case Mips::PseudoMFLO:
360  Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
361  expandPseudoMFHiLo(MBB, MI, Opc);
362  break;
363  case Mips::PseudoMFHI64:
364  expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
365  break;
366  case Mips::PseudoMFLO64:
367  expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
368  break;
369  case Mips::PseudoMTLOHI:
370  expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
371  break;
372  case Mips::PseudoMTLOHI64:
373  expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
374  break;
375  case Mips::PseudoMTLOHI_DSP:
376  expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
377  break;
378  case Mips::PseudoCVT_S_W:
379  expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
380  break;
381  case Mips::PseudoCVT_D32_W:
382  expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
383  break;
384  case Mips::PseudoCVT_S_L:
385  expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
386  break;
387  case Mips::PseudoCVT_D64_W:
388  expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
389  break;
390  case Mips::PseudoCVT_D64_L:
391  expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
392  break;
393  case Mips::BuildPairF64:
394  expandBuildPairF64(MBB, MI, false);
395  break;
396  case Mips::BuildPairF64_64:
397  expandBuildPairF64(MBB, MI, true);
398  break;
400  expandExtractElementF64(MBB, MI, false);
401  break;
402  case Mips::ExtractElementF64_64:
403  expandExtractElementF64(MBB, MI, true);
404  break;
405  case Mips::MIPSeh_return32:
406  case Mips::MIPSeh_return64:
407  expandEhReturn(MBB, MI);
408  break;
409  }
410 
411  MBB.erase(MI);
412  return true;
413 }
414 
415 /// getOppositeBranchOpc - Return the inverse of the specified
416 /// opcode, e.g. turning BEQ to BNE.
417 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
418  switch (Opc) {
419  default: llvm_unreachable("Illegal opcode!");
420  case Mips::BEQ: return Mips::BNE;
421  case Mips::BEQ_MM: return Mips::BNE_MM;
422  case Mips::BNE: return Mips::BEQ;
423  case Mips::BNE_MM: return Mips::BEQ_MM;
424  case Mips::BGTZ: return Mips::BLEZ;
425  case Mips::BGEZ: return Mips::BLTZ;
426  case Mips::BLTZ: return Mips::BGEZ;
427  case Mips::BLEZ: return Mips::BGTZ;
428  case Mips::BEQ64: return Mips::BNE64;
429  case Mips::BNE64: return Mips::BEQ64;
430  case Mips::BGTZ64: return Mips::BLEZ64;
431  case Mips::BGEZ64: return Mips::BLTZ64;
432  case Mips::BLTZ64: return Mips::BGEZ64;
433  case Mips::BLEZ64: return Mips::BGTZ64;
434  case Mips::BC1T: return Mips::BC1F;
435  case Mips::BC1F: return Mips::BC1T;
436  case Mips::BEQZC_MM: return Mips::BNEZC_MM;
437  case Mips::BNEZC_MM: return Mips::BEQZC_MM;
438  case Mips::BEQZC: return Mips::BNEZC;
439  case Mips::BNEZC: return Mips::BEQZC;
440  case Mips::BEQC: return Mips::BNEC;
441  case Mips::BNEC: return Mips::BEQC;
442  case Mips::BGTZC: return Mips::BLEZC;
443  case Mips::BGEZC: return Mips::BLTZC;
444  case Mips::BLTZC: return Mips::BGEZC;
445  case Mips::BLEZC: return Mips::BGTZC;
446  case Mips::BEQZC64: return Mips::BNEZC64;
447  case Mips::BNEZC64: return Mips::BEQZC64;
448  case Mips::BEQC64: return Mips::BNEC64;
449  case Mips::BNEC64: return Mips::BEQC64;
450  case Mips::BGEC64: return Mips::BLTC64;
451  case Mips::BGEUC64: return Mips::BLTUC64;
452  case Mips::BLTC64: return Mips::BGEC64;
453  case Mips::BLTUC64: return Mips::BGEUC64;
454  case Mips::BGTZC64: return Mips::BLEZC64;
455  case Mips::BGEZC64: return Mips::BLTZC64;
456  case Mips::BLTZC64: return Mips::BGEZC64;
457  case Mips::BLEZC64: return Mips::BGTZC64;
458  case Mips::BBIT0: return Mips::BBIT1;
459  case Mips::BBIT1: return Mips::BBIT0;
460  case Mips::BBIT032: return Mips::BBIT132;
461  case Mips::BBIT132: return Mips::BBIT032;
462  }
463 }
464 
465 /// Adjust SP by Amount bytes.
466 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
467  MachineBasicBlock &MBB,
469  MipsABIInfo ABI = Subtarget.getABI();
470  DebugLoc DL;
471  unsigned ADDiu = ABI.GetPtrAddiuOp();
472 
473  if (Amount == 0)
474  return;
475 
476  if (isInt<16>(Amount)) {
477  // addi sp, sp, amount
478  BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
479  } else {
480  // For numbers which are not 16bit integers we synthesize Amount inline
481  // then add or subtract it from sp.
482  unsigned Opc = ABI.GetPtrAdduOp();
483  if (Amount < 0) {
484  Opc = ABI.GetPtrSubuOp();
485  Amount = -Amount;
486  }
487  unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
488  BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
489  }
490 }
491 
492 /// This function generates the sequence of instructions needed to get the
493 /// result of adding register REG and immediate IMM.
496  const DebugLoc &DL,
497  unsigned *NewImm) const {
498  MipsAnalyzeImmediate AnalyzeImm;
499  const MipsSubtarget &STI = Subtarget;
500  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
501  unsigned Size = STI.isABI_N64() ? 64 : 32;
502  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
503  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
504  const TargetRegisterClass *RC = STI.isABI_N64() ?
505  &Mips::GPR64RegClass : &Mips::GPR32RegClass;
506  bool LastInstrIsADDiu = NewImm;
507 
508  const MipsAnalyzeImmediate::InstSeq &Seq =
509  AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
511 
512  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
513 
514  // The first instruction can be a LUi, which is different from other
515  // instructions (ADDiu, ORI and SLL) in that it does not have a register
516  // operand.
517  unsigned Reg = RegInfo.createVirtualRegister(RC);
518 
519  if (Inst->Opc == LUi)
520  BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
521  else
522  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
523  .addImm(SignExtend64<16>(Inst->ImmOpnd));
524 
525  // Build the remaining instructions in Seq.
526  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
527  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
528  .addImm(SignExtend64<16>(Inst->ImmOpnd));
529 
530  if (LastInstrIsADDiu)
531  *NewImm = Inst->ImmOpnd;
532 
533  return Reg;
534 }
535 
536 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
537  return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
538  Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
539  Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
540  Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
541  Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
542  Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
543  Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
544  Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
545  Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
546  Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
547  Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
548  Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
549  Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
550  Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
551  Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
552  Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
553  Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
554  Opc == Mips::BBIT132) ? Opc : 0;
555 }
556 
557 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
559 
561  if (Subtarget.isGP64bit())
562  MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
563  .addReg(Mips::RA_64, RegState::Undef);
564  else
565  MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
567 
568  // Retain any imp-use flags.
569  for (auto & MO : I->operands()) {
570  if (MO.isImplicit())
571  MIB.add(MO);
572  }
573 }
574 
575 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
576  MachineBasicBlock::iterator I) const {
577  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
578 }
579 
580 std::pair<bool, bool>
581 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
582  const MachineFunction &MF) const {
583  const MCInstrDesc &Desc = get(Opc);
584  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
585  const MipsRegisterInfo *RI = &getRegisterInfo();
586  unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
587  unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
588 
589  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
590 }
591 
592 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
594  unsigned NewOpc) const {
595  BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
596 }
597 
598 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
600  unsigned LoOpc,
601  unsigned HiOpc,
602  bool HasExplicitDef) const {
603  // Expand
604  // lo_hi pseudomtlohi $gpr0, $gpr1
605  // to these two instructions:
606  // mtlo $gpr0
607  // mthi $gpr1
608 
609  DebugLoc DL = I->getDebugLoc();
610  const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
611  MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
612  MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
613 
614  // Add lo/hi registers if the mtlo/hi instructions created have explicit
615  // def registers.
616  if (HasExplicitDef) {
617  unsigned DstReg = I->getOperand(0).getReg();
618  unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
619  unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
620  LoInst.addReg(DstLo, RegState::Define);
621  HiInst.addReg(DstHi, RegState::Define);
622  }
623 
624  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
625  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
626 }
627 
628 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
630  unsigned CvtOpc, unsigned MovOpc,
631  bool IsI64) const {
632  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
633  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
634  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
635  unsigned KillSrc = getKillRegState(Src.isKill());
636  DebugLoc DL = I->getDebugLoc();
637  bool DstIsLarger, SrcIsLarger;
638 
639  std::tie(DstIsLarger, SrcIsLarger) =
640  compareOpndSize(CvtOpc, *MBB.getParent());
641 
642  if (DstIsLarger)
643  TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
644 
645  if (SrcIsLarger)
646  DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
647 
648  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
649  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
650 }
651 
652 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
654  bool FP64) const {
655  unsigned DstReg = I->getOperand(0).getReg();
656  unsigned SrcReg = I->getOperand(1).getReg();
657  unsigned N = I->getOperand(2).getImm();
658  DebugLoc dl = I->getDebugLoc();
659 
660  assert(N < 2 && "Invalid immediate");
661  unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
662  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
663 
664  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
665  // in MipsSEFrameLowering.cpp.
667 
668  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
669  // in MipsSEFrameLowering.cpp.
671 
672  if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
673  // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
674  // claim to read the whole 64-bits as part of a white lie used to
675  // temporarily work around a widespread bug in the -mfp64 support.
676  // The problem is that none of the 32-bit fpu ops mention the fact
677  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
678  // requires a major overhaul of the FPU implementation which can't
679  // be done right now due to time constraints.
680  // MFHC1 is one of two instructions that are affected since they are
681  // the only instructions that don't read the lower 32-bits.
682  // We therefore pretend that it reads the bottom 32-bits to
683  // artificially create a dependency and prevent the scheduler
684  // changing the behaviour of the code.
685  BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
686  .addReg(SrcReg);
687  } else
688  BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
689 }
690 
691 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
693  bool FP64) const {
694  unsigned DstReg = I->getOperand(0).getReg();
695  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
696  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
697  DebugLoc dl = I->getDebugLoc();
698  const TargetRegisterInfo &TRI = getRegisterInfo();
699 
700  // When mthc1 is available, use:
701  // mtc1 Lo, $fp
702  // mthc1 Hi, $fp
703  //
704  // Otherwise, for O32 FPXX ABI:
705  // spill + reload via ldc1
706  // This case is handled by the frame lowering code.
707  //
708  // Otherwise, for FP32:
709  // mtc1 Lo, $fp
710  // mtc1 Hi, $fp + 1
711  //
712  // The case where dmtc1 is available doesn't need to be handled here
713  // because it never creates a BuildPairF64 node.
714 
715  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
716  // in MipsSEFrameLowering.cpp.
718 
719  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
720  // in MipsSEFrameLowering.cpp.
722 
723  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
724  .addReg(LoReg);
725 
726  if (Subtarget.hasMTHC1()) {
727  // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
728  // around a widespread bug in the -mfp64 support.
729  // The problem is that none of the 32-bit fpu ops mention the fact
730  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
731  // requires a major overhaul of the FPU implementation which can't
732  // be done right now due to time constraints.
733  // MTHC1 is one of two instructions that are affected since they are
734  // the only instructions that don't read the lower 32-bits.
735  // We therefore pretend that it reads the bottom 32-bits to
736  // artificially create a dependency and prevent the scheduler
737  // changing the behaviour of the code.
738  BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
739  .addReg(DstReg)
740  .addReg(HiReg);
741  } else if (Subtarget.isABI_FPXX())
742  llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
743  else
744  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
745  .addReg(HiReg);
746 }
747 
748 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
749  MachineBasicBlock::iterator I) const {
750  // This pseudo instruction is generated as part of the lowering of
751  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
752  // indirect jump to TargetReg
753  MipsABIInfo ABI = Subtarget.getABI();
754  unsigned ADDU = ABI.GetPtrAdduOp();
755  unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
756  unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
757  unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
758  unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
759  unsigned OffsetReg = I->getOperand(0).getReg();
760  unsigned TargetReg = I->getOperand(1).getReg();
761 
762  // addu $ra, $v0, $zero
763  // addu $sp, $sp, $v1
764  // jr $ra (via RetRA)
765  const TargetMachine &TM = MBB.getParent()->getTarget();
766  if (TM.isPositionIndependent())
767  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
768  .addReg(TargetReg)
769  .addReg(ZERO);
770  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
771  .addReg(TargetReg)
772  .addReg(ZERO);
773  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
774  expandRetRA(MBB, I);
775 }
776 
778  return new MipsSEInstrInfo(STI);
779 }
bool isABI_FPXX() const
const MachineInstrBuilder & add(const MachineOperand &MO) const
unsigned GetPtrAdduOp() const
Definition: MipsABIInfo.cpp:89
bool hasMTHC1() const
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:329
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:75
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
A debug info location.
Definition: DebugLoc.h:34
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MipsSEInstrInfo(const MipsSubtarget &STI)
return AArch64::GPR64RegClass contains(Reg)
SI optimize exec mask operations pre RA
A description of a memory reference used in the backend.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool inMicroMipsMode() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned SubReg
bool isGP64bit() const
Reg
All possible values of the reg field in the ModR/M byte.
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:46
static int getRegClass(RegisterKind Is, unsigned RegWidth)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
unsigned getKillRegState(bool B)
unsigned short NumOperands
Definition: MCInstrDesc.h:166
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned GetPtrAddiuOp() const
Definition: MipsABIInfo.cpp:93
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZeroImm(const MachineOperand &op) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MipsABIInfo & getABI() const
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned GetPtrSubuOp() const
Definition: MipsABIInfo.cpp:97
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isPositionIndependent() const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
bool useOddSPReg() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasMips32r2() const
bool isABI_N64() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isFP64bit() const