LLVM  8.0.0svn
MipsSEInstrInfo.cpp
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1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
25 
26 using namespace llvm;
27 
28 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
29  if (STI.inMicroMipsMode())
30  return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
31  return STI.isPositionIndependent() ? Mips::B : Mips::J;
32 }
33 
35  : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
36 
38  return RI;
39 }
40 
41 /// isLoadFromStackSlot - If the specified machine instruction is a direct
42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
47  int &FrameIndex) const {
48  unsigned Opc = MI.getOpcode();
49 
50  if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
51  (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
52  if ((MI.getOperand(1).isFI()) && // is a stack slot
53  (MI.getOperand(2).isImm()) && // the imm is zero
54  (isZeroImm(MI.getOperand(2)))) {
55  FrameIndex = MI.getOperand(1).getIndex();
56  return MI.getOperand(0).getReg();
57  }
58  }
59 
60  return 0;
61 }
62 
63 /// isStoreToStackSlot - If the specified machine instruction is a direct
64 /// store to a stack slot, return the virtual or physical register number of
65 /// the source reg along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than storing to the stack slot.
69  int &FrameIndex) const {
70  unsigned Opc = MI.getOpcode();
71 
72  if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
73  (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
74  if ((MI.getOperand(1).isFI()) && // is a stack slot
75  (MI.getOperand(2).isImm()) && // the imm is zero
76  (isZeroImm(MI.getOperand(2)))) {
77  FrameIndex = MI.getOperand(1).getIndex();
78  return MI.getOperand(0).getReg();
79  }
80  }
81  return 0;
82 }
83 
86  const DebugLoc &DL, unsigned DestReg,
87  unsigned SrcReg, bool KillSrc) const {
88  unsigned Opc = 0, ZeroReg = 0;
89  bool isMicroMips = Subtarget.inMicroMipsMode();
90 
91  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
92  if (Mips::GPR32RegClass.contains(SrcReg)) {
93  if (isMicroMips)
94  Opc = Mips::MOVE16_MM;
95  else
96  Opc = Mips::OR, ZeroReg = Mips::ZERO;
97  } else if (Mips::CCRRegClass.contains(SrcReg))
98  Opc = Mips::CFC1;
99  else if (Mips::FGR32RegClass.contains(SrcReg))
100  Opc = Mips::MFC1;
101  else if (Mips::HI32RegClass.contains(SrcReg)) {
102  Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
103  SrcReg = 0;
104  } else if (Mips::LO32RegClass.contains(SrcReg)) {
105  Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
106  SrcReg = 0;
107  } else if (Mips::HI32DSPRegClass.contains(SrcReg))
108  Opc = Mips::MFHI_DSP;
109  else if (Mips::LO32DSPRegClass.contains(SrcReg))
110  Opc = Mips::MFLO_DSP;
111  else if (Mips::DSPCCRegClass.contains(SrcReg)) {
112  BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
113  .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
114  return;
115  }
116  else if (Mips::MSACtrlRegClass.contains(SrcReg))
117  Opc = Mips::CFCMSA;
118  }
119  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
120  if (Mips::CCRRegClass.contains(DestReg))
121  Opc = Mips::CTC1;
122  else if (Mips::FGR32RegClass.contains(DestReg))
123  Opc = Mips::MTC1;
124  else if (Mips::HI32RegClass.contains(DestReg))
125  Opc = Mips::MTHI, DestReg = 0;
126  else if (Mips::LO32RegClass.contains(DestReg))
127  Opc = Mips::MTLO, DestReg = 0;
128  else if (Mips::HI32DSPRegClass.contains(DestReg))
129  Opc = Mips::MTHI_DSP;
130  else if (Mips::LO32DSPRegClass.contains(DestReg))
131  Opc = Mips::MTLO_DSP;
132  else if (Mips::DSPCCRegClass.contains(DestReg)) {
133  BuildMI(MBB, I, DL, get(Mips::WRDSP))
134  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
135  .addReg(DestReg, RegState::ImplicitDefine);
136  return;
137  } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
138  BuildMI(MBB, I, DL, get(Mips::CTCMSA))
139  .addReg(DestReg)
140  .addReg(SrcReg, getKillRegState(KillSrc));
141  return;
142  }
143  }
144  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
145  Opc = Mips::FMOV_S;
146  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
147  Opc = Mips::FMOV_D32;
148  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
149  Opc = Mips::FMOV_D64;
150  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
151  if (Mips::GPR64RegClass.contains(SrcReg))
152  Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
153  else if (Mips::HI64RegClass.contains(SrcReg))
154  Opc = Mips::MFHI64, SrcReg = 0;
155  else if (Mips::LO64RegClass.contains(SrcReg))
156  Opc = Mips::MFLO64, SrcReg = 0;
157  else if (Mips::FGR64RegClass.contains(SrcReg))
158  Opc = Mips::DMFC1;
159  }
160  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
161  if (Mips::HI64RegClass.contains(DestReg))
162  Opc = Mips::MTHI64, DestReg = 0;
163  else if (Mips::LO64RegClass.contains(DestReg))
164  Opc = Mips::MTLO64, DestReg = 0;
165  else if (Mips::FGR64RegClass.contains(DestReg))
166  Opc = Mips::DMTC1;
167  }
168  else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
169  if (Mips::MSA128BRegClass.contains(SrcReg))
170  Opc = Mips::MOVE_V;
171  }
172 
173  assert(Opc && "Cannot copy registers");
174 
175  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
176 
177  if (DestReg)
178  MIB.addReg(DestReg, RegState::Define);
179 
180  if (SrcReg)
181  MIB.addReg(SrcReg, getKillRegState(KillSrc));
182 
183  if (ZeroReg)
184  MIB.addReg(ZeroReg);
185 }
186 
187 static bool isORCopyInst(const MachineInstr &MI) {
188  switch (MI.getOpcode()) {
189  default:
190  break;
191  case Mips::OR_MM:
192  case Mips::OR:
193  if (MI.getOperand(2).getReg() == Mips::ZERO)
194  return true;
195  break;
196  case Mips::OR64:
197  if (MI.getOperand(2).getReg() == Mips::ZERO_64)
198  return true;
199  break;
200  }
201  return false;
202 }
203 
204 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
205 /// if it is WRDSP instruction.
206 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
207  switch (MI.getOpcode()) {
208  default:
209  return false;
210  case Mips::WRDSP:
211  case Mips::WRDSP_MM:
212  isWrite = true;
213  break;
214  case Mips::RDDSP:
215  case Mips::RDDSP_MM:
216  isWrite = false;
217  break;
218  }
219  return true;
220 }
221 
222 /// We check for the common case of 'or', as it's MIPS' preferred instruction
223 /// for GPRs but we have to check the operands to ensure that is the case.
224 /// Other move instructions for MIPS are directly identifiable.
226  const MachineOperand *&Src,
227  const MachineOperand *&Dest) const {
228  bool isDSPControlWrite = false;
229  // Condition is made to match the creation of WRDSP/RDDSP copy instruction
230  // from copyPhysReg function.
231  if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
232  if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
233  return false;
234  else if (isDSPControlWrite) {
235  Src = &MI.getOperand(0);
236  Dest = &MI.getOperand(2);
237  } else {
238  Dest = &MI.getOperand(0);
239  Src = &MI.getOperand(2);
240  }
241  return true;
242  } else if (MI.isMoveReg() || isORCopyInst(MI)) {
243  Dest = &MI.getOperand(0);
244  Src = &MI.getOperand(1);
245  return true;
246  }
247  return false;
248 }
249 
252  unsigned SrcReg, bool isKill, int FI,
253  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
254  int64_t Offset) const {
255  DebugLoc DL;
257 
258  unsigned Opc = 0;
259 
260  if (Mips::GPR32RegClass.hasSubClassEq(RC))
261  Opc = Mips::SW;
262  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
263  Opc = Mips::SD;
264  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
265  Opc = Mips::STORE_ACC64;
266  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
267  Opc = Mips::STORE_ACC64DSP;
268  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
269  Opc = Mips::STORE_ACC128;
270  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
271  Opc = Mips::STORE_CCOND_DSP;
272  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
273  Opc = Mips::SWC1;
274  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
275  Opc = Mips::SDC1;
276  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
277  Opc = Mips::SDC164;
278  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
279  Opc = Mips::ST_B;
280  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
281  TRI->isTypeLegalForClass(*RC, MVT::v8f16))
282  Opc = Mips::ST_H;
283  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
284  TRI->isTypeLegalForClass(*RC, MVT::v4f32))
285  Opc = Mips::ST_W;
286  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
287  TRI->isTypeLegalForClass(*RC, MVT::v2f64))
288  Opc = Mips::ST_D;
289  else if (Mips::LO32RegClass.hasSubClassEq(RC))
290  Opc = Mips::SW;
291  else if (Mips::LO64RegClass.hasSubClassEq(RC))
292  Opc = Mips::SD;
293  else if (Mips::HI32RegClass.hasSubClassEq(RC))
294  Opc = Mips::SW;
295  else if (Mips::HI64RegClass.hasSubClassEq(RC))
296  Opc = Mips::SD;
297  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
298  Opc = Mips::SWDSP;
299 
300  // Hi, Lo are normally caller save but they are callee save
301  // for interrupt handling.
302  const Function &Func = MBB.getParent()->getFunction();
303  if (Func.hasFnAttribute("interrupt")) {
304  if (Mips::HI32RegClass.hasSubClassEq(RC)) {
305  BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
306  SrcReg = Mips::K0;
307  } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
308  BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
309  SrcReg = Mips::K0_64;
310  } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
311  BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
312  SrcReg = Mips::K0;
313  } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
314  BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
315  SrcReg = Mips::K0_64;
316  }
317  }
318 
319  assert(Opc && "Register class not handled!");
320  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
321  .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
322 }
323 
326  unsigned DestReg, int FI, const TargetRegisterClass *RC,
327  const TargetRegisterInfo *TRI, int64_t Offset) const {
328  DebugLoc DL;
329  if (I != MBB.end()) DL = I->getDebugLoc();
331  unsigned Opc = 0;
332 
333  const Function &Func = MBB.getParent()->getFunction();
334  bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
335  (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
336  DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
337 
338  if (Mips::GPR32RegClass.hasSubClassEq(RC))
339  Opc = Mips::LW;
340  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
341  Opc = Mips::LD;
342  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
343  Opc = Mips::LOAD_ACC64;
344  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
345  Opc = Mips::LOAD_ACC64DSP;
346  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
347  Opc = Mips::LOAD_ACC128;
348  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
349  Opc = Mips::LOAD_CCOND_DSP;
350  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
351  Opc = Mips::LWC1;
352  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
353  Opc = Mips::LDC1;
354  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
355  Opc = Mips::LDC164;
356  else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
357  Opc = Mips::LD_B;
358  else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
359  TRI->isTypeLegalForClass(*RC, MVT::v8f16))
360  Opc = Mips::LD_H;
361  else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
362  TRI->isTypeLegalForClass(*RC, MVT::v4f32))
363  Opc = Mips::LD_W;
364  else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
365  TRI->isTypeLegalForClass(*RC, MVT::v2f64))
366  Opc = Mips::LD_D;
367  else if (Mips::HI32RegClass.hasSubClassEq(RC))
368  Opc = Mips::LW;
369  else if (Mips::HI64RegClass.hasSubClassEq(RC))
370  Opc = Mips::LD;
371  else if (Mips::LO32RegClass.hasSubClassEq(RC))
372  Opc = Mips::LW;
373  else if (Mips::LO64RegClass.hasSubClassEq(RC))
374  Opc = Mips::LD;
375  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
376  Opc = Mips::LWDSP;
377 
378  assert(Opc && "Register class not handled!");
379 
380  if (!ReqIndirectLoad)
381  BuildMI(MBB, I, DL, get(Opc), DestReg)
382  .addFrameIndex(FI)
383  .addImm(Offset)
384  .addMemOperand(MMO);
385  else {
386  // Load HI/LO through K0. Notably the DestReg is encoded into the
387  // instruction itself.
388  unsigned Reg = Mips::K0;
389  unsigned LdOp = Mips::MTLO;
390  if (DestReg == Mips::HI0)
391  LdOp = Mips::MTHI;
392 
393  if (Subtarget.getABI().ArePtrs64bit()) {
394  Reg = Mips::K0_64;
395  if (DestReg == Mips::HI0_64)
396  LdOp = Mips::MTHI64;
397  else
398  LdOp = Mips::MTLO64;
399  }
400 
401  BuildMI(MBB, I, DL, get(Opc), Reg)
402  .addFrameIndex(FI)
403  .addImm(Offset)
404  .addMemOperand(MMO);
405  BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
406  }
407 }
408 
410  MachineBasicBlock &MBB = *MI.getParent();
411  bool isMicroMips = Subtarget.inMicroMipsMode();
412  unsigned Opc;
413 
414  switch (MI.getDesc().getOpcode()) {
415  default:
416  return false;
417  case Mips::RetRA:
418  expandRetRA(MBB, MI);
419  break;
420  case Mips::ERet:
421  expandERet(MBB, MI);
422  break;
423  case Mips::PseudoMFHI:
424  expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
425  break;
426  case Mips::PseudoMFHI_MM:
427  expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
428  break;
429  case Mips::PseudoMFLO:
430  expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
431  break;
432  case Mips::PseudoMFLO_MM:
433  expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
434  break;
435  case Mips::PseudoMFHI64:
436  expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
437  break;
438  case Mips::PseudoMFLO64:
439  expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
440  break;
441  case Mips::PseudoMTLOHI:
442  expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
443  break;
444  case Mips::PseudoMTLOHI64:
445  expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
446  break;
447  case Mips::PseudoMTLOHI_DSP:
448  expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
449  break;
450  case Mips::PseudoCVT_S_W:
451  expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
452  break;
453  case Mips::PseudoCVT_D32_W:
454  Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
455  expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
456  break;
457  case Mips::PseudoCVT_S_L:
458  expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
459  break;
460  case Mips::PseudoCVT_D64_W:
461  Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
462  expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
463  break;
464  case Mips::PseudoCVT_D64_L:
465  expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
466  break;
467  case Mips::BuildPairF64:
468  expandBuildPairF64(MBB, MI, isMicroMips, false);
469  break;
470  case Mips::BuildPairF64_64:
471  expandBuildPairF64(MBB, MI, isMicroMips, true);
472  break;
474  expandExtractElementF64(MBB, MI, isMicroMips, false);
475  break;
476  case Mips::ExtractElementF64_64:
477  expandExtractElementF64(MBB, MI, isMicroMips, true);
478  break;
479  case Mips::MIPSeh_return32:
480  case Mips::MIPSeh_return64:
481  expandEhReturn(MBB, MI);
482  break;
483  }
484 
485  MBB.erase(MI);
486  return true;
487 }
488 
489 /// getOppositeBranchOpc - Return the inverse of the specified
490 /// opcode, e.g. turning BEQ to BNE.
491 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
492  switch (Opc) {
493  default: llvm_unreachable("Illegal opcode!");
494  case Mips::BEQ: return Mips::BNE;
495  case Mips::BEQ_MM: return Mips::BNE_MM;
496  case Mips::BNE: return Mips::BEQ;
497  case Mips::BNE_MM: return Mips::BEQ_MM;
498  case Mips::BGTZ: return Mips::BLEZ;
499  case Mips::BGEZ: return Mips::BLTZ;
500  case Mips::BLTZ: return Mips::BGEZ;
501  case Mips::BLEZ: return Mips::BGTZ;
502  case Mips::BGTZ_MM: return Mips::BLEZ_MM;
503  case Mips::BGEZ_MM: return Mips::BLTZ_MM;
504  case Mips::BLTZ_MM: return Mips::BGEZ_MM;
505  case Mips::BLEZ_MM: return Mips::BGTZ_MM;
506  case Mips::BEQ64: return Mips::BNE64;
507  case Mips::BNE64: return Mips::BEQ64;
508  case Mips::BGTZ64: return Mips::BLEZ64;
509  case Mips::BGEZ64: return Mips::BLTZ64;
510  case Mips::BLTZ64: return Mips::BGEZ64;
511  case Mips::BLEZ64: return Mips::BGTZ64;
512  case Mips::BC1T: return Mips::BC1F;
513  case Mips::BC1F: return Mips::BC1T;
514  case Mips::BC1T_MM: return Mips::BC1F_MM;
515  case Mips::BC1F_MM: return Mips::BC1T_MM;
516  case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
517  case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
518  case Mips::BEQZC_MM: return Mips::BNEZC_MM;
519  case Mips::BNEZC_MM: return Mips::BEQZC_MM;
520  case Mips::BEQZC: return Mips::BNEZC;
521  case Mips::BNEZC: return Mips::BEQZC;
522  case Mips::BLEZC: return Mips::BGTZC;
523  case Mips::BGEZC: return Mips::BLTZC;
524  case Mips::BGEC: return Mips::BLTC;
525  case Mips::BGTZC: return Mips::BLEZC;
526  case Mips::BLTZC: return Mips::BGEZC;
527  case Mips::BLTC: return Mips::BGEC;
528  case Mips::BGEUC: return Mips::BLTUC;
529  case Mips::BLTUC: return Mips::BGEUC;
530  case Mips::BEQC: return Mips::BNEC;
531  case Mips::BNEC: return Mips::BEQC;
532  case Mips::BC1EQZ: return Mips::BC1NEZ;
533  case Mips::BC1NEZ: return Mips::BC1EQZ;
534  case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
535  case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
536  case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
537  case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
538  case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
539  case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
540  case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
541  case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
542  case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
543  case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
544  case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
545  case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
546  case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
547  case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
548  case Mips::BEQZC64: return Mips::BNEZC64;
549  case Mips::BNEZC64: return Mips::BEQZC64;
550  case Mips::BEQC64: return Mips::BNEC64;
551  case Mips::BNEC64: return Mips::BEQC64;
552  case Mips::BGEC64: return Mips::BLTC64;
553  case Mips::BGEUC64: return Mips::BLTUC64;
554  case Mips::BLTC64: return Mips::BGEC64;
555  case Mips::BLTUC64: return Mips::BGEUC64;
556  case Mips::BGTZC64: return Mips::BLEZC64;
557  case Mips::BGEZC64: return Mips::BLTZC64;
558  case Mips::BLTZC64: return Mips::BGEZC64;
559  case Mips::BLEZC64: return Mips::BGTZC64;
560  case Mips::BBIT0: return Mips::BBIT1;
561  case Mips::BBIT1: return Mips::BBIT0;
562  case Mips::BBIT032: return Mips::BBIT132;
563  case Mips::BBIT132: return Mips::BBIT032;
564  case Mips::BZ_B: return Mips::BNZ_B;
565  case Mips::BZ_H: return Mips::BNZ_H;
566  case Mips::BZ_W: return Mips::BNZ_W;
567  case Mips::BZ_D: return Mips::BNZ_D;
568  case Mips::BZ_V: return Mips::BNZ_V;
569  case Mips::BNZ_B: return Mips::BZ_B;
570  case Mips::BNZ_H: return Mips::BZ_H;
571  case Mips::BNZ_W: return Mips::BZ_W;
572  case Mips::BNZ_D: return Mips::BZ_D;
573  case Mips::BNZ_V: return Mips::BZ_V;
574  }
575 }
576 
577 /// Adjust SP by Amount bytes.
578 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
579  MachineBasicBlock &MBB,
581  MipsABIInfo ABI = Subtarget.getABI();
582  DebugLoc DL;
583  unsigned ADDiu = ABI.GetPtrAddiuOp();
584 
585  if (Amount == 0)
586  return;
587 
588  if (isInt<16>(Amount)) {
589  // addi sp, sp, amount
590  BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
591  } else {
592  // For numbers which are not 16bit integers we synthesize Amount inline
593  // then add or subtract it from sp.
594  unsigned Opc = ABI.GetPtrAdduOp();
595  if (Amount < 0) {
596  Opc = ABI.GetPtrSubuOp();
597  Amount = -Amount;
598  }
599  unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
600  BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
601  }
602 }
603 
604 /// This function generates the sequence of instructions needed to get the
605 /// result of adding register REG and immediate IMM.
608  const DebugLoc &DL,
609  unsigned *NewImm) const {
610  MipsAnalyzeImmediate AnalyzeImm;
611  const MipsSubtarget &STI = Subtarget;
612  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
613  unsigned Size = STI.isABI_N64() ? 64 : 32;
614  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
615  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
616  const TargetRegisterClass *RC = STI.isABI_N64() ?
617  &Mips::GPR64RegClass : &Mips::GPR32RegClass;
618  bool LastInstrIsADDiu = NewImm;
619 
620  const MipsAnalyzeImmediate::InstSeq &Seq =
621  AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
623 
624  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
625 
626  // The first instruction can be a LUi, which is different from other
627  // instructions (ADDiu, ORI and SLL) in that it does not have a register
628  // operand.
629  unsigned Reg = RegInfo.createVirtualRegister(RC);
630 
631  if (Inst->Opc == LUi)
632  BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
633  else
634  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
635  .addImm(SignExtend64<16>(Inst->ImmOpnd));
636 
637  // Build the remaining instructions in Seq.
638  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
639  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
640  .addImm(SignExtend64<16>(Inst->ImmOpnd));
641 
642  if (LastInstrIsADDiu)
643  *NewImm = Inst->ImmOpnd;
644 
645  return Reg;
646 }
647 
648 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
649  return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
650  Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
651  Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
652  Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
653  Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
654  Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
655  Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
656  Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
657  Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
658  Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
659  Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
660  Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
661  Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
662  Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
663  Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
664  Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
665  Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
666  Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
667  Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
668  Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
669  Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
670  Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
671  Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
672  Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
673 }
674 
675 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
677 
679  if (Subtarget.isGP64bit())
680  MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
681  .addReg(Mips::RA_64, RegState::Undef);
682  else
683  MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
685 
686  // Retain any imp-use flags.
687  for (auto & MO : I->operands()) {
688  if (MO.isImplicit())
689  MIB.add(MO);
690  }
691 }
692 
693 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
694  MachineBasicBlock::iterator I) const {
695  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
696 }
697 
698 std::pair<bool, bool>
699 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
700  const MachineFunction &MF) const {
701  const MCInstrDesc &Desc = get(Opc);
702  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
703  const MipsRegisterInfo *RI = &getRegisterInfo();
704  unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
705  unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
706 
707  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
708 }
709 
710 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
712  unsigned NewOpc) const {
713  BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
714 }
715 
716 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
718  unsigned LoOpc,
719  unsigned HiOpc,
720  bool HasExplicitDef) const {
721  // Expand
722  // lo_hi pseudomtlohi $gpr0, $gpr1
723  // to these two instructions:
724  // mtlo $gpr0
725  // mthi $gpr1
726 
727  DebugLoc DL = I->getDebugLoc();
728  const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
729  MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
730  MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
731 
732  // Add lo/hi registers if the mtlo/hi instructions created have explicit
733  // def registers.
734  if (HasExplicitDef) {
735  unsigned DstReg = I->getOperand(0).getReg();
736  unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
737  unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
738  LoInst.addReg(DstLo, RegState::Define);
739  HiInst.addReg(DstHi, RegState::Define);
740  }
741 
742  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
743  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
744 }
745 
746 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
748  unsigned CvtOpc, unsigned MovOpc,
749  bool IsI64) const {
750  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
751  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
752  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
753  unsigned KillSrc = getKillRegState(Src.isKill());
754  DebugLoc DL = I->getDebugLoc();
755  bool DstIsLarger, SrcIsLarger;
756 
757  std::tie(DstIsLarger, SrcIsLarger) =
758  compareOpndSize(CvtOpc, *MBB.getParent());
759 
760  if (DstIsLarger)
761  TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
762 
763  if (SrcIsLarger)
764  DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
765 
766  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
767  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
768 }
769 
770 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
772  bool isMicroMips,
773  bool FP64) const {
774  unsigned DstReg = I->getOperand(0).getReg();
775  unsigned SrcReg = I->getOperand(1).getReg();
776  unsigned N = I->getOperand(2).getImm();
777  DebugLoc dl = I->getDebugLoc();
778 
779  assert(N < 2 && "Invalid immediate");
780  unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
781  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
782 
783  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
784  // in MipsSEFrameLowering.cpp.
786 
787  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
788  // in MipsSEFrameLowering.cpp.
790 
791  if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
792  // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
793  // claim to read the whole 64-bits as part of a white lie used to
794  // temporarily work around a widespread bug in the -mfp64 support.
795  // The problem is that none of the 32-bit fpu ops mention the fact
796  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
797  // requires a major overhaul of the FPU implementation which can't
798  // be done right now due to time constraints.
799  // MFHC1 is one of two instructions that are affected since they are
800  // the only instructions that don't read the lower 32-bits.
801  // We therefore pretend that it reads the bottom 32-bits to
802  // artificially create a dependency and prevent the scheduler
803  // changing the behaviour of the code.
804  BuildMI(MBB, I, dl,
805  get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
806  : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
807  DstReg)
808  .addReg(SrcReg);
809  } else
810  BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
811 }
812 
813 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
815  bool isMicroMips, bool FP64) const {
816  unsigned DstReg = I->getOperand(0).getReg();
817  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
818  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
819  DebugLoc dl = I->getDebugLoc();
821 
822  // When mthc1 is available, use:
823  // mtc1 Lo, $fp
824  // mthc1 Hi, $fp
825  //
826  // Otherwise, for O32 FPXX ABI:
827  // spill + reload via ldc1
828  // This case is handled by the frame lowering code.
829  //
830  // Otherwise, for FP32:
831  // mtc1 Lo, $fp
832  // mtc1 Hi, $fp + 1
833  //
834  // The case where dmtc1 is available doesn't need to be handled here
835  // because it never creates a BuildPairF64 node.
836 
837  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
838  // in MipsSEFrameLowering.cpp.
840 
841  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
842  // in MipsSEFrameLowering.cpp.
844 
845  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
846  .addReg(LoReg);
847 
848  if (Subtarget.hasMTHC1()) {
849  // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
850  // around a widespread bug in the -mfp64 support.
851  // The problem is that none of the 32-bit fpu ops mention the fact
852  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
853  // requires a major overhaul of the FPU implementation which can't
854  // be done right now due to time constraints.
855  // MTHC1 is one of two instructions that are affected since they are
856  // the only instructions that don't read the lower 32-bits.
857  // We therefore pretend that it reads the bottom 32-bits to
858  // artificially create a dependency and prevent the scheduler
859  // changing the behaviour of the code.
860  BuildMI(MBB, I, dl,
861  get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
862  : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
863  DstReg)
864  .addReg(DstReg)
865  .addReg(HiReg);
866  } else if (Subtarget.isABI_FPXX())
867  llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
868  else
869  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
870  .addReg(HiReg);
871 }
872 
873 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
874  MachineBasicBlock::iterator I) const {
875  // This pseudo instruction is generated as part of the lowering of
876  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
877  // indirect jump to TargetReg
878  MipsABIInfo ABI = Subtarget.getABI();
879  unsigned ADDU = ABI.GetPtrAdduOp();
880  unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
881  unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
882  unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
883  unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
884  unsigned OffsetReg = I->getOperand(0).getReg();
885  unsigned TargetReg = I->getOperand(1).getReg();
886 
887  // addu $ra, $v0, $zero
888  // addu $sp, $sp, $v1
889  // jr $ra (via RetRA)
890  const TargetMachine &TM = MBB.getParent()->getTarget();
891  if (TM.isPositionIndependent())
892  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
893  .addReg(TargetReg)
894  .addReg(ZERO);
895  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
896  .addReg(TargetReg)
897  .addReg(ZERO);
898  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
899  expandRetRA(MBB, I);
900 }
901 
903  return new MipsSEInstrInfo(STI);
904 }
bool isABI_FPXX() const
const MachineInstrBuilder & add(const MachineOperand &MO) const
unsigned GetPtrAdduOp() const
Definition: MipsABIInfo.cpp:91
bool hasMTHC1() const
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:328
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:75
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned Reg
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
static unsigned getUnconditionalBranch(const MipsSubtarget &STI)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MipsSEInstrInfo(const MipsSubtarget &STI)
return AArch64::GPR64RegClass contains(Reg)
SI optimize exec mask operations pre RA
A description of a memory reference used in the backend.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool inMicroMipsMode() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned SubReg
bool isGP64bit() const
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:46
static int getRegClass(RegisterKind Is, unsigned RegWidth)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
unsigned getKillRegState(bool B)
unsigned short NumOperands
Definition: MCInstrDesc.h:166
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned GetPtrAddiuOp() const
Definition: MipsABIInfo.cpp:95
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZeroImm(const MachineOperand &op) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MipsABIInfo & getABI() const
The memory access writes data.
bool isPositionIndependent() const
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned GetPtrSubuOp() const
Definition: MipsABIInfo.cpp:99
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:706
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isPositionIndependent() const
static bool isORCopyInst(const MachineInstr &MI)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
uint32_t Size
Definition: Profile.cpp:47
bool useOddSPReg() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasMips32r2() const
bool isABI_N64() const
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite)
If is WRDSP/RRDSP instruction return true with set to true if it is WRDSP instruction.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isFP64bit() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...