LLVM  6.0.0svn
MipsTargetMachine.cpp
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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetMachine.h"
17 #include "Mips.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "MipsSEISelDAGToDAG.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CodeGen.h"
33 #include "llvm/Support/Debug.h"
37 #include <string>
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "mips"
42 
43 extern "C" void LLVMInitializeMipsTarget() {
44  // Register the target.
49 }
50 
51 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
52  const TargetOptions &Options,
53  bool isLittle) {
54  std::string Ret;
55  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
56 
57  // There are both little and big endian mips.
58  if (isLittle)
59  Ret += "e";
60  else
61  Ret += "E";
62 
63  if (ABI.IsO32())
64  Ret += "-m:m";
65  else
66  Ret += "-m:e";
67 
68  // Pointers are 32 bit on some ABIs.
69  if (!ABI.IsN64())
70  Ret += "-p:32:32";
71 
72  // 8 and 16 bit integers only need to have natural alignment, but try to
73  // align them to 32 bits. 64 bit integers have natural alignment.
74  Ret += "-i8:8:32-i16:16:32-i64:64";
75 
76  // 32 bit registers are always available and the stack is at least 64 bit
77  // aligned. On N64 64 bit registers are also available and the stack is
78  // 128 bit aligned.
79  if (ABI.IsN64() || ABI.IsN32())
80  Ret += "-n32:64-S128";
81  else
82  Ret += "-n32-S64";
83 
84  return Ret;
85 }
86 
89  if (!RM.hasValue() || JIT)
90  return Reloc::Static;
91  return *RM;
92 }
93 
95  if (CM)
96  return *CM;
97  return CodeModel::Small;
98 }
99 
100 // On function prologue, the stack is created by decrementing
101 // its pointer. Once decremented, all references are done with positive
102 // offset from the stack/frame pointer, using StackGrowsUp enables
103 // an easier handling.
104 // Using CodeModel::Large enables different CALL behavior.
106  StringRef CPU, StringRef FS,
107  const TargetOptions &Options,
110  CodeGenOpt::Level OL, bool JIT,
111  bool isLittle)
112  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
113  CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
114  getEffectiveCodeModel(CM), OL),
115  isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
116  ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
117  Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
118  Options.StackAlignmentOverride),
119  NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
120  isLittle, *this, Options.StackAlignmentOverride),
121  Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
122  isLittle, *this, Options.StackAlignmentOverride) {
123  Subtarget = &DefaultSubtarget;
124  initAsmInfo();
125 }
126 
128 
129 void MipsebTargetMachine::anchor() {}
130 
132  StringRef CPU, StringRef FS,
133  const TargetOptions &Options,
136  CodeGenOpt::Level OL, bool JIT)
137  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
138 
139 void MipselTargetMachine::anchor() {}
140 
142  StringRef CPU, StringRef FS,
143  const TargetOptions &Options,
146  CodeGenOpt::Level OL, bool JIT)
147  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
148 
149 const MipsSubtarget *
151  Attribute CPUAttr = F.getFnAttribute("target-cpu");
152  Attribute FSAttr = F.getFnAttribute("target-features");
153 
154  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
155  ? CPUAttr.getValueAsString().str()
156  : TargetCPU;
157  std::string FS = !FSAttr.hasAttribute(Attribute::None)
158  ? FSAttr.getValueAsString().str()
159  : TargetFS;
160  bool hasMips16Attr =
162  bool hasNoMips16Attr =
164 
165  bool HasMicroMipsAttr =
167  bool HasNoMicroMipsAttr =
168  !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
169 
170  // FIXME: This is related to the code below to reset the target options,
171  // we need to know whether or not the soft float flag is set on the
172  // function, so we can enable it as a subtarget feature.
173  bool softFloat =
174  F.hasFnAttribute("use-soft-float") &&
175  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
176 
177  if (hasMips16Attr)
178  FS += FS.empty() ? "+mips16" : ",+mips16";
179  else if (hasNoMips16Attr)
180  FS += FS.empty() ? "-mips16" : ",-mips16";
181  if (HasMicroMipsAttr)
182  FS += FS.empty() ? "+micromips" : ",+micromips";
183  else if (HasNoMicroMipsAttr)
184  FS += FS.empty() ? "-micromips" : ",-micromips";
185  if (softFloat)
186  FS += FS.empty() ? "+soft-float" : ",+soft-float";
187 
188  auto &I = SubtargetMap[CPU + FS];
189  if (!I) {
190  // This needs to be done before we create a new subtarget since any
191  // creation will depend on the TM and the code generation flags on the
192  // function that reside in TargetOptions.
194  I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this,
196  }
197  return I.get();
198 }
199 
201  DEBUG(dbgs() << "resetSubtarget\n");
202 
203  Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
204  MF->setSubtarget(Subtarget);
205 }
206 
207 namespace {
208 
209 /// Mips Code Generator Pass Configuration Options.
210 class MipsPassConfig : public TargetPassConfig {
211 public:
212  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
213  : TargetPassConfig(TM, PM) {
214  // The current implementation of long branch pass requires a scratch
215  // register ($at) to be available before branch instructions. Tail merging
216  // can break this requirement, so disable it when long branch pass is
217  // enabled.
218  EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
219  }
220 
221  MipsTargetMachine &getMipsTargetMachine() const {
222  return getTM<MipsTargetMachine>();
223  }
224 
225  const MipsSubtarget &getMipsSubtarget() const {
226  return *getMipsTargetMachine().getSubtargetImpl();
227  }
228 
229  void addIRPasses() override;
230  bool addInstSelector() override;
231  void addPreEmitPass() override;
232  void addPreRegAlloc() override;
233 };
234 
235 } // end anonymous namespace
236 
238  return new MipsPassConfig(*this, PM);
239 }
240 
241 void MipsPassConfig::addIRPasses() {
243  addPass(createAtomicExpandPass());
244  if (getMipsSubtarget().os16())
245  addPass(createMipsOs16Pass());
246  if (getMipsSubtarget().inMips16HardFloat())
247  addPass(createMips16HardFloatPass());
248 }
249 // Install an instruction selector pass using
250 // the ISelDag to gen Mips code.
251 bool MipsPassConfig::addInstSelector() {
252  addPass(createMipsModuleISelDagPass());
253  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
254  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
255  return false;
256 }
257 
258 void MipsPassConfig::addPreRegAlloc() {
260 }
261 
263  return TargetIRAnalysis([this](const Function &F) {
264  if (Subtarget->allowMixed16_32()) {
265  DEBUG(errs() << "No Target Transform Info Pass Added\n");
266  // FIXME: This is no longer necessary as the TTI returned is per-function.
268  }
269 
270  DEBUG(errs() << "Target Transform Info Pass Added\n");
271  return TargetTransformInfo(BasicTTIImpl(this, F));
272  });
273 }
274 
275 // Implemented by targets that want to run passes immediately before
276 // machine code is emitted. return true if -print-machineinstrs should
277 // print out the code after the passes.
278 void MipsPassConfig::addPreEmitPass() {
280 
281  // The delay slot filler and the long branch passes can potientially create
282  // forbidden slot/ hazards for MIPSR6 which the hazard schedule pass will
283  // fix. Any new pass must come before the hazard schedule pass.
285  addPass(createMipsLongBranchPass());
286  addPass(createMipsHazardSchedule());
287  addPass(createMipsConstantIslandPass());
288 }
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
MCTargetOptions MCOptions
Machine level options.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:76
FunctionPass * createMicroMipsSizeReductionPass()
Returns an instance of the MicroMips size reduction pass.
Target & getTheMipselTarget()
Analysis pass providing the TargetTransformInfo.
FunctionPass * createMipsDelaySlotFillerPass()
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions ...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
void resetSubtarget(MachineFunction *MF)
Reset the subtarget for the Mips target.
F(f)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:944
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
bool IsN32() const
Definition: MipsABIInfo.h:43
Target-Independent Code Generator Pass Configuration Options.
bool IsN64() const
Definition: MipsABIInfo.h:44
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
Target & getTheMips64Target()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
FunctionPass * createMipsHazardSchedule()
Returns a pass that clears pipeline hazards.
ModulePass * createMipsOs16Pass()
Definition: MipsOs16.cpp:158
const MipsSubtarget * getSubtargetImpl() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
Target & getTheMips64elTarget()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Concrete BasicTTIImpl that can be used if no further customization is needed.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
FunctionPass * createMipsOptimizePICCallPass()
Return an OptimizeCall object.
~MipsTargetMachine() override
void setSubtarget(const TargetSubtargetInfo *ST)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
bool IsO32() const
Definition: MipsABIInfo.h:42
FunctionPass * createMipsConstantIslandPass()
Returns a pass that converts branches to long branches.
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
FunctionPass * createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
ModulePass * createMips16HardFloatPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:77
Target & getTheMipsTarget()
Basic Alias true
bool hasValue() const
Definition: Optional.h:137
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
TargetOptions Options
Definition: TargetMachine.h:96
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionPass * createMipsLongBranchPass()
createMipsLongBranchPass - Returns a pass that converts branches to long branches.
FunctionPass * createMipsModuleISelDagPass()
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool isLittle)
std::string TargetFS
Definition: TargetMachine.h:78
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Definition: MipsABIInfo.cpp:50
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:270
#define DEBUG(X)
Definition: Debug.h:118
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
void LLVMInitializeMipsTarget()