LLVM  8.0.0svn
MipsTargetMachine.cpp
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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetMachine.h"
17 #include "Mips.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "MipsSEISelDAGToDAG.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
32 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/Debug.h"
41 #include <string>
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "mips"
46 
47 extern "C" void LLVMInitializeMipsTarget() {
48  // Register the target.
53 
59 }
60 
61 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
62  const TargetOptions &Options,
63  bool isLittle) {
64  std::string Ret;
65  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
66 
67  // There are both little and big endian mips.
68  if (isLittle)
69  Ret += "e";
70  else
71  Ret += "E";
72 
73  if (ABI.IsO32())
74  Ret += "-m:m";
75  else
76  Ret += "-m:e";
77 
78  // Pointers are 32 bit on some ABIs.
79  if (!ABI.IsN64())
80  Ret += "-p:32:32";
81 
82  // 8 and 16 bit integers only need to have natural alignment, but try to
83  // align them to 32 bits. 64 bit integers have natural alignment.
84  Ret += "-i8:8:32-i16:16:32-i64:64";
85 
86  // 32 bit registers are always available and the stack is at least 64 bit
87  // aligned. On N64 64 bit registers are also available and the stack is
88  // 128 bit aligned.
89  if (ABI.IsN64() || ABI.IsN32())
90  Ret += "-n32:64-S128";
91  else
92  Ret += "-n32-S64";
93 
94  return Ret;
95 }
96 
99  if (!RM.hasValue() || JIT)
100  return Reloc::Static;
101  return *RM;
102 }
103 
104 // On function prologue, the stack is created by decrementing
105 // its pointer. Once decremented, all references are done with positive
106 // offset from the stack/frame pointer, using StackGrowsUp enables
107 // an easier handling.
108 // Using CodeModel::Large enables different CALL behavior.
110  StringRef CPU, StringRef FS,
111  const TargetOptions &Options,
114  CodeGenOpt::Level OL, bool JIT,
115  bool isLittle)
116  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
117  CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
118  getEffectiveCodeModel(CM, CodeModel::Small), OL),
119  isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
120  ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
121  Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
122  Options.StackAlignmentOverride),
123  NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
124  isLittle, *this, Options.StackAlignmentOverride),
125  Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
126  isLittle, *this, Options.StackAlignmentOverride) {
127  Subtarget = &DefaultSubtarget;
128  initAsmInfo();
129 }
130 
132 
133 void MipsebTargetMachine::anchor() {}
134 
136  StringRef CPU, StringRef FS,
137  const TargetOptions &Options,
140  CodeGenOpt::Level OL, bool JIT)
141  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
142 
143 void MipselTargetMachine::anchor() {}
144 
146  StringRef CPU, StringRef FS,
147  const TargetOptions &Options,
150  CodeGenOpt::Level OL, bool JIT)
151  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
152 
153 const MipsSubtarget *
155  Attribute CPUAttr = F.getFnAttribute("target-cpu");
156  Attribute FSAttr = F.getFnAttribute("target-features");
157 
158  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
159  ? CPUAttr.getValueAsString().str()
160  : TargetCPU;
161  std::string FS = !FSAttr.hasAttribute(Attribute::None)
162  ? FSAttr.getValueAsString().str()
163  : TargetFS;
164  bool hasMips16Attr =
166  bool hasNoMips16Attr =
168 
169  bool HasMicroMipsAttr =
171  bool HasNoMicroMipsAttr =
172  !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
173 
174  // FIXME: This is related to the code below to reset the target options,
175  // we need to know whether or not the soft float flag is set on the
176  // function, so we can enable it as a subtarget feature.
177  bool softFloat =
178  F.hasFnAttribute("use-soft-float") &&
179  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
180 
181  if (hasMips16Attr)
182  FS += FS.empty() ? "+mips16" : ",+mips16";
183  else if (hasNoMips16Attr)
184  FS += FS.empty() ? "-mips16" : ",-mips16";
185  if (HasMicroMipsAttr)
186  FS += FS.empty() ? "+micromips" : ",+micromips";
187  else if (HasNoMicroMipsAttr)
188  FS += FS.empty() ? "-micromips" : ",-micromips";
189  if (softFloat)
190  FS += FS.empty() ? "+soft-float" : ",+soft-float";
191 
192  auto &I = SubtargetMap[CPU + FS];
193  if (!I) {
194  // This needs to be done before we create a new subtarget since any
195  // creation will depend on the TM and the code generation flags on the
196  // function that reside in TargetOptions.
198  I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this,
200  }
201  return I.get();
202 }
203 
205  LLVM_DEBUG(dbgs() << "resetSubtarget\n");
206 
207  Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction()));
208  MF->setSubtarget(Subtarget);
209 }
210 
211 namespace {
212 
213 /// Mips Code Generator Pass Configuration Options.
214 class MipsPassConfig : public TargetPassConfig {
215 public:
216  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
217  : TargetPassConfig(TM, PM) {
218  // The current implementation of long branch pass requires a scratch
219  // register ($at) to be available before branch instructions. Tail merging
220  // can break this requirement, so disable it when long branch pass is
221  // enabled.
222  EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
223  }
224 
225  MipsTargetMachine &getMipsTargetMachine() const {
226  return getTM<MipsTargetMachine>();
227  }
228 
229  const MipsSubtarget &getMipsSubtarget() const {
230  return *getMipsTargetMachine().getSubtargetImpl();
231  }
232 
233  void addIRPasses() override;
234  bool addInstSelector() override;
235  void addPreEmitPass() override;
236  void addPreRegAlloc() override;
237  bool addIRTranslator() override;
238  bool addLegalizeMachineIR() override;
239  bool addRegBankSelect() override;
240  bool addGlobalInstructionSelect() override;
241 };
242 
243 } // end anonymous namespace
244 
246  return new MipsPassConfig(*this, PM);
247 }
248 
249 void MipsPassConfig::addIRPasses() {
251  addPass(createAtomicExpandPass());
252  if (getMipsSubtarget().os16())
253  addPass(createMipsOs16Pass());
254  if (getMipsSubtarget().inMips16HardFloat())
255  addPass(createMips16HardFloatPass());
256 }
257 // Install an instruction selector pass using
258 // the ISelDag to gen Mips code.
259 bool MipsPassConfig::addInstSelector() {
260  addPass(createMipsModuleISelDagPass());
261  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
262  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
263  return false;
264 }
265 
266 void MipsPassConfig::addPreRegAlloc() {
268 }
269 
272  if (Subtarget->allowMixed16_32()) {
273  LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
274  // FIXME: This is no longer necessary as the TTI returned is per-function.
276  }
277 
278  LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
279  return TargetTransformInfo(BasicTTIImpl(this, F));
280 }
281 
282 // Implemented by targets that want to run passes immediately before
283 // machine code is emitted. return true if -print-machineinstrs should
284 // print out the code after the passes.
285 void MipsPassConfig::addPreEmitPass() {
286  // Expand pseudo instructions that are sensitive to register allocation.
287  addPass(createMipsExpandPseudoPass());
288 
289  // The microMIPS size reduction pass performs instruction reselection for
290  // instructions which can be remapped to a 16 bit instruction.
292 
293  // The delay slot filler pass can potientially create forbidden slot hazards
294  // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
296 
297  // This pass expands branches and takes care about the forbidden slot hazards.
298  // Expanding branches may potentially create forbidden slot hazards for
299  // MIPSR6, and fixing such hazard may potentially break a branch by extending
300  // its offset out of range. That's why this pass combine these two tasks, and
301  // runs them alternately until one of them finishes without any changes. Only
302  // then we can be sure that all branches are expanded properly and no hazards
303  // exists.
304  // Any new pass should go before this pass.
305  addPass(createMipsBranchExpansion());
306 
307  addPass(createMipsConstantIslandPass());
308 }
309 
310 bool MipsPassConfig::addIRTranslator() {
311  addPass(new IRTranslator());
312  return false;
313 }
314 
315 bool MipsPassConfig::addLegalizeMachineIR() {
316  addPass(new Legalizer());
317  return false;
318 }
319 
320 bool MipsPassConfig::addRegBankSelect() {
321  addPass(new RegBankSelect());
322  return false;
323 }
324 
325 bool MipsPassConfig::addGlobalInstructionSelect() {
326  addPass(new InstructionSelect());
327  return false;
328 }
void initializeMipsBranchExpansionPass(PassRegistry &)
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
MCTargetOptions MCOptions
Machine level options.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
FunctionPass * createMipsBranchExpansion()
Target & getTheMipselTarget()
FunctionPass * createMipsDelaySlotFillerPass()
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions ...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
void resetSubtarget(MachineFunction *MF)
Reset the subtarget for the Mips target.
F(f)
block Block Frequency true
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1343
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:365
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
bool IsN32() const
Definition: MipsABIInfo.h:43
Target-Independent Code Generator Pass Configuration Options.
bool IsN64() const
Definition: MipsABIInfo.h:44
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
Target & getTheMips64Target()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
ModulePass * createMipsOs16Pass()
Definition: MipsOs16.cpp:160
const MipsSubtarget * getSubtargetImpl() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
Target & getTheMips64elTarget()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Concrete BasicTTIImpl that can be used if no further customization is needed.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
FunctionPass * createMipsOptimizePICCallPass()
Return an OptimizeCall object.
~MipsTargetMachine() override
void setSubtarget(const TargetSubtargetInfo *ST)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
bool IsO32() const
Definition: MipsABIInfo.h:42
FunctionPass * createMipsConstantIslandPass()
Returns a pass that converts branches to long branches.
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
FunctionPass * createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
ModulePass * createMips16HardFloatPass()
FunctionPass * createMipsExpandPseudoPass()
createMipsExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:204
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This pass is responsible for selecting generic machine instructions to target-specific instructions...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:79
void initializeMicroMipsSizeReducePass(PassRegistry &)
Target & getTheMipsTarget()
FunctionPass * createMicroMipsSizeReducePass()
Returns an instance of the MicroMips size reduction pass.
bool hasValue() const
Definition: Optional.h:165
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
TargetOptions Options
Definition: TargetMachine.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionPass * createMipsModuleISelDagPass()
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool isLittle)
std::string TargetFS
Definition: TargetMachine.h:80
This file declares the IRTranslator pass.
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Definition: MipsABIInfo.cpp:50
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
void initializeMipsDelaySlotFillerPass(PassRegistry &)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void LLVMInitializeMipsTarget()