LLVM  9.0.0svn
MipsTargetStreamer.cpp
Go to the documentation of this file.
1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSymbolELF.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33  "mips-round-section-sizes", cl::init(false),
34  cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
38  : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40 }
63 }
73 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
74  unsigned ReturnReg) {}
75 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
76 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
77 }
80 }
101 }
104 }
110  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
111  const MCSubtargetInfo *STI) {
113  return true;
114 }
115 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
116  const MCSymbol &Sym, bool IsReg) {
117 }
118 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
119  bool SaveLocationIsRegister) {}
120 
122 
125  report_fatal_error("+nooddspreg is only valid for O32");
126 }
139 }
143 }
144 
145 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
146  const MCSubtargetInfo *STI) {
147  MCInst TmpInst;
148  TmpInst.setOpcode(Opcode);
149  TmpInst.addOperand(MCOperand::createReg(Reg0));
150  TmpInst.setLoc(IDLoc);
151  getStreamer().EmitInstruction(TmpInst, *STI);
152 }
153 
154 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
155  SMLoc IDLoc, const MCSubtargetInfo *STI) {
156  MCInst TmpInst;
157  TmpInst.setOpcode(Opcode);
158  TmpInst.addOperand(MCOperand::createReg(Reg0));
159  TmpInst.addOperand(Op1);
160  TmpInst.setLoc(IDLoc);
161  getStreamer().EmitInstruction(TmpInst, *STI);
162 }
163 
164 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
165  SMLoc IDLoc, const MCSubtargetInfo *STI) {
166  emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
167 }
168 
169 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
170  SMLoc IDLoc, const MCSubtargetInfo *STI) {
171  emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
172 }
173 
174 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
175  SMLoc IDLoc, const MCSubtargetInfo *STI) {
176  MCInst TmpInst;
177  TmpInst.setOpcode(Opcode);
178  TmpInst.addOperand(MCOperand::createImm(Imm1));
179  TmpInst.addOperand(MCOperand::createImm(Imm2));
180  TmpInst.setLoc(IDLoc);
181  getStreamer().EmitInstruction(TmpInst, *STI);
182 }
183 
184 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
185  MCOperand Op2, SMLoc IDLoc,
186  const MCSubtargetInfo *STI) {
187  MCInst TmpInst;
188  TmpInst.setOpcode(Opcode);
189  TmpInst.addOperand(MCOperand::createReg(Reg0));
190  TmpInst.addOperand(MCOperand::createReg(Reg1));
191  TmpInst.addOperand(Op2);
192  TmpInst.setLoc(IDLoc);
193  getStreamer().EmitInstruction(TmpInst, *STI);
194 }
195 
196 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
197  unsigned Reg2, SMLoc IDLoc,
198  const MCSubtargetInfo *STI) {
199  emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
200 }
201 
202 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
203  int16_t Imm, SMLoc IDLoc,
204  const MCSubtargetInfo *STI) {
205  emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
206 }
207 
208 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
209  unsigned Reg1, int16_t Imm0, int16_t Imm1,
210  int16_t Imm2, SMLoc IDLoc,
211  const MCSubtargetInfo *STI) {
212  MCInst TmpInst;
213  TmpInst.setOpcode(Opcode);
214  TmpInst.addOperand(MCOperand::createReg(Reg0));
215  TmpInst.addOperand(MCOperand::createReg(Reg1));
216  TmpInst.addOperand(MCOperand::createImm(Imm0));
217  TmpInst.addOperand(MCOperand::createImm(Imm1));
218  TmpInst.addOperand(MCOperand::createImm(Imm2));
219  TmpInst.setLoc(IDLoc);
220  getStreamer().EmitInstruction(TmpInst, *STI);
221 }
222 
223 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
224  unsigned TrgReg, bool Is64Bit,
225  const MCSubtargetInfo *STI) {
226  emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
227  STI);
228 }
229 
230 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
231  int16_t ShiftAmount, SMLoc IDLoc,
232  const MCSubtargetInfo *STI) {
233  if (ShiftAmount >= 32) {
234  emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
235  return;
236  }
237 
238  emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
239 }
240 
242  const MCSubtargetInfo *STI) {
243  if (hasShortDelaySlot)
244  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
245  else
246  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
247 }
248 
250  const FeatureBitset &Features = STI->getFeatureBits();
251  if (Features[Mips::FeatureMicroMips])
252  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
253  else
254  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
255 }
256 
257 /// Emit the $gp restore operation for .cprestore.
259  const MCSubtargetInfo *STI) {
260  emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
261  STI);
262 }
263 
264 /// Emit a store instruction with an immediate offset.
266  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
267  function_ref<unsigned()> GetATReg, SMLoc IDLoc,
268  const MCSubtargetInfo *STI) {
269  if (isInt<16>(Offset)) {
270  emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
271  return;
272  }
273 
274  // sw $8, offset($8) => lui $at, %hi(offset)
275  // add $at, $at, $8
276  // sw $8, %lo(offset)($at)
277 
278  unsigned ATReg = GetATReg();
279  if (!ATReg)
280  return;
281 
282  unsigned LoOffset = Offset & 0x0000ffff;
283  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
284 
285  // If msb of LoOffset is 1(negative number) we must increment HiOffset
286  // to account for the sign-extension of the low part.
287  if (LoOffset & 0x8000)
288  HiOffset++;
289 
290  // Generate the base address in ATReg.
291  emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
292  if (BaseReg != Mips::ZERO)
293  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
294  // Emit the store with the adjusted base and offset.
295  emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
296 }
297 
298 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
299 /// out of range for a simm16 will be expanded to appropriate instructions.
301  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
302  MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
303  const MCSubtargetInfo *STI) {
304  // sw $8, sym => lui $at, %hi(sym)
305  // sw $8, %lo(sym)($at)
306 
307  // Generate the base address in ATReg.
308  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
309  if (BaseReg != Mips::ZERO)
310  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
311  // Emit the store with the adjusted base and offset.
312  emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
313 }
314 
315 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
316 /// permitted to be the same register iff DstReg is distinct from BaseReg and
317 /// DstReg is a GPR. It is the callers responsibility to identify such cases
318 /// and pass the appropriate register in TmpReg.
319 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
320  unsigned BaseReg, int64_t Offset,
321  unsigned TmpReg, SMLoc IDLoc,
322  const MCSubtargetInfo *STI) {
323  if (isInt<16>(Offset)) {
324  emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
325  return;
326  }
327 
328  // 1) lw $8, offset($9) => lui $8, %hi(offset)
329  // add $8, $8, $9
330  // lw $8, %lo(offset)($9)
331  // 2) lw $8, offset($8) => lui $at, %hi(offset)
332  // add $at, $at, $8
333  // lw $8, %lo(offset)($at)
334 
335  unsigned LoOffset = Offset & 0x0000ffff;
336  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
337 
338  // If msb of LoOffset is 1(negative number) we must increment HiOffset
339  // to account for the sign-extension of the low part.
340  if (LoOffset & 0x8000)
341  HiOffset++;
342 
343  // Generate the base address in TmpReg.
344  emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
345  if (BaseReg != Mips::ZERO)
346  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
347  // Emit the load with the adjusted base and offset.
348  emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
349 }
350 
351 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
352 /// out of range for a simm16 will be expanded to appropriate instructions.
353 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
354 /// GPR. It is the callers responsibility to identify such cases and pass the
355 /// appropriate register in TmpReg.
356 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
357  unsigned BaseReg,
358  MCOperand &HiOperand,
359  MCOperand &LoOperand,
360  unsigned TmpReg, SMLoc IDLoc,
361  const MCSubtargetInfo *STI) {
362  // 1) lw $8, sym => lui $8, %hi(sym)
363  // lw $8, %lo(sym)($8)
364  // 2) ldc1 $f0, sym => lui $at, %hi(sym)
365  // ldc1 $f0, %lo(sym)($at)
366 
367  // Generate the base address in TmpReg.
368  emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
369  if (BaseReg != Mips::ZERO)
370  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
371  // Emit the load with the adjusted base and offset.
372  emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
373 }
374 
377  : MipsTargetStreamer(S), OS(OS) {}
378 
380  OS << "\t.set\tmicromips\n";
382 }
383 
385  OS << "\t.set\tnomicromips\n";
387 }
388 
390  OS << "\t.set\tmips16\n";
392 }
393 
395  OS << "\t.set\tnomips16\n";
397 }
398 
400  OS << "\t.set\treorder\n";
402 }
403 
405  OS << "\t.set\tnoreorder\n";
407 }
408 
410  OS << "\t.set\tmacro\n";
412 }
413 
415  OS << "\t.set\tnomacro\n";
417 }
418 
420  OS << "\t.set\tmsa\n";
422 }
423 
425  OS << "\t.set\tnomsa\n";
427 }
428 
430  OS << "\t.set\tmt\n";
432 }
433 
435  OS << "\t.set\tnomt\n";
437 }
438 
440  OS << "\t.set\tcrc\n";
442 }
443 
445  OS << "\t.set\tnocrc\n";
447 }
448 
450  OS << "\t.set\tvirt\n";
452 }
453 
455  OS << "\t.set\tnovirt\n";
457 }
458 
460  OS << "\t.set\tginv\n";
462 }
463 
465  OS << "\t.set\tnoginv\n";
467 }
468 
470  OS << "\t.set\tat\n";
472 }
473 
475  OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
477 }
478 
480  OS << "\t.set\tnoat\n";
482 }
483 
485  OS << "\t.end\t" << Name << '\n';
486 }
487 
489  OS << "\t.ent\t" << Symbol.getName() << '\n';
490 }
491 
492 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
493 
494 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
495 
497  OS << "\t.nan\tlegacy\n";
498 }
499 
501  OS << "\t.option\tpic0\n";
502 }
503 
505  OS << "\t.option\tpic2\n";
506 }
507 
510  OS << "\t.insn\n";
511 }
512 
513 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
514  unsigned ReturnReg) {
515  OS << "\t.frame\t$"
516  << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
517  << StackSize << ",$"
518  << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
519 }
520 
522  OS << "\t.set arch=" << Arch << "\n";
524 }
525 
527  OS << "\t.set\tmips0\n";
529 }
530 
532  OS << "\t.set\tmips1\n";
534 }
535 
537  OS << "\t.set\tmips2\n";
539 }
540 
542  OS << "\t.set\tmips3\n";
544 }
545 
547  OS << "\t.set\tmips4\n";
549 }
550 
552  OS << "\t.set\tmips5\n";
554 }
555 
557  OS << "\t.set\tmips32\n";
559 }
560 
562  OS << "\t.set\tmips32r2\n";
564 }
565 
567  OS << "\t.set\tmips32r3\n";
569 }
570 
572  OS << "\t.set\tmips32r5\n";
574 }
575 
577  OS << "\t.set\tmips32r6\n";
579 }
580 
582  OS << "\t.set\tmips64\n";
584 }
585 
587  OS << "\t.set\tmips64r2\n";
589 }
590 
592  OS << "\t.set\tmips64r3\n";
594 }
595 
597  OS << "\t.set\tmips64r5\n";
599 }
600 
602  OS << "\t.set\tmips64r6\n";
604 }
605 
607  OS << "\t.set\tdsp\n";
609 }
610 
612  OS << "\t.set\tdspr2\n";
614 }
615 
617  OS << "\t.set\tnodsp\n";
619 }
620 
622  OS << "\t.set\tpop\n";
624 }
625 
627  OS << "\t.set\tpush\n";
629 }
630 
632  OS << "\t.set\tsoftfloat\n";
634 }
635 
637  OS << "\t.set\thardfloat\n";
639 }
640 
641 // Print a 32 bit hex number with all numbers.
642 static void printHex32(unsigned Value, raw_ostream &OS) {
643  OS << "0x";
644  for (int i = 7; i >= 0; i--)
645  OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
646 }
647 
648 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
649  int CPUTopSavedRegOff) {
650  OS << "\t.mask \t";
651  printHex32(CPUBitmask, OS);
652  OS << ',' << CPUTopSavedRegOff << '\n';
653 }
654 
655 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
656  int FPUTopSavedRegOff) {
657  OS << "\t.fmask\t";
658  printHex32(FPUBitmask, OS);
659  OS << "," << FPUTopSavedRegOff << '\n';
660 }
661 
663  OS << "\t.cpload\t$"
664  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
666 }
667 
669  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
670  const MCSubtargetInfo *STI) {
671  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
672  OS << "\t.cprestore\t" << Offset << "\n";
673  return true;
674 }
675 
677  int RegOrOffset,
678  const MCSymbol &Sym,
679  bool IsReg) {
680  OS << "\t.cpsetup\t$"
681  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
682 
683  if (IsReg)
684  OS << "$"
686  else
687  OS << RegOrOffset;
688 
689  OS << ", ";
690 
691  OS << Sym.getName();
693 }
694 
696  bool SaveLocationIsRegister) {
697  OS << "\t.cpreturn";
699 }
700 
702  OS << "\t.module\tfp=";
704 }
705 
709 
710  OS << "\t.set\tfp=";
711  OS << ABIFlagsSection.getFpABIString(Value) << "\n";
712 }
713 
716 
717  OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
718 }
719 
722  OS << "\t.set\toddspreg\n";
723 }
724 
727  OS << "\t.set\tnooddspreg\n";
728 }
729 
731  OS << "\t.module\tsoftfloat\n";
732 }
733 
735  OS << "\t.module\thardfloat\n";
736 }
737 
739  OS << "\t.module\tmt\n";
740 }
741 
743  OS << "\t.module\tcrc\n";
744 }
745 
747  OS << "\t.module\tnocrc\n";
748 }
749 
751  OS << "\t.module\tvirt\n";
752 }
753 
755  OS << "\t.module\tnovirt\n";
756 }
757 
759  OS << "\t.module\tginv\n";
760 }
761 
763  OS << "\t.module\tnoginv\n";
764 }
765 
766 // This part is for ELF object output.
768  const MCSubtargetInfo &STI)
769  : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
771 
772  // It's possible that MCObjectFileInfo isn't fully initialized at this point
773  // due to an initialization order problem where LLVMTargetMachine creates the
774  // target streamer before TargetLoweringObjectFile calls
775  // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
776  // covers all cases so this statement covers most cases and direct object
777  // emission must call setPic() once MCObjectFileInfo has been initialized. The
778  // cases we don't handle here are covered by MipsAsmPrinter.
780 
781  const FeatureBitset &Features = STI.getFeatureBits();
782 
783  // Set the header flags that we can in the constructor.
784  // FIXME: This is a fairly terrible hack. We set the rest
785  // of these in the destructor. The problem here is two-fold:
786  //
787  // a: Some of the eflags can be set/reset by directives.
788  // b: There aren't any usage paths that initialize the ABI
789  // pointer until after we initialize either an assembler
790  // or the target machine.
791  // We can fix this by making the target streamer construct
792  // the ABI, but this is fraught with wide ranging dependency
793  // issues as well.
794  unsigned EFlags = MCA.getELFHeaderEFlags();
795 
796  // FIXME: Fix a dependency issue by instantiating the ABI object to some
797  // default based off the triple. The triple doesn't describe the target
798  // fully, but any external user of the API that uses the MCTargetStreamer
799  // would otherwise crash on assertion failure.
800 
801  ABI = MipsABIInfo(
802  STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
803  STI.getTargetTriple().getArch() == Triple::ArchType::mips
804  ? MipsABIInfo::O32()
805  : MipsABIInfo::N64());
806 
807  // Architecture
808  if (Features[Mips::FeatureMips64r6])
809  EFlags |= ELF::EF_MIPS_ARCH_64R6;
810  else if (Features[Mips::FeatureMips64r2] ||
811  Features[Mips::FeatureMips64r3] ||
812  Features[Mips::FeatureMips64r5])
813  EFlags |= ELF::EF_MIPS_ARCH_64R2;
814  else if (Features[Mips::FeatureMips64])
815  EFlags |= ELF::EF_MIPS_ARCH_64;
816  else if (Features[Mips::FeatureMips5])
817  EFlags |= ELF::EF_MIPS_ARCH_5;
818  else if (Features[Mips::FeatureMips4])
819  EFlags |= ELF::EF_MIPS_ARCH_4;
820  else if (Features[Mips::FeatureMips3])
821  EFlags |= ELF::EF_MIPS_ARCH_3;
822  else if (Features[Mips::FeatureMips32r6])
823  EFlags |= ELF::EF_MIPS_ARCH_32R6;
824  else if (Features[Mips::FeatureMips32r2] ||
825  Features[Mips::FeatureMips32r3] ||
826  Features[Mips::FeatureMips32r5])
827  EFlags |= ELF::EF_MIPS_ARCH_32R2;
828  else if (Features[Mips::FeatureMips32])
829  EFlags |= ELF::EF_MIPS_ARCH_32;
830  else if (Features[Mips::FeatureMips2])
831  EFlags |= ELF::EF_MIPS_ARCH_2;
832  else
833  EFlags |= ELF::EF_MIPS_ARCH_1;
834 
835  // Machine
836  if (Features[Mips::FeatureCnMips])
837  EFlags |= ELF::EF_MIPS_MACH_OCTEON;
838 
839  // Other options.
840  if (Features[Mips::FeatureNaN2008])
841  EFlags |= ELF::EF_MIPS_NAN2008;
842 
843  MCA.setELFHeaderEFlags(EFlags);
844 }
845 
847  auto *Symbol = cast<MCSymbolELF>(S);
849  uint8_t Type = Symbol->getType();
850  if (Type != ELF::STT_FUNC)
851  return;
852 
853  if (isMicroMipsEnabled())
854  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
855 }
856 
859  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
860 
861  // .bss, .text and .data are always at least 16-byte aligned.
862  MCSection &TextSection = *OFI.getTextSection();
863  MCA.registerSection(TextSection);
864  MCSection &DataSection = *OFI.getDataSection();
865  MCA.registerSection(DataSection);
866  MCSection &BSSSection = *OFI.getBSSSection();
867  MCA.registerSection(BSSSection);
868 
869  TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
870  DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
871  BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
872 
873  if (RoundSectionSizes) {
874  // Make sections sizes a multiple of the alignment. This is useful for
875  // verifying the output of IAS against the output of other assemblers but
876  // it's not necessary to produce a correct object and increases section
877  // size.
878  MCStreamer &OS = getStreamer();
879  for (MCSection &S : MCA) {
880  MCSectionELF &Section = static_cast<MCSectionELF &>(S);
881 
882  unsigned Alignment = Section.getAlignment();
883  if (Alignment) {
884  OS.SwitchSection(&Section);
885  if (Section.UseCodeAlign())
886  OS.EmitCodeAlignment(Alignment, Alignment);
887  else
888  OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
889  }
890  }
891  }
892 
893  const FeatureBitset &Features = STI.getFeatureBits();
894 
895  // Update e_header flags. See the FIXME and comment above in
896  // the constructor for a full rundown on this.
897  unsigned EFlags = MCA.getELFHeaderEFlags();
898 
899  // ABI
900  // N64 does not require any ABI bits.
901  if (getABI().IsO32())
902  EFlags |= ELF::EF_MIPS_ABI_O32;
903  else if (getABI().IsN32())
904  EFlags |= ELF::EF_MIPS_ABI2;
905 
906  if (Features[Mips::FeatureGP64Bit]) {
907  if (getABI().IsO32())
908  EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
909  } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
910  EFlags |= ELF::EF_MIPS_32BITMODE;
911 
912  // -mplt is not implemented but we should act as if it was
913  // given.
914  if (!Features[Mips::FeatureNoABICalls])
915  EFlags |= ELF::EF_MIPS_CPIC;
916 
917  if (Pic)
919 
920  MCA.setELFHeaderEFlags(EFlags);
921 
922  // Emit all the option records.
923  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
924  // .reginfo.
925  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
926  MEF.EmitMipsOptionRecords();
927 
929 }
930 
932  auto *Symbol = cast<MCSymbolELF>(S);
933  // If on rhs is micromips symbol then mark Symbol as microMips.
934  if (Value->getKind() != MCExpr::SymbolRef)
935  return;
936  const auto &RhsSym = cast<MCSymbolELF>(
937  static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
938 
939  if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
940  return;
941 
942  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
943 }
944 
946  return static_cast<MCELFStreamer &>(Streamer);
947 }
948 
950  MicroMipsEnabled = true;
952 }
953 
955  MicroMipsEnabled = false;
957 }
958 
961  unsigned Flags = MCA.getELFHeaderEFlags();
962  Flags |= ELF::EF_MIPS_MICROMIPS;
963  MCA.setELFHeaderEFlags(Flags);
964 }
965 
968  unsigned Flags = MCA.getELFHeaderEFlags();
969  Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
970  MCA.setELFHeaderEFlags(Flags);
972 }
973 
976  unsigned Flags = MCA.getELFHeaderEFlags();
977  Flags |= ELF::EF_MIPS_NOREORDER;
978  MCA.setELFHeaderEFlags(Flags);
980 }
981 
984  MCContext &Context = MCA.getContext();
985  MCStreamer &OS = getStreamer();
986 
987  MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
988 
989  MCSymbol *Sym = Context.getOrCreateSymbol(Name);
990  const MCSymbolRefExpr *ExprRef =
992 
993  MCA.registerSection(*Sec);
994  Sec->setAlignment(4);
995 
996  OS.PushSection();
997 
998  OS.SwitchSection(Sec);
999 
1000  OS.EmitValueImpl(ExprRef, 4);
1001 
1002  OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1003  OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
1004 
1005  OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1006  OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
1007 
1008  OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1009  OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
1010  OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
1011 
1012  // The .end directive marks the end of a procedure. Invalidate
1013  // the information gathered up until this point.
1014  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1015 
1016  OS.PopSection();
1017 
1018  // .end also implicitly sets the size.
1019  MCSymbol *CurPCSym = Context.createTempSymbol();
1020  OS.EmitLabel(CurPCSym);
1023  ExprRef, Context);
1024 
1025  // The ELFObjectWriter can determine the absolute size as it has access to
1026  // the layout information of the assembly file, so a size expression rather
1027  // than an absolute value is ok here.
1028  static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1029 }
1030 
1032  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1033 
1034  // .ent also acts like an implicit '.type symbol, STT_FUNC'
1035  static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1036 }
1037 
1040  unsigned Flags = MCA.getELFHeaderEFlags();
1042  MCA.setELFHeaderEFlags(Flags);
1043 }
1044 
1047  unsigned Flags = MCA.getELFHeaderEFlags();
1048  Flags |= ELF::EF_MIPS_NAN2008;
1049  MCA.setELFHeaderEFlags(Flags);
1050 }
1051 
1054  unsigned Flags = MCA.getELFHeaderEFlags();
1055  Flags &= ~ELF::EF_MIPS_NAN2008;
1056  MCA.setELFHeaderEFlags(Flags);
1057 }
1058 
1061  unsigned Flags = MCA.getELFHeaderEFlags();
1062  // This option overrides other PIC options like -KPIC.
1063  Pic = false;
1064  Flags &= ~ELF::EF_MIPS_PIC;
1065  MCA.setELFHeaderEFlags(Flags);
1066 }
1067 
1070  unsigned Flags = MCA.getELFHeaderEFlags();
1071  Pic = true;
1072  // NOTE: We are following the GAS behaviour here which means the directive
1073  // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1074  // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1075  // EF_MIPS_CPIC to be mutually exclusive.
1077  MCA.setELFHeaderEFlags(Flags);
1078 }
1079 
1082  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1084 }
1085 
1086 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1087  unsigned ReturnReg_) {
1089  const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1090 
1091  FrameInfoSet = true;
1092  FrameReg = RegInfo->getEncodingValue(StackReg);
1093  FrameOffset = StackSize;
1094  ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1095 }
1096 
1097 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1098  int CPUTopSavedRegOff) {
1099  GPRInfoSet = true;
1100  GPRBitMask = CPUBitmask;
1101  GPROffset = CPUTopSavedRegOff;
1102 }
1103 
1104 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1105  int FPUTopSavedRegOff) {
1106  FPRInfoSet = true;
1107  FPRBitMask = FPUBitmask;
1108  FPROffset = FPUTopSavedRegOff;
1109 }
1110 
1112  // .cpload $reg
1113  // This directive expands to:
1114  // lui $gp, %hi(_gp_disp)
1115  // addui $gp, $gp, %lo(_gp_disp)
1116  // addu $gp, $gp, $reg
1117  // when support for position independent code is enabled.
1118  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1119  return;
1120 
1121  // There's a GNU extension controlled by -mno-shared that allows
1122  // locally-binding symbols to be accessed using absolute addresses.
1123  // This is currently not supported. When supported -mno-shared makes
1124  // .cpload expand to:
1125  // lui $gp, %hi(__gnu_local_gp)
1126  // addiu $gp, $gp, %lo(__gnu_local_gp)
1127 
1128  StringRef SymName("_gp_disp");
1130  MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1131  MCA.registerSymbol(*GP_Disp);
1132 
1133  MCInst TmpInst;
1134  TmpInst.setOpcode(Mips::LUi);
1135  TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1136  const MCExpr *HiSym = MipsMCExpr::create(
1139  MCA.getContext()),
1140  MCA.getContext());
1141  TmpInst.addOperand(MCOperand::createExpr(HiSym));
1142  getStreamer().EmitInstruction(TmpInst, STI);
1143 
1144  TmpInst.clear();
1145 
1146  TmpInst.setOpcode(Mips::ADDiu);
1147  TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1148  TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1149  const MCExpr *LoSym = MipsMCExpr::create(
1152  MCA.getContext()),
1153  MCA.getContext());
1154  TmpInst.addOperand(MCOperand::createExpr(LoSym));
1155  getStreamer().EmitInstruction(TmpInst, STI);
1156 
1157  TmpInst.clear();
1158 
1159  TmpInst.setOpcode(Mips::ADDu);
1160  TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1161  TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1162  TmpInst.addOperand(MCOperand::createReg(RegNo));
1163  getStreamer().EmitInstruction(TmpInst, STI);
1164 
1166 }
1167 
1169  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1170  const MCSubtargetInfo *STI) {
1171  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1172  // .cprestore offset
1173  // When PIC mode is enabled and the O32 ABI is used, this directive expands
1174  // to:
1175  // sw $gp, offset($sp)
1176  // and adds a corresponding LW after every JAL.
1177 
1178  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1179  // is used in non-PIC mode.
1180  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1181  return true;
1182 
1183  // Store the $gp on the stack.
1184  emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1185  STI);
1186  return true;
1187 }
1188 
1190  int RegOrOffset,
1191  const MCSymbol &Sym,
1192  bool IsReg) {
1193  // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1194  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1195  return;
1196 
1198 
1200  MCInst Inst;
1201 
1202  // Either store the old $gp in a register or on the stack
1203  if (IsReg) {
1204  // move $save, $gpreg
1205  emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1206  } else {
1207  // sd $gpreg, offset($sp)
1208  emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1209  }
1210 
1211  if (getABI().IsN32()) {
1212  MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1213  const MipsMCExpr *HiExpr = MipsMCExpr::create(
1215  MCA.getContext());
1216  const MipsMCExpr *LoExpr = MipsMCExpr::create(
1218  MCA.getContext());
1219 
1220  // lui $gp, %hi(__gnu_local_gp)
1221  emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1222 
1223  // addiu $gp, $gp, %lo(__gnu_local_gp)
1224  emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1225  SMLoc(), &STI);
1226 
1227  return;
1228  }
1229 
1230  const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1232  MCA.getContext());
1233  const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1235  MCA.getContext());
1236 
1237  // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1238  emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1239 
1240  // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1241  emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1242  SMLoc(), &STI);
1243 
1244  // daddu $gp, $gp, $funcreg
1245  emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1246 }
1247 
1249  bool SaveLocationIsRegister) {
1250  // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1251  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1252  return;
1253 
1254  MCInst Inst;
1255  // Either restore the old $gp from a register or on the stack
1256  if (SaveLocationIsRegister) {
1257  Inst.setOpcode(Mips::OR);
1258  Inst.addOperand(MCOperand::createReg(Mips::GP));
1259  Inst.addOperand(MCOperand::createReg(SaveLocation));
1260  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1261  } else {
1262  Inst.setOpcode(Mips::LD);
1263  Inst.addOperand(MCOperand::createReg(Mips::GP));
1264  Inst.addOperand(MCOperand::createReg(Mips::SP));
1265  Inst.addOperand(MCOperand::createImm(SaveLocation));
1266  }
1267  getStreamer().EmitInstruction(Inst, STI);
1268 
1270 }
1271 
1274  MCContext &Context = MCA.getContext();
1275  MCStreamer &OS = getStreamer();
1276  MCSectionELF *Sec = Context.getELFSection(
1277  ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1278  MCA.registerSection(*Sec);
1279  Sec->setAlignment(8);
1280  OS.SwitchSection(Sec);
1281 
1282  OS << ABIFlagsSection;
1283 }
void emitDirectiveEnd(StringRef Name) override
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
virtual void emitDirectiveModuleGINV()
void emitDirectiveModuleSoftFloat() override
void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
bool UseCodeAlign() const override
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
virtual void emitDirectiveOptionPic2()
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void emitDirectiveSetNoMicroMips() override
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI)
Target specific streamer interface.
Definition: MCStreamer.h:83
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void setAlignment(unsigned Value)
Definition: MCSection.h:121
const FeatureBitset Features
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:116
virtual void emitDirectiveSetNoReorder()
virtual void emitDirectiveModuleHardFloat()
void registerSymbol(const MCSymbol &Symbol, bool *Created=nullptr)
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:367
virtual void emitDirectiveModuleNoGINV()
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit the $gp restore operation for .cprestore.
block Block Frequency true
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Emit the expression Value into the output as a native integer of the given Size bytes.
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
Emit a .cprestore directive.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:955
void emitDirectiveCpLoad(unsigned RegNo) override
const Triple & getTargetTriple() const
unsigned getAlignment() const
Definition: MCSection.h:120
virtual void emitDirectiveSetMips32R3()
const MipsABIInfo & getABI() const
MCContext & getContext() const
Definition: MCAssembler.h:284
virtual void emitDirectiveSetMicroMips()
virtual void emitDirectiveSetMips3()
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an immediate offset.
const FeatureBitset & getFeatureBits() const
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
virtual void emitDirectiveSetMips0()
virtual void emitDirectiveSetSoftFloat()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool registerSection(MCSection &Section)
virtual void emitDirectiveEnd(StringRef Name)
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
MCSection * getBSSSection() const
MCSection * getDataSection() const
virtual void emitDirectiveSetMips32R6()
void createPendingLabelRelocs()
Mark labels as microMIPS, if necessary for the subtarget.
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips1()
virtual void emitDirectiveModuleOddSPReg()
Context object for machine code objects.
Definition: MCContext.h:62
void emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveModuleSoftFloat()
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
MipsABIFlagsSection ABIFlagsSection
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void emitLabel(MCSymbol *Symbol) override
virtual void emitDirectiveSetOddSPReg()
virtual void emitDirectiveSetMips64R2()
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:123
virtual void emitDirectiveSetNoOddSPReg()
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:336
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
Streaming machine code generation interface.
Definition: MCStreamer.h:188
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:216
virtual void emitDirectiveSetMips4()
Container class for subtarget features.
static const MipsMCExpr * createGpOff(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:32
static bool hasShortDelaySlot(MCInst &Inst)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
virtual void emitDirectiveSetNoMicroMips()
StringRef getFpABIString(FpABIKind Value)
virtual void emitDirectiveModuleVirt()
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
static MipsABIInfo O32()
Definition: MipsABIInfo.h:34
MCAssembler & getAssembler()
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
virtual void emitDirectiveSetMacro()
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveCpLoad(unsigned RegNo)
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI)
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:296
virtual void emitDirectiveSetArch(StringRef Arch)
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:254
virtual void emitDirectiveSetNoCRC()
virtual void emitDirectiveSetMips32R5()
virtual void emitDirectiveSetMips32R2()
void setLoc(SMLoc loc)
Definition: MCInst.h:176
void emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an symbol offset.
virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)
void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveAbiCalls()
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips64R6()
void emitDirectiveEnt(const MCSymbol &Symbol) override
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
void emitDirectiveEnt(const MCSymbol &Symbol) override
virtual void emitDirectiveModuleNoVirt()
void setOpcode(unsigned Op)
Definition: MCInst.h:170
virtual void emitDirectiveOptionPic0()
void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI)
ExprKind getKind() const
Definition: MCExpr.h:72
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override
virtual void emitDirectiveSetNoGINV()
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCStreamer & Streamer
Definition: MCStreamer.h:85
virtual void emitDirectiveSetNoMips16()
void emitDirectiveSetNoOddSPReg() override
void emitDirectiveSetAtWithArg(unsigned RegNo) override
void emitDirectiveEnd(StringRef Name) override
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitMipsOptionRecords()
Emits all the option records stored up until the point it&#39;s called.
virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg)
static const MipsMCExpr * create(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:27
virtual void emitDirectiveSetNoVirt()
void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an offset.
virtual void emitDirectiveSetMips64R3()
virtual void emitDirectiveSetMips64R5()
void emitDirectiveCpLoad(unsigned RegNo) override
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
virtual void emitDirectiveSetHardFloat()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:122
virtual void emitDirectiveSetMips64()
virtual bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveSetMips5()
virtual void emitDirectiveSetMips2()
Generic base class for all target subtargets.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
References to labels and assigned expressions.
Definition: MCExpr.h:40
uint32_t Size
Definition: Profile.cpp:46
void emitDirectiveSetNoMicroMips() override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
void emitDirectiveSetArch(StringRef Arch) override
void emitDirectiveModuleOddSPReg() override
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:202
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCSection * getTextSection() const
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:376
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:388
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
LLVM Value Representation.
Definition: Value.h:72
virtual void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister)
llvm::Optional< MipsABIInfo > ABI
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:346
void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
virtual void emitDirectiveSetMips32()
virtual void emitDirectiveSetNoMsa()
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual void emitDirectiveModuleNoCRC()
bool isPositionIndependent() const
static void printHex32(unsigned Value, raw_ostream &OS)
Represents a location in source code.
Definition: SMLoc.h:23
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
virtual void emitDirectiveSetAtWithArg(unsigned RegNo)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static MipsABIInfo N64()
Definition: MipsABIInfo.h:36
void emitDirectiveModuleHardFloat() override
void emitStoreWithSymOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an symbol offset.