LLVM  10.0.0svn
MipsTargetStreamer.cpp
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1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSymbolELF.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33  "mips-round-section-sizes", cl::init(false),
34  cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
37 static bool isMipsR6(const MCSubtargetInfo *STI) {
38  return STI->getFeatureBits()[Mips::FeatureMips32r6] ||
39  STI->getFeatureBits()[Mips::FeatureMips64r6];
40 }
41 
42 static bool isMicroMips(const MCSubtargetInfo *STI) {
43  return STI->getFeatureBits()[Mips::FeatureMicroMips];
44 }
45 
47  : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
49 }
72 }
82 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
83  unsigned ReturnReg) {}
84 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
85 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
86 }
89 }
110 }
113 }
119  // .cplocal $reg
120  // This directive forces to use the alternate register for context pointer.
121  // For example
122  // .cplocal $4
123  // jal foo
124  // expands to
125  // ld $25, %call16(foo)($4)
126  // jalr $25
127 
128  if (!getABI().IsN32() && !getABI().IsN64())
129  return;
130 
131  GPReg = RegNo;
132 
134 }
136  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
137  const MCSubtargetInfo *STI) {
139  return true;
140 }
141 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
142  const MCSymbol &Sym, bool IsReg) {
143 }
144 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
145  bool SaveLocationIsRegister) {}
146 
148 
151  report_fatal_error("+nooddspreg is only valid for O32");
152 }
165 }
169 }
170 
171 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
172  const MCSubtargetInfo *STI) {
173  MCInst TmpInst;
174  TmpInst.setOpcode(Opcode);
175  TmpInst.addOperand(MCOperand::createReg(Reg0));
176  TmpInst.setLoc(IDLoc);
177  getStreamer().EmitInstruction(TmpInst, *STI);
178 }
179 
180 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
181  SMLoc IDLoc, const MCSubtargetInfo *STI) {
182  MCInst TmpInst;
183  TmpInst.setOpcode(Opcode);
184  TmpInst.addOperand(MCOperand::createReg(Reg0));
185  TmpInst.addOperand(Op1);
186  TmpInst.setLoc(IDLoc);
187  getStreamer().EmitInstruction(TmpInst, *STI);
188 }
189 
190 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
191  SMLoc IDLoc, const MCSubtargetInfo *STI) {
192  emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
193 }
194 
195 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
196  SMLoc IDLoc, const MCSubtargetInfo *STI) {
197  emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
198 }
199 
200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
201  SMLoc IDLoc, const MCSubtargetInfo *STI) {
202  MCInst TmpInst;
203  TmpInst.setOpcode(Opcode);
204  TmpInst.addOperand(MCOperand::createImm(Imm1));
205  TmpInst.addOperand(MCOperand::createImm(Imm2));
206  TmpInst.setLoc(IDLoc);
207  getStreamer().EmitInstruction(TmpInst, *STI);
208 }
209 
210 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
211  MCOperand Op2, SMLoc IDLoc,
212  const MCSubtargetInfo *STI) {
213  MCInst TmpInst;
214  TmpInst.setOpcode(Opcode);
215  TmpInst.addOperand(MCOperand::createReg(Reg0));
216  TmpInst.addOperand(MCOperand::createReg(Reg1));
217  TmpInst.addOperand(Op2);
218  TmpInst.setLoc(IDLoc);
219  getStreamer().EmitInstruction(TmpInst, *STI);
220 }
221 
222 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
223  unsigned Reg2, SMLoc IDLoc,
224  const MCSubtargetInfo *STI) {
225  emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
226 }
227 
228 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
229  unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
230  const MCSubtargetInfo *STI) {
231  MCInst TmpInst;
232  TmpInst.setOpcode(Opcode);
233  TmpInst.addOperand(MCOperand::createReg(Reg0));
234  TmpInst.addOperand(MCOperand::createReg(Reg1));
235  TmpInst.addOperand(MCOperand::createReg(Reg2));
236  TmpInst.addOperand(Op3);
237  TmpInst.setLoc(IDLoc);
238  getStreamer().EmitInstruction(TmpInst, *STI);
239 }
240 
241 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
242  int16_t Imm, SMLoc IDLoc,
243  const MCSubtargetInfo *STI) {
244  emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
245 }
246 
247 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
248  unsigned Reg1, int16_t Imm0, int16_t Imm1,
249  int16_t Imm2, SMLoc IDLoc,
250  const MCSubtargetInfo *STI) {
251  MCInst TmpInst;
252  TmpInst.setOpcode(Opcode);
253  TmpInst.addOperand(MCOperand::createReg(Reg0));
254  TmpInst.addOperand(MCOperand::createReg(Reg1));
255  TmpInst.addOperand(MCOperand::createImm(Imm0));
256  TmpInst.addOperand(MCOperand::createImm(Imm1));
257  TmpInst.addOperand(MCOperand::createImm(Imm2));
258  TmpInst.setLoc(IDLoc);
259  getStreamer().EmitInstruction(TmpInst, *STI);
260 }
261 
262 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
263  unsigned TrgReg, bool Is64Bit,
264  const MCSubtargetInfo *STI) {
265  emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
266  STI);
267 }
268 
269 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
270  int16_t ShiftAmount, SMLoc IDLoc,
271  const MCSubtargetInfo *STI) {
272  if (ShiftAmount >= 32) {
273  emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
274  return;
275  }
276 
277  emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
278 }
279 
281  const MCSubtargetInfo *STI) {
282  if (hasShortDelaySlot)
283  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
284  else
285  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
286 }
287 
289  if (isMicroMips(STI))
290  emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
291  else
292  emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
293 }
294 
295 /// Emit the $gp restore operation for .cprestore.
297  const MCSubtargetInfo *STI) {
298  emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
299 }
300 
301 /// Emit a store instruction with an immediate offset.
303  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
304  function_ref<unsigned()> GetATReg, SMLoc IDLoc,
305  const MCSubtargetInfo *STI) {
306  if (isInt<16>(Offset)) {
307  emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
308  return;
309  }
310 
311  // sw $8, offset($8) => lui $at, %hi(offset)
312  // add $at, $at, $8
313  // sw $8, %lo(offset)($at)
314 
315  unsigned ATReg = GetATReg();
316  if (!ATReg)
317  return;
318 
319  unsigned LoOffset = Offset & 0x0000ffff;
320  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
321 
322  // If msb of LoOffset is 1(negative number) we must increment HiOffset
323  // to account for the sign-extension of the low part.
324  if (LoOffset & 0x8000)
325  HiOffset++;
326 
327  // Generate the base address in ATReg.
328  emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
329  if (BaseReg != Mips::ZERO)
330  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
331  // Emit the store with the adjusted base and offset.
332  emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
333 }
334 
335 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
336 /// out of range for a simm16 will be expanded to appropriate instructions.
338  unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
339  MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
340  const MCSubtargetInfo *STI) {
341  // sw $8, sym => lui $at, %hi(sym)
342  // sw $8, %lo(sym)($at)
343 
344  // Generate the base address in ATReg.
345  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
346  if (BaseReg != Mips::ZERO)
347  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
348  // Emit the store with the adjusted base and offset.
349  emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
350 }
351 
352 /// Emit a store instruction with an symbol offset.
353 void MipsTargetStreamer::emitSCWithSymOffset(unsigned Opcode, unsigned SrcReg,
354  unsigned BaseReg,
355  MCOperand &HiOperand,
356  MCOperand &LoOperand,
357  unsigned ATReg, SMLoc IDLoc,
358  const MCSubtargetInfo *STI) {
359  // sc $8, sym => lui $at, %hi(sym)
360  // sc $8, %lo(sym)($at)
361 
362  // Generate the base address in ATReg.
363  emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
364  if (!isMicroMips(STI) && isMipsR6(STI)) {
365  // For non-micromips r6 offset for 'sc' is not in the lower 16 bits so we
366  // put it in 'at'.
367  // sc $8, sym => lui $at, %hi(sym)
368  // addiu $at, $at, %lo(sym)
369  // sc $8, 0($at)
370  emitRRX(Mips::ADDiu, ATReg, ATReg, LoOperand, IDLoc, STI);
371  MCOperand Offset = MCOperand::createImm(0);
372  // Emit the store with the adjusted base and offset.
373  emitRRRX(Opcode, SrcReg, SrcReg, ATReg, Offset, IDLoc, STI);
374  } else {
375  if (BaseReg != Mips::ZERO)
376  emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
377  // Emit the store with the adjusted base and offset.
378  emitRRRX(Opcode, SrcReg, SrcReg, ATReg, LoOperand, IDLoc, STI);
379  }
380 }
381 
382 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
383 /// permitted to be the same register iff DstReg is distinct from BaseReg and
384 /// DstReg is a GPR. It is the callers responsibility to identify such cases
385 /// and pass the appropriate register in TmpReg.
386 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
387  unsigned BaseReg, int64_t Offset,
388  unsigned TmpReg, SMLoc IDLoc,
389  const MCSubtargetInfo *STI) {
390  if (isInt<16>(Offset)) {
391  emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
392  return;
393  }
394 
395  // 1) lw $8, offset($9) => lui $8, %hi(offset)
396  // add $8, $8, $9
397  // lw $8, %lo(offset)($9)
398  // 2) lw $8, offset($8) => lui $at, %hi(offset)
399  // add $at, $at, $8
400  // lw $8, %lo(offset)($at)
401 
402  unsigned LoOffset = Offset & 0x0000ffff;
403  unsigned HiOffset = (Offset & 0xffff0000) >> 16;
404 
405  // If msb of LoOffset is 1(negative number) we must increment HiOffset
406  // to account for the sign-extension of the low part.
407  if (LoOffset & 0x8000)
408  HiOffset++;
409 
410  // Generate the base address in TmpReg.
411  emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
412  if (BaseReg != Mips::ZERO)
413  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
414  // Emit the load with the adjusted base and offset.
415  emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
416 }
417 
418 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
419 /// out of range for a simm16 will be expanded to appropriate instructions.
420 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
421 /// GPR. It is the callers responsibility to identify such cases and pass the
422 /// appropriate register in TmpReg.
423 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
424  unsigned BaseReg,
425  MCOperand &HiOperand,
426  MCOperand &LoOperand,
427  unsigned TmpReg, SMLoc IDLoc,
428  const MCSubtargetInfo *STI) {
429  // 1) lw $8, sym => lui $8, %hi(sym)
430  // lw $8, %lo(sym)($8)
431  // 2) ldc1 $f0, sym => lui $at, %hi(sym)
432  // ldc1 $f0, %lo(sym)($at)
433 
434  // Generate the base address in TmpReg.
435  emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
436  if (BaseReg != Mips::ZERO)
437  emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
438  // Emit the load with the adjusted base and offset.
439  emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
440 }
441 
444  : MipsTargetStreamer(S), OS(OS) {}
445 
447  OS << "\t.set\tmicromips\n";
449 }
450 
452  OS << "\t.set\tnomicromips\n";
454 }
455 
457  OS << "\t.set\tmips16\n";
459 }
460 
462  OS << "\t.set\tnomips16\n";
464 }
465 
467  OS << "\t.set\treorder\n";
469 }
470 
472  OS << "\t.set\tnoreorder\n";
474 }
475 
477  OS << "\t.set\tmacro\n";
479 }
480 
482  OS << "\t.set\tnomacro\n";
484 }
485 
487  OS << "\t.set\tmsa\n";
489 }
490 
492  OS << "\t.set\tnomsa\n";
494 }
495 
497  OS << "\t.set\tmt\n";
499 }
500 
502  OS << "\t.set\tnomt\n";
504 }
505 
507  OS << "\t.set\tcrc\n";
509 }
510 
512  OS << "\t.set\tnocrc\n";
514 }
515 
517  OS << "\t.set\tvirt\n";
519 }
520 
522  OS << "\t.set\tnovirt\n";
524 }
525 
527  OS << "\t.set\tginv\n";
529 }
530 
532  OS << "\t.set\tnoginv\n";
534 }
535 
537  OS << "\t.set\tat\n";
539 }
540 
542  OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
544 }
545 
547  OS << "\t.set\tnoat\n";
549 }
550 
552  OS << "\t.end\t" << Name << '\n';
553 }
554 
556  OS << "\t.ent\t" << Symbol.getName() << '\n';
557 }
558 
559 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
560 
561 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
562 
564  OS << "\t.nan\tlegacy\n";
565 }
566 
568  OS << "\t.option\tpic0\n";
569 }
570 
572  OS << "\t.option\tpic2\n";
573 }
574 
577  OS << "\t.insn\n";
578 }
579 
580 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
581  unsigned ReturnReg) {
582  OS << "\t.frame\t$"
583  << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
584  << StackSize << ",$"
585  << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
586 }
587 
589  OS << "\t.set arch=" << Arch << "\n";
591 }
592 
594  OS << "\t.set\tmips0\n";
596 }
597 
599  OS << "\t.set\tmips1\n";
601 }
602 
604  OS << "\t.set\tmips2\n";
606 }
607 
609  OS << "\t.set\tmips3\n";
611 }
612 
614  OS << "\t.set\tmips4\n";
616 }
617 
619  OS << "\t.set\tmips5\n";
621 }
622 
624  OS << "\t.set\tmips32\n";
626 }
627 
629  OS << "\t.set\tmips32r2\n";
631 }
632 
634  OS << "\t.set\tmips32r3\n";
636 }
637 
639  OS << "\t.set\tmips32r5\n";
641 }
642 
644  OS << "\t.set\tmips32r6\n";
646 }
647 
649  OS << "\t.set\tmips64\n";
651 }
652 
654  OS << "\t.set\tmips64r2\n";
656 }
657 
659  OS << "\t.set\tmips64r3\n";
661 }
662 
664  OS << "\t.set\tmips64r5\n";
666 }
667 
669  OS << "\t.set\tmips64r6\n";
671 }
672 
674  OS << "\t.set\tdsp\n";
676 }
677 
679  OS << "\t.set\tdspr2\n";
681 }
682 
684  OS << "\t.set\tnodsp\n";
686 }
687 
689  OS << "\t.set\tpop\n";
691 }
692 
694  OS << "\t.set\tpush\n";
696 }
697 
699  OS << "\t.set\tsoftfloat\n";
701 }
702 
704  OS << "\t.set\thardfloat\n";
706 }
707 
708 // Print a 32 bit hex number with all numbers.
709 static void printHex32(unsigned Value, raw_ostream &OS) {
710  OS << "0x";
711  for (int i = 7; i >= 0; i--)
712  OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
713 }
714 
715 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
716  int CPUTopSavedRegOff) {
717  OS << "\t.mask \t";
718  printHex32(CPUBitmask, OS);
719  OS << ',' << CPUTopSavedRegOff << '\n';
720 }
721 
722 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
723  int FPUTopSavedRegOff) {
724  OS << "\t.fmask\t";
725  printHex32(FPUBitmask, OS);
726  OS << "," << FPUTopSavedRegOff << '\n';
727 }
728 
730  OS << "\t.cpload\t$"
731  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
733 }
734 
736  OS << "\t.cplocal\t$"
737  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
739 }
740 
742  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
743  const MCSubtargetInfo *STI) {
744  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
745  OS << "\t.cprestore\t" << Offset << "\n";
746  return true;
747 }
748 
750  int RegOrOffset,
751  const MCSymbol &Sym,
752  bool IsReg) {
753  OS << "\t.cpsetup\t$"
754  << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
755 
756  if (IsReg)
757  OS << "$"
759  else
760  OS << RegOrOffset;
761 
762  OS << ", ";
763 
764  OS << Sym.getName();
766 }
767 
769  bool SaveLocationIsRegister) {
770  OS << "\t.cpreturn";
772 }
773 
777  OS << "\t.module\tsoftfloat\n";
778  else
779  OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
780 }
781 
785 
786  OS << "\t.set\tfp=";
787  OS << ABIFlagsSection.getFpABIString(Value) << "\n";
788 }
789 
792 
793  OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
794 }
795 
798  OS << "\t.set\toddspreg\n";
799 }
800 
803  OS << "\t.set\tnooddspreg\n";
804 }
805 
807  OS << "\t.module\tsoftfloat\n";
808 }
809 
811  OS << "\t.module\thardfloat\n";
812 }
813 
815  OS << "\t.module\tmt\n";
816 }
817 
819  OS << "\t.module\tcrc\n";
820 }
821 
823  OS << "\t.module\tnocrc\n";
824 }
825 
827  OS << "\t.module\tvirt\n";
828 }
829 
831  OS << "\t.module\tnovirt\n";
832 }
833 
835  OS << "\t.module\tginv\n";
836 }
837 
839  OS << "\t.module\tnoginv\n";
840 }
841 
842 // This part is for ELF object output.
844  const MCSubtargetInfo &STI)
845  : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
847 
848  // It's possible that MCObjectFileInfo isn't fully initialized at this point
849  // due to an initialization order problem where LLVMTargetMachine creates the
850  // target streamer before TargetLoweringObjectFile calls
851  // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
852  // covers all cases so this statement covers most cases and direct object
853  // emission must call setPic() once MCObjectFileInfo has been initialized. The
854  // cases we don't handle here are covered by MipsAsmPrinter.
856 
857  const FeatureBitset &Features = STI.getFeatureBits();
858 
859  // Set the header flags that we can in the constructor.
860  // FIXME: This is a fairly terrible hack. We set the rest
861  // of these in the destructor. The problem here is two-fold:
862  //
863  // a: Some of the eflags can be set/reset by directives.
864  // b: There aren't any usage paths that initialize the ABI
865  // pointer until after we initialize either an assembler
866  // or the target machine.
867  // We can fix this by making the target streamer construct
868  // the ABI, but this is fraught with wide ranging dependency
869  // issues as well.
870  unsigned EFlags = MCA.getELFHeaderEFlags();
871 
872  // FIXME: Fix a dependency issue by instantiating the ABI object to some
873  // default based off the triple. The triple doesn't describe the target
874  // fully, but any external user of the API that uses the MCTargetStreamer
875  // would otherwise crash on assertion failure.
876 
877  ABI = MipsABIInfo(
878  STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
879  STI.getTargetTriple().getArch() == Triple::ArchType::mips
880  ? MipsABIInfo::O32()
881  : MipsABIInfo::N64());
882 
883  // Architecture
884  if (Features[Mips::FeatureMips64r6])
885  EFlags |= ELF::EF_MIPS_ARCH_64R6;
886  else if (Features[Mips::FeatureMips64r2] ||
887  Features[Mips::FeatureMips64r3] ||
888  Features[Mips::FeatureMips64r5])
889  EFlags |= ELF::EF_MIPS_ARCH_64R2;
890  else if (Features[Mips::FeatureMips64])
891  EFlags |= ELF::EF_MIPS_ARCH_64;
892  else if (Features[Mips::FeatureMips5])
893  EFlags |= ELF::EF_MIPS_ARCH_5;
894  else if (Features[Mips::FeatureMips4])
895  EFlags |= ELF::EF_MIPS_ARCH_4;
896  else if (Features[Mips::FeatureMips3])
897  EFlags |= ELF::EF_MIPS_ARCH_3;
898  else if (Features[Mips::FeatureMips32r6])
899  EFlags |= ELF::EF_MIPS_ARCH_32R6;
900  else if (Features[Mips::FeatureMips32r2] ||
901  Features[Mips::FeatureMips32r3] ||
902  Features[Mips::FeatureMips32r5])
903  EFlags |= ELF::EF_MIPS_ARCH_32R2;
904  else if (Features[Mips::FeatureMips32])
905  EFlags |= ELF::EF_MIPS_ARCH_32;
906  else if (Features[Mips::FeatureMips2])
907  EFlags |= ELF::EF_MIPS_ARCH_2;
908  else
909  EFlags |= ELF::EF_MIPS_ARCH_1;
910 
911  // Machine
912  if (Features[Mips::FeatureCnMips])
913  EFlags |= ELF::EF_MIPS_MACH_OCTEON;
914 
915  // Other options.
916  if (Features[Mips::FeatureNaN2008])
917  EFlags |= ELF::EF_MIPS_NAN2008;
918 
919  MCA.setELFHeaderEFlags(EFlags);
920 }
921 
923  auto *Symbol = cast<MCSymbolELF>(S);
925  uint8_t Type = Symbol->getType();
926  if (Type != ELF::STT_FUNC)
927  return;
928 
929  if (isMicroMipsEnabled())
930  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
931 }
932 
935  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
936 
937  // .bss, .text and .data are always at least 16-byte aligned.
938  MCSection &TextSection = *OFI.getTextSection();
939  MCA.registerSection(TextSection);
940  MCSection &DataSection = *OFI.getDataSection();
941  MCA.registerSection(DataSection);
942  MCSection &BSSSection = *OFI.getBSSSection();
943  MCA.registerSection(BSSSection);
944 
945  TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
946  DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
947  BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
948 
949  if (RoundSectionSizes) {
950  // Make sections sizes a multiple of the alignment. This is useful for
951  // verifying the output of IAS against the output of other assemblers but
952  // it's not necessary to produce a correct object and increases section
953  // size.
954  MCStreamer &OS = getStreamer();
955  for (MCSection &S : MCA) {
956  MCSectionELF &Section = static_cast<MCSectionELF &>(S);
957 
958  unsigned Alignment = Section.getAlignment();
959  if (Alignment) {
960  OS.SwitchSection(&Section);
961  if (Section.UseCodeAlign())
962  OS.EmitCodeAlignment(Alignment, Alignment);
963  else
964  OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
965  }
966  }
967  }
968 
969  const FeatureBitset &Features = STI.getFeatureBits();
970 
971  // Update e_header flags. See the FIXME and comment above in
972  // the constructor for a full rundown on this.
973  unsigned EFlags = MCA.getELFHeaderEFlags();
974 
975  // ABI
976  // N64 does not require any ABI bits.
977  if (getABI().IsO32())
978  EFlags |= ELF::EF_MIPS_ABI_O32;
979  else if (getABI().IsN32())
980  EFlags |= ELF::EF_MIPS_ABI2;
981 
982  if (Features[Mips::FeatureGP64Bit]) {
983  if (getABI().IsO32())
984  EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
985  } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
986  EFlags |= ELF::EF_MIPS_32BITMODE;
987 
988  // -mplt is not implemented but we should act as if it was
989  // given.
990  if (!Features[Mips::FeatureNoABICalls])
991  EFlags |= ELF::EF_MIPS_CPIC;
992 
993  if (Pic)
995 
996  MCA.setELFHeaderEFlags(EFlags);
997 
998  // Emit all the option records.
999  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
1000  // .reginfo.
1001  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1002  MEF.EmitMipsOptionRecords();
1003 
1004  emitMipsAbiFlags();
1005 }
1006 
1008  auto *Symbol = cast<MCSymbolELF>(S);
1009  // If on rhs is micromips symbol then mark Symbol as microMips.
1010  if (Value->getKind() != MCExpr::SymbolRef)
1011  return;
1012  const auto &RhsSym = cast<MCSymbolELF>(
1013  static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
1014 
1015  if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
1016  return;
1017 
1018  Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
1019 }
1020 
1022  return static_cast<MCELFStreamer &>(Streamer);
1023 }
1024 
1026  MicroMipsEnabled = true;
1028 }
1029 
1031  MicroMipsEnabled = false;
1033 }
1034 
1037  unsigned Flags = MCA.getELFHeaderEFlags();
1038  Flags |= ELF::EF_MIPS_MICROMIPS;
1039  MCA.setELFHeaderEFlags(Flags);
1040 }
1041 
1044  unsigned Flags = MCA.getELFHeaderEFlags();
1045  Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1046  MCA.setELFHeaderEFlags(Flags);
1048 }
1049 
1052  unsigned Flags = MCA.getELFHeaderEFlags();
1053  Flags |= ELF::EF_MIPS_NOREORDER;
1054  MCA.setELFHeaderEFlags(Flags);
1056 }
1057 
1060  MCContext &Context = MCA.getContext();
1061  MCStreamer &OS = getStreamer();
1062 
1063  MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1064 
1065  MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1066  const MCSymbolRefExpr *ExprRef =
1068 
1069  MCA.registerSection(*Sec);
1070  Sec->setAlignment(4);
1071 
1072  OS.PushSection();
1073 
1074  OS.SwitchSection(Sec);
1075 
1076  OS.EmitValueImpl(ExprRef, 4);
1077 
1078  OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1079  OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
1080 
1081  OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1082  OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
1083 
1084  OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1085  OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
1086  OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
1087 
1088  // The .end directive marks the end of a procedure. Invalidate
1089  // the information gathered up until this point.
1090  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1091 
1092  OS.PopSection();
1093 
1094  // .end also implicitly sets the size.
1095  MCSymbol *CurPCSym = Context.createTempSymbol();
1096  OS.EmitLabel(CurPCSym);
1099  ExprRef, Context);
1100 
1101  // The ELFObjectWriter can determine the absolute size as it has access to
1102  // the layout information of the assembly file, so a size expression rather
1103  // than an absolute value is ok here.
1104  static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1105 }
1106 
1108  GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1109 
1110  // .ent also acts like an implicit '.type symbol, STT_FUNC'
1111  static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1112 }
1113 
1116  unsigned Flags = MCA.getELFHeaderEFlags();
1118  MCA.setELFHeaderEFlags(Flags);
1119 }
1120 
1123  unsigned Flags = MCA.getELFHeaderEFlags();
1124  Flags |= ELF::EF_MIPS_NAN2008;
1125  MCA.setELFHeaderEFlags(Flags);
1126 }
1127 
1130  unsigned Flags = MCA.getELFHeaderEFlags();
1131  Flags &= ~ELF::EF_MIPS_NAN2008;
1132  MCA.setELFHeaderEFlags(Flags);
1133 }
1134 
1137  unsigned Flags = MCA.getELFHeaderEFlags();
1138  // This option overrides other PIC options like -KPIC.
1139  Pic = false;
1140  Flags &= ~ELF::EF_MIPS_PIC;
1141  MCA.setELFHeaderEFlags(Flags);
1142 }
1143 
1146  unsigned Flags = MCA.getELFHeaderEFlags();
1147  Pic = true;
1148  // NOTE: We are following the GAS behaviour here which means the directive
1149  // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1150  // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1151  // EF_MIPS_CPIC to be mutually exclusive.
1153  MCA.setELFHeaderEFlags(Flags);
1154 }
1155 
1158  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1160 }
1161 
1162 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1163  unsigned ReturnReg_) {
1165  const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1166 
1167  FrameInfoSet = true;
1168  FrameReg = RegInfo->getEncodingValue(StackReg);
1169  FrameOffset = StackSize;
1170  ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1171 }
1172 
1173 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1174  int CPUTopSavedRegOff) {
1175  GPRInfoSet = true;
1176  GPRBitMask = CPUBitmask;
1177  GPROffset = CPUTopSavedRegOff;
1178 }
1179 
1180 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1181  int FPUTopSavedRegOff) {
1182  FPRInfoSet = true;
1183  FPRBitMask = FPUBitmask;
1184  FPROffset = FPUTopSavedRegOff;
1185 }
1186 
1188  // .cpload $reg
1189  // This directive expands to:
1190  // lui $gp, %hi(_gp_disp)
1191  // addui $gp, $gp, %lo(_gp_disp)
1192  // addu $gp, $gp, $reg
1193  // when support for position independent code is enabled.
1194  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1195  return;
1196 
1197  // There's a GNU extension controlled by -mno-shared that allows
1198  // locally-binding symbols to be accessed using absolute addresses.
1199  // This is currently not supported. When supported -mno-shared makes
1200  // .cpload expand to:
1201  // lui $gp, %hi(__gnu_local_gp)
1202  // addiu $gp, $gp, %lo(__gnu_local_gp)
1203 
1204  StringRef SymName("_gp_disp");
1206  MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1207  MCA.registerSymbol(*GP_Disp);
1208 
1209  MCInst TmpInst;
1210  TmpInst.setOpcode(Mips::LUi);
1212  const MCExpr *HiSym = MipsMCExpr::create(
1215  MCA.getContext()),
1216  MCA.getContext());
1217  TmpInst.addOperand(MCOperand::createExpr(HiSym));
1218  getStreamer().EmitInstruction(TmpInst, STI);
1219 
1220  TmpInst.clear();
1221 
1222  TmpInst.setOpcode(Mips::ADDiu);
1225  const MCExpr *LoSym = MipsMCExpr::create(
1228  MCA.getContext()),
1229  MCA.getContext());
1230  TmpInst.addOperand(MCOperand::createExpr(LoSym));
1231  getStreamer().EmitInstruction(TmpInst, STI);
1232 
1233  TmpInst.clear();
1234 
1235  TmpInst.setOpcode(Mips::ADDu);
1238  TmpInst.addOperand(MCOperand::createReg(RegNo));
1239  getStreamer().EmitInstruction(TmpInst, STI);
1240 
1242 }
1243 
1245  if (Pic)
1247 }
1248 
1250  int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1251  const MCSubtargetInfo *STI) {
1252  MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1253  // .cprestore offset
1254  // When PIC mode is enabled and the O32 ABI is used, this directive expands
1255  // to:
1256  // sw $gp, offset($sp)
1257  // and adds a corresponding LW after every JAL.
1258 
1259  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1260  // is used in non-PIC mode.
1261  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1262  return true;
1263 
1264  // Store the $gp on the stack.
1265  emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1266  STI);
1267  return true;
1268 }
1269 
1271  int RegOrOffset,
1272  const MCSymbol &Sym,
1273  bool IsReg) {
1274  // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1275  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1276  return;
1277 
1279 
1281  MCInst Inst;
1282 
1283  // Either store the old $gp in a register or on the stack
1284  if (IsReg) {
1285  // move $save, $gpreg
1286  emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1287  } else {
1288  // sd $gpreg, offset($sp)
1289  emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1290  }
1291 
1292  if (getABI().IsN32()) {
1293  MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1294  const MipsMCExpr *HiExpr = MipsMCExpr::create(
1296  MCA.getContext());
1297  const MipsMCExpr *LoExpr = MipsMCExpr::create(
1299  MCA.getContext());
1300 
1301  // lui $gp, %hi(__gnu_local_gp)
1302  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1303 
1304  // addiu $gp, $gp, %lo(__gnu_local_gp)
1305  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1306  &STI);
1307 
1308  return;
1309  }
1310 
1311  const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1313  MCA.getContext());
1314  const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1316  MCA.getContext());
1317 
1318  // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1319  emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1320 
1321  // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1322  emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1323  &STI);
1324 
1325  // daddu $gp, $gp, $funcreg
1326  emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1327 }
1328 
1330  bool SaveLocationIsRegister) {
1331  // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1332  if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1333  return;
1334 
1335  MCInst Inst;
1336  // Either restore the old $gp from a register or on the stack
1337  if (SaveLocationIsRegister) {
1338  Inst.setOpcode(Mips::OR);
1340  Inst.addOperand(MCOperand::createReg(SaveLocation));
1341  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1342  } else {
1343  Inst.setOpcode(Mips::LD);
1345  Inst.addOperand(MCOperand::createReg(Mips::SP));
1346  Inst.addOperand(MCOperand::createImm(SaveLocation));
1347  }
1348  getStreamer().EmitInstruction(Inst, STI);
1349 
1351 }
1352 
1355  MCContext &Context = MCA.getContext();
1356  MCStreamer &OS = getStreamer();
1357  MCSectionELF *Sec = Context.getELFSection(
1358  ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1359  MCA.registerSection(*Sec);
1360  Sec->setAlignment(8);
1361  OS.SwitchSection(Sec);
1362 
1363  OS << ABIFlagsSection;
1364 }
void emitDirectiveEnd(StringRef Name) override
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
virtual void emitDirectiveModuleGINV()
void emitDirectiveModuleSoftFloat() override
void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
bool UseCodeAlign() const override
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
virtual void emitDirectiveOptionPic2()
void emitDirectiveCpLocal(unsigned RegNo) override
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:331
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void emitDirectiveSetNoMicroMips() override
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit, const MCSubtargetInfo *STI)
Target specific streamer interface.
Definition: MCStreamer.h:84
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void setAlignment(unsigned Value)
Definition: MCSection.h:121
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:116
virtual void emitDirectiveSetNoReorder()
virtual void emitDirectiveModuleHardFloat()
void registerSymbol(const MCSymbol &Symbol, bool *Created=nullptr)
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:366
virtual void emitDirectiveModuleNoGINV()
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit the $gp restore operation for .cprestore.
block Block Frequency true
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Emit the expression Value into the output as a native integer of the given Size bytes.
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
Emit a .cprestore directive.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
void emitDirectiveCpLoad(unsigned RegNo) override
const Triple & getTargetTriple() const
unsigned getAlignment() const
Definition: MCSection.h:120
virtual void emitDirectiveSetMips32R3()
const MipsABIInfo & getABI() const
MCContext & getContext() const
Definition: MCAssembler.h:284
virtual void emitDirectiveSetMicroMips()
virtual void emitDirectiveSetMips3()
void emitDirectiveCpLocal(unsigned RegNo) override
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an immediate offset.
const FeatureBitset & getFeatureBits() const
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
virtual void emitDirectiveSetMips0()
virtual void emitDirectiveSetSoftFloat()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool registerSection(MCSection &Section)
virtual void emitDirectiveEnd(StringRef Name)
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:173
MCSection * getBSSSection() const
MCSection * getDataSection() const
virtual void emitDirectiveSetMips32R6()
void createPendingLabelRelocs()
Mark labels as microMIPS, if necessary for the subtarget.
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips1()
virtual void emitDirectiveModuleOddSPReg()
Context object for machine code objects.
Definition: MCContext.h:65
void emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveModuleSoftFloat()
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:554
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI)
MipsABIFlagsSection ABIFlagsSection
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void emitLabel(MCSymbol *Symbol) override
virtual void emitDirectiveSetOddSPReg()
virtual void emitDirectiveSetMips64R2()
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
virtual void emitDirectiveSetNoOddSPReg()
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Streaming machine code generation interface.
Definition: MCStreamer.h:189
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:225
virtual void emitDirectiveSetMips4()
Container class for subtarget features.
static const MipsMCExpr * createGpOff(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:32
static bool hasShortDelaySlot(MCInst &Inst)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
virtual void emitDirectiveSetNoMicroMips()
StringRef getFpABIString(FpABIKind Value)
virtual void emitDirectiveModuleVirt()
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
static MipsABIInfo O32()
Definition: MipsABIInfo.h:34
MCAssembler & getAssembler()
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
virtual void emitDirectiveSetMacro()
void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister) override
void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveCpLoad(unsigned RegNo)
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, const MCSubtargetInfo *STI)
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:322
virtual void emitDirectiveSetArch(StringRef Arch)
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:254
virtual void emitDirectiveSetNoCRC()
virtual void emitDirectiveSetMips32R5()
virtual void emitDirectiveSetMips32R2()
void setLoc(SMLoc loc)
Definition: MCInst.h:176
void emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a load instruction with an symbol offset.
virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)
void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveAbiCalls()
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override
virtual void emitDirectiveSetMips64R6()
void emitDirectiveEnt(const MCSymbol &Symbol) override
MCStreamer & getStreamer()
Definition: MCStreamer.h:92
void emitDirectiveEnt(const MCSymbol &Symbol) override
virtual void emitDirectiveModuleNoVirt()
void setOpcode(unsigned Op)
Definition: MCInst.h:170
virtual void emitDirectiveCpLocal(unsigned RegNo)
virtual void emitDirectiveOptionPic0()
void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI)
ExprKind getKind() const
Definition: MCExpr.h:72
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override
virtual void emitDirectiveSetNoGINV()
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCStreamer & Streamer
Definition: MCStreamer.h:86
virtual void emitDirectiveSetNoMips16()
void emitDirectiveSetNoOddSPReg() override
void emitDirectiveSetAtWithArg(unsigned RegNo) override
void emitDirectiveEnd(StringRef Name) override
static bool isMipsR6(const MCSubtargetInfo *STI)
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitMipsOptionRecords()
Emits all the option records stored up until the point it&#39;s called.
virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg)
static const MipsMCExpr * create(MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: MipsMCExpr.cpp:27
virtual void emitDirectiveSetNoVirt()
void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an offset.
virtual void emitDirectiveSetMips64R3()
virtual void emitDirectiveSetMips64R5()
void emitDirectiveCpLoad(unsigned RegNo) override
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
virtual void emitDirectiveSetHardFloat()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:129
virtual bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
virtual void emitDirectiveSetMips5()
virtual void emitDirectiveSetMips2()
Generic base class for all target subtargets.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
References to labels and assigned expressions.
Definition: MCExpr.h:40
uint32_t Size
Definition: Profile.cpp:46
void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg) override
void emitDirectiveSetArch(StringRef Arch) override
void emitDirectiveModuleOddSPReg() override
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:204
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI)
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
void emitSCWithSymOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an symbol offset.
void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI)
MCSection * getTextSection() const
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:375
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:424
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:320
LLVM Value Representation.
Definition: Value.h:73
virtual void emitDirectiveCpreturn(unsigned SaveLocation, bool SaveLocationIsRegister)
llvm::Optional< MipsABIInfo > ABI
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:397
void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
virtual void emitDirectiveSetMips32()
virtual void emitDirectiveSetNoMsa()
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual void emitDirectiveModuleNoCRC()
bool isPositionIndependent() const
static void printHex32(unsigned Value, raw_ostream &OS)
Represents a location in source code.
Definition: SMLoc.h:23
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool emitDirectiveCpRestore(int Offset, function_ref< unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) override
virtual void emitDirectiveSetAtWithArg(unsigned RegNo)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static MipsABIInfo N64()
Definition: MipsABIInfo.h:36
void emitDirectiveModuleHardFloat() override
void emitStoreWithSymOffset(unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI)
Emit a store instruction with an symbol offset.
static bool isMicroMips(const MCSubtargetInfo *STI)