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NVPTXTargetMachine.cpp
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1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the NVPTX target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "NVPTXTargetMachine.h"
14 #include "NVPTX.h"
15 #include "NVPTXAllocaHoisting.h"
16 #include "NVPTXLowerAggrCopies.h"
17 #include "NVPTXTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Pass.h"
32 #include "llvm/Transforms/Scalar.h"
35 #include <cassert>
36 #include <string>
37 
38 using namespace llvm;
39 
40 // LSV is still relatively new; this switch lets us turn it off in case we
41 // encounter (or suspect) a bug.
42 static cl::opt<bool>
43  DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
44  cl::desc("Disable load/store vectorizer"),
45  cl::init(false), cl::Hidden);
46 
47 // TODO: Remove this flag when we are confident with no regressions.
49  "disable-nvptx-require-structured-cfg",
50  cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
51  "structured CFG. The requirement should be disabled only when "
52  "unexpected regressions happen."),
53  cl::init(false), cl::Hidden);
54 
56  "nvptx-short-ptr",
57  cl::desc(
58  "Use 32-bit pointers for accessing const/local/shared address spaces."),
59  cl::init(false), cl::Hidden);
60 
61 namespace llvm {
62 
72 
73 } // end namespace llvm
74 
75 extern "C" void LLVMInitializeNVPTXTarget() {
76  // Register the target.
79 
80  // FIXME: This pass is really intended to be invoked during IR optimization,
81  // but it's very NVPTX-specific.
92 }
93 
94 static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
95  std::string Ret = "e";
96 
97  if (!is64Bit)
98  Ret += "-p:32:32";
99  else if (UseShortPointers)
100  Ret += "-p3:32:32-p4:32:32-p5:32:32";
101 
102  Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
103 
104  return Ret;
105 }
106 
108  StringRef CPU, StringRef FS,
109  const TargetOptions &Options,
112  CodeGenOpt::Level OL, bool is64bit)
113  // The pic relocation model is used regardless of what the client has
114  // specified, as it is the only relocation model currently supported.
116  CPU, FS, Options, Reloc::PIC_,
117  getEffectiveCodeModel(CM, CodeModel::Small), OL),
118  is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
120  Subtarget(TT, CPU, FS, *this) {
121  if (TT.getOS() == Triple::NVCL)
122  drvInterface = NVPTX::NVCL;
123  else
124  drvInterface = NVPTX::CUDA;
127  initAsmInfo();
128 }
129 
131 
132 void NVPTXTargetMachine32::anchor() {}
133 
135  StringRef CPU, StringRef FS,
136  const TargetOptions &Options,
139  CodeGenOpt::Level OL, bool JIT)
140  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
141 
142 void NVPTXTargetMachine64::anchor() {}
143 
145  StringRef CPU, StringRef FS,
146  const TargetOptions &Options,
149  CodeGenOpt::Level OL, bool JIT)
150  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
151 
152 namespace {
153 
154 class NVPTXPassConfig : public TargetPassConfig {
155 public:
156  NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
157  : TargetPassConfig(TM, PM) {}
158 
159  NVPTXTargetMachine &getNVPTXTargetMachine() const {
160  return getTM<NVPTXTargetMachine>();
161  }
162 
163  void addIRPasses() override;
164  bool addInstSelector() override;
165  void addPreRegAlloc() override;
166  void addPostRegAlloc() override;
167  void addMachineSSAOptimization() override;
168 
169  FunctionPass *createTargetRegisterAllocator(bool) override;
170  void addFastRegAlloc() override;
171  void addOptimizedRegAlloc() override;
172 
173  bool addRegAssignmentFast() override {
174  llvm_unreachable("should not be used");
175  }
176 
177  bool addRegAssignmentOptimized() override {
178  llvm_unreachable("should not be used");
179  }
180 
181 private:
182  // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
183  // function is only called in opt mode.
184  void addEarlyCSEOrGVNPass();
185 
186  // Add passes that propagate special memory spaces.
187  void addAddressSpaceInferencePasses();
188 
189  // Add passes that perform straight-line scalar optimizations.
190  void addStraightLineScalarOptimizationPasses();
191 };
192 
193 } // end anonymous namespace
194 
196  return new NVPTXPassConfig(*this, PM);
197 }
198 
200  Builder.addExtension(
202  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
203  PM.add(createNVVMReflectPass(Subtarget.getSmVersion()));
204  PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
205  });
206 }
207 
210  return TargetTransformInfo(NVPTXTTIImpl(this, F));
211 }
212 
213 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
215  addPass(createGVNPass());
216  else
217  addPass(createEarlyCSEPass());
218 }
219 
220 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
221  // NVPTXLowerArgs emits alloca for byval parameters which can often
222  // be eliminated by SROA.
223  addPass(createSROAPass());
224  addPass(createNVPTXLowerAllocaPass());
225  addPass(createInferAddressSpacesPass());
226 }
227 
228 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
231  // ReassociateGEPs exposes more opportunites for SLSR. See
232  // the example in reassociate-geps-and-slsr.ll.
234  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
235  // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
236  // for some of our benchmarks.
237  addEarlyCSEOrGVNPass();
238  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
239  addPass(createNaryReassociatePass());
240  // NaryReassociate on GEPs creates redundant common expressions, so run
241  // EarlyCSE after it.
242  addPass(createEarlyCSEPass());
243 }
244 
245 void NVPTXPassConfig::addIRPasses() {
246  // The following passes are known to not play well with virtual regs hanging
247  // around after register allocation (which in our case, is *all* registers).
248  // We explicitly disable them here. We do, however, need some functionality
249  // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
250  // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
251  disablePass(&PrologEpilogCodeInserterID);
252  disablePass(&MachineCopyPropagationID);
253  disablePass(&TailDuplicateID);
254  disablePass(&StackMapLivenessID);
255  disablePass(&LiveDebugValuesID);
256  disablePass(&PostRAMachineSinkingID);
257  disablePass(&PostRASchedulerID);
258  disablePass(&FuncletLayoutID);
259  disablePass(&PatchableFunctionID);
260  disablePass(&ShrinkWrapID);
261 
262  // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
263  // it here does nothing. But since we need it for correctness when lowering
264  // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
265  // call addEarlyAsPossiblePasses.
266  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
267  addPass(createNVVMReflectPass(ST.getSmVersion()));
268 
269  if (getOptLevel() != CodeGenOpt::None)
272  addPass(createGenericToNVVMPass());
273 
274  // NVPTXLowerArgs is required for correctness and should be run right
275  // before the address space inference passes.
276  addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
277  if (getOptLevel() != CodeGenOpt::None) {
278  addAddressSpaceInferencePasses();
281  addStraightLineScalarOptimizationPasses();
282  }
283 
284  // === LSR and other generic IR passes ===
286  // EarlyCSE is not always strong enough to clean up what LSR produces. For
287  // example, GVN can combine
288  //
289  // %0 = add %a, %b
290  // %1 = add %b, %a
291  //
292  // and
293  //
294  // %0 = shl nsw %a, 2
295  // %1 = shl %a, 2
296  //
297  // but EarlyCSE can do neither of them.
298  if (getOptLevel() != CodeGenOpt::None)
299  addEarlyCSEOrGVNPass();
300 }
301 
302 bool NVPTXPassConfig::addInstSelector() {
303  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
304 
305  addPass(createLowerAggrCopies());
306  addPass(createAllocaHoisting());
307  addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
308 
309  if (!ST.hasImageHandles())
311 
312  return false;
313 }
314 
315 void NVPTXPassConfig::addPreRegAlloc() {
316  // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
318 }
319 
320 void NVPTXPassConfig::addPostRegAlloc() {
321  addPass(createNVPTXPrologEpilogPass(), false);
322  if (getOptLevel() != CodeGenOpt::None) {
323  // NVPTXPrologEpilogPass calculates frame object offset and replace frame
324  // index with VRFrame register. NVPTXPeephole need to be run after that and
325  // will replace VRFrame with VRFrameLocal when possible.
326  addPass(createNVPTXPeephole());
327  }
328 }
329 
330 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
331  return nullptr; // No reg alloc
332 }
333 
334 void NVPTXPassConfig::addFastRegAlloc() {
335  addPass(&PHIEliminationID);
336  addPass(&TwoAddressInstructionPassID);
337 }
338 
339 void NVPTXPassConfig::addOptimizedRegAlloc() {
340  addPass(&ProcessImplicitDefsID);
341  addPass(&LiveVariablesID);
342  addPass(&MachineLoopInfoID);
343  addPass(&PHIEliminationID);
344 
345  addPass(&TwoAddressInstructionPassID);
346  addPass(&RegisterCoalescerID);
347 
348  // PreRA instruction scheduling.
349  if (addPass(&MachineSchedulerID))
350  printAndVerify("After Machine Scheduling");
351 
352 
353  addPass(&StackSlotColoringID);
354 
355  // FIXME: Needs physical registers
356  //addPass(&MachineLICMID);
357 
358  printAndVerify("After StackSlotColoring");
359 }
360 
361 void NVPTXPassConfig::addMachineSSAOptimization() {
362  // Pre-ra tail duplication.
363  if (addPass(&EarlyTailDuplicateID))
364  printAndVerify("After Pre-RegAlloc TailDuplicate");
365 
366  // Optimize PHIs before DCE: removing dead PHI cycles may make more
367  // instructions dead.
368  addPass(&OptimizePHIsID);
369 
370  // This pass merges large allocas. StackSlotColoring is a different pass
371  // which merges spill slots.
372  addPass(&StackColoringID);
373 
374  // If the target requests it, assign local variables to stack slots relative
375  // to one another and simplify frame index references where possible.
376  addPass(&LocalStackSlotAllocationID);
377 
378  // With optimization, dead code should already be eliminated. However
379  // there is one known exception: lowered code for arguments that are only
380  // used by tail calls, where the tail calls reuse the incoming stack
381  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
383  printAndVerify("After codegen DCE pass");
384 
385  // Allow targets to insert passes that improve instruction level parallelism,
386  // like if-conversion. Such passes will typically need dominator trees and
387  // loop info, just like LICM and CSE below.
388  if (addILPOpts())
389  printAndVerify("After ILP optimizations");
390 
391  addPass(&EarlyMachineLICMID);
392  addPass(&MachineCSEID);
393 
394  addPass(&MachineSinkingID);
395  printAndVerify("After Machine LICM, CSE and Sinking passes");
396 
397  addPass(&PeepholeOptimizerID);
398  printAndVerify("After codegen peephole optimization pass");
399 }
FunctionPass * createSpeculativeExecutionPass()
FunctionPass * createStraightLineStrengthReducePass()
FunctionPass * createGVNPass(bool NoLoads=false)
Create a legacy GVN pass.
Definition: GVN.cpp:2586
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void initializeNVPTXLowerArgsPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
MachineFunctionPass * createNVPTXProxyRegErasurePass()
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void LLVMInitializeNVPTXTarget()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:304
ModulePass * createNVPTXAssignValidGlobalNamesPass()
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createAllocaHoisting()
static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
MachineFunctionPass * createNVPTXPrologEpilogPass()
F(f)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
block Block Frequency true
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1437
ModulePass * createGenericToNVVMPass()
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)
FunctionPass * createNVVMReflectPass(unsigned int SmVersion)
Definition: NVVMReflect.cpp:62
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
bool hasImageHandles() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Target-Independent Code Generator Pass Configuration Options.
Target & getTheNVPTXTarget64()
static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:142
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createNVPTXImageOptimizerPass()
void initializeNVVMIntrRangePass(PassRegistry &)
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
Target & getTheNVPTXTarget32()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
This file a TargetTransformInfo::Concept conforming object specific to the NVPTX target machine...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static std::string computeDataLayout(bool is64Bit, bool UseShortPointers)
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)
void initializeNVVMReflectPass(PassRegistry &)
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OP, bool is64bit)
This file provides the interface for LLVM&#39;s Global Value Numbering pass which eliminates fully redund...
static bool is64Bit(const char *name)
MachineFunctionPass * createNVPTXReplaceImageHandlesPass()
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
void initializeNVPTXAllocaHoistingPass(PassRegistry &)
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void initializeGenericToNVVMPass(PassRegistry &)
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations, allowing them to see the code as it is coming out of the frontend.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
void initializeNVPTXLowerAllocaPass(PassRegistry &)
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
BasicBlockPass * createNVPTXLowerAllocaPass()
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
void setRequiresStructuredCFG(bool Value)
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Target - Wrapper for Target specific information.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
NVPTXTargetMachine.
MachineFunctionPass * createNVPTXPeephole()
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG, ready for instruction scheduling.
~NVPTXTargetMachine() override
FunctionPass * createNVVMIntrRangePass(unsigned int SmVersion)
FunctionPass * createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM)
FunctionPass * createLowerAggrCopies()
TargetOptions Options
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
FunctionPass * createSROAPass()
Definition: SROA.cpp:4635
const NVPTXSubtarget * getSubtargetImpl() const
unsigned int getSmVersion() const
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1409
static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:249
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
This pass exposes codegen information to IR-level passes.
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
FunctionPass * createNaryReassociatePass()