LLVM  6.0.0svn
PPCAsmParser.cpp
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1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/Support/SourceMgr.h"
31 
32 using namespace llvm;
33 
34 static const MCPhysReg RRegs[32] = {
35  PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42  PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 };
44 static const MCPhysReg RRegsNoR0[32] = {
45  PPC::ZERO,
46  PPC::R1, PPC::R2, PPC::R3,
47  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53  PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 };
55 static const MCPhysReg XRegs[32] = {
56  PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63  PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 };
65 static const MCPhysReg XRegsNoX0[32] = {
66  PPC::ZERO8,
67  PPC::X1, PPC::X2, PPC::X3,
68  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74  PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 };
76 static const MCPhysReg FRegs[32] = {
77  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84  PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86 static const MCPhysReg VFRegs[32] = {
87  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
88  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
89  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
90  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
91  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
92  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
93  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
94  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
95 };
96 static const MCPhysReg VRegs[32] = {
97  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
98  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
99  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
100  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
101  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
102  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
103  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
104  PPC::V28, PPC::V29, PPC::V30, PPC::V31
105 };
106 static const MCPhysReg VSRegs[64] = {
107  PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
108  PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
109  PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
110  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
111  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
112  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
113  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
114  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
115 
116  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
117  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
118  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
119  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
120  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
121  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
122  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
123  PPC::V28, PPC::V29, PPC::V30, PPC::V31
124 };
125 static const MCPhysReg VSFRegs[64] = {
126  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
127  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
128  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
129  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
130  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
131  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
132  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
133  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
134 
135  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
136  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
137  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
138  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
139  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
140  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
141  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
142  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
143 };
144 static const MCPhysReg VSSRegs[64] = {
145  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
146  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
147  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
148  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
149  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
150  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
151  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
152  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
153 
154  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
155  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
156  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
157  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
158  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
159  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
160  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
161  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
162 };
163 static unsigned QFRegs[32] = {
164  PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
165  PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
166  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
167  PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
168  PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
169  PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
170  PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
171  PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
172 };
173 static const MCPhysReg CRBITRegs[32] = {
174  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
175  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
176  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
177  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
178  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
179  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
180  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
181  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
182 };
183 static const MCPhysReg CRRegs[8] = {
184  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
185  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
186 };
187 
188 // Evaluate an expression containing condition register
189 // or condition register field symbols. Returns positive
190 // value on success, or -1 on error.
191 static int64_t
193  switch (E->getKind()) {
194  case MCExpr::Target:
195  return -1;
196 
197  case MCExpr::Constant: {
198  int64_t Res = cast<MCConstantExpr>(E)->getValue();
199  return Res < 0 ? -1 : Res;
200  }
201 
202  case MCExpr::SymbolRef: {
203  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
204  StringRef Name = SRE->getSymbol().getName();
205 
206  if (Name == "lt") return 0;
207  if (Name == "gt") return 1;
208  if (Name == "eq") return 2;
209  if (Name == "so") return 3;
210  if (Name == "un") return 3;
211 
212  if (Name == "cr0") return 0;
213  if (Name == "cr1") return 1;
214  if (Name == "cr2") return 2;
215  if (Name == "cr3") return 3;
216  if (Name == "cr4") return 4;
217  if (Name == "cr5") return 5;
218  if (Name == "cr6") return 6;
219  if (Name == "cr7") return 7;
220 
221  return -1;
222  }
223 
224  case MCExpr::Unary:
225  return -1;
226 
227  case MCExpr::Binary: {
228  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
229  int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
230  int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
231  int64_t Res;
232 
233  if (LHSVal < 0 || RHSVal < 0)
234  return -1;
235 
236  switch (BE->getOpcode()) {
237  default: return -1;
238  case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
239  case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
240  }
241 
242  return Res < 0 ? -1 : Res;
243  }
244  }
245 
246  llvm_unreachable("Invalid expression kind!");
247 }
248 
249 namespace {
250 
251 struct PPCOperand;
252 
253 class PPCAsmParser : public MCTargetAsmParser {
254  bool IsPPC64;
255  bool IsDarwin;
256 
257  void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
258 
259  bool isPPC64() const { return IsPPC64; }
260  bool isDarwin() const { return IsDarwin; }
261 
262  bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
263 
264  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
265 
266  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
267  PPCMCExpr::VariantKind &Variant);
268  const MCExpr *FixupVariantKind(const MCExpr *E);
269  bool ParseExpression(const MCExpr *&EVal);
270  bool ParseDarwinExpression(const MCExpr *&EVal);
271 
272  bool ParseOperand(OperandVector &Operands);
273 
274  bool ParseDirectiveWord(unsigned Size, AsmToken ID);
275  bool ParseDirectiveTC(unsigned Size, AsmToken ID);
276  bool ParseDirectiveMachine(SMLoc L);
277  bool ParseDarwinDirectiveMachine(SMLoc L);
278  bool ParseDirectiveAbiVersion(SMLoc L);
279  bool ParseDirectiveLocalEntry(SMLoc L);
280 
281  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
282  OperandVector &Operands, MCStreamer &Out,
283  uint64_t &ErrorInfo,
284  bool MatchingInlineAsm) override;
285 
286  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
287 
288  /// @name Auto-generated Match Functions
289  /// {
290 
291 #define GET_ASSEMBLER_HEADER
292 #include "PPCGenAsmMatcher.inc"
293 
294  /// }
295 
296 
297 public:
298  PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
299  const MCInstrInfo &MII, const MCTargetOptions &Options)
300  : MCTargetAsmParser(Options, STI, MII) {
301  // Check for 64-bit vs. 32-bit pointer mode.
302  const Triple &TheTriple = STI.getTargetTriple();
303  IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
304  TheTriple.getArch() == Triple::ppc64le);
305  IsDarwin = TheTriple.isMacOSX();
306  // Initialize the set of available features.
307  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
308  }
309 
310  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
311  SMLoc NameLoc, OperandVector &Operands) override;
312 
313  bool ParseDirective(AsmToken DirectiveID) override;
314 
315  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
316  unsigned Kind) override;
317 
318  const MCExpr *applyModifierToExpr(const MCExpr *E,
320  MCContext &Ctx) override;
321 };
322 
323 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
324 /// instruction.
325 struct PPCOperand : public MCParsedAsmOperand {
326  enum KindTy {
327  Token,
328  Immediate,
329  ContextImmediate,
330  Expression,
331  TLSRegister
332  } Kind;
333 
334  SMLoc StartLoc, EndLoc;
335  bool IsPPC64;
336 
337  struct TokOp {
338  const char *Data;
339  unsigned Length;
340  };
341 
342  struct ImmOp {
343  int64_t Val;
344  };
345 
346  struct ExprOp {
347  const MCExpr *Val;
348  int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
349  };
350 
351  struct TLSRegOp {
352  const MCSymbolRefExpr *Sym;
353  };
354 
355  union {
356  struct TokOp Tok;
357  struct ImmOp Imm;
358  struct ExprOp Expr;
359  struct TLSRegOp TLSReg;
360  };
361 
362  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
363 public:
364  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
365  Kind = o.Kind;
366  StartLoc = o.StartLoc;
367  EndLoc = o.EndLoc;
368  IsPPC64 = o.IsPPC64;
369  switch (Kind) {
370  case Token:
371  Tok = o.Tok;
372  break;
373  case Immediate:
374  case ContextImmediate:
375  Imm = o.Imm;
376  break;
377  case Expression:
378  Expr = o.Expr;
379  break;
380  case TLSRegister:
381  TLSReg = o.TLSReg;
382  break;
383  }
384  }
385 
386  // Disable use of sized deallocation due to overallocation of PPCOperand
387  // objects in CreateTokenWithStringCopy.
388  void operator delete(void *p) { ::operator delete(p); }
389 
390  /// getStartLoc - Get the location of the first token of this operand.
391  SMLoc getStartLoc() const override { return StartLoc; }
392 
393  /// getEndLoc - Get the location of the last token of this operand.
394  SMLoc getEndLoc() const override { return EndLoc; }
395 
396  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
397  bool isPPC64() const { return IsPPC64; }
398 
399  int64_t getImm() const {
400  assert(Kind == Immediate && "Invalid access!");
401  return Imm.Val;
402  }
403  int64_t getImmS16Context() const {
404  assert((Kind == Immediate || Kind == ContextImmediate) &&
405  "Invalid access!");
406  if (Kind == Immediate)
407  return Imm.Val;
408  return static_cast<int16_t>(Imm.Val);
409  }
410  int64_t getImmU16Context() const {
411  assert((Kind == Immediate || Kind == ContextImmediate) &&
412  "Invalid access!");
413  return Imm.Val;
414  }
415 
416  const MCExpr *getExpr() const {
417  assert(Kind == Expression && "Invalid access!");
418  return Expr.Val;
419  }
420 
421  int64_t getExprCRVal() const {
422  assert(Kind == Expression && "Invalid access!");
423  return Expr.CRVal;
424  }
425 
426  const MCExpr *getTLSReg() const {
427  assert(Kind == TLSRegister && "Invalid access!");
428  return TLSReg.Sym;
429  }
430 
431  unsigned getReg() const override {
432  assert(isRegNumber() && "Invalid access!");
433  return (unsigned) Imm.Val;
434  }
435 
436  unsigned getVSReg() const {
437  assert(isVSRegNumber() && "Invalid access!");
438  return (unsigned) Imm.Val;
439  }
440 
441  unsigned getCCReg() const {
442  assert(isCCRegNumber() && "Invalid access!");
443  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
444  }
445 
446  unsigned getCRBit() const {
447  assert(isCRBitNumber() && "Invalid access!");
448  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
449  }
450 
451  unsigned getCRBitMask() const {
452  assert(isCRBitMask() && "Invalid access!");
453  return 7 - countTrailingZeros<uint64_t>(Imm.Val);
454  }
455 
456  bool isToken() const override { return Kind == Token; }
457  bool isImm() const override {
458  return Kind == Immediate || Kind == Expression;
459  }
460  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
461  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
462  bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
463  bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
464  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
465  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
466  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
467  bool isU6ImmX2() const { return Kind == Immediate &&
468  isUInt<6>(getImm()) &&
469  (getImm() & 1) == 0; }
470  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
471  bool isU7ImmX4() const { return Kind == Immediate &&
472  isUInt<7>(getImm()) &&
473  (getImm() & 3) == 0; }
474  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
475  bool isU8ImmX8() const { return Kind == Immediate &&
476  isUInt<8>(getImm()) &&
477  (getImm() & 7) == 0; }
478 
479  bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
480  bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
481  bool isU16Imm() const {
482  switch (Kind) {
483  case Expression:
484  return true;
485  case Immediate:
486  case ContextImmediate:
487  return isUInt<16>(getImmU16Context());
488  default:
489  return false;
490  }
491  }
492  bool isS16Imm() const {
493  switch (Kind) {
494  case Expression:
495  return true;
496  case Immediate:
497  case ContextImmediate:
498  return isInt<16>(getImmS16Context());
499  default:
500  return false;
501  }
502  }
503  bool isS16ImmX4() const { return Kind == Expression ||
504  (Kind == Immediate && isInt<16>(getImm()) &&
505  (getImm() & 3) == 0); }
506  bool isS16ImmX16() const { return Kind == Expression ||
507  (Kind == Immediate && isInt<16>(getImm()) &&
508  (getImm() & 15) == 0); }
509  bool isS17Imm() const {
510  switch (Kind) {
511  case Expression:
512  return true;
513  case Immediate:
514  case ContextImmediate:
515  return isInt<17>(getImmS16Context());
516  default:
517  return false;
518  }
519  }
520  bool isTLSReg() const { return Kind == TLSRegister; }
521  bool isDirectBr() const {
522  if (Kind == Expression)
523  return true;
524  if (Kind != Immediate)
525  return false;
526  // Operand must be 64-bit aligned, signed 27-bit immediate.
527  if ((getImm() & 3) != 0)
528  return false;
529  if (isInt<26>(getImm()))
530  return true;
531  if (!IsPPC64) {
532  // In 32-bit mode, large 32-bit quantities wrap around.
533  if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
534  return true;
535  }
536  return false;
537  }
538  bool isCondBr() const { return Kind == Expression ||
539  (Kind == Immediate && isInt<16>(getImm()) &&
540  (getImm() & 3) == 0); }
541  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
542  bool isVSRegNumber() const {
543  return Kind == Immediate && isUInt<6>(getImm());
544  }
545  bool isCCRegNumber() const { return (Kind == Expression
546  && isUInt<3>(getExprCRVal())) ||
547  (Kind == Immediate
548  && isUInt<3>(getImm())); }
549  bool isCRBitNumber() const { return (Kind == Expression
550  && isUInt<5>(getExprCRVal())) ||
551  (Kind == Immediate
552  && isUInt<5>(getImm())); }
553  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
554  isPowerOf2_32(getImm()); }
555  bool isATBitsAsHint() const { return false; }
556  bool isMem() const override { return false; }
557  bool isReg() const override { return false; }
558 
559  void addRegOperands(MCInst &Inst, unsigned N) const {
560  llvm_unreachable("addRegOperands");
561  }
562 
563  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
564  assert(N == 1 && "Invalid number of operands!");
566  }
567 
568  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
569  assert(N == 1 && "Invalid number of operands!");
571  }
572 
573  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
574  assert(N == 1 && "Invalid number of operands!");
576  }
577 
578  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
579  assert(N == 1 && "Invalid number of operands!");
581  }
582 
583  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
584  if (isPPC64())
585  addRegG8RCOperands(Inst, N);
586  else
587  addRegGPRCOperands(Inst, N);
588  }
589 
590  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
591  if (isPPC64())
592  addRegG8RCNoX0Operands(Inst, N);
593  else
594  addRegGPRCNoR0Operands(Inst, N);
595  }
596 
597  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
598  assert(N == 1 && "Invalid number of operands!");
600  }
601 
602  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
603  assert(N == 1 && "Invalid number of operands!");
605  }
606 
607  void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
608  assert(N == 1 && "Invalid number of operands!");
610  }
611 
612  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
613  assert(N == 1 && "Invalid number of operands!");
615  }
616 
617  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
618  assert(N == 1 && "Invalid number of operands!");
619  Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
620  }
621 
622  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
623  assert(N == 1 && "Invalid number of operands!");
624  Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
625  }
626 
627  void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
628  assert(N == 1 && "Invalid number of operands!");
629  Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
630  }
631 
632  void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
633  assert(N == 1 && "Invalid number of operands!");
634  Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
635  }
636 
637  void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
638  assert(N == 1 && "Invalid number of operands!");
639  Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
640  }
641 
642  void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
643  assert(N == 1 && "Invalid number of operands!");
644  Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
645  }
646 
647  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
648  assert(N == 1 && "Invalid number of operands!");
649  Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
650  }
651 
652  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
653  assert(N == 1 && "Invalid number of operands!");
654  Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
655  }
656 
657  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
658  assert(N == 1 && "Invalid number of operands!");
659  Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
660  }
661 
662  void addImmOperands(MCInst &Inst, unsigned N) const {
663  assert(N == 1 && "Invalid number of operands!");
664  if (Kind == Immediate)
665  Inst.addOperand(MCOperand::createImm(getImm()));
666  else
668  }
669 
670  void addS16ImmOperands(MCInst &Inst, unsigned N) const {
671  assert(N == 1 && "Invalid number of operands!");
672  switch (Kind) {
673  case Immediate:
674  Inst.addOperand(MCOperand::createImm(getImm()));
675  break;
676  case ContextImmediate:
677  Inst.addOperand(MCOperand::createImm(getImmS16Context()));
678  break;
679  default:
681  break;
682  }
683  }
684 
685  void addU16ImmOperands(MCInst &Inst, unsigned N) const {
686  assert(N == 1 && "Invalid number of operands!");
687  switch (Kind) {
688  case Immediate:
689  Inst.addOperand(MCOperand::createImm(getImm()));
690  break;
691  case ContextImmediate:
692  Inst.addOperand(MCOperand::createImm(getImmU16Context()));
693  break;
694  default:
696  break;
697  }
698  }
699 
700  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
701  assert(N == 1 && "Invalid number of operands!");
702  if (Kind == Immediate)
703  Inst.addOperand(MCOperand::createImm(getImm() / 4));
704  else
706  }
707 
708  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
709  assert(N == 1 && "Invalid number of operands!");
710  Inst.addOperand(MCOperand::createExpr(getTLSReg()));
711  }
712 
713  StringRef getToken() const {
714  assert(Kind == Token && "Invalid access!");
715  return StringRef(Tok.Data, Tok.Length);
716  }
717 
718  void print(raw_ostream &OS) const override;
719 
720  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
721  bool IsPPC64) {
722  auto Op = make_unique<PPCOperand>(Token);
723  Op->Tok.Data = Str.data();
724  Op->Tok.Length = Str.size();
725  Op->StartLoc = S;
726  Op->EndLoc = S;
727  Op->IsPPC64 = IsPPC64;
728  return Op;
729  }
730 
731  static std::unique_ptr<PPCOperand>
732  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
733  // Allocate extra memory for the string and copy it.
734  // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
735  // deleter which will destroy them by simply using "delete", not correctly
736  // calling operator delete on this extra memory after calling the dtor
737  // explicitly.
738  void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
739  std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
740  Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
741  Op->Tok.Length = Str.size();
742  std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
743  Op->StartLoc = S;
744  Op->EndLoc = S;
745  Op->IsPPC64 = IsPPC64;
746  return Op;
747  }
748 
749  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
750  bool IsPPC64) {
751  auto Op = make_unique<PPCOperand>(Immediate);
752  Op->Imm.Val = Val;
753  Op->StartLoc = S;
754  Op->EndLoc = E;
755  Op->IsPPC64 = IsPPC64;
756  return Op;
757  }
758 
759  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
760  SMLoc E, bool IsPPC64) {
761  auto Op = make_unique<PPCOperand>(Expression);
762  Op->Expr.Val = Val;
763  Op->Expr.CRVal = EvaluateCRExpr(Val);
764  Op->StartLoc = S;
765  Op->EndLoc = E;
766  Op->IsPPC64 = IsPPC64;
767  return Op;
768  }
769 
770  static std::unique_ptr<PPCOperand>
771  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
772  auto Op = make_unique<PPCOperand>(TLSRegister);
773  Op->TLSReg.Sym = Sym;
774  Op->StartLoc = S;
775  Op->EndLoc = E;
776  Op->IsPPC64 = IsPPC64;
777  return Op;
778  }
779 
780  static std::unique_ptr<PPCOperand>
781  CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
782  auto Op = make_unique<PPCOperand>(ContextImmediate);
783  Op->Imm.Val = Val;
784  Op->StartLoc = S;
785  Op->EndLoc = E;
786  Op->IsPPC64 = IsPPC64;
787  return Op;
788  }
789 
790  static std::unique_ptr<PPCOperand>
791  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
792  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
793  return CreateImm(CE->getValue(), S, E, IsPPC64);
794 
795  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
796  if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
797  return CreateTLSReg(SRE, S, E, IsPPC64);
798 
799  if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
800  int64_t Res;
801  if (TE->evaluateAsConstant(Res))
802  return CreateContextImm(Res, S, E, IsPPC64);
803  }
804 
805  return CreateExpr(Val, S, E, IsPPC64);
806  }
807 };
808 
809 } // end anonymous namespace.
810 
811 void PPCOperand::print(raw_ostream &OS) const {
812  switch (Kind) {
813  case Token:
814  OS << "'" << getToken() << "'";
815  break;
816  case Immediate:
817  case ContextImmediate:
818  OS << getImm();
819  break;
820  case Expression:
821  OS << *getExpr();
822  break;
823  case TLSRegister:
824  OS << *getTLSReg();
825  break;
826  }
827 }
828 
829 static void
831  if (Op.isImm()) {
833  return;
834  }
835  const MCExpr *Expr = Op.getExpr();
836  if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
837  if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
838  Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
839  return;
840  }
841  } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
842  if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
843  const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
844  BinExpr->getLHS(), Ctx);
846  return;
847  }
848  }
850 }
851 
852 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
853  const OperandVector &Operands) {
854  int Opcode = Inst.getOpcode();
855  switch (Opcode) {
856  case PPC::DCBTx:
857  case PPC::DCBTT:
858  case PPC::DCBTSTx:
859  case PPC::DCBTSTT: {
860  MCInst TmpInst;
861  TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
862  PPC::DCBT : PPC::DCBTST);
864  (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
865  TmpInst.addOperand(Inst.getOperand(0));
866  TmpInst.addOperand(Inst.getOperand(1));
867  Inst = TmpInst;
868  break;
869  }
870  case PPC::DCBTCT:
871  case PPC::DCBTDS: {
872  MCInst TmpInst;
873  TmpInst.setOpcode(PPC::DCBT);
874  TmpInst.addOperand(Inst.getOperand(2));
875  TmpInst.addOperand(Inst.getOperand(0));
876  TmpInst.addOperand(Inst.getOperand(1));
877  Inst = TmpInst;
878  break;
879  }
880  case PPC::DCBTSTCT:
881  case PPC::DCBTSTDS: {
882  MCInst TmpInst;
883  TmpInst.setOpcode(PPC::DCBTST);
884  TmpInst.addOperand(Inst.getOperand(2));
885  TmpInst.addOperand(Inst.getOperand(0));
886  TmpInst.addOperand(Inst.getOperand(1));
887  Inst = TmpInst;
888  break;
889  }
890  case PPC::DCBFx:
891  case PPC::DCBFL:
892  case PPC::DCBFLP: {
893  int L = 0;
894  if (Opcode == PPC::DCBFL)
895  L = 1;
896  else if (Opcode == PPC::DCBFLP)
897  L = 3;
898 
899  MCInst TmpInst;
900  TmpInst.setOpcode(PPC::DCBF);
901  TmpInst.addOperand(MCOperand::createImm(L));
902  TmpInst.addOperand(Inst.getOperand(0));
903  TmpInst.addOperand(Inst.getOperand(1));
904  Inst = TmpInst;
905  break;
906  }
907  case PPC::LAx: {
908  MCInst TmpInst;
909  TmpInst.setOpcode(PPC::LA);
910  TmpInst.addOperand(Inst.getOperand(0));
911  TmpInst.addOperand(Inst.getOperand(2));
912  TmpInst.addOperand(Inst.getOperand(1));
913  Inst = TmpInst;
914  break;
915  }
916  case PPC::SUBI: {
917  MCInst TmpInst;
918  TmpInst.setOpcode(PPC::ADDI);
919  TmpInst.addOperand(Inst.getOperand(0));
920  TmpInst.addOperand(Inst.getOperand(1));
921  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
922  Inst = TmpInst;
923  break;
924  }
925  case PPC::SUBIS: {
926  MCInst TmpInst;
927  TmpInst.setOpcode(PPC::ADDIS);
928  TmpInst.addOperand(Inst.getOperand(0));
929  TmpInst.addOperand(Inst.getOperand(1));
930  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
931  Inst = TmpInst;
932  break;
933  }
934  case PPC::SUBIC: {
935  MCInst TmpInst;
936  TmpInst.setOpcode(PPC::ADDIC);
937  TmpInst.addOperand(Inst.getOperand(0));
938  TmpInst.addOperand(Inst.getOperand(1));
939  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
940  Inst = TmpInst;
941  break;
942  }
943  case PPC::SUBICo: {
944  MCInst TmpInst;
945  TmpInst.setOpcode(PPC::ADDICo);
946  TmpInst.addOperand(Inst.getOperand(0));
947  TmpInst.addOperand(Inst.getOperand(1));
948  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
949  Inst = TmpInst;
950  break;
951  }
952  case PPC::EXTLWI:
953  case PPC::EXTLWIo: {
954  MCInst TmpInst;
955  int64_t N = Inst.getOperand(2).getImm();
956  int64_t B = Inst.getOperand(3).getImm();
957  TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
958  TmpInst.addOperand(Inst.getOperand(0));
959  TmpInst.addOperand(Inst.getOperand(1));
960  TmpInst.addOperand(MCOperand::createImm(B));
961  TmpInst.addOperand(MCOperand::createImm(0));
962  TmpInst.addOperand(MCOperand::createImm(N - 1));
963  Inst = TmpInst;
964  break;
965  }
966  case PPC::EXTRWI:
967  case PPC::EXTRWIo: {
968  MCInst TmpInst;
969  int64_t N = Inst.getOperand(2).getImm();
970  int64_t B = Inst.getOperand(3).getImm();
971  TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
972  TmpInst.addOperand(Inst.getOperand(0));
973  TmpInst.addOperand(Inst.getOperand(1));
974  TmpInst.addOperand(MCOperand::createImm(B + N));
975  TmpInst.addOperand(MCOperand::createImm(32 - N));
976  TmpInst.addOperand(MCOperand::createImm(31));
977  Inst = TmpInst;
978  break;
979  }
980  case PPC::INSLWI:
981  case PPC::INSLWIo: {
982  MCInst TmpInst;
983  int64_t N = Inst.getOperand(2).getImm();
984  int64_t B = Inst.getOperand(3).getImm();
985  TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
986  TmpInst.addOperand(Inst.getOperand(0));
987  TmpInst.addOperand(Inst.getOperand(0));
988  TmpInst.addOperand(Inst.getOperand(1));
989  TmpInst.addOperand(MCOperand::createImm(32 - B));
990  TmpInst.addOperand(MCOperand::createImm(B));
991  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
992  Inst = TmpInst;
993  break;
994  }
995  case PPC::INSRWI:
996  case PPC::INSRWIo: {
997  MCInst TmpInst;
998  int64_t N = Inst.getOperand(2).getImm();
999  int64_t B = Inst.getOperand(3).getImm();
1000  TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
1001  TmpInst.addOperand(Inst.getOperand(0));
1002  TmpInst.addOperand(Inst.getOperand(0));
1003  TmpInst.addOperand(Inst.getOperand(1));
1004  TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
1005  TmpInst.addOperand(MCOperand::createImm(B));
1006  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
1007  Inst = TmpInst;
1008  break;
1009  }
1010  case PPC::ROTRWI:
1011  case PPC::ROTRWIo: {
1012  MCInst TmpInst;
1013  int64_t N = Inst.getOperand(2).getImm();
1014  TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
1015  TmpInst.addOperand(Inst.getOperand(0));
1016  TmpInst.addOperand(Inst.getOperand(1));
1017  TmpInst.addOperand(MCOperand::createImm(32 - N));
1018  TmpInst.addOperand(MCOperand::createImm(0));
1019  TmpInst.addOperand(MCOperand::createImm(31));
1020  Inst = TmpInst;
1021  break;
1022  }
1023  case PPC::SLWI:
1024  case PPC::SLWIo: {
1025  MCInst TmpInst;
1026  int64_t N = Inst.getOperand(2).getImm();
1027  TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1028  TmpInst.addOperand(Inst.getOperand(0));
1029  TmpInst.addOperand(Inst.getOperand(1));
1030  TmpInst.addOperand(MCOperand::createImm(N));
1031  TmpInst.addOperand(MCOperand::createImm(0));
1032  TmpInst.addOperand(MCOperand::createImm(31 - N));
1033  Inst = TmpInst;
1034  break;
1035  }
1036  case PPC::SRWI:
1037  case PPC::SRWIo: {
1038  MCInst TmpInst;
1039  int64_t N = Inst.getOperand(2).getImm();
1040  TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1041  TmpInst.addOperand(Inst.getOperand(0));
1042  TmpInst.addOperand(Inst.getOperand(1));
1043  TmpInst.addOperand(MCOperand::createImm(32 - N));
1044  TmpInst.addOperand(MCOperand::createImm(N));
1045  TmpInst.addOperand(MCOperand::createImm(31));
1046  Inst = TmpInst;
1047  break;
1048  }
1049  case PPC::CLRRWI:
1050  case PPC::CLRRWIo: {
1051  MCInst TmpInst;
1052  int64_t N = Inst.getOperand(2).getImm();
1053  TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1054  TmpInst.addOperand(Inst.getOperand(0));
1055  TmpInst.addOperand(Inst.getOperand(1));
1056  TmpInst.addOperand(MCOperand::createImm(0));
1057  TmpInst.addOperand(MCOperand::createImm(0));
1058  TmpInst.addOperand(MCOperand::createImm(31 - N));
1059  Inst = TmpInst;
1060  break;
1061  }
1062  case PPC::CLRLSLWI:
1063  case PPC::CLRLSLWIo: {
1064  MCInst TmpInst;
1065  int64_t B = Inst.getOperand(2).getImm();
1066  int64_t N = Inst.getOperand(3).getImm();
1067  TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1068  TmpInst.addOperand(Inst.getOperand(0));
1069  TmpInst.addOperand(Inst.getOperand(1));
1070  TmpInst.addOperand(MCOperand::createImm(N));
1071  TmpInst.addOperand(MCOperand::createImm(B - N));
1072  TmpInst.addOperand(MCOperand::createImm(31 - N));
1073  Inst = TmpInst;
1074  break;
1075  }
1076  case PPC::EXTLDI:
1077  case PPC::EXTLDIo: {
1078  MCInst TmpInst;
1079  int64_t N = Inst.getOperand(2).getImm();
1080  int64_t B = Inst.getOperand(3).getImm();
1081  TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1082  TmpInst.addOperand(Inst.getOperand(0));
1083  TmpInst.addOperand(Inst.getOperand(1));
1084  TmpInst.addOperand(MCOperand::createImm(B));
1085  TmpInst.addOperand(MCOperand::createImm(N - 1));
1086  Inst = TmpInst;
1087  break;
1088  }
1089  case PPC::EXTRDI:
1090  case PPC::EXTRDIo: {
1091  MCInst TmpInst;
1092  int64_t N = Inst.getOperand(2).getImm();
1093  int64_t B = Inst.getOperand(3).getImm();
1094  TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1095  TmpInst.addOperand(Inst.getOperand(0));
1096  TmpInst.addOperand(Inst.getOperand(1));
1097  TmpInst.addOperand(MCOperand::createImm(B + N));
1098  TmpInst.addOperand(MCOperand::createImm(64 - N));
1099  Inst = TmpInst;
1100  break;
1101  }
1102  case PPC::INSRDI:
1103  case PPC::INSRDIo: {
1104  MCInst TmpInst;
1105  int64_t N = Inst.getOperand(2).getImm();
1106  int64_t B = Inst.getOperand(3).getImm();
1107  TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1108  TmpInst.addOperand(Inst.getOperand(0));
1109  TmpInst.addOperand(Inst.getOperand(0));
1110  TmpInst.addOperand(Inst.getOperand(1));
1111  TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1112  TmpInst.addOperand(MCOperand::createImm(B));
1113  Inst = TmpInst;
1114  break;
1115  }
1116  case PPC::ROTRDI:
1117  case PPC::ROTRDIo: {
1118  MCInst TmpInst;
1119  int64_t N = Inst.getOperand(2).getImm();
1120  TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1121  TmpInst.addOperand(Inst.getOperand(0));
1122  TmpInst.addOperand(Inst.getOperand(1));
1123  TmpInst.addOperand(MCOperand::createImm(64 - N));
1124  TmpInst.addOperand(MCOperand::createImm(0));
1125  Inst = TmpInst;
1126  break;
1127  }
1128  case PPC::SLDI:
1129  case PPC::SLDIo: {
1130  MCInst TmpInst;
1131  int64_t N = Inst.getOperand(2).getImm();
1132  TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1133  TmpInst.addOperand(Inst.getOperand(0));
1134  TmpInst.addOperand(Inst.getOperand(1));
1135  TmpInst.addOperand(MCOperand::createImm(N));
1136  TmpInst.addOperand(MCOperand::createImm(63 - N));
1137  Inst = TmpInst;
1138  break;
1139  }
1140  case PPC::SUBPCIS: {
1141  MCInst TmpInst;
1142  int64_t N = Inst.getOperand(1).getImm();
1143  TmpInst.setOpcode(PPC::ADDPCIS);
1144  TmpInst.addOperand(Inst.getOperand(0));
1145  TmpInst.addOperand(MCOperand::createImm(-N));
1146  Inst = TmpInst;
1147  break;
1148  }
1149  case PPC::SRDI:
1150  case PPC::SRDIo: {
1151  MCInst TmpInst;
1152  int64_t N = Inst.getOperand(2).getImm();
1153  TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1154  TmpInst.addOperand(Inst.getOperand(0));
1155  TmpInst.addOperand(Inst.getOperand(1));
1156  TmpInst.addOperand(MCOperand::createImm(64 - N));
1157  TmpInst.addOperand(MCOperand::createImm(N));
1158  Inst = TmpInst;
1159  break;
1160  }
1161  case PPC::CLRRDI:
1162  case PPC::CLRRDIo: {
1163  MCInst TmpInst;
1164  int64_t N = Inst.getOperand(2).getImm();
1165  TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1166  TmpInst.addOperand(Inst.getOperand(0));
1167  TmpInst.addOperand(Inst.getOperand(1));
1168  TmpInst.addOperand(MCOperand::createImm(0));
1169  TmpInst.addOperand(MCOperand::createImm(63 - N));
1170  Inst = TmpInst;
1171  break;
1172  }
1173  case PPC::CLRLSLDI:
1174  case PPC::CLRLSLDIo: {
1175  MCInst TmpInst;
1176  int64_t B = Inst.getOperand(2).getImm();
1177  int64_t N = Inst.getOperand(3).getImm();
1178  TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1179  TmpInst.addOperand(Inst.getOperand(0));
1180  TmpInst.addOperand(Inst.getOperand(1));
1181  TmpInst.addOperand(MCOperand::createImm(N));
1182  TmpInst.addOperand(MCOperand::createImm(B - N));
1183  Inst = TmpInst;
1184  break;
1185  }
1186  case PPC::RLWINMbm:
1187  case PPC::RLWINMobm: {
1188  unsigned MB, ME;
1189  int64_t BM = Inst.getOperand(3).getImm();
1190  if (!isRunOfOnes(BM, MB, ME))
1191  break;
1192 
1193  MCInst TmpInst;
1194  TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1195  TmpInst.addOperand(Inst.getOperand(0));
1196  TmpInst.addOperand(Inst.getOperand(1));
1197  TmpInst.addOperand(Inst.getOperand(2));
1198  TmpInst.addOperand(MCOperand::createImm(MB));
1199  TmpInst.addOperand(MCOperand::createImm(ME));
1200  Inst = TmpInst;
1201  break;
1202  }
1203  case PPC::RLWIMIbm:
1204  case PPC::RLWIMIobm: {
1205  unsigned MB, ME;
1206  int64_t BM = Inst.getOperand(3).getImm();
1207  if (!isRunOfOnes(BM, MB, ME))
1208  break;
1209 
1210  MCInst TmpInst;
1211  TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1212  TmpInst.addOperand(Inst.getOperand(0));
1213  TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1214  TmpInst.addOperand(Inst.getOperand(1));
1215  TmpInst.addOperand(Inst.getOperand(2));
1216  TmpInst.addOperand(MCOperand::createImm(MB));
1217  TmpInst.addOperand(MCOperand::createImm(ME));
1218  Inst = TmpInst;
1219  break;
1220  }
1221  case PPC::RLWNMbm:
1222  case PPC::RLWNMobm: {
1223  unsigned MB, ME;
1224  int64_t BM = Inst.getOperand(3).getImm();
1225  if (!isRunOfOnes(BM, MB, ME))
1226  break;
1227 
1228  MCInst TmpInst;
1229  TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1230  TmpInst.addOperand(Inst.getOperand(0));
1231  TmpInst.addOperand(Inst.getOperand(1));
1232  TmpInst.addOperand(Inst.getOperand(2));
1233  TmpInst.addOperand(MCOperand::createImm(MB));
1234  TmpInst.addOperand(MCOperand::createImm(ME));
1235  Inst = TmpInst;
1236  break;
1237  }
1238  case PPC::MFTB: {
1239  if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1240  assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1241  Inst.setOpcode(PPC::MFSPR);
1242  }
1243  break;
1244  }
1245  case PPC::CP_COPYx:
1246  case PPC::CP_COPY_FIRST: {
1247  MCInst TmpInst;
1248  TmpInst.setOpcode(PPC::CP_COPY);
1249  TmpInst.addOperand(Inst.getOperand(0));
1250  TmpInst.addOperand(Inst.getOperand(1));
1251  TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1252 
1253  Inst = TmpInst;
1254  break;
1255  }
1256  case PPC::CP_PASTEx :
1257  case PPC::CP_PASTE_LAST: {
1258  MCInst TmpInst;
1259  TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1260  PPC::CP_PASTE : PPC::CP_PASTEo);
1261  TmpInst.addOperand(Inst.getOperand(0));
1262  TmpInst.addOperand(Inst.getOperand(1));
1263  TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1264 
1265  Inst = TmpInst;
1266  break;
1267  }
1268  }
1269 }
1270 
1271 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1272  OperandVector &Operands,
1273  MCStreamer &Out, uint64_t &ErrorInfo,
1274  bool MatchingInlineAsm) {
1275  MCInst Inst;
1276 
1277  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1278  case Match_Success:
1279  // Post-process instructions (typically extended mnemonics)
1280  ProcessInstruction(Inst, Operands);
1281  Inst.setLoc(IDLoc);
1282  Out.EmitInstruction(Inst, getSTI());
1283  return false;
1284  case Match_MissingFeature:
1285  return Error(IDLoc, "instruction use requires an option to be enabled");
1286  case Match_MnemonicFail:
1287  return Error(IDLoc, "unrecognized instruction mnemonic");
1288  case Match_InvalidOperand: {
1289  SMLoc ErrorLoc = IDLoc;
1290  if (ErrorInfo != ~0ULL) {
1291  if (ErrorInfo >= Operands.size())
1292  return Error(IDLoc, "too few operands for instruction");
1293 
1294  ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1295  if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1296  }
1297 
1298  return Error(ErrorLoc, "invalid operand for instruction");
1299  }
1300  }
1301 
1302  llvm_unreachable("Implement any new match types added!");
1303 }
1304 
1305 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1306  if (getParser().getTok().is(AsmToken::Identifier)) {
1307  StringRef Name = getParser().getTok().getString();
1308  if (Name.equals_lower("lr")) {
1309  RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1310  IntVal = 8;
1311  } else if (Name.equals_lower("ctr")) {
1312  RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1313  IntVal = 9;
1314  } else if (Name.equals_lower("vrsave")) {
1315  RegNo = PPC::VRSAVE;
1316  IntVal = 256;
1317  } else if (Name.startswith_lower("r") &&
1318  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1319  RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1320  } else if (Name.startswith_lower("f") &&
1321  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1322  RegNo = FRegs[IntVal];
1323  } else if (Name.startswith_lower("vs") &&
1324  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1325  RegNo = VSRegs[IntVal];
1326  } else if (Name.startswith_lower("v") &&
1327  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1328  RegNo = VRegs[IntVal];
1329  } else if (Name.startswith_lower("q") &&
1330  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1331  RegNo = QFRegs[IntVal];
1332  } else if (Name.startswith_lower("cr") &&
1333  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1334  RegNo = CRRegs[IntVal];
1335  } else
1336  return true;
1337  getParser().Lex();
1338  return false;
1339  }
1340  return true;
1341 }
1342 
1343 bool PPCAsmParser::
1344 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1345  const AsmToken &Tok = getParser().getTok();
1346  StartLoc = Tok.getLoc();
1347  EndLoc = Tok.getEndLoc();
1348  RegNo = 0;
1349  int64_t IntVal;
1350  if (MatchRegisterName(RegNo, IntVal))
1351  return TokError("invalid register name");
1352  return false;
1353 }
1354 
1355 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1356 /// the expression and check for VK_PPC_LO/HI/HA
1357 /// symbol variants. If all symbols with modifier use the same
1358 /// variant, return the corresponding PPCMCExpr::VariantKind,
1359 /// and a modified expression using the default symbol variant.
1360 /// Otherwise, return NULL.
1361 const MCExpr *PPCAsmParser::
1362 ExtractModifierFromExpr(const MCExpr *E,
1363  PPCMCExpr::VariantKind &Variant) {
1364  MCContext &Context = getParser().getContext();
1365  Variant = PPCMCExpr::VK_PPC_None;
1366 
1367  switch (E->getKind()) {
1368  case MCExpr::Target:
1369  case MCExpr::Constant:
1370  return nullptr;
1371 
1372  case MCExpr::SymbolRef: {
1373  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1374 
1375  switch (SRE->getKind()) {
1377  Variant = PPCMCExpr::VK_PPC_LO;
1378  break;
1380  Variant = PPCMCExpr::VK_PPC_HI;
1381  break;
1383  Variant = PPCMCExpr::VK_PPC_HA;
1384  break;
1386  Variant = PPCMCExpr::VK_PPC_HIGHER;
1387  break;
1389  Variant = PPCMCExpr::VK_PPC_HIGHERA;
1390  break;
1392  Variant = PPCMCExpr::VK_PPC_HIGHEST;
1393  break;
1395  Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1396  break;
1397  default:
1398  return nullptr;
1399  }
1400 
1401  return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1402  }
1403 
1404  case MCExpr::Unary: {
1405  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1406  const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1407  if (!Sub)
1408  return nullptr;
1409  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1410  }
1411 
1412  case MCExpr::Binary: {
1413  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1414  PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1415  const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1416  const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1417 
1418  if (!LHS && !RHS)
1419  return nullptr;
1420 
1421  if (!LHS) LHS = BE->getLHS();
1422  if (!RHS) RHS = BE->getRHS();
1423 
1424  if (LHSVariant == PPCMCExpr::VK_PPC_None)
1425  Variant = RHSVariant;
1426  else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1427  Variant = LHSVariant;
1428  else if (LHSVariant == RHSVariant)
1429  Variant = LHSVariant;
1430  else
1431  return nullptr;
1432 
1433  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1434  }
1435  }
1436 
1437  llvm_unreachable("Invalid expression kind!");
1438 }
1439 
1440 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1441 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1442 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1443 /// FIXME: This is a hack.
1444 const MCExpr *PPCAsmParser::
1445 FixupVariantKind(const MCExpr *E) {
1446  MCContext &Context = getParser().getContext();
1447 
1448  switch (E->getKind()) {
1449  case MCExpr::Target:
1450  case MCExpr::Constant:
1451  return E;
1452 
1453  case MCExpr::SymbolRef: {
1454  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1456 
1457  switch (SRE->getKind()) {
1460  break;
1463  break;
1464  default:
1465  return E;
1466  }
1467  return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1468  }
1469 
1470  case MCExpr::Unary: {
1471  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1472  const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1473  if (Sub == UE->getSubExpr())
1474  return E;
1475  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1476  }
1477 
1478  case MCExpr::Binary: {
1479  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1480  const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1481  const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1482  if (LHS == BE->getLHS() && RHS == BE->getRHS())
1483  return E;
1484  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1485  }
1486  }
1487 
1488  llvm_unreachable("Invalid expression kind!");
1489 }
1490 
1491 /// ParseExpression. This differs from the default "parseExpression" in that
1492 /// it handles modifiers.
1493 bool PPCAsmParser::
1494 ParseExpression(const MCExpr *&EVal) {
1495 
1496  if (isDarwin())
1497  return ParseDarwinExpression(EVal);
1498 
1499  // (ELF Platforms)
1500  // Handle \code @l/@ha \endcode
1501  if (getParser().parseExpression(EVal))
1502  return true;
1503 
1504  EVal = FixupVariantKind(EVal);
1505 
1506  PPCMCExpr::VariantKind Variant;
1507  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1508  if (E)
1509  EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1510 
1511  return false;
1512 }
1513 
1514 /// ParseDarwinExpression. (MachO Platforms)
1515 /// This differs from the default "parseExpression" in that it handles detection
1516 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1517 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1518 /// syntax form so it is done here. TODO: Determine if there is merit in
1519 /// arranging for this to be done at a higher level.
1520 bool PPCAsmParser::
1521 ParseDarwinExpression(const MCExpr *&EVal) {
1522  MCAsmParser &Parser = getParser();
1524  switch (getLexer().getKind()) {
1525  default:
1526  break;
1527  case AsmToken::Identifier:
1528  // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1529  // something starting with any other char should be part of the
1530  // asm syntax. If handwritten asm includes an identifier like lo16,
1531  // then all bets are off - but no-one would do that, right?
1532  StringRef poss = Parser.getTok().getString();
1533  if (poss.equals_lower("lo16")) {
1534  Variant = PPCMCExpr::VK_PPC_LO;
1535  } else if (poss.equals_lower("hi16")) {
1536  Variant = PPCMCExpr::VK_PPC_HI;
1537  } else if (poss.equals_lower("ha16")) {
1538  Variant = PPCMCExpr::VK_PPC_HA;
1539  }
1540  if (Variant != PPCMCExpr::VK_PPC_None) {
1541  Parser.Lex(); // Eat the xx16
1542  if (getLexer().isNot(AsmToken::LParen))
1543  return Error(Parser.getTok().getLoc(), "expected '('");
1544  Parser.Lex(); // Eat the '('
1545  }
1546  break;
1547  }
1548 
1549  if (getParser().parseExpression(EVal))
1550  return true;
1551 
1552  if (Variant != PPCMCExpr::VK_PPC_None) {
1553  if (getLexer().isNot(AsmToken::RParen))
1554  return Error(Parser.getTok().getLoc(), "expected ')'");
1555  Parser.Lex(); // Eat the ')'
1556  EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1557  }
1558  return false;
1559 }
1560 
1561 /// ParseOperand
1562 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1563 /// rNN for MachO.
1564 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1565  MCAsmParser &Parser = getParser();
1566  SMLoc S = Parser.getTok().getLoc();
1567  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1568  const MCExpr *EVal;
1569 
1570  // Attempt to parse the next token as an immediate
1571  switch (getLexer().getKind()) {
1572  // Special handling for register names. These are interpreted
1573  // as immediates corresponding to the register number.
1574  case AsmToken::Percent:
1575  Parser.Lex(); // Eat the '%'.
1576  unsigned RegNo;
1577  int64_t IntVal;
1578  if (MatchRegisterName(RegNo, IntVal))
1579  return Error(S, "invalid register name");
1580 
1581  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1582  return false;
1583 
1584  case AsmToken::Identifier:
1585  case AsmToken::LParen:
1586  case AsmToken::Plus:
1587  case AsmToken::Minus:
1588  case AsmToken::Integer:
1589  case AsmToken::Dot:
1590  case AsmToken::Dollar:
1591  case AsmToken::Exclaim:
1592  case AsmToken::Tilde:
1593  // Note that non-register-name identifiers from the compiler will begin
1594  // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1595  // identifiers like r31foo - so we fall through in the event that parsing
1596  // a register name fails.
1597  if (isDarwin()) {
1598  unsigned RegNo;
1599  int64_t IntVal;
1600  if (!MatchRegisterName(RegNo, IntVal)) {
1601  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1602  return false;
1603  }
1604  }
1605  // All other expressions
1606 
1607  if (!ParseExpression(EVal))
1608  break;
1609  // Fall-through
1611  default:
1612  return Error(S, "unknown operand");
1613  }
1614 
1615  // Push the parsed operand into the list of operands
1616  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1617 
1618  // Check whether this is a TLS call expression
1619  bool TLSCall = false;
1620  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1621  TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1622 
1623  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1624  const MCExpr *TLSSym;
1625 
1626  Parser.Lex(); // Eat the '('.
1627  S = Parser.getTok().getLoc();
1628  if (ParseExpression(TLSSym))
1629  return Error(S, "invalid TLS call expression");
1630  if (getLexer().isNot(AsmToken::RParen))
1631  return Error(Parser.getTok().getLoc(), "missing ')'");
1632  E = Parser.getTok().getLoc();
1633  Parser.Lex(); // Eat the ')'.
1634 
1635  Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1636  }
1637 
1638  // Otherwise, check for D-form memory operands
1639  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1640  Parser.Lex(); // Eat the '('.
1641  S = Parser.getTok().getLoc();
1642 
1643  int64_t IntVal;
1644  switch (getLexer().getKind()) {
1645  case AsmToken::Percent:
1646  Parser.Lex(); // Eat the '%'.
1647  unsigned RegNo;
1648  if (MatchRegisterName(RegNo, IntVal))
1649  return Error(S, "invalid register name");
1650  break;
1651 
1652  case AsmToken::Integer:
1653  if (isDarwin())
1654  return Error(S, "unexpected integer value");
1655  else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1656  IntVal > 31)
1657  return Error(S, "invalid register number");
1658  break;
1659  case AsmToken::Identifier:
1660  if (isDarwin()) {
1661  unsigned RegNo;
1662  if (!MatchRegisterName(RegNo, IntVal)) {
1663  break;
1664  }
1665  }
1667 
1668  default:
1669  return Error(S, "invalid memory operand");
1670  }
1671 
1672  E = Parser.getTok().getLoc();
1673  if (parseToken(AsmToken::RParen, "missing ')'"))
1674  return true;
1675  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1676  }
1677 
1678  return false;
1679 }
1680 
1681 /// Parse an instruction mnemonic followed by its operands.
1682 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1683  SMLoc NameLoc, OperandVector &Operands) {
1684  // The first operand is the token for the instruction name.
1685  // If the next character is a '+' or '-', we need to add it to the
1686  // instruction name, to match what TableGen is doing.
1687  std::string NewOpcode;
1688  if (parseOptionalToken(AsmToken::Plus)) {
1689  NewOpcode = Name;
1690  NewOpcode += '+';
1691  Name = NewOpcode;
1692  }
1693  if (parseOptionalToken(AsmToken::Minus)) {
1694  NewOpcode = Name;
1695  NewOpcode += '-';
1696  Name = NewOpcode;
1697  }
1698  // If the instruction ends in a '.', we need to create a separate
1699  // token for it, to match what TableGen is doing.
1700  size_t Dot = Name.find('.');
1701  StringRef Mnemonic = Name.slice(0, Dot);
1702  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1703  Operands.push_back(
1704  PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1705  else
1706  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1707  if (Dot != StringRef::npos) {
1708  SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1709  StringRef DotStr = Name.slice(Dot, StringRef::npos);
1710  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1711  Operands.push_back(
1712  PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1713  else
1714  Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1715  }
1716 
1717  // If there are no more operands then finish
1718  if (parseOptionalToken(AsmToken::EndOfStatement))
1719  return false;
1720 
1721  // Parse the first operand
1722  if (ParseOperand(Operands))
1723  return true;
1724 
1725  while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1726  if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1727  return true;
1728  }
1729 
1730  // We'll now deal with an unfortunate special case: the syntax for the dcbt
1731  // and dcbtst instructions differs for server vs. embedded cores.
1732  // The syntax for dcbt is:
1733  // dcbt ra, rb, th [server]
1734  // dcbt th, ra, rb [embedded]
1735  // where th can be omitted when it is 0. dcbtst is the same. We take the
1736  // server form to be the default, so swap the operands if we're parsing for
1737  // an embedded core (they'll be swapped again upon printing).
1738  if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1739  Operands.size() == 4 &&
1740  (Name == "dcbt" || Name == "dcbtst")) {
1741  std::swap(Operands[1], Operands[3]);
1742  std::swap(Operands[2], Operands[1]);
1743  }
1744 
1745  return false;
1746 }
1747 
1748 /// ParseDirective parses the PPC specific directives
1749 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1750  StringRef IDVal = DirectiveID.getIdentifier();
1751  if (isDarwin()) {
1752  if (IDVal == ".machine")
1753  ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1754  else
1755  return true;
1756  } else if (IDVal == ".word")
1757  ParseDirectiveWord(2, DirectiveID);
1758  else if (IDVal == ".llong")
1759  ParseDirectiveWord(8, DirectiveID);
1760  else if (IDVal == ".tc")
1761  ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1762  else if (IDVal == ".machine")
1763  ParseDirectiveMachine(DirectiveID.getLoc());
1764  else if (IDVal == ".abiversion")
1765  ParseDirectiveAbiVersion(DirectiveID.getLoc());
1766  else if (IDVal == ".localentry")
1767  ParseDirectiveLocalEntry(DirectiveID.getLoc());
1768  else
1769  return true;
1770  return false;
1771 }
1772 
1773 /// ParseDirectiveWord
1774 /// ::= .word [ expression (, expression)* ]
1775 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1776  auto parseOp = [&]() -> bool {
1777  const MCExpr *Value;
1778  SMLoc ExprLoc = getParser().getTok().getLoc();
1779  if (getParser().parseExpression(Value))
1780  return true;
1781  if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1782  assert(Size <= 8 && "Invalid size");
1783  uint64_t IntValue = MCE->getValue();
1784  if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1785  return Error(ExprLoc, "literal value out of range for '" +
1786  ID.getIdentifier() + "' directive");
1787  getStreamer().EmitIntValue(IntValue, Size);
1788  } else
1789  getStreamer().EmitValue(Value, Size, ExprLoc);
1790  return false;
1791  };
1792 
1793  if (parseMany(parseOp))
1794  return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1795  return false;
1796 }
1797 
1798 /// ParseDirectiveTC
1799 /// ::= .tc [ symbol (, expression)* ]
1800 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1801  MCAsmParser &Parser = getParser();
1802  // Skip TC symbol, which is only used with XCOFF.
1803  while (getLexer().isNot(AsmToken::EndOfStatement)
1804  && getLexer().isNot(AsmToken::Comma))
1805  Parser.Lex();
1806  if (parseToken(AsmToken::Comma))
1807  return addErrorSuffix(" in '.tc' directive");
1808 
1809  // Align to word size.
1810  getParser().getStreamer().EmitValueToAlignment(Size);
1811 
1812  // Emit expressions.
1813  return ParseDirectiveWord(Size, ID);
1814 }
1815 
1816 /// ParseDirectiveMachine (ELF platforms)
1817 /// ::= .machine [ cpu | "push" | "pop" ]
1818 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1819  MCAsmParser &Parser = getParser();
1820  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1821  Parser.getTok().isNot(AsmToken::String))
1822  return Error(L, "unexpected token in '.machine' directive");
1823 
1824  StringRef CPU = Parser.getTok().getIdentifier();
1825 
1826  // FIXME: Right now, the parser always allows any available
1827  // instruction, so the .machine directive is not useful.
1828  // Implement ".machine any" (by doing nothing) for the benefit
1829  // of existing assembler code. Likewise, we can then implement
1830  // ".machine push" and ".machine pop" as no-op.
1831  if (CPU != "any" && CPU != "push" && CPU != "pop")
1832  return TokError("unrecognized machine type");
1833 
1834  Parser.Lex();
1835 
1836  if (parseToken(AsmToken::EndOfStatement))
1837  return addErrorSuffix(" in '.machine' directive");
1838 
1839  PPCTargetStreamer &TStreamer =
1840  *static_cast<PPCTargetStreamer *>(
1841  getParser().getStreamer().getTargetStreamer());
1842  TStreamer.emitMachine(CPU);
1843 
1844  return false;
1845 }
1846 
1847 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1848 /// ::= .machine cpu-identifier
1849 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1850  MCAsmParser &Parser = getParser();
1851  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1852  Parser.getTok().isNot(AsmToken::String))
1853  return Error(L, "unexpected token in directive");
1854 
1855  StringRef CPU = Parser.getTok().getIdentifier();
1856  Parser.Lex();
1857 
1858  // FIXME: this is only the 'default' set of cpu variants.
1859  // However we don't act on this information at present, this is simply
1860  // allowing parsing to proceed with minimal sanity checking.
1861  if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L,
1862  "unrecognized cpu type") ||
1863  check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L,
1864  "wrong cpu type specified for 64bit") ||
1865  check(!isPPC64() && CPU == "ppc64", L,
1866  "wrong cpu type specified for 32bit") ||
1867  parseToken(AsmToken::EndOfStatement))
1868  return addErrorSuffix(" in '.machine' directive");
1869  return false;
1870 }
1871 
1872 /// ParseDirectiveAbiVersion
1873 /// ::= .abiversion constant-expression
1874 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1875  int64_t AbiVersion;
1876  if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1877  "expected constant expression") ||
1878  parseToken(AsmToken::EndOfStatement))
1879  return addErrorSuffix(" in '.abiversion' directive");
1880 
1881  PPCTargetStreamer &TStreamer =
1882  *static_cast<PPCTargetStreamer *>(
1883  getParser().getStreamer().getTargetStreamer());
1884  TStreamer.emitAbiVersion(AbiVersion);
1885 
1886  return false;
1887 }
1888 
1889 /// ParseDirectiveLocalEntry
1890 /// ::= .localentry symbol, expression
1891 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1892  StringRef Name;
1893  if (getParser().parseIdentifier(Name))
1894  return Error(L, "expected identifier in '.localentry' directive");
1895 
1896  MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1897  const MCExpr *Expr;
1898 
1899  if (parseToken(AsmToken::Comma) ||
1900  check(getParser().parseExpression(Expr), L, "expected expression") ||
1901  parseToken(AsmToken::EndOfStatement))
1902  return addErrorSuffix(" in '.localentry' directive");
1903 
1904  PPCTargetStreamer &TStreamer =
1905  *static_cast<PPCTargetStreamer *>(
1906  getParser().getStreamer().getTargetStreamer());
1907  TStreamer.emitLocalEntry(Sym, Expr);
1908 
1909  return false;
1910 }
1911 
1912 
1913 
1914 /// Force static initialization.
1919 }
1920 
1921 #define GET_REGISTER_MATCHER
1922 #define GET_MATCHER_IMPLEMENTATION
1923 #include "PPCGenAsmMatcher.inc"
1924 
1925 // Define this matcher function after the auto-generated include so we
1926 // have the match class enum definitions.
1927 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1928  unsigned Kind) {
1929  // If the kind is a token for a literal immediate, check if our asm
1930  // operand matches. This is for InstAliases which have a fixed-value
1931  // immediate in the syntax.
1932  int64_t ImmVal;
1933  switch (Kind) {
1934  case MCK_0: ImmVal = 0; break;
1935  case MCK_1: ImmVal = 1; break;
1936  case MCK_2: ImmVal = 2; break;
1937  case MCK_3: ImmVal = 3; break;
1938  case MCK_4: ImmVal = 4; break;
1939  case MCK_5: ImmVal = 5; break;
1940  case MCK_6: ImmVal = 6; break;
1941  case MCK_7: ImmVal = 7; break;
1942  default: return Match_InvalidOperand;
1943  }
1944 
1945  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1946  if (Op.isImm() && Op.getImm() == ImmVal)
1947  return Match_Success;
1948 
1949  return Match_InvalidOperand;
1950 }
1951 
1952 const MCExpr *
1953 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1955  MCContext &Ctx) {
1956  switch (Variant) {
1958  return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1960  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1962  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1964  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1966  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1968  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1970  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1971  default:
1972  return nullptr;
1973  }
1974 }
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t CallInst * C
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:341
static const MCPhysReg XRegsNoX0[32]
void push_back(const T &Elt)
Definition: SmallVector.h:212
bool isImm() const
Definition: MCInst.h:59
static int64_t EvaluateCRExpr(const MCExpr *E)
LLVM_NODISCARD bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
Definition: StringRef.cpp:62
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmLexer.h:116
#define R4(n)
LLVMContext & Context
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static unsigned MatchRegisterName(StringRef Name)
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:442
VariantKind getKind() const
Definition: MCExpr.h:320
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:176
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:110
static const MCPhysReg VFRegs[32]
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
Definition: PPCMCExpr.cpp:22
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Multiplication.
Definition: MCExpr.h:417
Target & getThePPC32Target()
bool isNot(TokenKind K) const
Definition: MCAsmLexer.h:89
Opcode getOpcode() const
Get the kind of this unary expression.
Definition: MCExpr.h:386
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:546
static const MCPhysReg VRegs[32]
static const MCPhysReg CRBITRegs[32]
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
static const MCPhysReg FRegs[32]
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
#define R2(n)
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:863
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmLexer.h:105
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static const MCPhysReg VSSRegs[64]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:27
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
static const MCPhysReg CRRegs[8]
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:137
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static const MCPhysReg XRegs[32]
Context object for machine code objects.
Definition: MCContext.h:59
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static unsigned QFRegs[32]
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:549
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
Unary assembler expressions.
Definition: MCExpr.h:342
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
const MCExpr * getExpr() const
Definition: MCInst.h:96
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
Target & getThePPC64Target()
Unary expressions.
Definition: MCExpr.h:42
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:148
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
int64_t getImm() const
Definition: MCInst.h:76
const char * getPointer() const
Definition: SMLoc.h:35
Streaming machine code generation interface.
Definition: MCStreamer.h:169
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:154
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:335
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void emitAbiVersion(int AbiVersion)=0
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
void LLVMInitializePowerPCAsmParser()
Force static initialization.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
unsigned getNumOperands() const
Definition: MCInst.h:182
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:390
Binary assembler expressions.
Definition: MCExpr.h:399
void setLoc(SMLoc loc)
Definition: MCInst.h:177
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:369
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
void setOpcode(unsigned Op)
Definition: MCInst.h:171
#define R6(n)
const MCSymbol & getSymbol() const
Definition: MCExpr.h:318
ExprKind getKind() const
Definition: MCExpr.h:73
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:710
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
Target & getThePPC64LETarget()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:331
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
static const MCPhysReg VSRegs[64]
static const size_t npos
Definition: StringRef.h:51
MCExpr const & getExpr(MCExpr const &Expr)
#define N
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:41
Unary minus.
Definition: MCExpr.h:346
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:338
static const MCPhysReg RRegs[32]
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:543
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Definition: MCExpr.h:389
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static const MCPhysReg VSFRegs[64]
Constant expressions.
Definition: MCExpr.h:40
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
Binary expressions.
Definition: MCExpr.h:39
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
Subtraction.
Definition: MCExpr.h:423
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Target specific expression.
Definition: MCExpr.h:43
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
Definition: SMLoc.h:24
unsigned getOpcode() const
Definition: MCInst.h:172
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:385
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:298
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static const MCPhysReg RRegsNoR0[32]