44 int64_t Res = cast<MCConstantExpr>(
E)->getValue();
45 return Res < 0 ? -1 : Res;
52 if (Name ==
"lt")
return 0;
53 if (Name ==
"gt")
return 1;
54 if (Name ==
"eq")
return 2;
55 if (Name ==
"so")
return 3;
56 if (Name ==
"un")
return 3;
58 if (Name ==
"cr0")
return 0;
59 if (Name ==
"cr1")
return 1;
60 if (Name ==
"cr2")
return 2;
61 if (Name ==
"cr3")
return 3;
62 if (Name ==
"cr4")
return 4;
63 if (Name ==
"cr5")
return 5;
64 if (Name ==
"cr6")
return 6;
65 if (Name ==
"cr7")
return 7;
79 if (LHSVal < 0 || RHSVal < 0)
88 return Res < 0 ? -1 : Res;
105 bool isPPC64()
const {
return IsPPC64; }
106 bool isDarwin()
const {
return IsDarwin; }
110 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
115 bool ParseExpression(
const MCExpr *&EVal);
116 bool ParseDarwinExpression(
const MCExpr *&EVal);
121 bool ParseDirectiveTC(
unsigned Size,
AsmToken ID);
122 bool ParseDirectiveMachine(
SMLoc L);
123 bool ParseDarwinDirectiveMachine(
SMLoc L);
124 bool ParseDirectiveAbiVersion(
SMLoc L);
125 bool ParseDirectiveLocalEntry(
SMLoc L);
127 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
130 bool MatchingInlineAsm)
override;
137 #define GET_ASSEMBLER_HEADER 138 #include "PPCGenAsmMatcher.inc" 153 setAvailableFeatures(ComputeAvailableFeatures(STI.
getFeatureBits()));
159 bool ParseDirective(
AsmToken DirectiveID)
override;
162 unsigned Kind)
override;
180 SMLoc StartLoc, EndLoc;
205 struct TLSRegOp TLSReg;
212 StartLoc = o.StartLoc;
220 case ContextImmediate:
234 void operator delete(
void *p) { ::operator
delete(p); }
237 SMLoc getStartLoc()
const override {
return StartLoc; }
240 SMLoc getEndLoc()
const override {
return EndLoc; }
247 bool isPPC64()
const {
return IsPPC64; }
249 int64_t getImm()
const {
250 assert(Kind == Immediate &&
"Invalid access!");
253 int64_t getImmS16Context()
const {
254 assert((Kind == Immediate || Kind == ContextImmediate) &&
256 if (Kind == Immediate)
258 return static_cast<int16_t
>(Imm.Val);
260 int64_t getImmU16Context()
const {
261 assert((Kind == Immediate || Kind == ContextImmediate) &&
267 assert(Kind == Expression &&
"Invalid access!");
271 int64_t getExprCRVal()
const {
272 assert(Kind == Expression &&
"Invalid access!");
276 const MCExpr *getTLSReg()
const {
277 assert(Kind == TLSRegister &&
"Invalid access!");
281 unsigned getReg()
const override {
282 assert(isRegNumber() &&
"Invalid access!");
283 return (
unsigned) Imm.Val;
286 unsigned getVSReg()
const {
287 assert(isVSRegNumber() &&
"Invalid access!");
288 return (
unsigned) Imm.Val;
291 unsigned getCCReg()
const {
292 assert(isCCRegNumber() &&
"Invalid access!");
293 return (
unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
296 unsigned getCRBit()
const {
297 assert(isCRBitNumber() &&
"Invalid access!");
298 return (
unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
301 unsigned getCRBitMask()
const {
302 assert(isCRBitMask() &&
"Invalid access!");
303 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
306 bool isToken()
const override {
return Kind == Token; }
307 bool isImm()
const override {
308 return Kind == Immediate || Kind == Expression;
310 bool isU1Imm()
const {
return Kind == Immediate && isUInt<1>(getImm()); }
311 bool isU2Imm()
const {
return Kind == Immediate && isUInt<2>(getImm()); }
312 bool isU3Imm()
const {
return Kind == Immediate && isUInt<3>(getImm()); }
313 bool isU4Imm()
const {
return Kind == Immediate && isUInt<4>(getImm()); }
314 bool isU5Imm()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
315 bool isS5Imm()
const {
return Kind == Immediate && isInt<5>(getImm()); }
316 bool isU6Imm()
const {
return Kind == Immediate && isUInt<6>(getImm()); }
317 bool isU6ImmX2()
const {
return Kind == Immediate &&
318 isUInt<6>(getImm()) &&
319 (getImm() & 1) == 0; }
320 bool isU7Imm()
const {
return Kind == Immediate && isUInt<7>(getImm()); }
321 bool isU7ImmX4()
const {
return Kind == Immediate &&
322 isUInt<7>(getImm()) &&
323 (getImm() & 3) == 0; }
324 bool isU8Imm()
const {
return Kind == Immediate &&
isUInt<8>(getImm()); }
325 bool isU8ImmX8()
const {
return Kind == Immediate &&
327 (getImm() & 7) == 0; }
329 bool isU10Imm()
const {
return Kind == Immediate && isUInt<10>(getImm()); }
330 bool isU12Imm()
const {
return Kind == Immediate && isUInt<12>(getImm()); }
331 bool isU16Imm()
const {
336 case ContextImmediate:
342 bool isS16Imm()
const {
347 case ContextImmediate:
353 bool isS16ImmX4()
const {
return Kind == Expression ||
354 (Kind == Immediate &&
isInt<16>(getImm()) &&
355 (getImm() & 3) == 0); }
356 bool isS16ImmX16()
const {
return Kind == Expression ||
357 (Kind == Immediate &&
isInt<16>(getImm()) &&
358 (getImm() & 15) == 0); }
359 bool isS17Imm()
const {
364 case ContextImmediate:
365 return isInt<17>(getImmS16Context());
370 bool isTLSReg()
const {
return Kind == TLSRegister; }
371 bool isDirectBr()
const {
372 if (Kind == Expression)
374 if (Kind != Immediate)
377 if ((getImm() & 3) != 0)
379 if (isInt<26>(getImm()))
383 if (
isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
388 bool isCondBr()
const {
return Kind == Expression ||
389 (Kind == Immediate &&
isInt<16>(getImm()) &&
390 (getImm() & 3) == 0); }
391 bool isRegNumber()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
392 bool isVSRegNumber()
const {
393 return Kind == Immediate && isUInt<6>(getImm());
395 bool isCCRegNumber()
const {
return (Kind == Expression
396 && isUInt<3>(getExprCRVal())) ||
398 && isUInt<3>(getImm())); }
399 bool isCRBitNumber()
const {
return (Kind == Expression
400 && isUInt<5>(getExprCRVal())) ||
402 && isUInt<5>(getImm())); }
403 bool isCRBitMask()
const {
return Kind == Immediate &&
isUInt<8>(getImm()) &&
405 bool isATBitsAsHint()
const {
return false; }
406 bool isMem()
const override {
return false; }
407 bool isReg()
const override {
return false; }
409 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
413 void addRegGPRCOperands(
MCInst &Inst,
unsigned N)
const {
414 assert(N == 1 &&
"Invalid number of operands!");
418 void addRegGPRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
419 assert(N == 1 &&
"Invalid number of operands!");
423 void addRegG8RCOperands(
MCInst &Inst,
unsigned N)
const {
424 assert(N == 1 &&
"Invalid number of operands!");
428 void addRegG8RCNoX0Operands(
MCInst &Inst,
unsigned N)
const {
429 assert(N == 1 &&
"Invalid number of operands!");
433 void addRegGxRCOperands(
MCInst &Inst,
unsigned N)
const {
435 addRegG8RCOperands(Inst, N);
437 addRegGPRCOperands(Inst, N);
440 void addRegGxRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
442 addRegG8RCNoX0Operands(Inst, N);
444 addRegGPRCNoR0Operands(Inst, N);
447 void addRegF4RCOperands(
MCInst &Inst,
unsigned N)
const {
448 assert(N == 1 &&
"Invalid number of operands!");
452 void addRegF8RCOperands(
MCInst &Inst,
unsigned N)
const {
453 assert(N == 1 &&
"Invalid number of operands!");
457 void addRegVFRCOperands(
MCInst &Inst,
unsigned N)
const {
458 assert(N == 1 &&
"Invalid number of operands!");
462 void addRegVRRCOperands(
MCInst &Inst,
unsigned N)
const {
463 assert(N == 1 &&
"Invalid number of operands!");
467 void addRegVSRCOperands(
MCInst &Inst,
unsigned N)
const {
468 assert(N == 1 &&
"Invalid number of operands!");
472 void addRegVSFRCOperands(
MCInst &Inst,
unsigned N)
const {
473 assert(N == 1 &&
"Invalid number of operands!");
477 void addRegVSSRCOperands(
MCInst &Inst,
unsigned N)
const {
478 assert(N == 1 &&
"Invalid number of operands!");
482 void addRegQFRCOperands(
MCInst &Inst,
unsigned N)
const {
483 assert(N == 1 &&
"Invalid number of operands!");
487 void addRegQSRCOperands(
MCInst &Inst,
unsigned N)
const {
488 assert(N == 1 &&
"Invalid number of operands!");
492 void addRegQBRCOperands(
MCInst &Inst,
unsigned N)
const {
493 assert(N == 1 &&
"Invalid number of operands!");
497 void addRegSPE4RCOperands(
MCInst &Inst,
unsigned N)
const {
498 assert(N == 1 &&
"Invalid number of operands!");
502 void addRegSPERCOperands(
MCInst &Inst,
unsigned N)
const {
503 assert(N == 1 &&
"Invalid number of operands!");
507 void addRegCRBITRCOperands(
MCInst &Inst,
unsigned N)
const {
508 assert(N == 1 &&
"Invalid number of operands!");
512 void addRegCRRCOperands(
MCInst &Inst,
unsigned N)
const {
513 assert(N == 1 &&
"Invalid number of operands!");
517 void addCRBitMaskOperands(
MCInst &Inst,
unsigned N)
const {
518 assert(N == 1 &&
"Invalid number of operands!");
522 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
523 assert(N == 1 &&
"Invalid number of operands!");
524 if (Kind == Immediate)
530 void addS16ImmOperands(
MCInst &Inst,
unsigned N)
const {
531 assert(N == 1 &&
"Invalid number of operands!");
536 case ContextImmediate:
545 void addU16ImmOperands(
MCInst &Inst,
unsigned N)
const {
546 assert(N == 1 &&
"Invalid number of operands!");
551 case ContextImmediate:
560 void addBranchTargetOperands(
MCInst &Inst,
unsigned N)
const {
561 assert(N == 1 &&
"Invalid number of operands!");
562 if (Kind == Immediate)
568 void addTLSRegOperands(
MCInst &Inst,
unsigned N)
const {
569 assert(N == 1 &&
"Invalid number of operands!");
574 assert(Kind == Token &&
"Invalid access!");
580 static std::unique_ptr<PPCOperand> CreateToken(
StringRef Str,
SMLoc S,
582 auto Op = make_unique<PPCOperand>(Token);
583 Op->Tok.Data = Str.
data();
584 Op->Tok.Length = Str.
size();
587 Op->IsPPC64 = IsPPC64;
591 static std::unique_ptr<PPCOperand>
598 void *Mem = ::operator
new(
sizeof(PPCOperand) + Str.
size());
599 std::unique_ptr<PPCOperand>
Op(
new (Mem) PPCOperand(Token));
600 Op->Tok.Data =
reinterpret_cast<const char *
>(Op.get() + 1);
601 Op->Tok.Length = Str.
size();
602 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.
data(), Str.
size());
605 Op->IsPPC64 = IsPPC64;
609 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val,
SMLoc S,
SMLoc E,
611 auto Op = make_unique<PPCOperand>(Immediate);
615 Op->IsPPC64 = IsPPC64;
619 static std::unique_ptr<PPCOperand> CreateExpr(
const MCExpr *Val,
SMLoc S,
620 SMLoc E,
bool IsPPC64) {
621 auto Op = make_unique<PPCOperand>(Expression);
626 Op->IsPPC64 = IsPPC64;
630 static std::unique_ptr<PPCOperand>
632 auto Op = make_unique<PPCOperand>(TLSRegister);
633 Op->TLSReg.Sym = Sym;
636 Op->IsPPC64 = IsPPC64;
640 static std::unique_ptr<PPCOperand>
641 CreateContextImm(int64_t Val,
SMLoc S,
SMLoc E,
bool IsPPC64) {
642 auto Op = make_unique<PPCOperand>(ContextImmediate);
646 Op->IsPPC64 = IsPPC64;
650 static std::unique_ptr<PPCOperand>
653 return CreateImm(CE->getValue(), S,
E, IsPPC64);
657 return CreateTLSReg(SRE, S, E, IsPPC64);
659 if (
const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
661 if (TE->evaluateAsConstant(Res))
662 return CreateContextImm(Res, S, E, IsPPC64);
665 return CreateExpr(Val, S, E, IsPPC64);
677 case ContextImmediate:
696 if (
const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
701 }
else if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
704 BinExpr->getLHS(), Ctx);
712 void PPCAsmParser::ProcessInstruction(
MCInst &Inst,
721 TmpInst.
setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
722 PPC::DCBT : PPC::DCBTST);
724 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
741 case PPC::DCBTSTDS: {
754 if (Opcode == PPC::DCBFL)
756 else if (Opcode == PPC::DCBFLP)
817 TmpInst.
setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
831 TmpInst.
setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
845 TmpInst.
setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
860 TmpInst.
setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
874 TmpInst.
setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
887 TmpInst.
setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
900 TmpInst.
setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
913 TmpInst.
setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
923 case PPC::CLRLSLWIo: {
927 TmpInst.
setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
941 TmpInst.
setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
954 TmpInst.
setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
967 TmpInst.
setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
980 TmpInst.
setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
992 TmpInst.
setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1000 case PPC::SUBPCIS: {
1013 TmpInst.
setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1022 case PPC::CLRRDIo: {
1025 TmpInst.
setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1034 case PPC::CLRLSLDIo: {
1038 TmpInst.
setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1047 case PPC::RLWINMobm: {
1054 TmpInst.
setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1064 case PPC::RLWIMIobm: {
1071 TmpInst.
setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1082 case PPC::RLWNMobm: {
1089 TmpInst.
setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1099 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1106 case PPC::CP_COPY_FIRST: {
1116 case PPC::CP_PASTEx :
1117 case PPC::CP_PASTE_LAST: {
1119 TmpInst.
setOpcode(Opcode == PPC::CP_PASTEx ?
1120 PPC::CP_PASTE : PPC::CP_PASTEo);
1132 unsigned VariantID = 0);
1134 bool PPCAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
1137 bool MatchingInlineAsm) {
1140 switch (MatchInstructionImpl(Operands, Inst,
ErrorInfo, MatchingInlineAsm)) {
1143 ProcessInstruction(Inst, Operands);
1147 case Match_MissingFeature:
1148 return Error(IDLoc,
"instruction use requires an option to be enabled");
1149 case Match_MnemonicFail: {
1150 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1152 ((PPCOperand &)*Operands[0]).
getToken(), FBS);
1153 return Error(IDLoc,
"invalid instruction" + Suggestion,
1154 ((PPCOperand &)*Operands[0]).getLocRange());
1156 case Match_InvalidOperand: {
1157 SMLoc ErrorLoc = IDLoc;
1160 return Error(IDLoc,
"too few operands for instruction");
1162 ErrorLoc = ((PPCOperand &)*Operands[
ErrorInfo]).getStartLoc();
1163 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
1166 return Error(ErrorLoc,
"invalid operand for instruction");
1177 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1180 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1183 RegNo = PPC::VRSAVE;
1212 ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
1213 const AsmToken &Tok = getParser().getTok();
1219 return TokError(
"invalid register name");
1229 const MCExpr *PPCAsmParser::
1230 ExtractModifierFromExpr(
const MCExpr *
E,
1289 const MCExpr *LHS = ExtractModifierFromExpr(BE->
getLHS(), LHSVariant);
1290 const MCExpr *RHS = ExtractModifierFromExpr(BE->
getRHS(), RHSVariant);
1295 if (!LHS) LHS = BE->
getLHS();
1296 if (!RHS) RHS = BE->
getRHS();
1299 Variant = RHSVariant;
1301 Variant = LHSVariant;
1302 else if (LHSVariant == RHSVariant)
1303 Variant = LHSVariant;
1318 const MCExpr *PPCAsmParser::
1319 FixupVariantKind(
const MCExpr *E) {
1368 ParseExpression(
const MCExpr *&EVal) {
1371 return ParseDarwinExpression(EVal);
1375 if (getParser().parseExpression(EVal))
1378 EVal = FixupVariantKind(EVal);
1381 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1395 ParseDarwinExpression(
const MCExpr *&EVal) {
1398 switch (getLexer().getKind()) {
1423 if (getParser().parseExpression(EVal))
1445 switch (getLexer().getKind()) {
1453 return Error(S,
"invalid register name");
1455 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1475 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1481 if (!ParseExpression(EVal))
1486 return Error(S,
"unknown operand");
1490 Operands.
push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1493 bool TLSCall =
false;
1495 TLSCall =
Ref->getSymbol().getName() ==
"__tls_get_addr";
1502 if (ParseExpression(TLSSym))
1503 return Error(S,
"invalid TLS call expression");
1509 Operands.
push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1518 switch (getLexer().getKind()) {
1523 return Error(S,
"invalid register name");
1528 return Error(S,
"unexpected integer value");
1529 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1531 return Error(S,
"invalid register number");
1543 return Error(S,
"invalid memory operand");
1549 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1561 std::string NewOpcode;
1574 size_t Dot = Name.
find(
'.');
1576 if (!NewOpcode.empty())
1578 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1580 Operands.
push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1584 if (!NewOpcode.empty())
1586 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1588 Operands.
push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1596 if (ParseOperand(Operands))
1612 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1613 Operands.
size() == 4 &&
1614 (Name ==
"dcbt" || Name ==
"dcbtst")) {
1623 bool PPCAsmParser::ParseDirective(
AsmToken DirectiveID) {
1626 if (IDVal ==
".machine")
1627 ParseDarwinDirectiveMachine(DirectiveID.
getLoc());
1630 }
else if (IDVal ==
".word")
1631 ParseDirectiveWord(2, DirectiveID);
1632 else if (IDVal ==
".llong")
1633 ParseDirectiveWord(8, DirectiveID);
1634 else if (IDVal ==
".tc")
1635 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1636 else if (IDVal ==
".machine")
1637 ParseDirectiveMachine(DirectiveID.
getLoc());
1638 else if (IDVal ==
".abiversion")
1639 ParseDirectiveAbiVersion(DirectiveID.
getLoc());
1640 else if (IDVal ==
".localentry")
1641 ParseDirectiveLocalEntry(DirectiveID.
getLoc());
1649 bool PPCAsmParser::ParseDirectiveWord(
unsigned Size,
AsmToken ID) {
1650 auto parseOp = [&]() ->
bool {
1652 SMLoc ExprLoc = getParser().getTok().getLoc();
1653 if (getParser().parseExpression(Value))
1655 if (
const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1656 assert(Size <= 8 &&
"Invalid size");
1657 uint64_t IntValue = MCE->getValue();
1658 if (!
isUIntN(8 * Size, IntValue) && !
isIntN(8 * Size, IntValue))
1659 return Error(ExprLoc,
"literal value out of range for '" +
1661 getStreamer().EmitIntValue(IntValue, Size);
1663 getStreamer().EmitValue(Value, Size, ExprLoc);
1667 if (parseMany(parseOp))
1668 return addErrorSuffix(
" in '" + ID.
getIdentifier() +
"' directive");
1674 bool PPCAsmParser::ParseDirectiveTC(
unsigned Size,
AsmToken ID) {
1681 return addErrorSuffix(
" in '.tc' directive");
1684 getParser().getStreamer().EmitValueToAlignment(Size);
1687 return ParseDirectiveWord(Size, ID);
1692 bool PPCAsmParser::ParseDirectiveMachine(
SMLoc L) {
1696 return Error(L,
"unexpected token in '.machine' directive");
1705 if (CPU !=
"any" && CPU !=
"push" && CPU !=
"pop")
1706 return TokError(
"unrecognized machine type");
1711 return addErrorSuffix(
" in '.machine' directive");
1715 getParser().getStreamer().getTargetStreamer());
1723 bool PPCAsmParser::ParseDarwinDirectiveMachine(
SMLoc L) {
1727 return Error(L,
"unexpected token in directive");
1735 if (check(CPU !=
"ppc7400" && CPU !=
"ppc" && CPU !=
"ppc64", L,
1736 "unrecognized cpu type") ||
1737 check(isPPC64() && (CPU ==
"ppc7400" || CPU ==
"ppc"), L,
1738 "wrong cpu type specified for 64bit") ||
1739 check(!isPPC64() && CPU ==
"ppc64", L,
1740 "wrong cpu type specified for 32bit") ||
1742 return addErrorSuffix(
" in '.machine' directive");
1748 bool PPCAsmParser::ParseDirectiveAbiVersion(
SMLoc L) {
1750 if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1751 "expected constant expression") ||
1753 return addErrorSuffix(
" in '.abiversion' directive");
1757 getParser().getStreamer().getTargetStreamer());
1765 bool PPCAsmParser::ParseDirectiveLocalEntry(
SMLoc L) {
1767 if (getParser().parseIdentifier(Name))
1768 return Error(L,
"expected identifier in '.localentry' directive");
1770 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1774 check(getParser().parseExpression(Expr), L,
"expected expression") ||
1776 return addErrorSuffix(
" in '.localentry' directive");
1780 getParser().getStreamer().getTargetStreamer());
1795 #define GET_REGISTER_MATCHER 1796 #define GET_MATCHER_IMPLEMENTATION 1797 #define GET_MNEMONIC_SPELL_CHECKER 1798 #include "PPCGenAsmMatcher.inc" 1809 case MCK_0: ImmVal = 0;
break;
1810 case MCK_1: ImmVal = 1;
break;
1811 case MCK_2: ImmVal = 2;
break;
1812 case MCK_3: ImmVal = 3;
break;
1813 case MCK_4: ImmVal = 4;
break;
1814 case MCK_5: ImmVal = 5;
break;
1815 case MCK_6: ImmVal = 6;
break;
1816 case MCK_7: ImmVal = 7;
break;
1817 default:
return Match_InvalidOperand;
1820 PPCOperand &
Op =
static_cast<PPCOperand &
>(AsmOp);
1821 if (Op.isImm() && Op.getImm() == ImmVal)
1822 return Match_Success;
1824 return Match_InvalidOperand;
1828 PPCAsmParser::applyModifierToExpr(
const MCExpr *E,
static bool isReg(const MCInst &MI, unsigned OpNo)
constexpr bool isUInt< 32 >(uint64_t x)
Represents a range in source code.
static int64_t EvaluateCRExpr(const MCExpr *E)
LLVM_NODISCARD bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
This class represents lattice values for constants.
static unsigned MatchRegisterName(StringRef Name)
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
VariantKind getKind() const
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Generic assembler parser interface, for use by target specific assembly parsers.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
void push_back(const T &Elt)
Target & getThePPC32Target()
bool isNot(TokenKind K) const
Opcode getOpcode() const
Get the kind of this unary expression.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
constexpr bool isInt< 16 >(int64_t x)
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
const Triple & getTargetTriple() const
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
static MCOperand createReg(unsigned Reg)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
The access may reference the value stored in memory.
Target independent representation for an assembler token.
Represent a reference to a symbol from inside an expression.
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
static bool isMem(const MachineInstr &MI, unsigned Op)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
Context object for machine code objects.
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Unary assembler expressions.
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
LLVM_NODISCARD size_t size() const
size - Get the string size.
const MCExpr * getExpr() const
Target & getThePPC64Target()
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
const char * getPointer() const
Streaming machine code generation interface.
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
constexpr bool isUInt< 8 >(uint64_t x)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void emitAbiVersion(int AbiVersion)=0
Interface to description of machine instruction set.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
static bool isDarwin(object::Archive::Kind Kind)
void LLVMInitializePowerPCAsmParser()
Force static initialization.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
unsigned getNumOperands() const
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Binary assembler expressions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void setOpcode(unsigned Op)
const MCSymbol & getSymbol() const
const MCOperand & getOperand(unsigned i) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Target & getThePPC64LETarget()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
static SMLoc getFromPointer(const char *Ptr)
MCExpr const & getExpr(MCExpr const &Expr)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Generic base class for all target subtargets.
References to labels and assigned expressions.
constexpr bool isUInt< 16 >(uint64_t x)
Opcode getOpcode() const
Get the kind of this binary expression.
StringRef getName() const
getName - Get the symbol name.
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
const MCExpr * getSubExpr() const
Get the child of this unary expression.
LLVM Value Representation.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
Target specific expression.
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
unsigned getOpcode() const
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
static std::string PPCMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID=0)