LLVM  8.0.0svn
PPCDisassembler.cpp
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1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "llvm/MC/MCInst.h"
15 #include "llvm/Support/Endian.h"
17 
18 using namespace llvm;
19 
20 #define DEBUG_TYPE "ppc-disassembler"
21 
23 
24 namespace {
25 class PPCDisassembler : public MCDisassembler {
26  bool IsLittleEndian;
27 
28 public:
29  PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
30  bool IsLittleEndian)
31  : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
32 
33  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
34  ArrayRef<uint8_t> Bytes, uint64_t Address,
35  raw_ostream &VStream,
36  raw_ostream &CStream) const override;
37 };
38 } // end anonymous namespace
39 
41  const MCSubtargetInfo &STI,
42  MCContext &Ctx) {
43  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
44 }
45 
47  const MCSubtargetInfo &STI,
48  MCContext &Ctx) {
49  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
50 }
51 
53  // Register the disassembler for each target.
60 }
61 
62 // FIXME: These can be generated by TableGen from the existing register
63 // encoding values!
64 
65 static const unsigned CRRegs[] = {
66  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
68 };
69 
70 static const unsigned CRBITRegs[] = {
71  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
72  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
73  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
74  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
75  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
76  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
77  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
78  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
79 };
80 
81 static const unsigned FRegs[] = {
82  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
83  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
84  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
85  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
86  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
87  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
88  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
89  PPC::F28, PPC::F29, PPC::F30, PPC::F31
90 };
91 
92 static const unsigned VFRegs[] = {
93  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
94  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
95  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
96  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
97  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
98  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
99  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
100  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
101 };
102 
103 static const unsigned VRegs[] = {
104  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
105  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
106  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
107  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
108  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
109  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
110  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
111  PPC::V28, PPC::V29, PPC::V30, PPC::V31
112 };
113 
114 static const unsigned VSRegs[] = {
115  PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
116  PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
117  PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
118  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
119  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
120  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
121  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
122  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
123 
124  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
125  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
126  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
127  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
128  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
129  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
130  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
131  PPC::V28, PPC::V29, PPC::V30, PPC::V31
132 };
133 
134 static const unsigned VSFRegs[] = {
135  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
136  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
137  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
138  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
139  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
140  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
141  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
142  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
143 
144  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
145  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
146  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
147  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
148  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
149  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
150  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
151  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
152 };
153 
154 static const unsigned VSSRegs[] = {
155  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
156  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
157  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
158  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
159  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
160  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
161  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
162  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
163 
164  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
165  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
166  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
167  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
168  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
169  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
170  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
171  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
172 };
173 
174 static const unsigned GPRegs[] = {
175  PPC::R0, PPC::R1, PPC::R2, PPC::R3,
176  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
177  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
178  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
179  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182  PPC::R28, PPC::R29, PPC::R30, PPC::R31
183 };
184 
185 static const unsigned GP0Regs[] = {
186  PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
187  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
188  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
189  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
190  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
191  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
192  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
193  PPC::R28, PPC::R29, PPC::R30, PPC::R31
194 };
195 
196 static const unsigned G8Regs[] = {
197  PPC::X0, PPC::X1, PPC::X2, PPC::X3,
198  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
199  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
200  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
201  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
202  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
203  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
204  PPC::X28, PPC::X29, PPC::X30, PPC::X31
205 };
206 
207 static const unsigned G80Regs[] = {
208  PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3,
209  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
210  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
211  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
212  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
213  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
214  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
215  PPC::X28, PPC::X29, PPC::X30, PPC::X31
216 };
217 
218 static const unsigned QFRegs[] = {
219  PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
220  PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
221  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
222  PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
223  PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
224  PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
225  PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
226  PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
227 };
228 
229 static const unsigned SPERegs[] = {
230  PPC::S0, PPC::S1, PPC::S2, PPC::S3,
231  PPC::S4, PPC::S5, PPC::S6, PPC::S7,
232  PPC::S8, PPC::S9, PPC::S10, PPC::S11,
233  PPC::S12, PPC::S13, PPC::S14, PPC::S15,
234  PPC::S16, PPC::S17, PPC::S18, PPC::S19,
235  PPC::S20, PPC::S21, PPC::S22, PPC::S23,
236  PPC::S24, PPC::S25, PPC::S26, PPC::S27,
237  PPC::S28, PPC::S29, PPC::S30, PPC::S31
238 };
239 
240 template <std::size_t N>
241 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
242  const unsigned (&Regs)[N]) {
243  assert(RegNo < N && "Invalid register number");
244  Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
246 }
247 
248 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
249  uint64_t Address,
250  const void *Decoder) {
251  return decodeRegisterClass(Inst, RegNo, CRRegs);
252 }
253 
254 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo,
255  uint64_t Address,
256  const void *Decoder) {
257  return decodeRegisterClass(Inst, RegNo, CRRegs);
258 }
259 
260 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
261  uint64_t Address,
262  const void *Decoder) {
263  return decodeRegisterClass(Inst, RegNo, CRBITRegs);
264 }
265 
266 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
267  uint64_t Address,
268  const void *Decoder) {
269  return decodeRegisterClass(Inst, RegNo, FRegs);
270 }
271 
272 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
273  uint64_t Address,
274  const void *Decoder) {
275  return decodeRegisterClass(Inst, RegNo, FRegs);
276 }
277 
278 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
279  uint64_t Address,
280  const void *Decoder) {
281  return decodeRegisterClass(Inst, RegNo, VFRegs);
282 }
283 
284 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
285  uint64_t Address,
286  const void *Decoder) {
287  return decodeRegisterClass(Inst, RegNo, VRegs);
288 }
289 
290 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
291  uint64_t Address,
292  const void *Decoder) {
293  return decodeRegisterClass(Inst, RegNo, VSRegs);
294 }
295 
296 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
297  uint64_t Address,
298  const void *Decoder) {
299  return decodeRegisterClass(Inst, RegNo, VSFRegs);
300 }
301 
302 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
303  uint64_t Address,
304  const void *Decoder) {
305  return decodeRegisterClass(Inst, RegNo, VSSRegs);
306 }
307 
308 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
309  uint64_t Address,
310  const void *Decoder) {
311  return decodeRegisterClass(Inst, RegNo, GPRegs);
312 }
313 
314 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
315  uint64_t Address,
316  const void *Decoder) {
317  return decodeRegisterClass(Inst, RegNo, GP0Regs);
318 }
319 
320 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
321  uint64_t Address,
322  const void *Decoder) {
323  return decodeRegisterClass(Inst, RegNo, G8Regs);
324 }
325 
326 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
327  uint64_t Address,
328  const void *Decoder) {
329  return decodeRegisterClass(Inst, RegNo, G80Regs);
330 }
331 
332 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
333 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
334 
335 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
336  uint64_t Address,
337  const void *Decoder) {
338  return decodeRegisterClass(Inst, RegNo, QFRegs);
339 }
340 
341 static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
342  uint64_t Address,
343  const void *Decoder) {
344  return decodeRegisterClass(Inst, RegNo, GPRegs);
345 }
346 
347 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
348  uint64_t Address,
349  const void *Decoder) {
350  return decodeRegisterClass(Inst, RegNo, SPERegs);
351 }
352 
353 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
354 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
355 
356 template<unsigned N>
357 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
358  int64_t Address, const void *Decoder) {
359  assert(isUInt<N>(Imm) && "Invalid immediate");
360  Inst.addOperand(MCOperand::createImm(Imm));
362 }
363 
364 template<unsigned N>
365 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
366  int64_t Address, const void *Decoder) {
367  assert(isUInt<N>(Imm) && "Invalid immediate");
368  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
370 }
371 
372 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
373  int64_t Address, const void *Decoder) {
374  // Decode the memri field (imm, reg), which has the low 16-bits as the
375  // displacement and the next 5 bits as the register #.
376 
377  uint64_t Base = Imm >> 16;
378  uint64_t Disp = Imm & 0xFFFF;
379 
380  assert(Base < 32 && "Invalid base register");
381 
382  switch (Inst.getOpcode()) {
383  default: break;
384  case PPC::LBZU:
385  case PPC::LHAU:
386  case PPC::LHZU:
387  case PPC::LWZU:
388  case PPC::LFSU:
389  case PPC::LFDU:
390  // Add the tied output operand.
391  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
392  break;
393  case PPC::STBU:
394  case PPC::STHU:
395  case PPC::STWU:
396  case PPC::STFSU:
397  case PPC::STFDU:
398  Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
399  break;
400  }
401 
402  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
403  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
405 }
406 
407 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
408  int64_t Address, const void *Decoder) {
409  // Decode the memrix field (imm, reg), which has the low 14-bits as the
410  // displacement and the next 5 bits as the register #.
411 
412  uint64_t Base = Imm >> 14;
413  uint64_t Disp = Imm & 0x3FFF;
414 
415  assert(Base < 32 && "Invalid base register");
416 
417  if (Inst.getOpcode() == PPC::LDU)
418  // Add the tied output operand.
419  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
420  else if (Inst.getOpcode() == PPC::STDU)
421  Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
422 
423  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
424  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
426 }
427 
428 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
429  int64_t Address, const void *Decoder) {
430  // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
431  // displacement with 16-byte aligned, and the next 5 bits as the register #.
432 
433  uint64_t Base = Imm >> 12;
434  uint64_t Disp = Imm & 0xFFF;
435 
436  assert(Base < 32 && "Invalid base register");
437 
438  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
439  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
441 }
442 
443 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
444  int64_t Address, const void *Decoder) {
445  // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
446  // displacement with 8-byte aligned, and the next 5 bits as the register #.
447 
448  uint64_t Base = Imm >> 5;
449  uint64_t Disp = Imm & 0x1F;
450 
451  assert(Base < 32 && "Invalid base register");
452 
453  Inst.addOperand(MCOperand::createImm(Disp << 3));
454  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
456 }
457 
458 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
459  int64_t Address, const void *Decoder) {
460  // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
461  // displacement with 4-byte aligned, and the next 5 bits as the register #.
462 
463  uint64_t Base = Imm >> 5;
464  uint64_t Disp = Imm & 0x1F;
465 
466  assert(Base < 32 && "Invalid base register");
467 
468  Inst.addOperand(MCOperand::createImm(Disp << 2));
469  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
471 }
472 
473 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
474  int64_t Address, const void *Decoder) {
475  // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
476  // displacement with 2-byte aligned, and the next 5 bits as the register #.
477 
478  uint64_t Base = Imm >> 5;
479  uint64_t Disp = Imm & 0x1F;
480 
481  assert(Base < 32 && "Invalid base register");
482 
483  Inst.addOperand(MCOperand::createImm(Disp << 1));
484  Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
486 }
487 
488 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
489  int64_t Address, const void *Decoder) {
490  // The cr bit encoding is 0x80 >> cr_reg_num.
491 
492  unsigned Zeros = countTrailingZeros(Imm);
493  assert(Zeros < 8 && "Invalid CR bit value");
494 
495  Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
497 }
498 
499 #include "PPCGenDisassemblerTables.inc"
500 
501 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
502  ArrayRef<uint8_t> Bytes,
503  uint64_t Address, raw_ostream &OS,
504  raw_ostream &CS) const {
505  // Get the four bytes of the instruction.
506  Size = 4;
507  if (Bytes.size() < 4) {
508  Size = 0;
509  return MCDisassembler::Fail;
510  }
511 
512  // Read the instruction in the proper endianness.
513  uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data())
514  : support::endian::read32be(Bytes.data());
515 
516  if (STI.getFeatureBits()[PPC::FeatureQPX]) {
517  DecodeStatus result =
518  decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
519  if (result != MCDisassembler::Fail)
520  return result;
521  } else if (STI.getFeatureBits()[PPC::FeatureSPE]) {
522  DecodeStatus result =
523  decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
524  if (result != MCDisassembler::Fail)
525  return result;
526  }
527 
528  return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
529 }
530 
iterator begin()
Definition: MCInst.h:194
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
#define R4(n)
static const unsigned GPRegs[]
static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static const unsigned VSSRegs[]
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static const unsigned SPERegs[]
Superclass for all disassemblers.
Target & getThePPC32Target()
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
#define R2(n)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
uint32_t read32be(const void *P)
Definition: Endian.h:372
static const unsigned VFRegs[]
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:63
static const unsigned VSRegs[]
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Target & getThePPC64Target()
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned GP0Regs[]
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned G8Regs[]
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static const unsigned FRegs[]
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
const T * data() const
Definition: ArrayRef.h:146
static const unsigned CRRegs[]
#define R6(n)
static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned VSFRegs[]
static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static const unsigned QFRegs[]
static const unsigned VRegs[]
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned(&Regs)[N])
void LLVMInitializePowerPCDisassembler()
static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
#define N
uint32_t read32le(const void *P)
Definition: Endian.h:369
Generic base class for all target subtargets.
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
uint32_t Size
Definition: Profile.cpp:47
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const unsigned G80Regs[]
static const unsigned CRBITRegs[]
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
unsigned getOpcode() const
Definition: MCInst.h:174
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123