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PPCFastISel.cpp
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1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "PPC.h"
18 #include "PPCCCState.h"
19 #include "PPCCallingConv.h"
20 #include "PPCISelLowering.h"
21 #include "PPCMachineFunctionInfo.h"
22 #include "PPCSubtarget.h"
23 #include "PPCTargetMachine.h"
24 #include "llvm/ADT/Optional.h"
26 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/GlobalAlias.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/IntrinsicInst.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/Support/Debug.h"
41 
42 //===----------------------------------------------------------------------===//
43 //
44 // TBD:
45 // fastLowerArguments: Handle simple cases.
46 // PPCMaterializeGV: Handle TLS.
47 // SelectCall: Handle function pointers.
48 // SelectCall: Handle multi-register return values.
49 // SelectCall: Optimize away nops for local calls.
50 // processCallArgs: Handle bit-converted arguments.
51 // finishCall: Handle multi-register return values.
52 // PPCComputeAddress: Handle parameter references as FrameIndex's.
53 // PPCEmitCmp: Handle immediate as operand 1.
54 // SelectCall: Handle small byval arguments.
55 // SelectIntrinsicCall: Implement.
56 // SelectSelect: Implement.
57 // Consider factoring isTypeLegal into the base class.
58 // Implement switches and jump tables.
59 //
60 //===----------------------------------------------------------------------===//
61 using namespace llvm;
62 
63 #define DEBUG_TYPE "ppcfastisel"
64 
65 namespace {
66 
67 typedef struct Address {
68  enum {
69  RegBase,
70  FrameIndexBase
71  } BaseType;
72 
73  union {
74  unsigned Reg;
75  int FI;
76  } Base;
77 
78  long Offset;
79 
80  // Innocuous defaults for our address.
81  Address()
82  : BaseType(RegBase), Offset(0) {
83  Base.Reg = 0;
84  }
85 } Address;
86 
87 class PPCFastISel final : public FastISel {
88 
89  const TargetMachine &TM;
90  const PPCSubtarget *PPCSubTarget;
91  PPCFunctionInfo *PPCFuncInfo;
92  const TargetInstrInfo &TII;
93  const TargetLowering &TLI;
95 
96  public:
97  explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
98  const TargetLibraryInfo *LibInfo)
99  : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
100  PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
101  PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
102  TII(*PPCSubTarget->getInstrInfo()),
103  TLI(*PPCSubTarget->getTargetLowering()),
104  Context(&FuncInfo.Fn->getContext()) {}
105 
106  // Backend specific FastISel code.
107  private:
108  bool fastSelectInstruction(const Instruction *I) override;
109  unsigned fastMaterializeConstant(const Constant *C) override;
110  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
111  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
112  const LoadInst *LI) override;
113  bool fastLowerArguments() override;
114  unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
115  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
116  const TargetRegisterClass *RC,
117  unsigned Op0, bool Op0IsKill,
118  uint64_t Imm);
119  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
120  const TargetRegisterClass *RC,
121  unsigned Op0, bool Op0IsKill);
122  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
123  const TargetRegisterClass *RC,
124  unsigned Op0, bool Op0IsKill,
125  unsigned Op1, bool Op1IsKill);
126 
127  bool fastLowerCall(CallLoweringInfo &CLI) override;
128 
129  // Instruction selection routines.
130  private:
131  bool SelectLoad(const Instruction *I);
132  bool SelectStore(const Instruction *I);
133  bool SelectBranch(const Instruction *I);
134  bool SelectIndirectBr(const Instruction *I);
135  bool SelectFPExt(const Instruction *I);
136  bool SelectFPTrunc(const Instruction *I);
137  bool SelectIToFP(const Instruction *I, bool IsSigned);
138  bool SelectFPToI(const Instruction *I, bool IsSigned);
139  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
140  bool SelectRet(const Instruction *I);
141  bool SelectTrunc(const Instruction *I);
142  bool SelectIntExt(const Instruction *I);
143 
144  // Utility routines.
145  private:
146  bool isTypeLegal(Type *Ty, MVT &VT);
147  bool isLoadTypeLegal(Type *Ty, MVT &VT);
148  bool isValueAvailable(const Value *V) const;
149  bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
150  return RC->getID() == PPC::VSFRCRegClassID;
151  }
152  bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
153  return RC->getID() == PPC::VSSRCRegClassID;
154  }
155  bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
156  bool isZExt, unsigned DestReg,
157  const PPC::Predicate Pred);
158  bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
159  const TargetRegisterClass *RC, bool IsZExt = true,
160  unsigned FP64LoadOpc = PPC::LFD);
161  bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
162  bool PPCComputeAddress(const Value *Obj, Address &Addr);
163  void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
164  unsigned &IndexReg);
165  bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
166  unsigned DestReg, bool IsZExt);
167  unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
168  unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
169  unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
170  bool UseSExt = true);
171  unsigned PPCMaterialize32BitInt(int64_t Imm,
172  const TargetRegisterClass *RC);
173  unsigned PPCMaterialize64BitInt(int64_t Imm,
174  const TargetRegisterClass *RC);
175  unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
176  unsigned SrcReg, bool IsSigned);
177  unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
178 
179  // Call handling routines.
180  private:
181  bool processCallArgs(SmallVectorImpl<Value*> &Args,
182  SmallVectorImpl<unsigned> &ArgRegs,
183  SmallVectorImpl<MVT> &ArgVTs,
185  SmallVectorImpl<unsigned> &RegArgs,
186  CallingConv::ID CC,
187  unsigned &NumBytes,
188  bool IsVarArg);
189  bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
190  LLVM_ATTRIBUTE_UNUSED CCAssignFn *usePPC32CCs(unsigned Flag);
191 
192  private:
193  #include "PPCGenFastISel.inc"
194 
195 };
196 
197 } // end anonymous namespace
198 
199 #include "PPCGenCallingConv.inc"
200 
201 // Function whose sole purpose is to kill compiler warnings
202 // stemming from unused functions included from PPCGenCallingConv.inc.
203 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
204  if (Flag == 1)
205  return CC_PPC32_SVR4;
206  else if (Flag == 2)
207  return CC_PPC32_SVR4_ByVal;
208  else if (Flag == 3)
209  return CC_PPC32_SVR4_VarArg;
210  else if (Flag == 4)
211  return RetCC_PPC_Cold;
212  else
213  return RetCC_PPC;
214 }
215 
217  switch (Pred) {
218  // These are not representable with any single compare.
219  case CmpInst::FCMP_FALSE:
220  case CmpInst::FCMP_TRUE:
221  // Major concern about the following 6 cases is NaN result. The comparison
222  // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
223  // only one of which will be set. The result is generated by fcmpu
224  // instruction. However, bc instruction only inspects one of the first 3
225  // bits, so when un is set, bc instruction may jump to an undesired
226  // place.
227  //
228  // More specifically, if we expect an unordered comparison and un is set, we
229  // expect to always go to true branch; in such case UEQ, UGT and ULT still
230  // give false, which are undesired; but UNE, UGE, ULE happen to give true,
231  // since they are tested by inspecting !eq, !lt, !gt, respectively.
232  //
233  // Similarly, for ordered comparison, when un is set, we always expect the
234  // result to be false. In such case OGT, OLT and OEQ is good, since they are
235  // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
236  // and ONE are tested through !lt, !gt and !eq, and these are true.
237  case CmpInst::FCMP_UEQ:
238  case CmpInst::FCMP_UGT:
239  case CmpInst::FCMP_ULT:
240  case CmpInst::FCMP_OGE:
241  case CmpInst::FCMP_OLE:
242  case CmpInst::FCMP_ONE:
243  default:
244  return Optional<PPC::Predicate>();
245 
246  case CmpInst::FCMP_OEQ:
247  case CmpInst::ICMP_EQ:
248  return PPC::PRED_EQ;
249 
250  case CmpInst::FCMP_OGT:
251  case CmpInst::ICMP_UGT:
252  case CmpInst::ICMP_SGT:
253  return PPC::PRED_GT;
254 
255  case CmpInst::FCMP_UGE:
256  case CmpInst::ICMP_UGE:
257  case CmpInst::ICMP_SGE:
258  return PPC::PRED_GE;
259 
260  case CmpInst::FCMP_OLT:
261  case CmpInst::ICMP_ULT:
262  case CmpInst::ICMP_SLT:
263  return PPC::PRED_LT;
264 
265  case CmpInst::FCMP_ULE:
266  case CmpInst::ICMP_ULE:
267  case CmpInst::ICMP_SLE:
268  return PPC::PRED_LE;
269 
270  case CmpInst::FCMP_UNE:
271  case CmpInst::ICMP_NE:
272  return PPC::PRED_NE;
273 
274  case CmpInst::FCMP_ORD:
275  return PPC::PRED_NU;
276 
277  case CmpInst::FCMP_UNO:
278  return PPC::PRED_UN;
279  }
280 }
281 
282 // Determine whether the type Ty is simple enough to be handled by
283 // fast-isel, and return its equivalent machine type in VT.
284 // FIXME: Copied directly from ARM -- factor into base class?
285 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
286  EVT Evt = TLI.getValueType(DL, Ty, true);
287 
288  // Only handle simple types.
289  if (Evt == MVT::Other || !Evt.isSimple()) return false;
290  VT = Evt.getSimpleVT();
291 
292  // Handle all legal types, i.e. a register that will directly hold this
293  // value.
294  return TLI.isTypeLegal(VT);
295 }
296 
297 // Determine whether the type Ty is simple enough to be handled by
298 // fast-isel as a load target, and return its equivalent machine type in VT.
299 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
300  if (isTypeLegal(Ty, VT)) return true;
301 
302  // If this is a type than can be sign or zero-extended to a basic operation
303  // go ahead and accept it now.
304  if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
305  return true;
306  }
307 
308  return false;
309 }
310 
311 bool PPCFastISel::isValueAvailable(const Value *V) const {
312  if (!isa<Instruction>(V))
313  return true;
314 
315  const auto *I = cast<Instruction>(V);
316  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
317 }
318 
319 // Given a value Obj, create an Address object Addr that represents its
320 // address. Return false if we can't handle it.
321 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
322  const User *U = nullptr;
323  unsigned Opcode = Instruction::UserOp1;
324  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
325  // Don't walk into other basic blocks unless the object is an alloca from
326  // another block, otherwise it may not have a virtual register assigned.
327  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
328  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
329  Opcode = I->getOpcode();
330  U = I;
331  }
332  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
333  Opcode = C->getOpcode();
334  U = C;
335  }
336 
337  switch (Opcode) {
338  default:
339  break;
340  case Instruction::BitCast:
341  // Look through bitcasts.
342  return PPCComputeAddress(U->getOperand(0), Addr);
343  case Instruction::IntToPtr:
344  // Look past no-op inttoptrs.
345  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
346  TLI.getPointerTy(DL))
347  return PPCComputeAddress(U->getOperand(0), Addr);
348  break;
349  case Instruction::PtrToInt:
350  // Look past no-op ptrtoints.
351  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
352  return PPCComputeAddress(U->getOperand(0), Addr);
353  break;
354  case Instruction::GetElementPtr: {
355  Address SavedAddr = Addr;
356  long TmpOffset = Addr.Offset;
357 
358  // Iterate through the GEP folding the constants into offsets where
359  // we can.
361  for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
362  II != IE; ++II, ++GTI) {
363  const Value *Op = *II;
364  if (StructType *STy = GTI.getStructTypeOrNull()) {
365  const StructLayout *SL = DL.getStructLayout(STy);
366  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
367  TmpOffset += SL->getElementOffset(Idx);
368  } else {
369  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
370  for (;;) {
371  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
372  // Constant-offset addressing.
373  TmpOffset += CI->getSExtValue() * S;
374  break;
375  }
376  if (canFoldAddIntoGEP(U, Op)) {
377  // A compatible add with a constant operand. Fold the constant.
378  ConstantInt *CI =
379  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
380  TmpOffset += CI->getSExtValue() * S;
381  // Iterate on the other operand.
382  Op = cast<AddOperator>(Op)->getOperand(0);
383  continue;
384  }
385  // Unsupported
386  goto unsupported_gep;
387  }
388  }
389  }
390 
391  // Try to grab the base operand now.
392  Addr.Offset = TmpOffset;
393  if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
394 
395  // We failed, restore everything and try the other options.
396  Addr = SavedAddr;
397 
398  unsupported_gep:
399  break;
400  }
401  case Instruction::Alloca: {
402  const AllocaInst *AI = cast<AllocaInst>(Obj);
404  FuncInfo.StaticAllocaMap.find(AI);
405  if (SI != FuncInfo.StaticAllocaMap.end()) {
406  Addr.BaseType = Address::FrameIndexBase;
407  Addr.Base.FI = SI->second;
408  return true;
409  }
410  break;
411  }
412  }
413 
414  // FIXME: References to parameters fall through to the behavior
415  // below. They should be able to reference a frame index since
416  // they are stored to the stack, so we can get "ld rx, offset(r1)"
417  // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
418  // just contain the parameter. Try to handle this with a FI.
419 
420  // Try to get this in a register if nothing else has worked.
421  if (Addr.Base.Reg == 0)
422  Addr.Base.Reg = getRegForValue(Obj);
423 
424  // Prevent assignment of base register to X0, which is inappropriate
425  // for loads and stores alike.
426  if (Addr.Base.Reg != 0)
427  MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
428 
429  return Addr.Base.Reg != 0;
430 }
431 
432 // Fix up some addresses that can't be used directly. For example, if
433 // an offset won't fit in an instruction field, we may need to move it
434 // into an index register.
435 void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
436  unsigned &IndexReg) {
437 
438  // Check whether the offset fits in the instruction field.
439  if (!isInt<16>(Addr.Offset))
440  UseOffset = false;
441 
442  // If this is a stack pointer and the offset needs to be simplified then
443  // put the alloca address into a register, set the base type back to
444  // register and continue. This should almost never happen.
445  if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
446  unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
447  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
448  ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
449  Addr.Base.Reg = ResultReg;
450  Addr.BaseType = Address::RegBase;
451  }
452 
453  if (!UseOffset) {
454  IntegerType *OffsetTy = Type::getInt64Ty(*Context);
455  const ConstantInt *Offset =
456  ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
457  IndexReg = PPCMaterializeInt(Offset, MVT::i64);
458  assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
459  }
460 }
461 
462 // Emit a load instruction if possible, returning true if we succeeded,
463 // otherwise false. See commentary below for how the register class of
464 // the load is determined.
465 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
466  const TargetRegisterClass *RC,
467  bool IsZExt, unsigned FP64LoadOpc) {
468  unsigned Opc;
469  bool UseOffset = true;
470  bool HasSPE = PPCSubTarget->hasSPE();
471 
472  // If ResultReg is given, it determines the register class of the load.
473  // Otherwise, RC is the register class to use. If the result of the
474  // load isn't anticipated in this block, both may be zero, in which
475  // case we must make a conservative guess. In particular, don't assign
476  // R0 or X0 to the result register, as the result may be used in a load,
477  // store, add-immediate, or isel that won't permit this. (Though
478  // perhaps the spill and reload of live-exit values would handle this?)
479  const TargetRegisterClass *UseRC =
480  (ResultReg ? MRI.getRegClass(ResultReg) :
481  (RC ? RC :
482  (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
483  (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
484  (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
485  &PPC::GPRC_and_GPRC_NOR0RegClass)))));
486 
487  bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
488 
489  switch (VT.SimpleTy) {
490  default: // e.g., vector types not handled
491  return false;
492  case MVT::i8:
493  Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
494  break;
495  case MVT::i16:
496  Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
497  : (Is32BitInt ? PPC::LHA : PPC::LHA8));
498  break;
499  case MVT::i32:
500  Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
501  : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
502  if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
503  UseOffset = false;
504  break;
505  case MVT::i64:
506  Opc = PPC::LD;
507  assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
508  "64-bit load with 32-bit target??");
509  UseOffset = ((Addr.Offset & 3) == 0);
510  break;
511  case MVT::f32:
512  Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
513  break;
514  case MVT::f64:
515  Opc = FP64LoadOpc;
516  break;
517  }
518 
519  // If necessary, materialize the offset into a register and use
520  // the indexed form. Also handle stack pointers with special needs.
521  unsigned IndexReg = 0;
522  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
523 
524  // If this is a potential VSX load with an offset of 0, a VSX indexed load can
525  // be used.
526  bool IsVSSRC = isVSSRCRegClass(UseRC);
527  bool IsVSFRC = isVSFRCRegClass(UseRC);
528  bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
529  bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
530  if ((Is32VSXLoad || Is64VSXLoad) &&
531  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
532  (Addr.Offset == 0)) {
533  UseOffset = false;
534  }
535 
536  if (ResultReg == 0)
537  ResultReg = createResultReg(UseRC);
538 
539  // Note: If we still have a frame index here, we know the offset is
540  // in range, as otherwise PPCSimplifyAddress would have converted it
541  // into a RegBase.
542  if (Addr.BaseType == Address::FrameIndexBase) {
543  // VSX only provides an indexed load.
544  if (Is32VSXLoad || Is64VSXLoad) return false;
545 
546  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
547  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
548  Addr.Offset),
549  MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
550  MFI.getObjectAlignment(Addr.Base.FI));
551 
552  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
553  .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
554 
555  // Base reg with offset in range.
556  } else if (UseOffset) {
557  // VSX only provides an indexed load.
558  if (Is32VSXLoad || Is64VSXLoad) return false;
559 
560  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
561  .addImm(Addr.Offset).addReg(Addr.Base.Reg);
562 
563  // Indexed form.
564  } else {
565  // Get the RR opcode corresponding to the RI one. FIXME: It would be
566  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
567  // is hard to get at.
568  switch (Opc) {
569  default: llvm_unreachable("Unexpected opcode!");
570  case PPC::LBZ: Opc = PPC::LBZX; break;
571  case PPC::LBZ8: Opc = PPC::LBZX8; break;
572  case PPC::LHZ: Opc = PPC::LHZX; break;
573  case PPC::LHZ8: Opc = PPC::LHZX8; break;
574  case PPC::LHA: Opc = PPC::LHAX; break;
575  case PPC::LHA8: Opc = PPC::LHAX8; break;
576  case PPC::LWZ: Opc = PPC::LWZX; break;
577  case PPC::LWZ8: Opc = PPC::LWZX8; break;
578  case PPC::LWA: Opc = PPC::LWAX; break;
579  case PPC::LWA_32: Opc = PPC::LWAX_32; break;
580  case PPC::LD: Opc = PPC::LDX; break;
581  case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
582  case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
583  case PPC::EVLDD: Opc = PPC::EVLDDX; break;
584  case PPC::SPELWZ: Opc = PPC::SPELWZX; break;
585  }
586 
587  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
588  ResultReg);
589 
590  // If we have an index register defined we use it in the store inst,
591  // otherwise we use X0 as base as it makes the vector instructions to
592  // use zero in the computation of the effective address regardless the
593  // content of the register.
594  if (IndexReg)
595  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
596  else
597  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
598  }
599 
600  return true;
601 }
602 
603 // Attempt to fast-select a load instruction.
604 bool PPCFastISel::SelectLoad(const Instruction *I) {
605  // FIXME: No atomic loads are supported.
606  if (cast<LoadInst>(I)->isAtomic())
607  return false;
608 
609  // Verify we have a legal type before going any further.
610  MVT VT;
611  if (!isLoadTypeLegal(I->getType(), VT))
612  return false;
613 
614  // See if we can handle this address.
615  Address Addr;
616  if (!PPCComputeAddress(I->getOperand(0), Addr))
617  return false;
618 
619  // Look at the currently assigned register for this instruction
620  // to determine the required register class. This is necessary
621  // to constrain RA from using R0/X0 when this is not legal.
622  unsigned AssignedReg = FuncInfo.ValueMap[I];
623  const TargetRegisterClass *RC =
624  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
625 
626  unsigned ResultReg = 0;
627  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
628  PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
629  return false;
630  updateValueMap(I, ResultReg);
631  return true;
632 }
633 
634 // Emit a store instruction to store SrcReg at Addr.
635 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
636  assert(SrcReg && "Nothing to store!");
637  unsigned Opc;
638  bool UseOffset = true;
639 
640  const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
641  bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
642 
643  switch (VT.SimpleTy) {
644  default: // e.g., vector types not handled
645  return false;
646  case MVT::i8:
647  Opc = Is32BitInt ? PPC::STB : PPC::STB8;
648  break;
649  case MVT::i16:
650  Opc = Is32BitInt ? PPC::STH : PPC::STH8;
651  break;
652  case MVT::i32:
653  assert(Is32BitInt && "Not GPRC for i32??");
654  Opc = PPC::STW;
655  break;
656  case MVT::i64:
657  Opc = PPC::STD;
658  UseOffset = ((Addr.Offset & 3) == 0);
659  break;
660  case MVT::f32:
661  Opc = PPCSubTarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
662  break;
663  case MVT::f64:
664  Opc = PPCSubTarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
665  break;
666  }
667 
668  // If necessary, materialize the offset into a register and use
669  // the indexed form. Also handle stack pointers with special needs.
670  unsigned IndexReg = 0;
671  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
672 
673  // If this is a potential VSX store with an offset of 0, a VSX indexed store
674  // can be used.
675  bool IsVSSRC = isVSSRCRegClass(RC);
676  bool IsVSFRC = isVSFRCRegClass(RC);
677  bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
678  bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
679  if ((Is32VSXStore || Is64VSXStore) &&
680  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
681  (Addr.Offset == 0)) {
682  UseOffset = false;
683  }
684 
685  // Note: If we still have a frame index here, we know the offset is
686  // in range, as otherwise PPCSimplifyAddress would have converted it
687  // into a RegBase.
688  if (Addr.BaseType == Address::FrameIndexBase) {
689  // VSX only provides an indexed store.
690  if (Is32VSXStore || Is64VSXStore) return false;
691 
692  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
693  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
694  Addr.Offset),
695  MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
696  MFI.getObjectAlignment(Addr.Base.FI));
697 
698  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
699  .addReg(SrcReg)
700  .addImm(Addr.Offset)
701  .addFrameIndex(Addr.Base.FI)
702  .addMemOperand(MMO);
703 
704  // Base reg with offset in range.
705  } else if (UseOffset) {
706  // VSX only provides an indexed store.
707  if (Is32VSXStore || Is64VSXStore)
708  return false;
709 
710  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
711  .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
712 
713  // Indexed form.
714  } else {
715  // Get the RR opcode corresponding to the RI one. FIXME: It would be
716  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
717  // is hard to get at.
718  switch (Opc) {
719  default: llvm_unreachable("Unexpected opcode!");
720  case PPC::STB: Opc = PPC::STBX; break;
721  case PPC::STH : Opc = PPC::STHX; break;
722  case PPC::STW : Opc = PPC::STWX; break;
723  case PPC::STB8: Opc = PPC::STBX8; break;
724  case PPC::STH8: Opc = PPC::STHX8; break;
725  case PPC::STW8: Opc = PPC::STWX8; break;
726  case PPC::STD: Opc = PPC::STDX; break;
727  case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
728  case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
729  case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
730  case PPC::SPESTW: Opc = PPC::SPESTWX; break;
731  }
732 
733  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
734  .addReg(SrcReg);
735 
736  // If we have an index register defined we use it in the store inst,
737  // otherwise we use X0 as base as it makes the vector instructions to
738  // use zero in the computation of the effective address regardless the
739  // content of the register.
740  if (IndexReg)
741  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
742  else
743  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
744  }
745 
746  return true;
747 }
748 
749 // Attempt to fast-select a store instruction.
750 bool PPCFastISel::SelectStore(const Instruction *I) {
751  Value *Op0 = I->getOperand(0);
752  unsigned SrcReg = 0;
753 
754  // FIXME: No atomics loads are supported.
755  if (cast<StoreInst>(I)->isAtomic())
756  return false;
757 
758  // Verify we have a legal type before going any further.
759  MVT VT;
760  if (!isLoadTypeLegal(Op0->getType(), VT))
761  return false;
762 
763  // Get the value to be stored into a register.
764  SrcReg = getRegForValue(Op0);
765  if (SrcReg == 0)
766  return false;
767 
768  // See if we can handle this address.
769  Address Addr;
770  if (!PPCComputeAddress(I->getOperand(1), Addr))
771  return false;
772 
773  if (!PPCEmitStore(VT, SrcReg, Addr))
774  return false;
775 
776  return true;
777 }
778 
779 // Attempt to fast-select a branch instruction.
780 bool PPCFastISel::SelectBranch(const Instruction *I) {
781  const BranchInst *BI = cast<BranchInst>(I);
782  MachineBasicBlock *BrBB = FuncInfo.MBB;
783  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
784  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
785 
786  // For now, just try the simplest case where it's fed by a compare.
787  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
788  if (isValueAvailable(CI)) {
789  Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
790  if (!OptPPCPred)
791  return false;
792 
793  PPC::Predicate PPCPred = OptPPCPred.getValue();
794 
795  // Take advantage of fall-through opportunities.
796  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
797  std::swap(TBB, FBB);
798  PPCPred = PPC::InvertPredicate(PPCPred);
799  }
800 
801  unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
802 
803  if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
804  CondReg, PPCPred))
805  return false;
806 
807  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
808  .addImm(PPCSubTarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
809  .addReg(CondReg).addMBB(TBB);
810  finishCondBranch(BI->getParent(), TBB, FBB);
811  return true;
812  }
813  } else if (const ConstantInt *CI =
814  dyn_cast<ConstantInt>(BI->getCondition())) {
815  uint64_t Imm = CI->getZExtValue();
816  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
817  fastEmitBranch(Target, DbgLoc);
818  return true;
819  }
820 
821  // FIXME: ARM looks for a case where the block containing the compare
822  // has been split from the block containing the branch. If this happens,
823  // there is a vreg available containing the result of the compare. I'm
824  // not sure we can do much, as we've lost the predicate information with
825  // the compare instruction -- we have a 4-bit CR but don't know which bit
826  // to test here.
827  return false;
828 }
829 
830 // Attempt to emit a compare of the two source values. Signed and unsigned
831 // comparisons are supported. Return false if we can't handle it.
832 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
833  bool IsZExt, unsigned DestReg,
834  const PPC::Predicate Pred) {
835  Type *Ty = SrcValue1->getType();
836  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
837  if (!SrcEVT.isSimple())
838  return false;
839  MVT SrcVT = SrcEVT.getSimpleVT();
840 
841  if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
842  return false;
843 
844  // See if operand 2 is an immediate encodeable in the compare.
845  // FIXME: Operands are not in canonical order at -O0, so an immediate
846  // operand in position 1 is a lost opportunity for now. We are
847  // similar to ARM in this regard.
848  long Imm = 0;
849  bool UseImm = false;
850  const bool HasSPE = PPCSubTarget->hasSPE();
851 
852  // Only 16-bit integer constants can be represented in compares for
853  // PowerPC. Others will be materialized into a register.
854  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
855  if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
856  SrcVT == MVT::i8 || SrcVT == MVT::i1) {
857  const APInt &CIVal = ConstInt->getValue();
858  Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
859  if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
860  UseImm = true;
861  }
862  }
863 
864  unsigned CmpOpc;
865  bool NeedsExt = false;
866  switch (SrcVT.SimpleTy) {
867  default: return false;
868  case MVT::f32:
869  if (HasSPE) {
870  switch (Pred) {
871  default: return false;
872  case PPC::PRED_EQ:
873  CmpOpc = PPC::EFSCMPEQ;
874  break;
875  case PPC::PRED_LT:
876  CmpOpc = PPC::EFSCMPLT;
877  break;
878  case PPC::PRED_GT:
879  CmpOpc = PPC::EFSCMPGT;
880  break;
881  }
882  } else
883  CmpOpc = PPC::FCMPUS;
884  break;
885  case MVT::f64:
886  if (HasSPE) {
887  switch (Pred) {
888  default: return false;
889  case PPC::PRED_EQ:
890  CmpOpc = PPC::EFDCMPEQ;
891  break;
892  case PPC::PRED_LT:
893  CmpOpc = PPC::EFDCMPLT;
894  break;
895  case PPC::PRED_GT:
896  CmpOpc = PPC::EFDCMPGT;
897  break;
898  }
899  } else
900  CmpOpc = PPC::FCMPUD;
901  break;
902  case MVT::i1:
903  case MVT::i8:
904  case MVT::i16:
905  NeedsExt = true;
906  // Intentional fall-through.
907  case MVT::i32:
908  if (!UseImm)
909  CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
910  else
911  CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
912  break;
913  case MVT::i64:
914  if (!UseImm)
915  CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
916  else
917  CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
918  break;
919  }
920 
921  unsigned SrcReg1 = getRegForValue(SrcValue1);
922  if (SrcReg1 == 0)
923  return false;
924 
925  unsigned SrcReg2 = 0;
926  if (!UseImm) {
927  SrcReg2 = getRegForValue(SrcValue2);
928  if (SrcReg2 == 0)
929  return false;
930  }
931 
932  if (NeedsExt) {
933  unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
934  if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
935  return false;
936  SrcReg1 = ExtReg;
937 
938  if (!UseImm) {
939  unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
940  if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
941  return false;
942  SrcReg2 = ExtReg;
943  }
944  }
945 
946  if (!UseImm)
947  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
948  .addReg(SrcReg1).addReg(SrcReg2);
949  else
950  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
951  .addReg(SrcReg1).addImm(Imm);
952 
953  return true;
954 }
955 
956 // Attempt to fast-select a floating-point extend instruction.
957 bool PPCFastISel::SelectFPExt(const Instruction *I) {
958  Value *Src = I->getOperand(0);
959  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
960  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
961 
962  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
963  return false;
964 
965  unsigned SrcReg = getRegForValue(Src);
966  if (!SrcReg)
967  return false;
968 
969  // No code is generated for a FP extend.
970  updateValueMap(I, SrcReg);
971  return true;
972 }
973 
974 // Attempt to fast-select a floating-point truncate instruction.
975 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
976  Value *Src = I->getOperand(0);
977  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
978  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
979 
980  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
981  return false;
982 
983  unsigned SrcReg = getRegForValue(Src);
984  if (!SrcReg)
985  return false;
986 
987  // Round the result to single precision.
988  unsigned DestReg;
989 
990  if (PPCSubTarget->hasSPE()) {
991  DestReg = createResultReg(&PPC::SPE4RCRegClass);
992  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
993  TII.get(PPC::EFSCFD), DestReg)
994  .addReg(SrcReg);
995  } else {
996  DestReg = createResultReg(&PPC::F4RCRegClass);
997  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
998  TII.get(PPC::FRSP), DestReg)
999  .addReg(SrcReg);
1000  }
1001 
1002  updateValueMap(I, DestReg);
1003  return true;
1004 }
1005 
1006 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1007 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1008 // those should be used instead of moving via a stack slot when the
1009 // subtarget permits.
1010 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
1011 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
1012 // case to 8 bytes which produces tighter code but wastes stack space.
1013 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1014  bool IsSigned) {
1015 
1016  // If necessary, extend 32-bit int to 64-bit.
1017  if (SrcVT == MVT::i32) {
1018  unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1019  if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1020  return 0;
1021  SrcReg = TmpReg;
1022  }
1023 
1024  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1025  Address Addr;
1026  Addr.BaseType = Address::FrameIndexBase;
1027  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1028 
1029  // Store the value from the GPR.
1030  if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1031  return 0;
1032 
1033  // Load the integer value into an FPR. The kind of load used depends
1034  // on a number of conditions.
1035  unsigned LoadOpc = PPC::LFD;
1036 
1037  if (SrcVT == MVT::i32) {
1038  if (!IsSigned) {
1039  LoadOpc = PPC::LFIWZX;
1040  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1041  } else if (PPCSubTarget->hasLFIWAX()) {
1042  LoadOpc = PPC::LFIWAX;
1043  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1044  }
1045  }
1046 
1047  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1048  unsigned ResultReg = 0;
1049  if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1050  return 0;
1051 
1052  return ResultReg;
1053 }
1054 
1055 // Attempt to fast-select an integer-to-floating-point conversion.
1056 // FIXME: Once fast-isel has better support for VSX, conversions using
1057 // direct moves should be implemented.
1058 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1059  MVT DstVT;
1060  Type *DstTy = I->getType();
1061  if (!isTypeLegal(DstTy, DstVT))
1062  return false;
1063 
1064  if (DstVT != MVT::f32 && DstVT != MVT::f64)
1065  return false;
1066 
1067  Value *Src = I->getOperand(0);
1068  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1069  if (!SrcEVT.isSimple())
1070  return false;
1071 
1072  MVT SrcVT = SrcEVT.getSimpleVT();
1073 
1074  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1075  SrcVT != MVT::i32 && SrcVT != MVT::i64)
1076  return false;
1077 
1078  unsigned SrcReg = getRegForValue(Src);
1079  if (SrcReg == 0)
1080  return false;
1081 
1082  // Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs
1083  if (PPCSubTarget->hasSPE()) {
1084  unsigned Opc;
1085  if (DstVT == MVT::f32)
1086  Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1087  else
1088  Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1089 
1090  unsigned DestReg = createResultReg(&PPC::SPERCRegClass);
1091  // Generate the convert.
1092  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1093  .addReg(SrcReg);
1094  updateValueMap(I, DestReg);
1095  return true;
1096  }
1097 
1098  // We can only lower an unsigned convert if we have the newer
1099  // floating-point conversion operations.
1100  if (!IsSigned && !PPCSubTarget->hasFPCVT())
1101  return false;
1102 
1103  // FIXME: For now we require the newer floating-point conversion operations
1104  // (which are present only on P7 and A2 server models) when converting
1105  // to single-precision float. Otherwise we have to generate a lot of
1106  // fiddly code to avoid double rounding. If necessary, the fiddly code
1107  // can be found in PPCTargetLowering::LowerINT_TO_FP().
1108  if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1109  return false;
1110 
1111  // Extend the input if necessary.
1112  if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1113  unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1114  if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1115  return false;
1116  SrcVT = MVT::i64;
1117  SrcReg = TmpReg;
1118  }
1119 
1120  // Move the integer value to an FPR.
1121  unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1122  if (FPReg == 0)
1123  return false;
1124 
1125  // Determine the opcode for the conversion.
1126  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1127  unsigned DestReg = createResultReg(RC);
1128  unsigned Opc;
1129 
1130  if (DstVT == MVT::f32)
1131  Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1132  else
1133  Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1134 
1135  // Generate the convert.
1136  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1137  .addReg(FPReg);
1138 
1139  updateValueMap(I, DestReg);
1140  return true;
1141 }
1142 
1143 // Move the floating-point value in SrcReg into an integer destination
1144 // register, and return the register (or zero if we can't handle it).
1145 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1146 // those should be used instead of moving via a stack slot when the
1147 // subtarget permits.
1148 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1149  unsigned SrcReg, bool IsSigned) {
1150  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1151  // Note that if have STFIWX available, we could use a 4-byte stack
1152  // slot for i32, but this being fast-isel we'll just go with the
1153  // easiest code gen possible.
1154  Address Addr;
1155  Addr.BaseType = Address::FrameIndexBase;
1156  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1157 
1158  // Store the value from the FPR.
1159  if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1160  return 0;
1161 
1162  // Reload it into a GPR. If we want an i32 on big endian, modify the
1163  // address to have a 4-byte offset so we load from the right place.
1164  if (VT == MVT::i32)
1165  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1166 
1167  // Look at the currently assigned register for this instruction
1168  // to determine the required register class.
1169  unsigned AssignedReg = FuncInfo.ValueMap[I];
1170  const TargetRegisterClass *RC =
1171  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1172 
1173  unsigned ResultReg = 0;
1174  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1175  return 0;
1176 
1177  return ResultReg;
1178 }
1179 
1180 // Attempt to fast-select a floating-point-to-integer conversion.
1181 // FIXME: Once fast-isel has better support for VSX, conversions using
1182 // direct moves should be implemented.
1183 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1184  MVT DstVT, SrcVT;
1185  Type *DstTy = I->getType();
1186  if (!isTypeLegal(DstTy, DstVT))
1187  return false;
1188 
1189  if (DstVT != MVT::i32 && DstVT != MVT::i64)
1190  return false;
1191 
1192  // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1193  if (DstVT == MVT::i64 && !IsSigned &&
1194  !PPCSubTarget->hasFPCVT() && !PPCSubTarget->hasSPE())
1195  return false;
1196 
1197  Value *Src = I->getOperand(0);
1198  Type *SrcTy = Src->getType();
1199  if (!isTypeLegal(SrcTy, SrcVT))
1200  return false;
1201 
1202  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1203  return false;
1204 
1205  unsigned SrcReg = getRegForValue(Src);
1206  if (SrcReg == 0)
1207  return false;
1208 
1209  // Convert f32 to f64 if necessary. This is just a meaningless copy
1210  // to get the register class right.
1211  const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1212  if (InRC == &PPC::F4RCRegClass) {
1213  unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1214  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1215  TII.get(TargetOpcode::COPY), TmpReg)
1216  .addReg(SrcReg);
1217  SrcReg = TmpReg;
1218  }
1219 
1220  // Determine the opcode for the conversion, which takes place
1221  // entirely within FPRs.
1222  unsigned DestReg;
1223  unsigned Opc;
1224 
1225  if (PPCSubTarget->hasSPE()) {
1226  DestReg = createResultReg(&PPC::GPRCRegClass);
1227  if (IsSigned)
1228  Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1229  else
1230  Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1231  } else {
1232  DestReg = createResultReg(&PPC::F8RCRegClass);
1233  if (DstVT == MVT::i32)
1234  if (IsSigned)
1235  Opc = PPC::FCTIWZ;
1236  else
1237  Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1238  else
1239  Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1240  }
1241 
1242  // Generate the convert.
1243  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1244  .addReg(SrcReg);
1245 
1246  // Now move the integer value from a float register to an integer register.
1247  unsigned IntReg = PPCSubTarget->hasSPE() ? DestReg :
1248  PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1249 
1250  if (IntReg == 0)
1251  return false;
1252 
1253  updateValueMap(I, IntReg);
1254  return true;
1255 }
1256 
1257 // Attempt to fast-select a binary integer operation that isn't already
1258 // handled automatically.
1259 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1260  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1261 
1262  // We can get here in the case when we have a binary operation on a non-legal
1263  // type and the target independent selector doesn't know how to handle it.
1264  if (DestVT != MVT::i16 && DestVT != MVT::i8)
1265  return false;
1266 
1267  // Look at the currently assigned register for this instruction
1268  // to determine the required register class. If there is no register,
1269  // make a conservative choice (don't assign R0).
1270  unsigned AssignedReg = FuncInfo.ValueMap[I];
1271  const TargetRegisterClass *RC =
1272  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1273  &PPC::GPRC_and_GPRC_NOR0RegClass);
1274  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1275 
1276  unsigned Opc;
1277  switch (ISDOpcode) {
1278  default: return false;
1279  case ISD::ADD:
1280  Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1281  break;
1282  case ISD::OR:
1283  Opc = IsGPRC ? PPC::OR : PPC::OR8;
1284  break;
1285  case ISD::SUB:
1286  Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1287  break;
1288  }
1289 
1290  unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1291  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1292  if (SrcReg1 == 0) return false;
1293 
1294  // Handle case of small immediate operand.
1295  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1296  const APInt &CIVal = ConstInt->getValue();
1297  int Imm = (int)CIVal.getSExtValue();
1298  bool UseImm = true;
1299  if (isInt<16>(Imm)) {
1300  switch (Opc) {
1301  default:
1302  llvm_unreachable("Missing case!");
1303  case PPC::ADD4:
1304  Opc = PPC::ADDI;
1305  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1306  break;
1307  case PPC::ADD8:
1308  Opc = PPC::ADDI8;
1309  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1310  break;
1311  case PPC::OR:
1312  Opc = PPC::ORI;
1313  break;
1314  case PPC::OR8:
1315  Opc = PPC::ORI8;
1316  break;
1317  case PPC::SUBF:
1318  if (Imm == -32768)
1319  UseImm = false;
1320  else {
1321  Opc = PPC::ADDI;
1322  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1323  Imm = -Imm;
1324  }
1325  break;
1326  case PPC::SUBF8:
1327  if (Imm == -32768)
1328  UseImm = false;
1329  else {
1330  Opc = PPC::ADDI8;
1331  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1332  Imm = -Imm;
1333  }
1334  break;
1335  }
1336 
1337  if (UseImm) {
1338  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1339  ResultReg)
1340  .addReg(SrcReg1)
1341  .addImm(Imm);
1342  updateValueMap(I, ResultReg);
1343  return true;
1344  }
1345  }
1346  }
1347 
1348  // Reg-reg case.
1349  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1350  if (SrcReg2 == 0) return false;
1351 
1352  // Reverse operands for subtract-from.
1353  if (ISDOpcode == ISD::SUB)
1354  std::swap(SrcReg1, SrcReg2);
1355 
1356  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1357  .addReg(SrcReg1).addReg(SrcReg2);
1358  updateValueMap(I, ResultReg);
1359  return true;
1360 }
1361 
1362 // Handle arguments to a call that we're attempting to fast-select.
1363 // Return false if the arguments are too complex for us at the moment.
1364 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1365  SmallVectorImpl<unsigned> &ArgRegs,
1366  SmallVectorImpl<MVT> &ArgVTs,
1368  SmallVectorImpl<unsigned> &RegArgs,
1369  CallingConv::ID CC,
1370  unsigned &NumBytes,
1371  bool IsVarArg) {
1373  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1374 
1375  // Reserve space for the linkage area on the stack.
1376  unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1377  CCInfo.AllocateStack(LinkageSize, 8);
1378 
1379  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1380 
1381  // Bail out if we can't handle any of the arguments.
1382  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1383  CCValAssign &VA = ArgLocs[I];
1384  MVT ArgVT = ArgVTs[VA.getValNo()];
1385 
1386  // Skip vector arguments for now, as well as long double and
1387  // uint128_t, and anything that isn't passed in a register.
1388  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1389  !VA.isRegLoc() || VA.needsCustom())
1390  return false;
1391 
1392  // Skip bit-converted arguments for now.
1393  if (VA.getLocInfo() == CCValAssign::BCvt)
1394  return false;
1395  }
1396 
1397  // Get a count of how many bytes are to be pushed onto the stack.
1398  NumBytes = CCInfo.getNextStackOffset();
1399 
1400  // The prolog code of the callee may store up to 8 GPR argument registers to
1401  // the stack, allowing va_start to index over them in memory if its varargs.
1402  // Because we cannot tell if this is needed on the caller side, we have to
1403  // conservatively assume that it is needed. As such, make sure we have at
1404  // least enough stack space for the caller to store the 8 GPRs.
1405  // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1406  NumBytes = std::max(NumBytes, LinkageSize + 64);
1407 
1408  // Issue CALLSEQ_START.
1409  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1410  TII.get(TII.getCallFrameSetupOpcode()))
1411  .addImm(NumBytes).addImm(0);
1412 
1413  // Prepare to assign register arguments. Every argument uses up a
1414  // GPR protocol register even if it's passed in a floating-point
1415  // register (unless we're using the fast calling convention).
1416  unsigned NextGPR = PPC::X3;
1417  unsigned NextFPR = PPC::F1;
1418 
1419  // Process arguments.
1420  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1421  CCValAssign &VA = ArgLocs[I];
1422  unsigned Arg = ArgRegs[VA.getValNo()];
1423  MVT ArgVT = ArgVTs[VA.getValNo()];
1424 
1425  // Handle argument promotion and bitcasts.
1426  switch (VA.getLocInfo()) {
1427  default:
1428  llvm_unreachable("Unknown loc info!");
1429  case CCValAssign::Full:
1430  break;
1431  case CCValAssign::SExt: {
1432  MVT DestVT = VA.getLocVT();
1433  const TargetRegisterClass *RC =
1434  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1435  unsigned TmpReg = createResultReg(RC);
1436  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1437  llvm_unreachable("Failed to emit a sext!");
1438  ArgVT = DestVT;
1439  Arg = TmpReg;
1440  break;
1441  }
1442  case CCValAssign::AExt:
1443  case CCValAssign::ZExt: {
1444  MVT DestVT = VA.getLocVT();
1445  const TargetRegisterClass *RC =
1446  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1447  unsigned TmpReg = createResultReg(RC);
1448  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1449  llvm_unreachable("Failed to emit a zext!");
1450  ArgVT = DestVT;
1451  Arg = TmpReg;
1452  break;
1453  }
1454  case CCValAssign::BCvt: {
1455  // FIXME: Not yet handled.
1456  llvm_unreachable("Should have bailed before getting here!");
1457  break;
1458  }
1459  }
1460 
1461  // Copy this argument to the appropriate register.
1462  unsigned ArgReg;
1463  if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1464  ArgReg = NextFPR++;
1465  if (CC != CallingConv::Fast)
1466  ++NextGPR;
1467  } else
1468  ArgReg = NextGPR++;
1469 
1470  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1471  TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1472  RegArgs.push_back(ArgReg);
1473  }
1474 
1475  return true;
1476 }
1477 
1478 // For a call that we've determined we can fast-select, finish the
1479 // call sequence and generate a copy to obtain the return value (if any).
1480 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1481  CallingConv::ID CC = CLI.CallConv;
1482 
1483  // Issue CallSEQ_END.
1484  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1485  TII.get(TII.getCallFrameDestroyOpcode()))
1486  .addImm(NumBytes).addImm(0);
1487 
1488  // Next, generate a copy to obtain the return value.
1489  // FIXME: No multi-register return values yet, though I don't foresee
1490  // any real difficulties there.
1491  if (RetVT != MVT::isVoid) {
1493  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1494  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1495  CCValAssign &VA = RVLocs[0];
1496  assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1497  assert(VA.isRegLoc() && "Can only return in registers!");
1498 
1499  MVT DestVT = VA.getValVT();
1500  MVT CopyVT = DestVT;
1501 
1502  // Ints smaller than a register still arrive in a full 64-bit
1503  // register, so make sure we recognize this.
1504  if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1505  CopyVT = MVT::i64;
1506 
1507  unsigned SourcePhysReg = VA.getLocReg();
1508  unsigned ResultReg = 0;
1509 
1510  if (RetVT == CopyVT) {
1511  const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1512  ResultReg = createResultReg(CpyRC);
1513 
1514  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1515  TII.get(TargetOpcode::COPY), ResultReg)
1516  .addReg(SourcePhysReg);
1517 
1518  // If necessary, round the floating result to single precision.
1519  } else if (CopyVT == MVT::f64) {
1520  ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1521  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1522  ResultReg).addReg(SourcePhysReg);
1523 
1524  // If only the low half of a general register is needed, generate
1525  // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1526  // used along the fast-isel path (not lowered), and downstream logic
1527  // also doesn't like a direct subreg copy on a physical reg.)
1528  } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1529  ResultReg = createResultReg(&PPC::GPRCRegClass);
1530  // Convert physical register from G8RC to GPRC.
1531  SourcePhysReg -= PPC::X0 - PPC::R0;
1532  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1533  TII.get(TargetOpcode::COPY), ResultReg)
1534  .addReg(SourcePhysReg);
1535  }
1536 
1537  assert(ResultReg && "ResultReg unset!");
1538  CLI.InRegs.push_back(SourcePhysReg);
1539  CLI.ResultReg = ResultReg;
1540  CLI.NumResultRegs = 1;
1541  }
1542 
1543  return true;
1544 }
1545 
1546 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1547  CallingConv::ID CC = CLI.CallConv;
1548  bool IsTailCall = CLI.IsTailCall;
1549  bool IsVarArg = CLI.IsVarArg;
1550  const Value *Callee = CLI.Callee;
1551  const MCSymbol *Symbol = CLI.Symbol;
1552 
1553  if (!Callee && !Symbol)
1554  return false;
1555 
1556  // Allow SelectionDAG isel to handle tail calls.
1557  if (IsTailCall)
1558  return false;
1559 
1560  // Let SDISel handle vararg functions.
1561  if (IsVarArg)
1562  return false;
1563 
1564  // Handle simple calls for now, with legal return types and
1565  // those that can be extended.
1566  Type *RetTy = CLI.RetTy;
1567  MVT RetVT;
1568  if (RetTy->isVoidTy())
1569  RetVT = MVT::isVoid;
1570  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1571  RetVT != MVT::i8)
1572  return false;
1573  else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1574  // We can't handle boolean returns when CR bits are in use.
1575  return false;
1576 
1577  // FIXME: No multi-register return values yet.
1578  if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1579  RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1580  RetVT != MVT::f64) {
1582  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1583  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1584  if (RVLocs.size() > 1)
1585  return false;
1586  }
1587 
1588  // Bail early if more than 8 arguments, as we only currently
1589  // handle arguments passed in registers.
1590  unsigned NumArgs = CLI.OutVals.size();
1591  if (NumArgs > 8)
1592  return false;
1593 
1594  // Set up the argument vectors.
1596  SmallVector<unsigned, 8> ArgRegs;
1597  SmallVector<MVT, 8> ArgVTs;
1599 
1600  Args.reserve(NumArgs);
1601  ArgRegs.reserve(NumArgs);
1602  ArgVTs.reserve(NumArgs);
1603  ArgFlags.reserve(NumArgs);
1604 
1605  for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1606  // Only handle easy calls for now. It would be reasonably easy
1607  // to handle <= 8-byte structures passed ByVal in registers, but we
1608  // have to ensure they are right-justified in the register.
1609  ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1610  if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1611  return false;
1612 
1613  Value *ArgValue = CLI.OutVals[i];
1614  Type *ArgTy = ArgValue->getType();
1615  MVT ArgVT;
1616  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1617  return false;
1618 
1619  if (ArgVT.isVector())
1620  return false;
1621 
1622  unsigned Arg = getRegForValue(ArgValue);
1623  if (Arg == 0)
1624  return false;
1625 
1626  Args.push_back(ArgValue);
1627  ArgRegs.push_back(Arg);
1628  ArgVTs.push_back(ArgVT);
1629  ArgFlags.push_back(Flags);
1630  }
1631 
1632  // Process the arguments.
1633  SmallVector<unsigned, 8> RegArgs;
1634  unsigned NumBytes;
1635 
1636  if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1637  RegArgs, CC, NumBytes, IsVarArg))
1638  return false;
1639 
1640  MachineInstrBuilder MIB;
1641  // FIXME: No handling for function pointers yet. This requires
1642  // implementing the function descriptor (OPD) setup.
1643  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1644  if (!GV) {
1645  // patchpoints are a special case; they always dispatch to a pointer value.
1646  // However, we don't actually want to generate the indirect call sequence
1647  // here (that will be generated, as necessary, during asm printing), and
1648  // the call we generate here will be erased by FastISel::selectPatchpoint,
1649  // so don't try very hard...
1650  if (CLI.IsPatchPoint)
1651  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1652  else
1653  return false;
1654  } else {
1655  // Build direct call with NOP for TOC restore.
1656  // FIXME: We can and should optimize away the NOP for local calls.
1657  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1658  TII.get(PPC::BL8_NOP));
1659  // Add callee.
1660  MIB.addGlobalAddress(GV);
1661  }
1662 
1663  // Add implicit physical register uses to the call.
1664  for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1665  MIB.addReg(RegArgs[II], RegState::Implicit);
1666 
1667  // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1668  // into the call.
1669  PPCFuncInfo->setUsesTOCBasePtr();
1670  MIB.addReg(PPC::X2, RegState::Implicit);
1671 
1672  // Add a register mask with the call-preserved registers. Proper
1673  // defs for return values will be added by setPhysRegsDeadExcept().
1674  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1675 
1676  CLI.Call = MIB;
1677 
1678  // Finish off the call including any return values.
1679  return finishCall(RetVT, CLI, NumBytes);
1680 }
1681 
1682 // Attempt to fast-select a return instruction.
1683 bool PPCFastISel::SelectRet(const Instruction *I) {
1684 
1685  if (!FuncInfo.CanLowerReturn)
1686  return false;
1687 
1688  if (TLI.supportSplitCSR(FuncInfo.MF))
1689  return false;
1690 
1691  const ReturnInst *Ret = cast<ReturnInst>(I);
1692  const Function &F = *I->getParent()->getParent();
1693 
1694  // Build a list of return value registers.
1695  SmallVector<unsigned, 4> RetRegs;
1696  CallingConv::ID CC = F.getCallingConv();
1697 
1698  if (Ret->getNumOperands() > 0) {
1700  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1701 
1702  // Analyze operands of the call, assigning locations to each operand.
1704  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1705  CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1706  const Value *RV = Ret->getOperand(0);
1707 
1708  // FIXME: Only one output register for now.
1709  if (ValLocs.size() > 1)
1710  return false;
1711 
1712  // Special case for returning a constant integer of any size - materialize
1713  // the constant as an i64 and copy it to the return register.
1714  if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1715  CCValAssign &VA = ValLocs[0];
1716 
1717  unsigned RetReg = VA.getLocReg();
1718  // We still need to worry about properly extending the sign. For example,
1719  // we could have only a single bit or a constant that needs zero
1720  // extension rather than sign extension. Make sure we pass the return
1721  // value extension property to integer materialization.
1722  unsigned SrcReg =
1723  PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1724 
1725  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1726  TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1727 
1728  RetRegs.push_back(RetReg);
1729 
1730  } else {
1731  unsigned Reg = getRegForValue(RV);
1732 
1733  if (Reg == 0)
1734  return false;
1735 
1736  // Copy the result values into the output registers.
1737  for (unsigned i = 0; i < ValLocs.size(); ++i) {
1738 
1739  CCValAssign &VA = ValLocs[i];
1740  assert(VA.isRegLoc() && "Can only return in registers!");
1741  RetRegs.push_back(VA.getLocReg());
1742  unsigned SrcReg = Reg + VA.getValNo();
1743 
1744  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1745  if (!RVEVT.isSimple())
1746  return false;
1747  MVT RVVT = RVEVT.getSimpleVT();
1748  MVT DestVT = VA.getLocVT();
1749 
1750  if (RVVT != DestVT && RVVT != MVT::i8 &&
1751  RVVT != MVT::i16 && RVVT != MVT::i32)
1752  return false;
1753 
1754  if (RVVT != DestVT) {
1755  switch (VA.getLocInfo()) {
1756  default:
1757  llvm_unreachable("Unknown loc info!");
1758  case CCValAssign::Full:
1759  llvm_unreachable("Full value assign but types don't match?");
1760  case CCValAssign::AExt:
1761  case CCValAssign::ZExt: {
1762  const TargetRegisterClass *RC =
1763  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1764  unsigned TmpReg = createResultReg(RC);
1765  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1766  return false;
1767  SrcReg = TmpReg;
1768  break;
1769  }
1770  case CCValAssign::SExt: {
1771  const TargetRegisterClass *RC =
1772  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1773  unsigned TmpReg = createResultReg(RC);
1774  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1775  return false;
1776  SrcReg = TmpReg;
1777  break;
1778  }
1779  }
1780  }
1781 
1782  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1783  TII.get(TargetOpcode::COPY), RetRegs[i])
1784  .addReg(SrcReg);
1785  }
1786  }
1787  }
1788 
1789  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1790  TII.get(PPC::BLR8));
1791 
1792  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1793  MIB.addReg(RetRegs[i], RegState::Implicit);
1794 
1795  return true;
1796 }
1797 
1798 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1799 // signed and zero extensions are supported. Return false if we
1800 // can't handle it.
1801 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1802  unsigned DestReg, bool IsZExt) {
1803  if (DestVT != MVT::i32 && DestVT != MVT::i64)
1804  return false;
1805  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1806  return false;
1807 
1808  // Signed extensions use EXTSB, EXTSH, EXTSW.
1809  if (!IsZExt) {
1810  unsigned Opc;
1811  if (SrcVT == MVT::i8)
1812  Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1813  else if (SrcVT == MVT::i16)
1814  Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1815  else {
1816  assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1817  Opc = PPC::EXTSW_32_64;
1818  }
1819  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1820  .addReg(SrcReg);
1821 
1822  // Unsigned 32-bit extensions use RLWINM.
1823  } else if (DestVT == MVT::i32) {
1824  unsigned MB;
1825  if (SrcVT == MVT::i8)
1826  MB = 24;
1827  else {
1828  assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1829  MB = 16;
1830  }
1831  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1832  DestReg)
1833  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1834 
1835  // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1836  } else {
1837  unsigned MB;
1838  if (SrcVT == MVT::i8)
1839  MB = 56;
1840  else if (SrcVT == MVT::i16)
1841  MB = 48;
1842  else
1843  MB = 32;
1844  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1845  TII.get(PPC::RLDICL_32_64), DestReg)
1846  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1847  }
1848 
1849  return true;
1850 }
1851 
1852 // Attempt to fast-select an indirect branch instruction.
1853 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1854  unsigned AddrReg = getRegForValue(I->getOperand(0));
1855  if (AddrReg == 0)
1856  return false;
1857 
1858  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1859  .addReg(AddrReg);
1860  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1861 
1862  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1863  for (const BasicBlock *SuccBB : IB->successors())
1864  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1865 
1866  return true;
1867 }
1868 
1869 // Attempt to fast-select an integer truncate instruction.
1870 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1871  Value *Src = I->getOperand(0);
1872  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1873  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1874 
1875  if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1876  return false;
1877 
1878  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1879  return false;
1880 
1881  unsigned SrcReg = getRegForValue(Src);
1882  if (!SrcReg)
1883  return false;
1884 
1885  // The only interesting case is when we need to switch register classes.
1886  if (SrcVT == MVT::i64) {
1887  unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1888  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1889  TII.get(TargetOpcode::COPY),
1890  ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1891  SrcReg = ResultReg;
1892  }
1893 
1894  updateValueMap(I, SrcReg);
1895  return true;
1896 }
1897 
1898 // Attempt to fast-select an integer extend instruction.
1899 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1900  Type *DestTy = I->getType();
1901  Value *Src = I->getOperand(0);
1902  Type *SrcTy = Src->getType();
1903 
1904  bool IsZExt = isa<ZExtInst>(I);
1905  unsigned SrcReg = getRegForValue(Src);
1906  if (!SrcReg) return false;
1907 
1908  EVT SrcEVT, DestEVT;
1909  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1910  DestEVT = TLI.getValueType(DL, DestTy, true);
1911  if (!SrcEVT.isSimple())
1912  return false;
1913  if (!DestEVT.isSimple())
1914  return false;
1915 
1916  MVT SrcVT = SrcEVT.getSimpleVT();
1917  MVT DestVT = DestEVT.getSimpleVT();
1918 
1919  // If we know the register class needed for the result of this
1920  // instruction, use it. Otherwise pick the register class of the
1921  // correct size that does not contain X0/R0, since we don't know
1922  // whether downstream uses permit that assignment.
1923  unsigned AssignedReg = FuncInfo.ValueMap[I];
1924  const TargetRegisterClass *RC =
1925  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1926  (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1927  &PPC::GPRC_and_GPRC_NOR0RegClass));
1928  unsigned ResultReg = createResultReg(RC);
1929 
1930  if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1931  return false;
1932 
1933  updateValueMap(I, ResultReg);
1934  return true;
1935 }
1936 
1937 // Attempt to fast-select an instruction that wasn't handled by
1938 // the table-generated machinery.
1939 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1940 
1941  switch (I->getOpcode()) {
1942  case Instruction::Load:
1943  return SelectLoad(I);
1944  case Instruction::Store:
1945  return SelectStore(I);
1946  case Instruction::Br:
1947  return SelectBranch(I);
1948  case Instruction::IndirectBr:
1949  return SelectIndirectBr(I);
1950  case Instruction::FPExt:
1951  return SelectFPExt(I);
1952  case Instruction::FPTrunc:
1953  return SelectFPTrunc(I);
1954  case Instruction::SIToFP:
1955  return SelectIToFP(I, /*IsSigned*/ true);
1956  case Instruction::UIToFP:
1957  return SelectIToFP(I, /*IsSigned*/ false);
1958  case Instruction::FPToSI:
1959  return SelectFPToI(I, /*IsSigned*/ true);
1960  case Instruction::FPToUI:
1961  return SelectFPToI(I, /*IsSigned*/ false);
1962  case Instruction::Add:
1963  return SelectBinaryIntOp(I, ISD::ADD);
1964  case Instruction::Or:
1965  return SelectBinaryIntOp(I, ISD::OR);
1966  case Instruction::Sub:
1967  return SelectBinaryIntOp(I, ISD::SUB);
1968  case Instruction::Call:
1969  return selectCall(I);
1970  case Instruction::Ret:
1971  return SelectRet(I);
1972  case Instruction::Trunc:
1973  return SelectTrunc(I);
1974  case Instruction::ZExt:
1975  case Instruction::SExt:
1976  return SelectIntExt(I);
1977  // Here add other flavors of Instruction::XXX that automated
1978  // cases don't catch. For example, switches are terminators
1979  // that aren't yet handled.
1980  default:
1981  break;
1982  }
1983  return false;
1984 }
1985 
1986 // Materialize a floating-point constant into a register, and return
1987 // the register number (or zero if we failed to handle it).
1988 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1989  // No plans to handle long double here.
1990  if (VT != MVT::f32 && VT != MVT::f64)
1991  return 0;
1992 
1993  // All FP constants are loaded from the constant pool.
1994  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1995  assert(Align > 0 && "Unexpectedly missing alignment information!");
1996  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1997  const bool HasSPE = PPCSubTarget->hasSPE();
1998  const TargetRegisterClass *RC;
1999  if (HasSPE)
2000  RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
2001  else
2002  RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2003 
2004  unsigned DestReg = createResultReg(RC);
2005  CodeModel::Model CModel = TM.getCodeModel();
2006 
2007  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2009  MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
2010 
2011  unsigned Opc;
2012 
2013  if (HasSPE)
2014  Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2015  else
2016  Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2017 
2018  unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2019 
2020  PPCFuncInfo->setUsesTOCBasePtr();
2021  // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2022  if (CModel == CodeModel::Small) {
2023  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2024  TmpReg)
2025  .addConstantPoolIndex(Idx).addReg(PPC::X2);
2026  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2027  .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2028  } else {
2029  // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
2030  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
2031  TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2032  // But for large code model, we must generate a LDtocL followed
2033  // by the LF[SD].
2034  if (CModel == CodeModel::Large) {
2035  unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2036  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2037  TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2038  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2039  .addImm(0)
2040  .addReg(TmpReg2);
2041  } else
2042  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2043  .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
2044  .addReg(TmpReg)
2045  .addMemOperand(MMO);
2046  }
2047 
2048  return DestReg;
2049 }
2050 
2051 // Materialize the address of a global value into a register, and return
2052 // the register number (or zero if we failed to handle it).
2053 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2054  assert(VT == MVT::i64 && "Non-address!");
2055  const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2056  unsigned DestReg = createResultReg(RC);
2057 
2058  // Global values may be plain old object addresses, TLS object
2059  // addresses, constant pool entries, or jump tables. How we generate
2060  // code for these may depend on small, medium, or large code model.
2061  CodeModel::Model CModel = TM.getCodeModel();
2062 
2063  // FIXME: Jump tables are not yet required because fast-isel doesn't
2064  // handle switches; if that changes, we need them as well. For now,
2065  // what follows assumes everything's a generic (or TLS) global address.
2066 
2067  // FIXME: We don't yet handle the complexity of TLS.
2068  if (GV->isThreadLocal())
2069  return 0;
2070 
2071  PPCFuncInfo->setUsesTOCBasePtr();
2072  // For small code model, generate a simple TOC load.
2073  if (CModel == CodeModel::Small)
2074  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2075  DestReg)
2076  .addGlobalAddress(GV)
2077  .addReg(PPC::X2);
2078  else {
2079  // If the address is an externally defined symbol, a symbol with common
2080  // or externally available linkage, a non-local function address, or a
2081  // jump table address (not yet needed), or if we are generating code
2082  // for large code model, we generate:
2083  // LDtocL(GV, ADDIStocHA(%x2, GV))
2084  // Otherwise we generate:
2085  // ADDItocL(ADDIStocHA(%x2, GV), GV)
2086  // Either way, start with the ADDIStocHA:
2087  unsigned HighPartReg = createResultReg(RC);
2088  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
2089  HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2090 
2091  unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
2092  if (GVFlags & PPCII::MO_NLP_FLAG) {
2093  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2094  DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2095  } else {
2096  // Otherwise generate the ADDItocL.
2097  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2098  DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2099  }
2100  }
2101 
2102  return DestReg;
2103 }
2104 
2105 // Materialize a 32-bit integer constant into a register, and return
2106 // the register number (or zero if we failed to handle it).
2107 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2108  const TargetRegisterClass *RC) {
2109  unsigned Lo = Imm & 0xFFFF;
2110  unsigned Hi = (Imm >> 16) & 0xFFFF;
2111 
2112  unsigned ResultReg = createResultReg(RC);
2113  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2114 
2115  if (isInt<16>(Imm))
2116  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2117  TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2118  .addImm(Imm);
2119  else if (Lo) {
2120  // Both Lo and Hi have nonzero bits.
2121  unsigned TmpReg = createResultReg(RC);
2122  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2123  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2124  .addImm(Hi);
2125  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2126  TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2127  .addReg(TmpReg).addImm(Lo);
2128  } else
2129  // Just Hi bits.
2130  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2131  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2132  .addImm(Hi);
2133 
2134  return ResultReg;
2135 }
2136 
2137 // Materialize a 64-bit integer constant into a register, and return
2138 // the register number (or zero if we failed to handle it).
2139 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2140  const TargetRegisterClass *RC) {
2141  unsigned Remainder = 0;
2142  unsigned Shift = 0;
2143 
2144  // If the value doesn't fit in 32 bits, see if we can shift it
2145  // so that it fits in 32 bits.
2146  if (!isInt<32>(Imm)) {
2147  Shift = countTrailingZeros<uint64_t>(Imm);
2148  int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2149 
2150  if (isInt<32>(ImmSh))
2151  Imm = ImmSh;
2152  else {
2153  Remainder = Imm;
2154  Shift = 32;
2155  Imm >>= 32;
2156  }
2157  }
2158 
2159  // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2160  // (if not shifted).
2161  unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2162  if (!Shift)
2163  return TmpReg1;
2164 
2165  // If upper 32 bits were not zero, we've built them and need to shift
2166  // them into place.
2167  unsigned TmpReg2;
2168  if (Imm) {
2169  TmpReg2 = createResultReg(RC);
2170  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2171  TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2172  } else
2173  TmpReg2 = TmpReg1;
2174 
2175  unsigned TmpReg3, Hi, Lo;
2176  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2177  TmpReg3 = createResultReg(RC);
2178  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2179  TmpReg3).addReg(TmpReg2).addImm(Hi);
2180  } else
2181  TmpReg3 = TmpReg2;
2182 
2183  if ((Lo = Remainder & 0xFFFF)) {
2184  unsigned ResultReg = createResultReg(RC);
2185  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2186  ResultReg).addReg(TmpReg3).addImm(Lo);
2187  return ResultReg;
2188  }
2189 
2190  return TmpReg3;
2191 }
2192 
2193 // Materialize an integer constant into a register, and return
2194 // the register number (or zero if we failed to handle it).
2195 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2196  bool UseSExt) {
2197  // If we're using CR bit registers for i1 values, handle that as a special
2198  // case first.
2199  if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2200  unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2201  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2202  TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2203  return ImmReg;
2204  }
2205 
2206  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2207  VT != MVT::i1)
2208  return 0;
2209 
2210  const TargetRegisterClass *RC =
2211  ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2212  int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2213 
2214  // If the constant is in range, use a load-immediate.
2215  // Since LI will sign extend the constant we need to make sure that for
2216  // our zeroext constants that the sign extended constant fits into 16-bits -
2217  // a range of 0..0x7fff.
2218  if (isInt<16>(Imm)) {
2219  unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2220  unsigned ImmReg = createResultReg(RC);
2221  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2222  .addImm(Imm);
2223  return ImmReg;
2224  }
2225 
2226  // Construct the constant piecewise.
2227  if (VT == MVT::i64)
2228  return PPCMaterialize64BitInt(Imm, RC);
2229  else if (VT == MVT::i32)
2230  return PPCMaterialize32BitInt(Imm, RC);
2231 
2232  return 0;
2233 }
2234 
2235 // Materialize a constant into a register, and return the register
2236 // number (or zero if we failed to handle it).
2237 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2238  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2239 
2240  // Only handle simple types.
2241  if (!CEVT.isSimple()) return 0;
2242  MVT VT = CEVT.getSimpleVT();
2243 
2244  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2245  return PPCMaterializeFP(CFP, VT);
2246  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2247  return PPCMaterializeGV(GV, VT);
2248  else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2249  // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2250  // assumes that constant PHI operands will be zero extended, and failure to
2251  // match that assumption will cause problems if we sign extend here but
2252  // some user of a PHI is in a block for which we fall back to full SDAG
2253  // instruction selection.
2254  return PPCMaterializeInt(CI, VT, false);
2255 
2256  return 0;
2257 }
2258 
2259 // Materialize the address created by an alloca into a register, and
2260 // return the register number (or zero if we failed to handle it).
2261 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2262  // Don't handle dynamic allocas.
2263  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2264 
2265  MVT VT;
2266  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2267 
2269  FuncInfo.StaticAllocaMap.find(AI);
2270 
2271  if (SI != FuncInfo.StaticAllocaMap.end()) {
2272  unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2273  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2274  ResultReg).addFrameIndex(SI->second).addImm(0);
2275  return ResultReg;
2276  }
2277 
2278  return 0;
2279 }
2280 
2281 // Fold loads into extends when possible.
2282 // FIXME: We can have multiple redundant extend/trunc instructions
2283 // following a load. The folding only picks up one. Extend this
2284 // to check subsequent instructions for the same pattern and remove
2285 // them. Thus ResultReg should be the def reg for the last redundant
2286 // instruction in a chain, and all intervening instructions can be
2287 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2288 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2289 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2290  const LoadInst *LI) {
2291  // Verify we have a legal type before going any further.
2292  MVT VT;
2293  if (!isLoadTypeLegal(LI->getType(), VT))
2294  return false;
2295 
2296  // Combine load followed by zero- or sign-extend.
2297  bool IsZExt = false;
2298  switch(MI->getOpcode()) {
2299  default:
2300  return false;
2301 
2302  case PPC::RLDICL:
2303  case PPC::RLDICL_32_64: {
2304  IsZExt = true;
2305  unsigned MB = MI->getOperand(3).getImm();
2306  if ((VT == MVT::i8 && MB <= 56) ||
2307  (VT == MVT::i16 && MB <= 48) ||
2308  (VT == MVT::i32 && MB <= 32))
2309  break;
2310  return false;
2311  }
2312 
2313  case PPC::RLWINM:
2314  case PPC::RLWINM8: {
2315  IsZExt = true;
2316  unsigned MB = MI->getOperand(3).getImm();
2317  if ((VT == MVT::i8 && MB <= 24) ||
2318  (VT == MVT::i16 && MB <= 16))
2319  break;
2320  return false;
2321  }
2322 
2323  case PPC::EXTSB:
2324  case PPC::EXTSB8:
2325  case PPC::EXTSB8_32_64:
2326  /* There is no sign-extending load-byte instruction. */
2327  return false;
2328 
2329  case PPC::EXTSH:
2330  case PPC::EXTSH8:
2331  case PPC::EXTSH8_32_64: {
2332  if (VT != MVT::i16 && VT != MVT::i8)
2333  return false;
2334  break;
2335  }
2336 
2337  case PPC::EXTSW:
2338  case PPC::EXTSW_32:
2339  case PPC::EXTSW_32_64: {
2340  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2341  return false;
2342  break;
2343  }
2344  }
2345 
2346  // See if we can handle this address.
2347  Address Addr;
2348  if (!PPCComputeAddress(LI->getOperand(0), Addr))
2349  return false;
2350 
2351  unsigned ResultReg = MI->getOperand(0).getReg();
2352 
2353  if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2354  PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
2355  return false;
2356 
2357  MI->eraseFromParent();
2358  return true;
2359 }
2360 
2361 // Attempt to lower call arguments in a faster way than done by
2362 // the selection DAG code.
2363 bool PPCFastISel::fastLowerArguments() {
2364  // Defer to normal argument lowering for now. It's reasonably
2365  // efficient. Consider doing something like ARM to handle the
2366  // case where all args fit in registers, no varargs, no float
2367  // or vector args.
2368  return false;
2369 }
2370 
2371 // Handle materializing integer constants into a register. This is not
2372 // automatically generated for PowerPC, so must be explicitly created here.
2373 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2374 
2375  if (Opc != ISD::Constant)
2376  return 0;
2377 
2378  // If we're using CR bit registers for i1 values, handle that as a special
2379  // case first.
2380  if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2381  unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2382  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2383  TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2384  return ImmReg;
2385  }
2386 
2387  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2388  VT != MVT::i1)
2389  return 0;
2390 
2391  const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2392  &PPC::GPRCRegClass);
2393  if (VT == MVT::i64)
2394  return PPCMaterialize64BitInt(Imm, RC);
2395  else
2396  return PPCMaterialize32BitInt(Imm, RC);
2397 }
2398 
2399 // Override for ADDI and ADDI8 to set the correct register class
2400 // on RHS operand 0. The automatic infrastructure naively assumes
2401 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2402 // for these cases. At the moment, none of the other automatically
2403 // generated RI instructions require special treatment. However, once
2404 // SelectSelect is implemented, "isel" requires similar handling.
2405 //
2406 // Also be conservative about the output register class. Avoid
2407 // assigning R0 or X0 to the output register for GPRC and G8RC
2408 // register classes, as any such result could be used in ADDI, etc.,
2409 // where those regs have another meaning.
2410 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2411  const TargetRegisterClass *RC,
2412  unsigned Op0, bool Op0IsKill,
2413  uint64_t Imm) {
2414  if (MachineInstOpcode == PPC::ADDI)
2415  MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2416  else if (MachineInstOpcode == PPC::ADDI8)
2417  MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2418 
2419  const TargetRegisterClass *UseRC =
2420  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2421  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2422 
2423  return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2424  Op0, Op0IsKill, Imm);
2425 }
2426 
2427 // Override for instructions with one register operand to avoid use of
2428 // R0/X0. The automatic infrastructure isn't aware of the context so
2429 // we must be conservative.
2430 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2431  const TargetRegisterClass* RC,
2432  unsigned Op0, bool Op0IsKill) {
2433  const TargetRegisterClass *UseRC =
2434  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2435  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2436 
2437  return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2438 }
2439 
2440 // Override for instructions with two register operands to avoid use
2441 // of R0/X0. The automatic infrastructure isn't aware of the context
2442 // so we must be conservative.
2443 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2444  const TargetRegisterClass* RC,
2445  unsigned Op0, bool Op0IsKill,
2446  unsigned Op1, bool Op1IsKill) {
2447  const TargetRegisterClass *UseRC =
2448  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2449  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2450 
2451  return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2452  Op1, Op1IsKill);
2453 }
2454 
2455 namespace llvm {
2456  // Create the fast instruction selector for PowerPC64 ELF.
2458  const TargetLibraryInfo *LibInfo) {
2459  // Only available on 64-bit ELF for now.
2460  const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2461  if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2462  return new PPCFastISel(FuncInfo, LibInfo);
2463  return nullptr;
2464  }
2465 }
uint64_t CallInst * C
Return a value (possibly void), from a function.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
Definition: SmallVector.h:218
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:675
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1557
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
bool isVector() const
Return true if this is a vector value type.
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
unsigned less or equal
Definition: InstrTypes.h:711
unsigned less than
Definition: InstrTypes.h:710
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:691
unsigned getValNo() const
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:701
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
F(f)
An instruction for reading from memory.
Definition: Instructions.h:168
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:177
Value * getCondition() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
void reserve(size_type N)
Definition: SmallVector.h:376
op_iterator op_begin()
Definition: User.h:230
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
bool needsCustom() const
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:696
unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:2093
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:521
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:695
A description of a memory reference used in the backend.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill)
Emit a MachineInstr with one register operand and a result register in the given register class...
Definition: FastISel.cpp:2020
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:692
SimpleValueType SimpleTy
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
LocInfo getLocInfo() const
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:885
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1569
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:180
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
amdgpu Simplify well known AMD library false Value * Callee
Value * getOperand(unsigned i) const
Definition: User.h:170
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:149
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Conditional or Unconditional Branch instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:87
Indirect Branch Instruction.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
op_iterator op_end()
Definition: User.h:232
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:183
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:685
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:694
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Class to represent integer types.
Definition: DerivedTypes.h:40
const MachineInstrBuilder & addFrameIndex(int Idx) const
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:702
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
Extended Value Type.
Definition: ValueTypes.h:34
size_t size() const
Definition: SmallVector.h:53
static bool isAtomic(Instruction *I)
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:700
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:712
The memory access writes data.
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:689
unsigned getNumOperands() const
Definition: User.h:192
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:182
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:699
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:714
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2041
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
Definition: Constants.cpp:635
int64_t getImm() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
signed less or equal
Definition: InstrTypes.h:715
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:70
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
This file defines the FastISel class.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
amdgpu Simplify well known AMD library false Value Value * Arg
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:543
unsigned greater or equal
Definition: InstrTypes.h:709
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
#define I(x, y, z)
Definition: MD5.cpp:58
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:193
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:693
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:697
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:688
LLVM Value Representation.
Definition: Value.h:73
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:698
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:247
IRTranslator LLVM IR MI
unsigned greater than
Definition: InstrTypes.h:708
bool isSVR4ABI() const
Definition: PPCSubtarget.h:310
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:147
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
static Optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:690
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:687
signed greater or equal
Definition: InstrTypes.h:713
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:67
an instruction to allocate memory on the stack
Definition: Instructions.h:60
gep_type_iterator gep_type_begin(const User *GEP)