LLVM  9.0.0svn
PPCFastISel.cpp
Go to the documentation of this file.
1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the PowerPC-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // PPCGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14 
16 #include "PPC.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
25 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/Debug.h"
40 
41 //===----------------------------------------------------------------------===//
42 //
43 // TBD:
44 // fastLowerArguments: Handle simple cases.
45 // PPCMaterializeGV: Handle TLS.
46 // SelectCall: Handle function pointers.
47 // SelectCall: Handle multi-register return values.
48 // SelectCall: Optimize away nops for local calls.
49 // processCallArgs: Handle bit-converted arguments.
50 // finishCall: Handle multi-register return values.
51 // PPCComputeAddress: Handle parameter references as FrameIndex's.
52 // PPCEmitCmp: Handle immediate as operand 1.
53 // SelectCall: Handle small byval arguments.
54 // SelectIntrinsicCall: Implement.
55 // SelectSelect: Implement.
56 // Consider factoring isTypeLegal into the base class.
57 // Implement switches and jump tables.
58 //
59 //===----------------------------------------------------------------------===//
60 using namespace llvm;
61 
62 #define DEBUG_TYPE "ppcfastisel"
63 
64 namespace {
65 
66 typedef struct Address {
67  enum {
68  RegBase,
69  FrameIndexBase
70  } BaseType;
71 
72  union {
73  unsigned Reg;
74  int FI;
75  } Base;
76 
77  long Offset;
78 
79  // Innocuous defaults for our address.
80  Address()
81  : BaseType(RegBase), Offset(0) {
82  Base.Reg = 0;
83  }
84 } Address;
85 
86 class PPCFastISel final : public FastISel {
87 
88  const TargetMachine &TM;
89  const PPCSubtarget *PPCSubTarget;
90  PPCFunctionInfo *PPCFuncInfo;
91  const TargetInstrInfo &TII;
92  const TargetLowering &TLI;
94 
95  public:
96  explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97  const TargetLibraryInfo *LibInfo)
98  : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99  PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100  PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101  TII(*PPCSubTarget->getInstrInfo()),
102  TLI(*PPCSubTarget->getTargetLowering()),
103  Context(&FuncInfo.Fn->getContext()) {}
104 
105  // Backend specific FastISel code.
106  private:
107  bool fastSelectInstruction(const Instruction *I) override;
108  unsigned fastMaterializeConstant(const Constant *C) override;
109  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111  const LoadInst *LI) override;
112  bool fastLowerArguments() override;
113  unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115  const TargetRegisterClass *RC,
116  unsigned Op0, bool Op0IsKill,
117  uint64_t Imm);
118  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119  const TargetRegisterClass *RC,
120  unsigned Op0, bool Op0IsKill);
121  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122  const TargetRegisterClass *RC,
123  unsigned Op0, bool Op0IsKill,
124  unsigned Op1, bool Op1IsKill);
125 
126  bool fastLowerCall(CallLoweringInfo &CLI) override;
127 
128  // Instruction selection routines.
129  private:
130  bool SelectLoad(const Instruction *I);
131  bool SelectStore(const Instruction *I);
132  bool SelectBranch(const Instruction *I);
133  bool SelectIndirectBr(const Instruction *I);
134  bool SelectFPExt(const Instruction *I);
135  bool SelectFPTrunc(const Instruction *I);
136  bool SelectIToFP(const Instruction *I, bool IsSigned);
137  bool SelectFPToI(const Instruction *I, bool IsSigned);
138  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139  bool SelectRet(const Instruction *I);
140  bool SelectTrunc(const Instruction *I);
141  bool SelectIntExt(const Instruction *I);
142 
143  // Utility routines.
144  private:
145  bool isTypeLegal(Type *Ty, MVT &VT);
146  bool isLoadTypeLegal(Type *Ty, MVT &VT);
147  bool isValueAvailable(const Value *V) const;
148  bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
149  return RC->getID() == PPC::VSFRCRegClassID;
150  }
151  bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
152  return RC->getID() == PPC::VSSRCRegClassID;
153  }
154  bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
155  bool isZExt, unsigned DestReg,
156  const PPC::Predicate Pred);
157  bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
158  const TargetRegisterClass *RC, bool IsZExt = true,
159  unsigned FP64LoadOpc = PPC::LFD);
160  bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
161  bool PPCComputeAddress(const Value *Obj, Address &Addr);
162  void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
163  unsigned &IndexReg);
164  bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
165  unsigned DestReg, bool IsZExt);
166  unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
167  unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
168  unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
169  bool UseSExt = true);
170  unsigned PPCMaterialize32BitInt(int64_t Imm,
171  const TargetRegisterClass *RC);
172  unsigned PPCMaterialize64BitInt(int64_t Imm,
173  const TargetRegisterClass *RC);
174  unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
175  unsigned SrcReg, bool IsSigned);
176  unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
177 
178  // Call handling routines.
179  private:
180  bool processCallArgs(SmallVectorImpl<Value*> &Args,
181  SmallVectorImpl<unsigned> &ArgRegs,
182  SmallVectorImpl<MVT> &ArgVTs,
184  SmallVectorImpl<unsigned> &RegArgs,
185  CallingConv::ID CC,
186  unsigned &NumBytes,
187  bool IsVarArg);
188  bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
189  LLVM_ATTRIBUTE_UNUSED CCAssignFn *usePPC32CCs(unsigned Flag);
190 
191  private:
192  #include "PPCGenFastISel.inc"
193 
194 };
195 
196 } // end anonymous namespace
197 
198 #include "PPCGenCallingConv.inc"
199 
200 // Function whose sole purpose is to kill compiler warnings
201 // stemming from unused functions included from PPCGenCallingConv.inc.
202 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
203  if (Flag == 1)
204  return CC_PPC32_SVR4;
205  else if (Flag == 2)
206  return CC_PPC32_SVR4_ByVal;
207  else if (Flag == 3)
208  return CC_PPC32_SVR4_VarArg;
209  else if (Flag == 4)
210  return RetCC_PPC_Cold;
211  else
212  return RetCC_PPC;
213 }
214 
216  switch (Pred) {
217  // These are not representable with any single compare.
218  case CmpInst::FCMP_FALSE:
219  case CmpInst::FCMP_TRUE:
220  // Major concern about the following 6 cases is NaN result. The comparison
221  // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
222  // only one of which will be set. The result is generated by fcmpu
223  // instruction. However, bc instruction only inspects one of the first 3
224  // bits, so when un is set, bc instruction may jump to an undesired
225  // place.
226  //
227  // More specifically, if we expect an unordered comparison and un is set, we
228  // expect to always go to true branch; in such case UEQ, UGT and ULT still
229  // give false, which are undesired; but UNE, UGE, ULE happen to give true,
230  // since they are tested by inspecting !eq, !lt, !gt, respectively.
231  //
232  // Similarly, for ordered comparison, when un is set, we always expect the
233  // result to be false. In such case OGT, OLT and OEQ is good, since they are
234  // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
235  // and ONE are tested through !lt, !gt and !eq, and these are true.
236  case CmpInst::FCMP_UEQ:
237  case CmpInst::FCMP_UGT:
238  case CmpInst::FCMP_ULT:
239  case CmpInst::FCMP_OGE:
240  case CmpInst::FCMP_OLE:
241  case CmpInst::FCMP_ONE:
242  default:
243  return Optional<PPC::Predicate>();
244 
245  case CmpInst::FCMP_OEQ:
246  case CmpInst::ICMP_EQ:
247  return PPC::PRED_EQ;
248 
249  case CmpInst::FCMP_OGT:
250  case CmpInst::ICMP_UGT:
251  case CmpInst::ICMP_SGT:
252  return PPC::PRED_GT;
253 
254  case CmpInst::FCMP_UGE:
255  case CmpInst::ICMP_UGE:
256  case CmpInst::ICMP_SGE:
257  return PPC::PRED_GE;
258 
259  case CmpInst::FCMP_OLT:
260  case CmpInst::ICMP_ULT:
261  case CmpInst::ICMP_SLT:
262  return PPC::PRED_LT;
263 
264  case CmpInst::FCMP_ULE:
265  case CmpInst::ICMP_ULE:
266  case CmpInst::ICMP_SLE:
267  return PPC::PRED_LE;
268 
269  case CmpInst::FCMP_UNE:
270  case CmpInst::ICMP_NE:
271  return PPC::PRED_NE;
272 
273  case CmpInst::FCMP_ORD:
274  return PPC::PRED_NU;
275 
276  case CmpInst::FCMP_UNO:
277  return PPC::PRED_UN;
278  }
279 }
280 
281 // Determine whether the type Ty is simple enough to be handled by
282 // fast-isel, and return its equivalent machine type in VT.
283 // FIXME: Copied directly from ARM -- factor into base class?
284 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
285  EVT Evt = TLI.getValueType(DL, Ty, true);
286 
287  // Only handle simple types.
288  if (Evt == MVT::Other || !Evt.isSimple()) return false;
289  VT = Evt.getSimpleVT();
290 
291  // Handle all legal types, i.e. a register that will directly hold this
292  // value.
293  return TLI.isTypeLegal(VT);
294 }
295 
296 // Determine whether the type Ty is simple enough to be handled by
297 // fast-isel as a load target, and return its equivalent machine type in VT.
298 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
299  if (isTypeLegal(Ty, VT)) return true;
300 
301  // If this is a type than can be sign or zero-extended to a basic operation
302  // go ahead and accept it now.
303  if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
304  return true;
305  }
306 
307  return false;
308 }
309 
310 bool PPCFastISel::isValueAvailable(const Value *V) const {
311  if (!isa<Instruction>(V))
312  return true;
313 
314  const auto *I = cast<Instruction>(V);
315  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
316 }
317 
318 // Given a value Obj, create an Address object Addr that represents its
319 // address. Return false if we can't handle it.
320 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
321  const User *U = nullptr;
322  unsigned Opcode = Instruction::UserOp1;
323  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
324  // Don't walk into other basic blocks unless the object is an alloca from
325  // another block, otherwise it may not have a virtual register assigned.
326  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
327  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
328  Opcode = I->getOpcode();
329  U = I;
330  }
331  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
332  Opcode = C->getOpcode();
333  U = C;
334  }
335 
336  switch (Opcode) {
337  default:
338  break;
339  case Instruction::BitCast:
340  // Look through bitcasts.
341  return PPCComputeAddress(U->getOperand(0), Addr);
342  case Instruction::IntToPtr:
343  // Look past no-op inttoptrs.
344  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
345  TLI.getPointerTy(DL))
346  return PPCComputeAddress(U->getOperand(0), Addr);
347  break;
348  case Instruction::PtrToInt:
349  // Look past no-op ptrtoints.
350  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
351  return PPCComputeAddress(U->getOperand(0), Addr);
352  break;
353  case Instruction::GetElementPtr: {
354  Address SavedAddr = Addr;
355  long TmpOffset = Addr.Offset;
356 
357  // Iterate through the GEP folding the constants into offsets where
358  // we can.
360  for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
361  II != IE; ++II, ++GTI) {
362  const Value *Op = *II;
363  if (StructType *STy = GTI.getStructTypeOrNull()) {
364  const StructLayout *SL = DL.getStructLayout(STy);
365  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
366  TmpOffset += SL->getElementOffset(Idx);
367  } else {
368  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
369  for (;;) {
370  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
371  // Constant-offset addressing.
372  TmpOffset += CI->getSExtValue() * S;
373  break;
374  }
375  if (canFoldAddIntoGEP(U, Op)) {
376  // A compatible add with a constant operand. Fold the constant.
377  ConstantInt *CI =
378  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
379  TmpOffset += CI->getSExtValue() * S;
380  // Iterate on the other operand.
381  Op = cast<AddOperator>(Op)->getOperand(0);
382  continue;
383  }
384  // Unsupported
385  goto unsupported_gep;
386  }
387  }
388  }
389 
390  // Try to grab the base operand now.
391  Addr.Offset = TmpOffset;
392  if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
393 
394  // We failed, restore everything and try the other options.
395  Addr = SavedAddr;
396 
397  unsupported_gep:
398  break;
399  }
400  case Instruction::Alloca: {
401  const AllocaInst *AI = cast<AllocaInst>(Obj);
403  FuncInfo.StaticAllocaMap.find(AI);
404  if (SI != FuncInfo.StaticAllocaMap.end()) {
405  Addr.BaseType = Address::FrameIndexBase;
406  Addr.Base.FI = SI->second;
407  return true;
408  }
409  break;
410  }
411  }
412 
413  // FIXME: References to parameters fall through to the behavior
414  // below. They should be able to reference a frame index since
415  // they are stored to the stack, so we can get "ld rx, offset(r1)"
416  // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
417  // just contain the parameter. Try to handle this with a FI.
418 
419  // Try to get this in a register if nothing else has worked.
420  if (Addr.Base.Reg == 0)
421  Addr.Base.Reg = getRegForValue(Obj);
422 
423  // Prevent assignment of base register to X0, which is inappropriate
424  // for loads and stores alike.
425  if (Addr.Base.Reg != 0)
426  MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
427 
428  return Addr.Base.Reg != 0;
429 }
430 
431 // Fix up some addresses that can't be used directly. For example, if
432 // an offset won't fit in an instruction field, we may need to move it
433 // into an index register.
434 void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
435  unsigned &IndexReg) {
436 
437  // Check whether the offset fits in the instruction field.
438  if (!isInt<16>(Addr.Offset))
439  UseOffset = false;
440 
441  // If this is a stack pointer and the offset needs to be simplified then
442  // put the alloca address into a register, set the base type back to
443  // register and continue. This should almost never happen.
444  if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
445  unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
446  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
447  ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
448  Addr.Base.Reg = ResultReg;
449  Addr.BaseType = Address::RegBase;
450  }
451 
452  if (!UseOffset) {
453  IntegerType *OffsetTy = Type::getInt64Ty(*Context);
454  const ConstantInt *Offset =
455  ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
456  IndexReg = PPCMaterializeInt(Offset, MVT::i64);
457  assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
458  }
459 }
460 
461 // Emit a load instruction if possible, returning true if we succeeded,
462 // otherwise false. See commentary below for how the register class of
463 // the load is determined.
464 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
465  const TargetRegisterClass *RC,
466  bool IsZExt, unsigned FP64LoadOpc) {
467  unsigned Opc;
468  bool UseOffset = true;
469  bool HasSPE = PPCSubTarget->hasSPE();
470 
471  // If ResultReg is given, it determines the register class of the load.
472  // Otherwise, RC is the register class to use. If the result of the
473  // load isn't anticipated in this block, both may be zero, in which
474  // case we must make a conservative guess. In particular, don't assign
475  // R0 or X0 to the result register, as the result may be used in a load,
476  // store, add-immediate, or isel that won't permit this. (Though
477  // perhaps the spill and reload of live-exit values would handle this?)
478  const TargetRegisterClass *UseRC =
479  (ResultReg ? MRI.getRegClass(ResultReg) :
480  (RC ? RC :
481  (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
482  (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
483  (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
484  &PPC::GPRC_and_GPRC_NOR0RegClass)))));
485 
486  bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
487 
488  switch (VT.SimpleTy) {
489  default: // e.g., vector types not handled
490  return false;
491  case MVT::i8:
492  Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
493  break;
494  case MVT::i16:
495  Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
496  : (Is32BitInt ? PPC::LHA : PPC::LHA8));
497  break;
498  case MVT::i32:
499  Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
500  : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
501  if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
502  UseOffset = false;
503  break;
504  case MVT::i64:
505  Opc = PPC::LD;
506  assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
507  "64-bit load with 32-bit target??");
508  UseOffset = ((Addr.Offset & 3) == 0);
509  break;
510  case MVT::f32:
511  Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
512  break;
513  case MVT::f64:
514  Opc = FP64LoadOpc;
515  break;
516  }
517 
518  // If necessary, materialize the offset into a register and use
519  // the indexed form. Also handle stack pointers with special needs.
520  unsigned IndexReg = 0;
521  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
522 
523  // If this is a potential VSX load with an offset of 0, a VSX indexed load can
524  // be used.
525  bool IsVSSRC = isVSSRCRegClass(UseRC);
526  bool IsVSFRC = isVSFRCRegClass(UseRC);
527  bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
528  bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
529  if ((Is32VSXLoad || Is64VSXLoad) &&
530  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
531  (Addr.Offset == 0)) {
532  UseOffset = false;
533  }
534 
535  if (ResultReg == 0)
536  ResultReg = createResultReg(UseRC);
537 
538  // Note: If we still have a frame index here, we know the offset is
539  // in range, as otherwise PPCSimplifyAddress would have converted it
540  // into a RegBase.
541  if (Addr.BaseType == Address::FrameIndexBase) {
542  // VSX only provides an indexed load.
543  if (Is32VSXLoad || Is64VSXLoad) return false;
544 
545  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
546  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
547  Addr.Offset),
548  MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
549  MFI.getObjectAlignment(Addr.Base.FI));
550 
551  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
552  .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
553 
554  // Base reg with offset in range.
555  } else if (UseOffset) {
556  // VSX only provides an indexed load.
557  if (Is32VSXLoad || Is64VSXLoad) return false;
558 
559  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
560  .addImm(Addr.Offset).addReg(Addr.Base.Reg);
561 
562  // Indexed form.
563  } else {
564  // Get the RR opcode corresponding to the RI one. FIXME: It would be
565  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
566  // is hard to get at.
567  switch (Opc) {
568  default: llvm_unreachable("Unexpected opcode!");
569  case PPC::LBZ: Opc = PPC::LBZX; break;
570  case PPC::LBZ8: Opc = PPC::LBZX8; break;
571  case PPC::LHZ: Opc = PPC::LHZX; break;
572  case PPC::LHZ8: Opc = PPC::LHZX8; break;
573  case PPC::LHA: Opc = PPC::LHAX; break;
574  case PPC::LHA8: Opc = PPC::LHAX8; break;
575  case PPC::LWZ: Opc = PPC::LWZX; break;
576  case PPC::LWZ8: Opc = PPC::LWZX8; break;
577  case PPC::LWA: Opc = PPC::LWAX; break;
578  case PPC::LWA_32: Opc = PPC::LWAX_32; break;
579  case PPC::LD: Opc = PPC::LDX; break;
580  case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
581  case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
582  case PPC::EVLDD: Opc = PPC::EVLDDX; break;
583  case PPC::SPELWZ: Opc = PPC::SPELWZX; break;
584  }
585 
586  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
587  ResultReg);
588 
589  // If we have an index register defined we use it in the store inst,
590  // otherwise we use X0 as base as it makes the vector instructions to
591  // use zero in the computation of the effective address regardless the
592  // content of the register.
593  if (IndexReg)
594  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
595  else
596  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
597  }
598 
599  return true;
600 }
601 
602 // Attempt to fast-select a load instruction.
603 bool PPCFastISel::SelectLoad(const Instruction *I) {
604  // FIXME: No atomic loads are supported.
605  if (cast<LoadInst>(I)->isAtomic())
606  return false;
607 
608  // Verify we have a legal type before going any further.
609  MVT VT;
610  if (!isLoadTypeLegal(I->getType(), VT))
611  return false;
612 
613  // See if we can handle this address.
614  Address Addr;
615  if (!PPCComputeAddress(I->getOperand(0), Addr))
616  return false;
617 
618  // Look at the currently assigned register for this instruction
619  // to determine the required register class. This is necessary
620  // to constrain RA from using R0/X0 when this is not legal.
621  unsigned AssignedReg = FuncInfo.ValueMap[I];
622  const TargetRegisterClass *RC =
623  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
624 
625  unsigned ResultReg = 0;
626  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
627  PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
628  return false;
629  updateValueMap(I, ResultReg);
630  return true;
631 }
632 
633 // Emit a store instruction to store SrcReg at Addr.
634 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
635  assert(SrcReg && "Nothing to store!");
636  unsigned Opc;
637  bool UseOffset = true;
638 
639  const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
640  bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
641 
642  switch (VT.SimpleTy) {
643  default: // e.g., vector types not handled
644  return false;
645  case MVT::i8:
646  Opc = Is32BitInt ? PPC::STB : PPC::STB8;
647  break;
648  case MVT::i16:
649  Opc = Is32BitInt ? PPC::STH : PPC::STH8;
650  break;
651  case MVT::i32:
652  assert(Is32BitInt && "Not GPRC for i32??");
653  Opc = PPC::STW;
654  break;
655  case MVT::i64:
656  Opc = PPC::STD;
657  UseOffset = ((Addr.Offset & 3) == 0);
658  break;
659  case MVT::f32:
660  Opc = PPCSubTarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
661  break;
662  case MVT::f64:
663  Opc = PPCSubTarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
664  break;
665  }
666 
667  // If necessary, materialize the offset into a register and use
668  // the indexed form. Also handle stack pointers with special needs.
669  unsigned IndexReg = 0;
670  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
671 
672  // If this is a potential VSX store with an offset of 0, a VSX indexed store
673  // can be used.
674  bool IsVSSRC = isVSSRCRegClass(RC);
675  bool IsVSFRC = isVSFRCRegClass(RC);
676  bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
677  bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
678  if ((Is32VSXStore || Is64VSXStore) &&
679  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
680  (Addr.Offset == 0)) {
681  UseOffset = false;
682  }
683 
684  // Note: If we still have a frame index here, we know the offset is
685  // in range, as otherwise PPCSimplifyAddress would have converted it
686  // into a RegBase.
687  if (Addr.BaseType == Address::FrameIndexBase) {
688  // VSX only provides an indexed store.
689  if (Is32VSXStore || Is64VSXStore) return false;
690 
691  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
692  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
693  Addr.Offset),
694  MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
695  MFI.getObjectAlignment(Addr.Base.FI));
696 
697  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
698  .addReg(SrcReg)
699  .addImm(Addr.Offset)
700  .addFrameIndex(Addr.Base.FI)
701  .addMemOperand(MMO);
702 
703  // Base reg with offset in range.
704  } else if (UseOffset) {
705  // VSX only provides an indexed store.
706  if (Is32VSXStore || Is64VSXStore)
707  return false;
708 
709  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
710  .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
711 
712  // Indexed form.
713  } else {
714  // Get the RR opcode corresponding to the RI one. FIXME: It would be
715  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
716  // is hard to get at.
717  switch (Opc) {
718  default: llvm_unreachable("Unexpected opcode!");
719  case PPC::STB: Opc = PPC::STBX; break;
720  case PPC::STH : Opc = PPC::STHX; break;
721  case PPC::STW : Opc = PPC::STWX; break;
722  case PPC::STB8: Opc = PPC::STBX8; break;
723  case PPC::STH8: Opc = PPC::STHX8; break;
724  case PPC::STW8: Opc = PPC::STWX8; break;
725  case PPC::STD: Opc = PPC::STDX; break;
726  case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
727  case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
728  case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
729  case PPC::SPESTW: Opc = PPC::SPESTWX; break;
730  }
731 
732  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
733  .addReg(SrcReg);
734 
735  // If we have an index register defined we use it in the store inst,
736  // otherwise we use X0 as base as it makes the vector instructions to
737  // use zero in the computation of the effective address regardless the
738  // content of the register.
739  if (IndexReg)
740  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
741  else
742  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
743  }
744 
745  return true;
746 }
747 
748 // Attempt to fast-select a store instruction.
749 bool PPCFastISel::SelectStore(const Instruction *I) {
750  Value *Op0 = I->getOperand(0);
751  unsigned SrcReg = 0;
752 
753  // FIXME: No atomics loads are supported.
754  if (cast<StoreInst>(I)->isAtomic())
755  return false;
756 
757  // Verify we have a legal type before going any further.
758  MVT VT;
759  if (!isLoadTypeLegal(Op0->getType(), VT))
760  return false;
761 
762  // Get the value to be stored into a register.
763  SrcReg = getRegForValue(Op0);
764  if (SrcReg == 0)
765  return false;
766 
767  // See if we can handle this address.
768  Address Addr;
769  if (!PPCComputeAddress(I->getOperand(1), Addr))
770  return false;
771 
772  if (!PPCEmitStore(VT, SrcReg, Addr))
773  return false;
774 
775  return true;
776 }
777 
778 // Attempt to fast-select a branch instruction.
779 bool PPCFastISel::SelectBranch(const Instruction *I) {
780  const BranchInst *BI = cast<BranchInst>(I);
781  MachineBasicBlock *BrBB = FuncInfo.MBB;
782  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
783  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
784 
785  // For now, just try the simplest case where it's fed by a compare.
786  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
787  if (isValueAvailable(CI)) {
788  Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
789  if (!OptPPCPred)
790  return false;
791 
792  PPC::Predicate PPCPred = OptPPCPred.getValue();
793 
794  // Take advantage of fall-through opportunities.
795  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
796  std::swap(TBB, FBB);
797  PPCPred = PPC::InvertPredicate(PPCPred);
798  }
799 
800  unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
801 
802  if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
803  CondReg, PPCPred))
804  return false;
805 
806  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
807  .addImm(PPCSubTarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
808  .addReg(CondReg).addMBB(TBB);
809  finishCondBranch(BI->getParent(), TBB, FBB);
810  return true;
811  }
812  } else if (const ConstantInt *CI =
813  dyn_cast<ConstantInt>(BI->getCondition())) {
814  uint64_t Imm = CI->getZExtValue();
815  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
816  fastEmitBranch(Target, DbgLoc);
817  return true;
818  }
819 
820  // FIXME: ARM looks for a case where the block containing the compare
821  // has been split from the block containing the branch. If this happens,
822  // there is a vreg available containing the result of the compare. I'm
823  // not sure we can do much, as we've lost the predicate information with
824  // the compare instruction -- we have a 4-bit CR but don't know which bit
825  // to test here.
826  return false;
827 }
828 
829 // Attempt to emit a compare of the two source values. Signed and unsigned
830 // comparisons are supported. Return false if we can't handle it.
831 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
832  bool IsZExt, unsigned DestReg,
833  const PPC::Predicate Pred) {
834  Type *Ty = SrcValue1->getType();
835  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
836  if (!SrcEVT.isSimple())
837  return false;
838  MVT SrcVT = SrcEVT.getSimpleVT();
839 
840  if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
841  return false;
842 
843  // See if operand 2 is an immediate encodeable in the compare.
844  // FIXME: Operands are not in canonical order at -O0, so an immediate
845  // operand in position 1 is a lost opportunity for now. We are
846  // similar to ARM in this regard.
847  long Imm = 0;
848  bool UseImm = false;
849  const bool HasSPE = PPCSubTarget->hasSPE();
850 
851  // Only 16-bit integer constants can be represented in compares for
852  // PowerPC. Others will be materialized into a register.
853  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
854  if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
855  SrcVT == MVT::i8 || SrcVT == MVT::i1) {
856  const APInt &CIVal = ConstInt->getValue();
857  Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
858  if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
859  UseImm = true;
860  }
861  }
862 
863  unsigned SrcReg1 = getRegForValue(SrcValue1);
864  if (SrcReg1 == 0)
865  return false;
866 
867  unsigned SrcReg2 = 0;
868  if (!UseImm) {
869  SrcReg2 = getRegForValue(SrcValue2);
870  if (SrcReg2 == 0)
871  return false;
872  }
873 
874  unsigned CmpOpc;
875  bool NeedsExt = false;
876  auto RC = MRI.getRegClass(SrcReg1);
877  switch (SrcVT.SimpleTy) {
878  default: return false;
879  case MVT::f32:
880  if (HasSPE) {
881  switch (Pred) {
882  default: return false;
883  case PPC::PRED_EQ:
884  CmpOpc = PPC::EFSCMPEQ;
885  break;
886  case PPC::PRED_LT:
887  CmpOpc = PPC::EFSCMPLT;
888  break;
889  case PPC::PRED_GT:
890  CmpOpc = PPC::EFSCMPGT;
891  break;
892  }
893  } else {
894  CmpOpc = PPC::FCMPUS;
895  if (isVSSRCRegClass(RC)) {
896  unsigned TmpReg = createResultReg(&PPC::F4RCRegClass);
897  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
898  TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg1);
899  SrcReg1 = TmpReg;
900  }
901  }
902  break;
903  case MVT::f64:
904  if (HasSPE) {
905  switch (Pred) {
906  default: return false;
907  case PPC::PRED_EQ:
908  CmpOpc = PPC::EFDCMPEQ;
909  break;
910  case PPC::PRED_LT:
911  CmpOpc = PPC::EFDCMPLT;
912  break;
913  case PPC::PRED_GT:
914  CmpOpc = PPC::EFDCMPGT;
915  break;
916  }
917  } else if (isVSFRCRegClass(RC)) {
918  CmpOpc = PPC::XSCMPUDP;
919  } else {
920  CmpOpc = PPC::FCMPUD;
921  }
922  break;
923  case MVT::i1:
924  case MVT::i8:
925  case MVT::i16:
926  NeedsExt = true;
928  case MVT::i32:
929  if (!UseImm)
930  CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
931  else
932  CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
933  break;
934  case MVT::i64:
935  if (!UseImm)
936  CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
937  else
938  CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
939  break;
940  }
941 
942  if (NeedsExt) {
943  unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
944  if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
945  return false;
946  SrcReg1 = ExtReg;
947 
948  if (!UseImm) {
949  unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
950  if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
951  return false;
952  SrcReg2 = ExtReg;
953  }
954  }
955 
956  if (!UseImm)
957  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
958  .addReg(SrcReg1).addReg(SrcReg2);
959  else
960  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
961  .addReg(SrcReg1).addImm(Imm);
962 
963  return true;
964 }
965 
966 // Attempt to fast-select a floating-point extend instruction.
967 bool PPCFastISel::SelectFPExt(const Instruction *I) {
968  Value *Src = I->getOperand(0);
969  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
970  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
971 
972  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
973  return false;
974 
975  unsigned SrcReg = getRegForValue(Src);
976  if (!SrcReg)
977  return false;
978 
979  // No code is generated for a FP extend.
980  updateValueMap(I, SrcReg);
981  return true;
982 }
983 
984 // Attempt to fast-select a floating-point truncate instruction.
985 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
986  Value *Src = I->getOperand(0);
987  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
988  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
989 
990  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
991  return false;
992 
993  unsigned SrcReg = getRegForValue(Src);
994  if (!SrcReg)
995  return false;
996 
997  // Round the result to single precision.
998  unsigned DestReg;
999 
1000  if (PPCSubTarget->hasSPE()) {
1001  DestReg = createResultReg(&PPC::SPE4RCRegClass);
1002  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1003  TII.get(PPC::EFSCFD), DestReg)
1004  .addReg(SrcReg);
1005  } else {
1006  DestReg = createResultReg(&PPC::F4RCRegClass);
1007  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1008  TII.get(PPC::FRSP), DestReg)
1009  .addReg(SrcReg);
1010  }
1011 
1012  updateValueMap(I, DestReg);
1013  return true;
1014 }
1015 
1016 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1017 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1018 // those should be used instead of moving via a stack slot when the
1019 // subtarget permits.
1020 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
1021 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
1022 // case to 8 bytes which produces tighter code but wastes stack space.
1023 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1024  bool IsSigned) {
1025 
1026  // If necessary, extend 32-bit int to 64-bit.
1027  if (SrcVT == MVT::i32) {
1028  unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1029  if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1030  return 0;
1031  SrcReg = TmpReg;
1032  }
1033 
1034  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1035  Address Addr;
1036  Addr.BaseType = Address::FrameIndexBase;
1037  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1038 
1039  // Store the value from the GPR.
1040  if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1041  return 0;
1042 
1043  // Load the integer value into an FPR. The kind of load used depends
1044  // on a number of conditions.
1045  unsigned LoadOpc = PPC::LFD;
1046 
1047  if (SrcVT == MVT::i32) {
1048  if (!IsSigned) {
1049  LoadOpc = PPC::LFIWZX;
1050  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1051  } else if (PPCSubTarget->hasLFIWAX()) {
1052  LoadOpc = PPC::LFIWAX;
1053  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1054  }
1055  }
1056 
1057  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1058  unsigned ResultReg = 0;
1059  if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1060  return 0;
1061 
1062  return ResultReg;
1063 }
1064 
1065 // Attempt to fast-select an integer-to-floating-point conversion.
1066 // FIXME: Once fast-isel has better support for VSX, conversions using
1067 // direct moves should be implemented.
1068 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1069  MVT DstVT;
1070  Type *DstTy = I->getType();
1071  if (!isTypeLegal(DstTy, DstVT))
1072  return false;
1073 
1074  if (DstVT != MVT::f32 && DstVT != MVT::f64)
1075  return false;
1076 
1077  Value *Src = I->getOperand(0);
1078  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1079  if (!SrcEVT.isSimple())
1080  return false;
1081 
1082  MVT SrcVT = SrcEVT.getSimpleVT();
1083 
1084  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1085  SrcVT != MVT::i32 && SrcVT != MVT::i64)
1086  return false;
1087 
1088  unsigned SrcReg = getRegForValue(Src);
1089  if (SrcReg == 0)
1090  return false;
1091 
1092  // Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs
1093  if (PPCSubTarget->hasSPE()) {
1094  unsigned Opc;
1095  if (DstVT == MVT::f32)
1096  Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1097  else
1098  Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1099 
1100  unsigned DestReg = createResultReg(&PPC::SPERCRegClass);
1101  // Generate the convert.
1102  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1103  .addReg(SrcReg);
1104  updateValueMap(I, DestReg);
1105  return true;
1106  }
1107 
1108  // We can only lower an unsigned convert if we have the newer
1109  // floating-point conversion operations.
1110  if (!IsSigned && !PPCSubTarget->hasFPCVT())
1111  return false;
1112 
1113  // FIXME: For now we require the newer floating-point conversion operations
1114  // (which are present only on P7 and A2 server models) when converting
1115  // to single-precision float. Otherwise we have to generate a lot of
1116  // fiddly code to avoid double rounding. If necessary, the fiddly code
1117  // can be found in PPCTargetLowering::LowerINT_TO_FP().
1118  if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1119  return false;
1120 
1121  // Extend the input if necessary.
1122  if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1123  unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1124  if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1125  return false;
1126  SrcVT = MVT::i64;
1127  SrcReg = TmpReg;
1128  }
1129 
1130  // Move the integer value to an FPR.
1131  unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1132  if (FPReg == 0)
1133  return false;
1134 
1135  // Determine the opcode for the conversion.
1136  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1137  unsigned DestReg = createResultReg(RC);
1138  unsigned Opc;
1139 
1140  if (DstVT == MVT::f32)
1141  Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1142  else
1143  Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1144 
1145  // Generate the convert.
1146  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1147  .addReg(FPReg);
1148 
1149  updateValueMap(I, DestReg);
1150  return true;
1151 }
1152 
1153 // Move the floating-point value in SrcReg into an integer destination
1154 // register, and return the register (or zero if we can't handle it).
1155 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1156 // those should be used instead of moving via a stack slot when the
1157 // subtarget permits.
1158 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1159  unsigned SrcReg, bool IsSigned) {
1160  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1161  // Note that if have STFIWX available, we could use a 4-byte stack
1162  // slot for i32, but this being fast-isel we'll just go with the
1163  // easiest code gen possible.
1164  Address Addr;
1165  Addr.BaseType = Address::FrameIndexBase;
1166  Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1167 
1168  // Store the value from the FPR.
1169  if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1170  return 0;
1171 
1172  // Reload it into a GPR. If we want an i32 on big endian, modify the
1173  // address to have a 4-byte offset so we load from the right place.
1174  if (VT == MVT::i32)
1175  Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1176 
1177  // Look at the currently assigned register for this instruction
1178  // to determine the required register class.
1179  unsigned AssignedReg = FuncInfo.ValueMap[I];
1180  const TargetRegisterClass *RC =
1181  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1182 
1183  unsigned ResultReg = 0;
1184  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1185  return 0;
1186 
1187  return ResultReg;
1188 }
1189 
1190 // Attempt to fast-select a floating-point-to-integer conversion.
1191 // FIXME: Once fast-isel has better support for VSX, conversions using
1192 // direct moves should be implemented.
1193 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1194  MVT DstVT, SrcVT;
1195  Type *DstTy = I->getType();
1196  if (!isTypeLegal(DstTy, DstVT))
1197  return false;
1198 
1199  if (DstVT != MVT::i32 && DstVT != MVT::i64)
1200  return false;
1201 
1202  // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1203  if (DstVT == MVT::i64 && !IsSigned &&
1204  !PPCSubTarget->hasFPCVT() && !PPCSubTarget->hasSPE())
1205  return false;
1206 
1207  Value *Src = I->getOperand(0);
1208  Type *SrcTy = Src->getType();
1209  if (!isTypeLegal(SrcTy, SrcVT))
1210  return false;
1211 
1212  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1213  return false;
1214 
1215  unsigned SrcReg = getRegForValue(Src);
1216  if (SrcReg == 0)
1217  return false;
1218 
1219  // Convert f32 to f64 if necessary. This is just a meaningless copy
1220  // to get the register class right.
1221  const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1222  if (InRC == &PPC::F4RCRegClass) {
1223  unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1224  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1225  TII.get(TargetOpcode::COPY), TmpReg)
1226  .addReg(SrcReg);
1227  SrcReg = TmpReg;
1228  }
1229 
1230  // Determine the opcode for the conversion, which takes place
1231  // entirely within FPRs.
1232  unsigned DestReg;
1233  unsigned Opc;
1234 
1235  if (PPCSubTarget->hasSPE()) {
1236  DestReg = createResultReg(&PPC::GPRCRegClass);
1237  if (IsSigned)
1238  Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1239  else
1240  Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1241  } else {
1242  DestReg = createResultReg(&PPC::F8RCRegClass);
1243  if (DstVT == MVT::i32)
1244  if (IsSigned)
1245  Opc = PPC::FCTIWZ;
1246  else
1247  Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1248  else
1249  Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1250  }
1251 
1252  // Generate the convert.
1253  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1254  .addReg(SrcReg);
1255 
1256  // Now move the integer value from a float register to an integer register.
1257  unsigned IntReg = PPCSubTarget->hasSPE() ? DestReg :
1258  PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1259 
1260  if (IntReg == 0)
1261  return false;
1262 
1263  updateValueMap(I, IntReg);
1264  return true;
1265 }
1266 
1267 // Attempt to fast-select a binary integer operation that isn't already
1268 // handled automatically.
1269 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1270  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1271 
1272  // We can get here in the case when we have a binary operation on a non-legal
1273  // type and the target independent selector doesn't know how to handle it.
1274  if (DestVT != MVT::i16 && DestVT != MVT::i8)
1275  return false;
1276 
1277  // Look at the currently assigned register for this instruction
1278  // to determine the required register class. If there is no register,
1279  // make a conservative choice (don't assign R0).
1280  unsigned AssignedReg = FuncInfo.ValueMap[I];
1281  const TargetRegisterClass *RC =
1282  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1283  &PPC::GPRC_and_GPRC_NOR0RegClass);
1284  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1285 
1286  unsigned Opc;
1287  switch (ISDOpcode) {
1288  default: return false;
1289  case ISD::ADD:
1290  Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1291  break;
1292  case ISD::OR:
1293  Opc = IsGPRC ? PPC::OR : PPC::OR8;
1294  break;
1295  case ISD::SUB:
1296  Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1297  break;
1298  }
1299 
1300  unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1301  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1302  if (SrcReg1 == 0) return false;
1303 
1304  // Handle case of small immediate operand.
1305  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1306  const APInt &CIVal = ConstInt->getValue();
1307  int Imm = (int)CIVal.getSExtValue();
1308  bool UseImm = true;
1309  if (isInt<16>(Imm)) {
1310  switch (Opc) {
1311  default:
1312  llvm_unreachable("Missing case!");
1313  case PPC::ADD4:
1314  Opc = PPC::ADDI;
1315  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1316  break;
1317  case PPC::ADD8:
1318  Opc = PPC::ADDI8;
1319  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1320  break;
1321  case PPC::OR:
1322  Opc = PPC::ORI;
1323  break;
1324  case PPC::OR8:
1325  Opc = PPC::ORI8;
1326  break;
1327  case PPC::SUBF:
1328  if (Imm == -32768)
1329  UseImm = false;
1330  else {
1331  Opc = PPC::ADDI;
1332  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1333  Imm = -Imm;
1334  }
1335  break;
1336  case PPC::SUBF8:
1337  if (Imm == -32768)
1338  UseImm = false;
1339  else {
1340  Opc = PPC::ADDI8;
1341  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1342  Imm = -Imm;
1343  }
1344  break;
1345  }
1346 
1347  if (UseImm) {
1348  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1349  ResultReg)
1350  .addReg(SrcReg1)
1351  .addImm(Imm);
1352  updateValueMap(I, ResultReg);
1353  return true;
1354  }
1355  }
1356  }
1357 
1358  // Reg-reg case.
1359  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1360  if (SrcReg2 == 0) return false;
1361 
1362  // Reverse operands for subtract-from.
1363  if (ISDOpcode == ISD::SUB)
1364  std::swap(SrcReg1, SrcReg2);
1365 
1366  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1367  .addReg(SrcReg1).addReg(SrcReg2);
1368  updateValueMap(I, ResultReg);
1369  return true;
1370 }
1371 
1372 // Handle arguments to a call that we're attempting to fast-select.
1373 // Return false if the arguments are too complex for us at the moment.
1374 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1375  SmallVectorImpl<unsigned> &ArgRegs,
1376  SmallVectorImpl<MVT> &ArgVTs,
1378  SmallVectorImpl<unsigned> &RegArgs,
1379  CallingConv::ID CC,
1380  unsigned &NumBytes,
1381  bool IsVarArg) {
1383  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1384 
1385  // Reserve space for the linkage area on the stack.
1386  unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1387  CCInfo.AllocateStack(LinkageSize, 8);
1388 
1389  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1390 
1391  // Bail out if we can't handle any of the arguments.
1392  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1393  CCValAssign &VA = ArgLocs[I];
1394  MVT ArgVT = ArgVTs[VA.getValNo()];
1395 
1396  // Skip vector arguments for now, as well as long double and
1397  // uint128_t, and anything that isn't passed in a register.
1398  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1399  !VA.isRegLoc() || VA.needsCustom())
1400  return false;
1401 
1402  // Skip bit-converted arguments for now.
1403  if (VA.getLocInfo() == CCValAssign::BCvt)
1404  return false;
1405  }
1406 
1407  // Get a count of how many bytes are to be pushed onto the stack.
1408  NumBytes = CCInfo.getNextStackOffset();
1409 
1410  // The prolog code of the callee may store up to 8 GPR argument registers to
1411  // the stack, allowing va_start to index over them in memory if its varargs.
1412  // Because we cannot tell if this is needed on the caller side, we have to
1413  // conservatively assume that it is needed. As such, make sure we have at
1414  // least enough stack space for the caller to store the 8 GPRs.
1415  // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1416  NumBytes = std::max(NumBytes, LinkageSize + 64);
1417 
1418  // Issue CALLSEQ_START.
1419  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1420  TII.get(TII.getCallFrameSetupOpcode()))
1421  .addImm(NumBytes).addImm(0);
1422 
1423  // Prepare to assign register arguments. Every argument uses up a
1424  // GPR protocol register even if it's passed in a floating-point
1425  // register (unless we're using the fast calling convention).
1426  unsigned NextGPR = PPC::X3;
1427  unsigned NextFPR = PPC::F1;
1428 
1429  // Process arguments.
1430  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1431  CCValAssign &VA = ArgLocs[I];
1432  unsigned Arg = ArgRegs[VA.getValNo()];
1433  MVT ArgVT = ArgVTs[VA.getValNo()];
1434 
1435  // Handle argument promotion and bitcasts.
1436  switch (VA.getLocInfo()) {
1437  default:
1438  llvm_unreachable("Unknown loc info!");
1439  case CCValAssign::Full:
1440  break;
1441  case CCValAssign::SExt: {
1442  MVT DestVT = VA.getLocVT();
1443  const TargetRegisterClass *RC =
1444  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1445  unsigned TmpReg = createResultReg(RC);
1446  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1447  llvm_unreachable("Failed to emit a sext!");
1448  ArgVT = DestVT;
1449  Arg = TmpReg;
1450  break;
1451  }
1452  case CCValAssign::AExt:
1453  case CCValAssign::ZExt: {
1454  MVT DestVT = VA.getLocVT();
1455  const TargetRegisterClass *RC =
1456  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1457  unsigned TmpReg = createResultReg(RC);
1458  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1459  llvm_unreachable("Failed to emit a zext!");
1460  ArgVT = DestVT;
1461  Arg = TmpReg;
1462  break;
1463  }
1464  case CCValAssign::BCvt: {
1465  // FIXME: Not yet handled.
1466  llvm_unreachable("Should have bailed before getting here!");
1467  break;
1468  }
1469  }
1470 
1471  // Copy this argument to the appropriate register.
1472  unsigned ArgReg;
1473  if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1474  ArgReg = NextFPR++;
1475  if (CC != CallingConv::Fast)
1476  ++NextGPR;
1477  } else
1478  ArgReg = NextGPR++;
1479 
1480  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1481  TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1482  RegArgs.push_back(ArgReg);
1483  }
1484 
1485  return true;
1486 }
1487 
1488 // For a call that we've determined we can fast-select, finish the
1489 // call sequence and generate a copy to obtain the return value (if any).
1490 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1491  CallingConv::ID CC = CLI.CallConv;
1492 
1493  // Issue CallSEQ_END.
1494  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1495  TII.get(TII.getCallFrameDestroyOpcode()))
1496  .addImm(NumBytes).addImm(0);
1497 
1498  // Next, generate a copy to obtain the return value.
1499  // FIXME: No multi-register return values yet, though I don't foresee
1500  // any real difficulties there.
1501  if (RetVT != MVT::isVoid) {
1503  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1504  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1505  CCValAssign &VA = RVLocs[0];
1506  assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1507  assert(VA.isRegLoc() && "Can only return in registers!");
1508 
1509  MVT DestVT = VA.getValVT();
1510  MVT CopyVT = DestVT;
1511 
1512  // Ints smaller than a register still arrive in a full 64-bit
1513  // register, so make sure we recognize this.
1514  if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1515  CopyVT = MVT::i64;
1516 
1517  unsigned SourcePhysReg = VA.getLocReg();
1518  unsigned ResultReg = 0;
1519 
1520  if (RetVT == CopyVT) {
1521  const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1522  ResultReg = createResultReg(CpyRC);
1523 
1524  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1525  TII.get(TargetOpcode::COPY), ResultReg)
1526  .addReg(SourcePhysReg);
1527 
1528  // If necessary, round the floating result to single precision.
1529  } else if (CopyVT == MVT::f64) {
1530  ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1531  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1532  ResultReg).addReg(SourcePhysReg);
1533 
1534  // If only the low half of a general register is needed, generate
1535  // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1536  // used along the fast-isel path (not lowered), and downstream logic
1537  // also doesn't like a direct subreg copy on a physical reg.)
1538  } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1539  ResultReg = createResultReg(&PPC::GPRCRegClass);
1540  // Convert physical register from G8RC to GPRC.
1541  SourcePhysReg -= PPC::X0 - PPC::R0;
1542  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1543  TII.get(TargetOpcode::COPY), ResultReg)
1544  .addReg(SourcePhysReg);
1545  }
1546 
1547  assert(ResultReg && "ResultReg unset!");
1548  CLI.InRegs.push_back(SourcePhysReg);
1549  CLI.ResultReg = ResultReg;
1550  CLI.NumResultRegs = 1;
1551  }
1552 
1553  return true;
1554 }
1555 
1556 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1557  CallingConv::ID CC = CLI.CallConv;
1558  bool IsTailCall = CLI.IsTailCall;
1559  bool IsVarArg = CLI.IsVarArg;
1560  const Value *Callee = CLI.Callee;
1561  const MCSymbol *Symbol = CLI.Symbol;
1562 
1563  if (!Callee && !Symbol)
1564  return false;
1565 
1566  // Allow SelectionDAG isel to handle tail calls.
1567  if (IsTailCall)
1568  return false;
1569 
1570  // Let SDISel handle vararg functions.
1571  if (IsVarArg)
1572  return false;
1573 
1574  // Handle simple calls for now, with legal return types and
1575  // those that can be extended.
1576  Type *RetTy = CLI.RetTy;
1577  MVT RetVT;
1578  if (RetTy->isVoidTy())
1579  RetVT = MVT::isVoid;
1580  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1581  RetVT != MVT::i8)
1582  return false;
1583  else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1584  // We can't handle boolean returns when CR bits are in use.
1585  return false;
1586 
1587  // FIXME: No multi-register return values yet.
1588  if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1589  RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1590  RetVT != MVT::f64) {
1592  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1593  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1594  if (RVLocs.size() > 1)
1595  return false;
1596  }
1597 
1598  // Bail early if more than 8 arguments, as we only currently
1599  // handle arguments passed in registers.
1600  unsigned NumArgs = CLI.OutVals.size();
1601  if (NumArgs > 8)
1602  return false;
1603 
1604  // Set up the argument vectors.
1606  SmallVector<unsigned, 8> ArgRegs;
1607  SmallVector<MVT, 8> ArgVTs;
1609 
1610  Args.reserve(NumArgs);
1611  ArgRegs.reserve(NumArgs);
1612  ArgVTs.reserve(NumArgs);
1613  ArgFlags.reserve(NumArgs);
1614 
1615  for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1616  // Only handle easy calls for now. It would be reasonably easy
1617  // to handle <= 8-byte structures passed ByVal in registers, but we
1618  // have to ensure they are right-justified in the register.
1619  ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1620  if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1621  return false;
1622 
1623  Value *ArgValue = CLI.OutVals[i];
1624  Type *ArgTy = ArgValue->getType();
1625  MVT ArgVT;
1626  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1627  return false;
1628 
1629  if (ArgVT.isVector())
1630  return false;
1631 
1632  unsigned Arg = getRegForValue(ArgValue);
1633  if (Arg == 0)
1634  return false;
1635 
1636  Args.push_back(ArgValue);
1637  ArgRegs.push_back(Arg);
1638  ArgVTs.push_back(ArgVT);
1639  ArgFlags.push_back(Flags);
1640  }
1641 
1642  // Process the arguments.
1643  SmallVector<unsigned, 8> RegArgs;
1644  unsigned NumBytes;
1645 
1646  if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1647  RegArgs, CC, NumBytes, IsVarArg))
1648  return false;
1649 
1650  MachineInstrBuilder MIB;
1651  // FIXME: No handling for function pointers yet. This requires
1652  // implementing the function descriptor (OPD) setup.
1653  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1654  if (!GV) {
1655  // patchpoints are a special case; they always dispatch to a pointer value.
1656  // However, we don't actually want to generate the indirect call sequence
1657  // here (that will be generated, as necessary, during asm printing), and
1658  // the call we generate here will be erased by FastISel::selectPatchpoint,
1659  // so don't try very hard...
1660  if (CLI.IsPatchPoint)
1661  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1662  else
1663  return false;
1664  } else {
1665  // Build direct call with NOP for TOC restore.
1666  // FIXME: We can and should optimize away the NOP for local calls.
1667  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1668  TII.get(PPC::BL8_NOP));
1669  // Add callee.
1670  MIB.addGlobalAddress(GV);
1671  }
1672 
1673  // Add implicit physical register uses to the call.
1674  for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1675  MIB.addReg(RegArgs[II], RegState::Implicit);
1676 
1677  // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1678  // into the call.
1679  PPCFuncInfo->setUsesTOCBasePtr();
1680  MIB.addReg(PPC::X2, RegState::Implicit);
1681 
1682  // Add a register mask with the call-preserved registers. Proper
1683  // defs for return values will be added by setPhysRegsDeadExcept().
1684  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1685 
1686  CLI.Call = MIB;
1687 
1688  // Finish off the call including any return values.
1689  return finishCall(RetVT, CLI, NumBytes);
1690 }
1691 
1692 // Attempt to fast-select a return instruction.
1693 bool PPCFastISel::SelectRet(const Instruction *I) {
1694 
1695  if (!FuncInfo.CanLowerReturn)
1696  return false;
1697 
1698  if (TLI.supportSplitCSR(FuncInfo.MF))
1699  return false;
1700 
1701  const ReturnInst *Ret = cast<ReturnInst>(I);
1702  const Function &F = *I->getParent()->getParent();
1703 
1704  // Build a list of return value registers.
1705  SmallVector<unsigned, 4> RetRegs;
1706  CallingConv::ID CC = F.getCallingConv();
1707 
1708  if (Ret->getNumOperands() > 0) {
1710  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1711 
1712  // Analyze operands of the call, assigning locations to each operand.
1714  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1715  CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1716  const Value *RV = Ret->getOperand(0);
1717 
1718  // FIXME: Only one output register for now.
1719  if (ValLocs.size() > 1)
1720  return false;
1721 
1722  // Special case for returning a constant integer of any size - materialize
1723  // the constant as an i64 and copy it to the return register.
1724  if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1725  CCValAssign &VA = ValLocs[0];
1726 
1727  unsigned RetReg = VA.getLocReg();
1728  // We still need to worry about properly extending the sign. For example,
1729  // we could have only a single bit or a constant that needs zero
1730  // extension rather than sign extension. Make sure we pass the return
1731  // value extension property to integer materialization.
1732  unsigned SrcReg =
1733  PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1734 
1735  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1736  TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1737 
1738  RetRegs.push_back(RetReg);
1739 
1740  } else {
1741  unsigned Reg = getRegForValue(RV);
1742 
1743  if (Reg == 0)
1744  return false;
1745 
1746  // Copy the result values into the output registers.
1747  for (unsigned i = 0; i < ValLocs.size(); ++i) {
1748 
1749  CCValAssign &VA = ValLocs[i];
1750  assert(VA.isRegLoc() && "Can only return in registers!");
1751  RetRegs.push_back(VA.getLocReg());
1752  unsigned SrcReg = Reg + VA.getValNo();
1753 
1754  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1755  if (!RVEVT.isSimple())
1756  return false;
1757  MVT RVVT = RVEVT.getSimpleVT();
1758  MVT DestVT = VA.getLocVT();
1759 
1760  if (RVVT != DestVT && RVVT != MVT::i8 &&
1761  RVVT != MVT::i16 && RVVT != MVT::i32)
1762  return false;
1763 
1764  if (RVVT != DestVT) {
1765  switch (VA.getLocInfo()) {
1766  default:
1767  llvm_unreachable("Unknown loc info!");
1768  case CCValAssign::Full:
1769  llvm_unreachable("Full value assign but types don't match?");
1770  case CCValAssign::AExt:
1771  case CCValAssign::ZExt: {
1772  const TargetRegisterClass *RC =
1773  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1774  unsigned TmpReg = createResultReg(RC);
1775  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1776  return false;
1777  SrcReg = TmpReg;
1778  break;
1779  }
1780  case CCValAssign::SExt: {
1781  const TargetRegisterClass *RC =
1782  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1783  unsigned TmpReg = createResultReg(RC);
1784  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1785  return false;
1786  SrcReg = TmpReg;
1787  break;
1788  }
1789  }
1790  }
1791 
1792  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1793  TII.get(TargetOpcode::COPY), RetRegs[i])
1794  .addReg(SrcReg);
1795  }
1796  }
1797  }
1798 
1799  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1800  TII.get(PPC::BLR8));
1801 
1802  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1803  MIB.addReg(RetRegs[i], RegState::Implicit);
1804 
1805  return true;
1806 }
1807 
1808 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1809 // signed and zero extensions are supported. Return false if we
1810 // can't handle it.
1811 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1812  unsigned DestReg, bool IsZExt) {
1813  if (DestVT != MVT::i32 && DestVT != MVT::i64)
1814  return false;
1815  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1816  return false;
1817 
1818  // Signed extensions use EXTSB, EXTSH, EXTSW.
1819  if (!IsZExt) {
1820  unsigned Opc;
1821  if (SrcVT == MVT::i8)
1822  Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1823  else if (SrcVT == MVT::i16)
1824  Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1825  else {
1826  assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1827  Opc = PPC::EXTSW_32_64;
1828  }
1829  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1830  .addReg(SrcReg);
1831 
1832  // Unsigned 32-bit extensions use RLWINM.
1833  } else if (DestVT == MVT::i32) {
1834  unsigned MB;
1835  if (SrcVT == MVT::i8)
1836  MB = 24;
1837  else {
1838  assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1839  MB = 16;
1840  }
1841  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1842  DestReg)
1843  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1844 
1845  // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1846  } else {
1847  unsigned MB;
1848  if (SrcVT == MVT::i8)
1849  MB = 56;
1850  else if (SrcVT == MVT::i16)
1851  MB = 48;
1852  else
1853  MB = 32;
1854  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1855  TII.get(PPC::RLDICL_32_64), DestReg)
1856  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1857  }
1858 
1859  return true;
1860 }
1861 
1862 // Attempt to fast-select an indirect branch instruction.
1863 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1864  unsigned AddrReg = getRegForValue(I->getOperand(0));
1865  if (AddrReg == 0)
1866  return false;
1867 
1868  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1869  .addReg(AddrReg);
1870  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1871 
1872  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1873  for (const BasicBlock *SuccBB : IB->successors())
1874  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1875 
1876  return true;
1877 }
1878 
1879 // Attempt to fast-select an integer truncate instruction.
1880 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1881  Value *Src = I->getOperand(0);
1882  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1883  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1884 
1885  if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1886  return false;
1887 
1888  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1889  return false;
1890 
1891  unsigned SrcReg = getRegForValue(Src);
1892  if (!SrcReg)
1893  return false;
1894 
1895  // The only interesting case is when we need to switch register classes.
1896  if (SrcVT == MVT::i64) {
1897  unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1898  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1899  TII.get(TargetOpcode::COPY),
1900  ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1901  SrcReg = ResultReg;
1902  }
1903 
1904  updateValueMap(I, SrcReg);
1905  return true;
1906 }
1907 
1908 // Attempt to fast-select an integer extend instruction.
1909 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1910  Type *DestTy = I->getType();
1911  Value *Src = I->getOperand(0);
1912  Type *SrcTy = Src->getType();
1913 
1914  bool IsZExt = isa<ZExtInst>(I);
1915  unsigned SrcReg = getRegForValue(Src);
1916  if (!SrcReg) return false;
1917 
1918  EVT SrcEVT, DestEVT;
1919  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1920  DestEVT = TLI.getValueType(DL, DestTy, true);
1921  if (!SrcEVT.isSimple())
1922  return false;
1923  if (!DestEVT.isSimple())
1924  return false;
1925 
1926  MVT SrcVT = SrcEVT.getSimpleVT();
1927  MVT DestVT = DestEVT.getSimpleVT();
1928 
1929  // If we know the register class needed for the result of this
1930  // instruction, use it. Otherwise pick the register class of the
1931  // correct size that does not contain X0/R0, since we don't know
1932  // whether downstream uses permit that assignment.
1933  unsigned AssignedReg = FuncInfo.ValueMap[I];
1934  const TargetRegisterClass *RC =
1935  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1936  (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1937  &PPC::GPRC_and_GPRC_NOR0RegClass));
1938  unsigned ResultReg = createResultReg(RC);
1939 
1940  if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1941  return false;
1942 
1943  updateValueMap(I, ResultReg);
1944  return true;
1945 }
1946 
1947 // Attempt to fast-select an instruction that wasn't handled by
1948 // the table-generated machinery.
1949 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1950 
1951  switch (I->getOpcode()) {
1952  case Instruction::Load:
1953  return SelectLoad(I);
1954  case Instruction::Store:
1955  return SelectStore(I);
1956  case Instruction::Br:
1957  return SelectBranch(I);
1958  case Instruction::IndirectBr:
1959  return SelectIndirectBr(I);
1960  case Instruction::FPExt:
1961  return SelectFPExt(I);
1962  case Instruction::FPTrunc:
1963  return SelectFPTrunc(I);
1964  case Instruction::SIToFP:
1965  return SelectIToFP(I, /*IsSigned*/ true);
1966  case Instruction::UIToFP:
1967  return SelectIToFP(I, /*IsSigned*/ false);
1968  case Instruction::FPToSI:
1969  return SelectFPToI(I, /*IsSigned*/ true);
1970  case Instruction::FPToUI:
1971  return SelectFPToI(I, /*IsSigned*/ false);
1972  case Instruction::Add:
1973  return SelectBinaryIntOp(I, ISD::ADD);
1974  case Instruction::Or:
1975  return SelectBinaryIntOp(I, ISD::OR);
1976  case Instruction::Sub:
1977  return SelectBinaryIntOp(I, ISD::SUB);
1978  case Instruction::Call:
1979  return selectCall(I);
1980  case Instruction::Ret:
1981  return SelectRet(I);
1982  case Instruction::Trunc:
1983  return SelectTrunc(I);
1984  case Instruction::ZExt:
1985  case Instruction::SExt:
1986  return SelectIntExt(I);
1987  // Here add other flavors of Instruction::XXX that automated
1988  // cases don't catch. For example, switches are terminators
1989  // that aren't yet handled.
1990  default:
1991  break;
1992  }
1993  return false;
1994 }
1995 
1996 // Materialize a floating-point constant into a register, and return
1997 // the register number (or zero if we failed to handle it).
1998 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1999  // No plans to handle long double here.
2000  if (VT != MVT::f32 && VT != MVT::f64)
2001  return 0;
2002 
2003  // All FP constants are loaded from the constant pool.
2004  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
2005  assert(Align > 0 && "Unexpectedly missing alignment information!");
2006  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
2007  const bool HasSPE = PPCSubTarget->hasSPE();
2008  const TargetRegisterClass *RC;
2009  if (HasSPE)
2010  RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
2011  else
2012  RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2013 
2014  unsigned DestReg = createResultReg(RC);
2015  CodeModel::Model CModel = TM.getCodeModel();
2016 
2017  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2019  MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
2020 
2021  unsigned Opc;
2022 
2023  if (HasSPE)
2024  Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2025  else
2026  Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2027 
2028  unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2029 
2030  PPCFuncInfo->setUsesTOCBasePtr();
2031  // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2032  if (CModel == CodeModel::Small) {
2033  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2034  TmpReg)
2035  .addConstantPoolIndex(Idx).addReg(PPC::X2);
2036  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2037  .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2038  } else {
2039  // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
2040  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
2041  TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2042  // But for large code model, we must generate a LDtocL followed
2043  // by the LF[SD].
2044  if (CModel == CodeModel::Large) {
2045  unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2046  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2047  TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2048  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2049  .addImm(0)
2050  .addReg(TmpReg2);
2051  } else
2052  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2053  .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
2054  .addReg(TmpReg)
2055  .addMemOperand(MMO);
2056  }
2057 
2058  return DestReg;
2059 }
2060 
2061 // Materialize the address of a global value into a register, and return
2062 // the register number (or zero if we failed to handle it).
2063 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2064  assert(VT == MVT::i64 && "Non-address!");
2065  const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2066  unsigned DestReg = createResultReg(RC);
2067 
2068  // Global values may be plain old object addresses, TLS object
2069  // addresses, constant pool entries, or jump tables. How we generate
2070  // code for these may depend on small, medium, or large code model.
2071  CodeModel::Model CModel = TM.getCodeModel();
2072 
2073  // FIXME: Jump tables are not yet required because fast-isel doesn't
2074  // handle switches; if that changes, we need them as well. For now,
2075  // what follows assumes everything's a generic (or TLS) global address.
2076 
2077  // FIXME: We don't yet handle the complexity of TLS.
2078  if (GV->isThreadLocal())
2079  return 0;
2080 
2081  PPCFuncInfo->setUsesTOCBasePtr();
2082  // For small code model, generate a simple TOC load.
2083  if (CModel == CodeModel::Small)
2084  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2085  DestReg)
2086  .addGlobalAddress(GV)
2087  .addReg(PPC::X2);
2088  else {
2089  // If the address is an externally defined symbol, a symbol with common
2090  // or externally available linkage, a non-local function address, or a
2091  // jump table address (not yet needed), or if we are generating code
2092  // for large code model, we generate:
2093  // LDtocL(GV, ADDIStocHA(%x2, GV))
2094  // Otherwise we generate:
2095  // ADDItocL(ADDIStocHA(%x2, GV), GV)
2096  // Either way, start with the ADDIStocHA:
2097  unsigned HighPartReg = createResultReg(RC);
2098  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
2099  HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2100 
2101  unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
2102  if (GVFlags & PPCII::MO_NLP_FLAG) {
2103  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2104  DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2105  } else {
2106  // Otherwise generate the ADDItocL.
2107  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2108  DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2109  }
2110  }
2111 
2112  return DestReg;
2113 }
2114 
2115 // Materialize a 32-bit integer constant into a register, and return
2116 // the register number (or zero if we failed to handle it).
2117 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2118  const TargetRegisterClass *RC) {
2119  unsigned Lo = Imm & 0xFFFF;
2120  unsigned Hi = (Imm >> 16) & 0xFFFF;
2121 
2122  unsigned ResultReg = createResultReg(RC);
2123  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2124 
2125  if (isInt<16>(Imm))
2126  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2127  TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2128  .addImm(Imm);
2129  else if (Lo) {
2130  // Both Lo and Hi have nonzero bits.
2131  unsigned TmpReg = createResultReg(RC);
2132  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2133  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2134  .addImm(Hi);
2135  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2136  TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2137  .addReg(TmpReg).addImm(Lo);
2138  } else
2139  // Just Hi bits.
2140  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2141  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2142  .addImm(Hi);
2143 
2144  return ResultReg;
2145 }
2146 
2147 // Materialize a 64-bit integer constant into a register, and return
2148 // the register number (or zero if we failed to handle it).
2149 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2150  const TargetRegisterClass *RC) {
2151  unsigned Remainder = 0;
2152  unsigned Shift = 0;
2153 
2154  // If the value doesn't fit in 32 bits, see if we can shift it
2155  // so that it fits in 32 bits.
2156  if (!isInt<32>(Imm)) {
2157  Shift = countTrailingZeros<uint64_t>(Imm);
2158  int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2159 
2160  if (isInt<32>(ImmSh))
2161  Imm = ImmSh;
2162  else {
2163  Remainder = Imm;
2164  Shift = 32;
2165  Imm >>= 32;
2166  }
2167  }
2168 
2169  // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2170  // (if not shifted).
2171  unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2172  if (!Shift)
2173  return TmpReg1;
2174 
2175  // If upper 32 bits were not zero, we've built them and need to shift
2176  // them into place.
2177  unsigned TmpReg2;
2178  if (Imm) {
2179  TmpReg2 = createResultReg(RC);
2180  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2181  TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2182  } else
2183  TmpReg2 = TmpReg1;
2184 
2185  unsigned TmpReg3, Hi, Lo;
2186  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2187  TmpReg3 = createResultReg(RC);
2188  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2189  TmpReg3).addReg(TmpReg2).addImm(Hi);
2190  } else
2191  TmpReg3 = TmpReg2;
2192 
2193  if ((Lo = Remainder & 0xFFFF)) {
2194  unsigned ResultReg = createResultReg(RC);
2195  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2196  ResultReg).addReg(TmpReg3).addImm(Lo);
2197  return ResultReg;
2198  }
2199 
2200  return TmpReg3;
2201 }
2202 
2203 // Materialize an integer constant into a register, and return
2204 // the register number (or zero if we failed to handle it).
2205 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2206  bool UseSExt) {
2207  // If we're using CR bit registers for i1 values, handle that as a special
2208  // case first.
2209  if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2210  unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2211  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2212  TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2213  return ImmReg;
2214  }
2215 
2216  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2217  VT != MVT::i1)
2218  return 0;
2219 
2220  const TargetRegisterClass *RC =
2221  ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2222  int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2223 
2224  // If the constant is in range, use a load-immediate.
2225  // Since LI will sign extend the constant we need to make sure that for
2226  // our zeroext constants that the sign extended constant fits into 16-bits -
2227  // a range of 0..0x7fff.
2228  if (isInt<16>(Imm)) {
2229  unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2230  unsigned ImmReg = createResultReg(RC);
2231  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2232  .addImm(Imm);
2233  return ImmReg;
2234  }
2235 
2236  // Construct the constant piecewise.
2237  if (VT == MVT::i64)
2238  return PPCMaterialize64BitInt(Imm, RC);
2239  else if (VT == MVT::i32)
2240  return PPCMaterialize32BitInt(Imm, RC);
2241 
2242  return 0;
2243 }
2244 
2245 // Materialize a constant into a register, and return the register
2246 // number (or zero if we failed to handle it).
2247 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2248  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2249 
2250  // Only handle simple types.
2251  if (!CEVT.isSimple()) return 0;
2252  MVT VT = CEVT.getSimpleVT();
2253 
2254  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2255  return PPCMaterializeFP(CFP, VT);
2256  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2257  return PPCMaterializeGV(GV, VT);
2258  else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2259  // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2260  // assumes that constant PHI operands will be zero extended, and failure to
2261  // match that assumption will cause problems if we sign extend here but
2262  // some user of a PHI is in a block for which we fall back to full SDAG
2263  // instruction selection.
2264  return PPCMaterializeInt(CI, VT, false);
2265 
2266  return 0;
2267 }
2268 
2269 // Materialize the address created by an alloca into a register, and
2270 // return the register number (or zero if we failed to handle it).
2271 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2272  // Don't handle dynamic allocas.
2273  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2274 
2275  MVT VT;
2276  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2277 
2279  FuncInfo.StaticAllocaMap.find(AI);
2280 
2281  if (SI != FuncInfo.StaticAllocaMap.end()) {
2282  unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2283  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2284  ResultReg).addFrameIndex(SI->second).addImm(0);
2285  return ResultReg;
2286  }
2287 
2288  return 0;
2289 }
2290 
2291 // Fold loads into extends when possible.
2292 // FIXME: We can have multiple redundant extend/trunc instructions
2293 // following a load. The folding only picks up one. Extend this
2294 // to check subsequent instructions for the same pattern and remove
2295 // them. Thus ResultReg should be the def reg for the last redundant
2296 // instruction in a chain, and all intervening instructions can be
2297 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2298 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2299 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2300  const LoadInst *LI) {
2301  // Verify we have a legal type before going any further.
2302  MVT VT;
2303  if (!isLoadTypeLegal(LI->getType(), VT))
2304  return false;
2305 
2306  // Combine load followed by zero- or sign-extend.
2307  bool IsZExt = false;
2308  switch(MI->getOpcode()) {
2309  default:
2310  return false;
2311 
2312  case PPC::RLDICL:
2313  case PPC::RLDICL_32_64: {
2314  IsZExt = true;
2315  unsigned MB = MI->getOperand(3).getImm();
2316  if ((VT == MVT::i8 && MB <= 56) ||
2317  (VT == MVT::i16 && MB <= 48) ||
2318  (VT == MVT::i32 && MB <= 32))
2319  break;
2320  return false;
2321  }
2322 
2323  case PPC::RLWINM:
2324  case PPC::RLWINM8: {
2325  IsZExt = true;
2326  unsigned MB = MI->getOperand(3).getImm();
2327  if ((VT == MVT::i8 && MB <= 24) ||
2328  (VT == MVT::i16 && MB <= 16))
2329  break;
2330  return false;
2331  }
2332 
2333  case PPC::EXTSB:
2334  case PPC::EXTSB8:
2335  case PPC::EXTSB8_32_64:
2336  /* There is no sign-extending load-byte instruction. */
2337  return false;
2338 
2339  case PPC::EXTSH:
2340  case PPC::EXTSH8:
2341  case PPC::EXTSH8_32_64: {
2342  if (VT != MVT::i16 && VT != MVT::i8)
2343  return false;
2344  break;
2345  }
2346 
2347  case PPC::EXTSW:
2348  case PPC::EXTSW_32:
2349  case PPC::EXTSW_32_64: {
2350  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2351  return false;
2352  break;
2353  }
2354  }
2355 
2356  // See if we can handle this address.
2357  Address Addr;
2358  if (!PPCComputeAddress(LI->getOperand(0), Addr))
2359  return false;
2360 
2361  unsigned ResultReg = MI->getOperand(0).getReg();
2362 
2363  if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2364  PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
2365  return false;
2366 
2368  removeDeadCode(I, std::next(I));
2369  return true;
2370 }
2371 
2372 // Attempt to lower call arguments in a faster way than done by
2373 // the selection DAG code.
2374 bool PPCFastISel::fastLowerArguments() {
2375  // Defer to normal argument lowering for now. It's reasonably
2376  // efficient. Consider doing something like ARM to handle the
2377  // case where all args fit in registers, no varargs, no float
2378  // or vector args.
2379  return false;
2380 }
2381 
2382 // Handle materializing integer constants into a register. This is not
2383 // automatically generated for PowerPC, so must be explicitly created here.
2384 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2385 
2386  if (Opc != ISD::Constant)
2387  return 0;
2388 
2389  // If we're using CR bit registers for i1 values, handle that as a special
2390  // case first.
2391  if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2392  unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2393  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2394  TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2395  return ImmReg;
2396  }
2397 
2398  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2399  VT != MVT::i1)
2400  return 0;
2401 
2402  const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2403  &PPC::GPRCRegClass);
2404  if (VT == MVT::i64)
2405  return PPCMaterialize64BitInt(Imm, RC);
2406  else
2407  return PPCMaterialize32BitInt(Imm, RC);
2408 }
2409 
2410 // Override for ADDI and ADDI8 to set the correct register class
2411 // on RHS operand 0. The automatic infrastructure naively assumes
2412 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2413 // for these cases. At the moment, none of the other automatically
2414 // generated RI instructions require special treatment. However, once
2415 // SelectSelect is implemented, "isel" requires similar handling.
2416 //
2417 // Also be conservative about the output register class. Avoid
2418 // assigning R0 or X0 to the output register for GPRC and G8RC
2419 // register classes, as any such result could be used in ADDI, etc.,
2420 // where those regs have another meaning.
2421 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2422  const TargetRegisterClass *RC,
2423  unsigned Op0, bool Op0IsKill,
2424  uint64_t Imm) {
2425  if (MachineInstOpcode == PPC::ADDI)
2426  MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2427  else if (MachineInstOpcode == PPC::ADDI8)
2428  MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2429 
2430  const TargetRegisterClass *UseRC =
2431  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2432  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2433 
2434  return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2435  Op0, Op0IsKill, Imm);
2436 }
2437 
2438 // Override for instructions with one register operand to avoid use of
2439 // R0/X0. The automatic infrastructure isn't aware of the context so
2440 // we must be conservative.
2441 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2442  const TargetRegisterClass* RC,
2443  unsigned Op0, bool Op0IsKill) {
2444  const TargetRegisterClass *UseRC =
2445  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2446  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2447 
2448  return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2449 }
2450 
2451 // Override for instructions with two register operands to avoid use
2452 // of R0/X0. The automatic infrastructure isn't aware of the context
2453 // so we must be conservative.
2454 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2455  const TargetRegisterClass* RC,
2456  unsigned Op0, bool Op0IsKill,
2457  unsigned Op1, bool Op1IsKill) {
2458  const TargetRegisterClass *UseRC =
2459  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2460  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2461 
2462  return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2463  Op1, Op1IsKill);
2464 }
2465 
2466 namespace llvm {
2467  // Create the fast instruction selector for PowerPC64 ELF.
2469  const TargetLibraryInfo *LibInfo) {
2470  // Only available on 64-bit ELF for now.
2471  const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2472  if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2473  return new PPCFastISel(FuncInfo, LibInfo);
2474  return nullptr;
2475  }
2476 }
uint64_t CallInst * C
Return a value (possibly void), from a function.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:635
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
bool isVector() const
Return true if this is a vector value type.
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
unsigned less or equal
Definition: InstrTypes.h:671
unsigned less than
Definition: InstrTypes.h:670
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:651
unsigned getValNo() const
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:661
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
unsigned const TargetRegisterInfo * TRI
F(f)
An instruction for reading from memory.
Definition: Instructions.h:167
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:176
Value * getCondition() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
void reserve(size_type N)
Definition: SmallVector.h:368
op_iterator op_begin()
Definition: User.h:229
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
bool needsCustom() const
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:656
unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:2112
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:528
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:655
A description of a memory reference used in the backend.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
Class to represent struct types.
Definition: DerivedTypes.h:200
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill)
Emit a MachineInstr with one register operand and a result register in the given register class...
Definition: FastISel.cpp:2039
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:652
SimpleValueType SimpleTy
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
LocInfo getLocInfo() const
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getSizeInBits() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:162
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
amdgpu Simplify well known AMD library false Value * Callee
Value * getOperand(unsigned i) const
Definition: User.h:169
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Conditional or Unconditional Branch instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:86
Indirect Branch Instruction.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
op_iterator op_end()
Definition: User.h:231
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:182
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:645
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:654
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Class to represent integer types.
Definition: DerivedTypes.h:39
const MachineInstrBuilder & addFrameIndex(int Idx) const
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:662
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
static bool isAtomic(Instruction *I)
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:672
The memory access writes data.
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:649
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:181
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:659
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:674
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2060
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
Definition: Constants.cpp:635
int64_t getImm() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
signed less or equal
Definition: InstrTypes.h:675
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
This file defines the FastISel class.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
amdgpu Simplify well known AMD library false Value Value * Arg
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:550
unsigned greater or equal
Definition: InstrTypes.h:669
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
#define I(x, y, z)
Definition: MD5.cpp:58
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:192
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:653
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:657
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:648
LLVM Value Representation.
Definition: Value.h:72
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:658
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
IRTranslator LLVM IR MI
unsigned greater than
Definition: InstrTypes.h:668
bool isSVR4ABI() const
Definition: PPCSubtarget.h:309
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
static Optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:650
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:647
signed greater or equal
Definition: InstrTypes.h:673
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
an instruction to allocate memory on the stack
Definition: Instructions.h:59
gep_type_iterator gep_type_begin(const User *GEP)