LLVM  6.0.0svn
Macros | Enumerations | Functions | Variables
PPCISelDAGToDAG.cpp File Reference
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <new>
#include <tuple>
#include <utility>
#include "PPCGenDAGISel.inc"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "ppc-codegen"
 

Enumerations

enum  ICmpInGPRType {
  ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,
  ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,
  ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64
}
 

Functions

 STATISTIC (NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence.")
 
 STATISTIC (NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence.")
 
 STATISTIC (SignExtensionsAdded, "Number of sign extensions for compare inputs added.")
 
 STATISTIC (ZeroExtensionsAdded, "Number of zero extensions for compare inputs added.")
 
 STATISTIC (NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR.")
 
 STATISTIC (OmittedForNonExtendUses, "Number of compares not eliminated as they have non-extending uses.")
 
static bool isInt32Immediate (SDNode *N, unsigned &Imm)
 isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More...
 
static bool isInt64Immediate (SDNode *N, uint64_t &Imm)
 isInt64Immediate - This method tests to see if the node is a 64-bit constant operand. More...
 
static bool isInt32Immediate (SDValue N, unsigned &Imm)
 
static bool isInt64Immediate (SDValue N, uint64_t &Imm)
 isInt64Immediate - This method tests to see if the value is a 64-bit constant operand. More...
 
static unsigned getBranchHint (unsigned PCC, FunctionLoweringInfo *FuncInfo, const SDValue &DestMBB)
 
static bool isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
 
static unsigned selectI64ImmInstrCountDirect (int64_t Imm)
 
static uint64_t Rot64 (uint64_t Imm, unsigned R)
 
static unsigned selectI64ImmInstrCount (int64_t Imm)
 
static SDNodeselectI64ImmDirect (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
 
static SDNodeselectI64Imm (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
 
static unsigned allUsesTruncate (SelectionDAG *CurDAG, SDNode *N)
 
static SDNodeselectI64Imm (SelectionDAG *CurDAG, SDNode *N)
 
static PPC::Predicate getPredicateForSetCC (ISD::CondCode CC)
 
static unsigned getCRIdxForSetCC (ISD::CondCode CC, bool &Invert)
 getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted. More...
 
static unsigned int getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
 
static bool PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode *> &ToPromote)
 

Variables

cl::opt< boolANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
 
static cl::opt< boolUseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
 
static cl::opt< boolBPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)
 
static cl::opt< boolEnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
 
static cl::opt< ICmpInGPRTypeCmpInGPR ("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "ppc-codegen"

Definition at line 70 of file PPCISelDAGToDAG.cpp.

Enumeration Type Documentation

◆ ICmpInGPRType

Enumerator
ICGPR_All 
ICGPR_None 
ICGPR_I32 
ICGPR_I64 
ICGPR_NonExtIn 
ICGPR_Zext 
ICGPR_Sext 
ICGPR_ZextI32 
ICGPR_SextI32 
ICGPR_ZextI64 
ICGPR_SextI64 

Definition at line 104 of file PPCISelDAGToDAG.cpp.

Function Documentation

◆ allUsesTruncate()

static unsigned allUsesTruncate ( SelectionDAG CurDAG,
SDNode N 
)
static

◆ getBranchHint()

static unsigned getBranchHint ( unsigned  PCC,
FunctionLoweringInfo FuncInfo,
const SDValue DestMBB 
)
static

◆ getCRIdxForSetCC()

static unsigned getCRIdxForSetCC ( ISD::CondCode  CC,
bool Invert 
)
static

getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.

That is, lt = 0; ge = 0 inverted.

Definition at line 3530 of file PPCISelDAGToDAG.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by getVCmpInst().

◆ getPredicateForSetCC()

static PPC::Predicate getPredicateForSetCC ( ISD::CondCode  CC)
static

◆ getVCmpInst()

static unsigned int getVCmpInst ( MVT  VecVT,
ISD::CondCode  CC,
bool  HasVSX,
bool Swap,
bool Negate 
)
static

Definition at line 3562 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::allocateMemRefsArray(), llvm::ISD::AND, ANDIGlueBug, llvm::PPCISD::ANDIo_1_EQ_BIT, llvm::PPCISD::ANDIo_1_GT_BIT, llvm::ISD::ANY_EXTEND, assert(), llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::tgtok::Bits, llvm::ISD::BR_CC, llvm::ISD::BRIND, C, llvm::EVT::changeVectorElementTypeToInteger(), llvm::PPCSubtarget::classifyGlobalReference(), llvm::PPCISD::CMPB, llvm::PPCISD::COND_BRANCH, llvm::ISD::Constant, llvm::ISD::CopyFromReg, llvm::countTrailingOnes(), llvm::dbgs(), DEBUG, llvm::SDNode::dump(), llvm::dyn_cast(), llvm::SmallVectorBase::empty(), EnableBranchHint, llvm::SmallVectorTemplateCommon< T >::end(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FrameIndex, G, llvm::LSBaseSDNode::getAddressingMode(), llvm::LoadSDNode::getBasePtr(), getBranchHint(), llvm::MemSDNode::getChain(), llvm::TargetMachine::getCodeModel(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), getCRIdxForSetCC(), llvm::LoadSDNode::getExtensionType(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getMachineOpcode(), llvm::SDNode::getMachineOpcode(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::LoadSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), getPredicateForSetCC(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::APInt::getZExtValue(), llvm::PPCISD::GlobalBaseReg, llvm::MVT::Glue, llvm::PPCSubtarget::hasCMPB(), llvm::SDNode::hasOneUse(), llvm::PPCSubtarget::hasP8Vector(), llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::hasVSX(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86II::Imm64, llvm::MVT::isFloatingPoint(), isInt32Immediate(), isInt64Immediate(), llvm::isInt< 16 >(), llvm::isIntS16Immediate(), llvm::PPCSubtarget::isLittleEndian(), llvm::SDValue::isMachineOpcode(), llvm::SDNode::isMachineOpcode(), llvm::isMask_64(), llvm::ConstantSDNode::isNullValue(), isOpcWithIntImmediate(), llvm::PPCSubtarget::isPPC64(), llvm::isRunOfOnes(), llvm::PPCSubtarget::isSVR4ABI(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::CodeModel::Large, llvm::ARM_MB::LD, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MipsISD::Lo, llvm::ISD::LOAD, llvm::BitmaskEnumDetail::Mask(), llvm::CodeModel::Medium, llvm::PPCISD::MFOCRF, llvm::PPCII::MO_NLP_FLAG, llvm::PPCISD::MTCTR, N, llvm::AArch64ISD::NEG, llvm::CodeGenOpt::None, llvm::RISCVFenceField::O, llvm::SDNode::ops(), llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::PPCISD::PPC32_PICGOT, llvm::ISD::PRE_INC, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::PPCISD::READ_TIME_BASE, llvm::ISD::ROTL, llvm::ISD::SCALAR_TO_VECTOR, llvm::MCID::Select, llvm::ISD::SELECT_CC, selectI64Imm(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::SDNode::setNodeId(), llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::PPCISD::SRA_ADDZE, llvm::ISD::SRL, std::swap(), T, llvm::ISD::TargetConstant, llvm::ISD::TargetGlobalAddress, llvm::PPCISD::TOC_ENTRY, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_empty(), llvm::SDNode::use_end(), llvm::PPCSubtarget::useCRBits(), llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::PPCISD::VADD_SPLAT, llvm::ISD::VECTOR_SHUFFLE, llvm::MipsISD::VNOR, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::PPCISD::XXPERMDI, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.

◆ isInt32Immediate() [1/2]

static bool isInt32Immediate ( SDNode N,
unsigned Imm 
)
static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 432 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.

Referenced by getVCmpInst(), isInt32Immediate(), isOpcWithIntImmediate(), and selectI64Imm().

◆ isInt32Immediate() [2/2]

static bool isInt32Immediate ( SDValue  N,
unsigned Imm 
)
static

Definition at line 452 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isInt32Immediate().

◆ isInt64Immediate() [1/2]

static bool isInt64Immediate ( SDNode N,
uint64_t &  Imm 
)
static

isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 442 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i64, and N.

Referenced by getVCmpInst(), isInt64Immediate(), and selectI64Imm().

◆ isInt64Immediate() [2/2]

static bool isInt64Immediate ( SDValue  N,
uint64_t &  Imm 
)
static

isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 458 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isInt64Immediate().

◆ isOpcWithIntImmediate()

static bool isOpcWithIntImmediate ( SDNode N,
unsigned  Opc,
unsigned Imm 
)
static

◆ PeepholePPC64ZExtGather()

static bool PeepholePPC64ZExtGather ( SDValue  Op32,
SmallPtrSetImpl< SDNode *> &  ToPromote 
)
static

◆ Rot64()

static uint64_t Rot64 ( uint64_t  Imm,
unsigned  R 
)
static

Definition at line 718 of file PPCISelDAGToDAG.cpp.

Referenced by selectI64Imm(), and selectI64ImmInstrCount().

◆ selectI64Imm() [1/2]

static SDNode* selectI64Imm ( SelectionDAG CurDAG,
const SDLoc dl,
int64_t  Imm 
)
static

◆ selectI64Imm() [2/2]

static SDNode* selectI64Imm ( SelectionDAG CurDAG,
SDNode N 
)
static

Definition at line 954 of file PPCISelDAGToDAG.cpp.

References llvm::MCID::Add, allUsesTruncate(), llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::tgtok::Bits, BPermRewriterNoMasking, CmpInGPR, llvm::MCID::Compare, llvm::dbgs(), DEBUG, llvm::SDNode::dump(), llvm::dyn_cast(), E, llvm::MipsISD::Ext, F(), llvm::MVT::f32, llvm::MVT::f64, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::TargetLoweringBase::getPointerTy(), llvm::PPCInstrInfo::getRecordFormOpcode(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::Glue, llvm::SDValue::hasOneUse(), llvm::PPCSubtarget::hasVSX(), I, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, ICGPR_I32, ICGPR_I64, ICGPR_None, ICGPR_NonExtIn, ICGPR_Sext, ICGPR_SextI32, ICGPR_Zext, ICGPR_ZextI32, ICGPR_ZextI64, llvm::ARM_PROC::IE, llvm::isBitwiseNot(), isInt32Immediate(), isInt64Immediate(), llvm::isInt< 16 >(), llvm::isIntS16Immediate(), llvm::ConstantSDNode::isNullValue(), llvm::PPCTargetMachine::isPPC64(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::ISD::isUnsignedIntSetCC(), isZero(), Kind, LLVM_FALLTHROUGH, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::max(), N, llvm::AArch64ISD::NEG, llvm::CodeGenOpt::None, llvm::operator<(), OR, llvm::ISD::OR, Other, llvm::remove_if(), llvm::SmallVectorImpl< T >::resize(), llvm::NVPTX::PTXCvtMode::RN, llvm::ISD::ROTL, llvm::PPCISD::SC, second, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, selectI64Imm(), selectI64ImmInstrCount(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SignExtend64(), llvm::parallel::sort(), llvm::ISD::SRL, std::swap(), llvm::ISD::TRUNCATE, UseBitPermRewriter, llvm::SDNode::uses(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

◆ selectI64ImmDirect()

static SDNode* selectI64ImmDirect ( SelectionDAG CurDAG,
const SDLoc dl,
int64_t  Imm 
)
static

◆ selectI64ImmInstrCount()

static unsigned selectI64ImmInstrCount ( int64_t  Imm)
static

◆ selectI64ImmInstrCountDirect()

static unsigned selectI64ImmInstrCountDirect ( int64_t  Imm)
static

◆ STATISTIC() [1/6]

STATISTIC ( NumSextSetcc  ,
"Number of (sext(setcc)) nodes expanded into GPR sequence."   
)

◆ STATISTIC() [2/6]

STATISTIC ( NumZextSetcc  ,
"Number of (zext(setcc)) nodes expanded into GPR sequence."   
)

◆ STATISTIC() [3/6]

STATISTIC ( SignExtensionsAdded  ,
"Number of sign extensions for compare inputs added."   
)

◆ STATISTIC() [4/6]

STATISTIC ( ZeroExtensionsAdded  ,
"Number of zero extensions for compare inputs added."   
)

◆ STATISTIC() [5/6]

STATISTIC ( NumLogicOpsOnComparison  ,
"Number of logical ops on i1 values calculated in GPR."   
)

◆ STATISTIC() [6/6]

STATISTIC ( OmittedForNonExtendUses  ,
"Number of compares not eliminated as they have non-extending uses."   
)

Variable Documentation

◆ ANDIGlueBug

cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)

Referenced by getVCmpInst().

◆ BPermRewriterNoMasking

cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)
static

Referenced by selectI64Imm().

◆ CmpInGPR

cl::opt<ICmpInGPRType> CmpInGPR("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))
static

Referenced by selectI64Imm().

◆ EnableBranchHint

cl::opt<bool> EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static

Referenced by getVCmpInst().

◆ UseBitPermRewriter

cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
static

Referenced by selectI64Imm().