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PPCISelLowering.h
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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
17 
18 #include "PPC.h"
19 #include "PPCInstrInfo.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/InlineAsm.h"
32 #include "llvm/IR/Metadata.h"
33 #include "llvm/IR/Type.h"
34 #include <utility>
35 
36 namespace llvm {
37 
38  namespace PPCISD {
39 
40  // When adding a NEW PPCISD node please add it to the correct position in
41  // the enum. The order of elements in this enum matters!
42  // Values that are added after this entry:
43  // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
44  // are considerd memory opcodes and are treated differently than entries
45  // that come before it. For example, ADD or MUL should be placed before
46  // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
47  // after it.
48  enum NodeType : unsigned {
49  // Start the numbering where the builtin ops and target ops leave off.
51 
52  /// FSEL - Traditional three-operand fsel node.
53  ///
55 
56  /// FCFID - The FCFID instruction, taking an f64 operand and producing
57  /// and f64 value containing the FP representation of the integer that
58  /// was temporarily in the f64 operand.
60 
61  /// Newer FCFID[US] integer-to-floating-point conversion instructions for
62  /// unsigned integers and single-precision outputs.
64 
65  /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
66  /// operand, producing an f64 value containing the integer representation
67  /// of that FP value.
69 
70  /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
71  /// unsigned integers with round toward zero.
73 
74  /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
75  /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
77 
78  /// SExtVElems, takes an input vector of a smaller type and sign
79  /// extends to an output vector of a larger type.
81 
82  /// Reciprocal estimate instructions (unary FP ops).
84 
85  // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
86  // three v4f32 operands and producing a v4f32 result.
88 
89  /// VPERM - The PPC VPERM Instruction.
90  ///
92 
93  /// XXSPLT - The PPC VSX splat instructions
94  ///
96 
97  /// VECINSERT - The PPC vector insert instruction
98  ///
100 
101  /// XXREVERSE - The PPC VSX reverse instruction
102  ///
104 
105  /// VECSHL - The PPC vector shift left instruction
106  ///
108 
109  /// XXPERMDI - The PPC XXPERMDI instruction
110  ///
112 
113  /// The CMPB instruction (takes two operands of i32 or i64).
115 
116  /// Hi/Lo - These represent the high and low 16-bit parts of a global
117  /// address respectively. These nodes have two operands, the first of
118  /// which must be a TargetGlobalAddress, and the second of which must be a
119  /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
120  /// though these are usually folded into other nodes.
121  Hi, Lo,
122 
123  /// The following two target-specific nodes are used for calls through
124  /// function pointers in the 64-bit SVR4 ABI.
125 
126  /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
127  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
128  /// compute an allocation on the stack.
130 
131  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
132  /// compute an offset from native SP to the address of the most recent
133  /// dynamic alloca.
135 
136  /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
137  /// at function entry, used for PIC code.
139 
140  /// These nodes represent PPC shifts.
141  ///
142  /// For scalar types, only the last `n + 1` bits of the shift amounts
143  /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
144  /// for exact behaviors.
145  ///
146  /// For vector types, only the last n bits are used. See vsld.
148 
149  /// The combination of sra[wd]i and addze used to implemented signed
150  /// integer division by a power of 2. The first operand is the dividend,
151  /// and the second is the constant shift amount (representing the
152  /// divisor).
154 
155  /// CALL - A direct function call.
156  /// CALL_NOP is a call with the special NOP which follows 64-bit
157  /// SVR4 calls.
159 
160  /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
161  /// MTCTR instruction.
163 
164  /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
165  /// BCTRL instruction.
167 
168  /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
169  /// instruction and the TOC reload required on SVR4 PPC64.
171 
172  /// Return with a flag operand, matched by 'blr'
174 
175  /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
176  /// This copies the bits corresponding to the specified CRREG into the
177  /// resultant GPR. Bits corresponding to other CR regs are undefined.
179 
180  /// Direct move from a VSX register to a GPR
182 
183  /// Direct move from a GPR to a VSX register (algebraic)
185 
186  /// Direct move from a GPR to a VSX register (zero)
188 
189  /// Extract a subvector from signed integer vector and convert to FP.
190  /// It is primarily used to convert a (widened) illegal integer vector
191  /// type to a legal floating point vector type.
192  /// For example v2i32 -> widened to v4i32 -> v2f64
194 
195  /// Extract a subvector from unsigned integer vector and convert to FP.
196  /// As with SINT_VEC_TO_FP, used for converting illegal types.
198 
199  // FIXME: Remove these once the ANDI glue bug is fixed:
200  /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
201  /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
202  /// implement truncation of i32 or i64 to i1.
204 
205  // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
206  // target (returns (Lo, Hi)). It takes a chain operand.
208 
209  // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
211 
212  // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
214 
215  /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
216  /// instructions. For lack of better number, we use the opcode number
217  /// encoding for the OPC field to identify the compare. For example, 838
218  /// is VCMPGTSH.
220 
221  /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
222  /// altivec VCMP*o instructions. For lack of better number, we use the
223  /// opcode number encoding for the OPC field to identify the compare. For
224  /// example, 838 is VCMPGTSH.
226 
227  /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
228  /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
229  /// condition register to branch on, OPC is the branch opcode to use (e.g.
230  /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
231  /// an optional input flag argument.
233 
234  /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
235  /// loops.
237 
238  /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
239  /// towards zero. Used only as part of the long double-to-int
240  /// conversion sequence.
242 
243  /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
245 
246  /// TC_RETURN - A tail call return.
247  /// operand #0 chain
248  /// operand #1 callee (register or absolute)
249  /// operand #2 stack adjustment
250  /// operand #3 optional in flag
252 
253  /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
256 
257  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
258  /// on PPC32.
260 
261  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
262  /// local dynamic TLS on PPC32.
264 
265  /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
266  /// TLS model, produces an ADDIS8 instruction that adds the GOT
267  /// base to sym\@got\@tprel\@ha.
269 
270  /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
271  /// TLS model, produces a LD instruction with base register G8RReg
272  /// and offset sym\@got\@tprel\@l. This completes the addition that
273  /// finds the offset of "sym" relative to the thread pointer.
275 
276  /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
277  /// model, produces an ADD instruction that adds the contents of
278  /// G8RReg to the thread pointer. Symbol contains a relocation
279  /// sym\@tls which is to be replaced by the thread pointer and
280  /// identifies to the linker that the instruction is part of a
281  /// TLS sequence.
283 
284  /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
285  /// model, produces an ADDIS8 instruction that adds the GOT base
286  /// register to sym\@got\@tlsgd\@ha.
288 
289  /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
290  /// model, produces an ADDI8 instruction that adds G8RReg to
291  /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
292  /// ADDIS_TLSGD_L_ADDR until after register assignment.
294 
295  /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
296  /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
297  /// ADDIS_TLSGD_L_ADDR until after register assignment.
299 
300  /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
301  /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
302  /// register assignment.
304 
305  /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
306  /// model, produces an ADDIS8 instruction that adds the GOT base
307  /// register to sym\@got\@tlsld\@ha.
309 
310  /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
311  /// model, produces an ADDI8 instruction that adds G8RReg to
312  /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
313  /// ADDIS_TLSLD_L_ADDR until after register assignment.
315 
316  /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
317  /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
318  /// ADDIS_TLSLD_L_ADDR until after register assignment.
320 
321  /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
322  /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
323  /// following register assignment.
325 
326  /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
327  /// model, produces an ADDIS8 instruction that adds X3 to
328  /// sym\@dtprel\@ha.
330 
331  /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
332  /// model, produces an ADDI8 instruction that adds G8RReg to
333  /// sym\@got\@dtprel\@l.
335 
336  /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
337  /// during instruction selection to optimize a BUILD_VECTOR into
338  /// operations on splats. This is necessary to avoid losing these
339  /// optimizations due to constant folding.
341 
342  /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
343  /// operand identifies the operating system entry point.
344  SC,
345 
346  /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
348 
349  /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
350  /// history rolling buffer entry.
352 
353  /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
355 
356  /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
357  /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
358  /// or stxvd2x instruction. The chain is necessary because the
359  /// sequence replaces a load and needs to provide the same number
360  /// of outputs.
362 
363  /// An SDNode for swaps that are not associated with any loads/stores
364  /// and thereby have no chain.
366 
367  /// QVFPERM = This corresponds to the QPX qvfperm instruction.
369 
370  /// QVGPCI = This corresponds to the QPX qvgpci instruction.
372 
373  /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
375 
376  /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
378 
379  /// QBFLT = Access the underlying QPX floating-point boolean
380  /// representation.
382 
383  /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
384  /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
385  /// the GPRC input, then stores it through Ptr. Type can be either i16 or
386  /// i32.
388 
389  /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
390  /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
391  /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
392  /// or i32.
394 
395  /// STFIWX - The STFIWX instruction. The first operand is an input token
396  /// chain, then an f64 value to store, then an address to store it to.
398 
399  /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
400  /// load which sign-extends from a 32-bit integer value into the
401  /// destination 64-bit register.
403 
404  /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
405  /// load which zero-extends from a 32-bit integer value into the
406  /// destination 64-bit register.
408 
409  /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
410  /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
411  /// This can be used for converting loaded integers to floating point.
413 
414  /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
415  /// chain, then an f64 value to store, then an address to store it to,
416  /// followed by a byte-width for the store.
418 
419  /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
420  /// Maps directly to an lxvd2x instruction that will be followed by
421  /// an xxswapd.
423 
424  /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
425  /// Maps directly to an stxvd2x instruction that will be preceded by
426  /// an xxswapd.
428 
429  /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
430  /// The 4xf32 load used for v4i1 constants.
432 
433  /// GPRC = TOC_ENTRY GA, TOC
434  /// Loads the entry for GA from the TOC, where the TOC base is given by
435  /// the last operand.
437  };
438 
439  } // end namespace PPCISD
440 
441  /// Define some predicates that are used for node matching.
442  namespace PPC {
443 
444  /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
445  /// VPKUHUM instruction.
446  bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
447  SelectionDAG &DAG);
448 
449  /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
450  /// VPKUWUM instruction.
451  bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
452  SelectionDAG &DAG);
453 
454  /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
455  /// VPKUDUM instruction.
456  bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
457  SelectionDAG &DAG);
458 
459  /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
460  /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
461  bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
462  unsigned ShuffleKind, SelectionDAG &DAG);
463 
464  /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
465  /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
466  bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
467  unsigned ShuffleKind, SelectionDAG &DAG);
468 
469  /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
470  /// a VMRGEW or VMRGOW instruction
471  bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
472  unsigned ShuffleKind, SelectionDAG &DAG);
473  /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
474  /// for a XXSLDWI instruction.
475  bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
476  bool &Swap, bool IsLE);
477 
478  /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
479  /// for a XXBRH instruction.
481 
482  /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
483  /// for a XXBRW instruction.
485 
486  /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
487  /// for a XXBRD instruction.
489 
490  /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
491  /// for a XXBRQ instruction.
493 
494  /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
495  /// for a XXPERMDI instruction.
496  bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
497  bool &Swap, bool IsLE);
498 
499  /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
500  /// shift amount, otherwise return -1.
501  int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
502  SelectionDAG &DAG);
503 
504  /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
505  /// specifies a splat of a single element that is suitable for input to
506  /// VSPLTB/VSPLTH/VSPLTW.
507  bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
508 
509  /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
510  /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
511  /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
512  /// vector into the other. This function will also set a couple of
513  /// output parameters for how much the source vector needs to be shifted and
514  /// what byte number needs to be specified for the instruction to put the
515  /// element in the desired location of the target vector.
516  bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
517  unsigned &InsertAtByte, bool &Swap, bool IsLE);
518 
519  /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
520  /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
521  unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
522 
523  /// get_VSPLTI_elt - If this is a build_vector of constants which can be
524  /// formed by using a vspltis[bhw] instruction of the specified element
525  /// size, return the constant being splatted. The ByteSize field indicates
526  /// the number of bytes of each element [124] -> [bhw].
527  SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
528 
529  /// If this is a qvaligni shuffle mask, return the shift
530  /// amount, otherwise return -1.
532 
533  } // end namespace PPC
534 
536  const PPCSubtarget &Subtarget;
537 
538  public:
539  explicit PPCTargetLowering(const PPCTargetMachine &TM,
540  const PPCSubtarget &STI);
541 
542  /// getTargetNodeName() - This method returns the name of a target specific
543  /// DAG node.
544  const char *getTargetNodeName(unsigned Opcode) const override;
545 
546  /// getPreferredVectorAction - The code we generate when vector types are
547  /// legalized by promoting the integer element type is often much worse
548  /// than code we generate if we widen the type for applicable vector types.
549  /// The issue with promoting is that the vector is scalaraized, individual
550  /// elements promoted and then the vector is rebuilt. So say we load a pair
551  /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
552  /// loads, moves back into VSR's (or memory ops if we don't have moves) and
553  /// then the VPERM for the shuffle. All in all a very slow sequence.
555  const override {
556  if (VT.getScalarSizeInBits() % 8 == 0)
557  return TypeWidenVector;
559  }
560 
561  bool useSoftFloat() const override;
562 
563  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
564  return MVT::i32;
565  }
566 
567  bool isCheapToSpeculateCttz() const override {
568  return true;
569  }
570 
571  bool isCheapToSpeculateCtlz() const override {
572  return true;
573  }
574 
575  bool isCtlzFast() const override {
576  return true;
577  }
578 
579  bool hasAndNotCompare(SDValue) const override {
580  return true;
581  }
582 
583  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
584  return VT.isScalarInteger();
585  }
586 
587  bool supportSplitCSR(MachineFunction *MF) const override {
588  return
590  MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
591  }
592 
593  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
594 
595  void insertCopiesSplitCSR(
596  MachineBasicBlock *Entry,
597  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
598 
599  /// getSetCCResultType - Return the ISD::SETCC ValueType
600  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
601  EVT VT) const override;
602 
603  /// Return true if target always beneficiates from combining into FMA for a
604  /// given value type. This must typically return false on targets where FMA
605  /// takes more cycles to execute than FADD.
606  bool enableAggressiveFMAFusion(EVT VT) const override;
607 
608  /// getPreIndexedAddressParts - returns true by value, base pointer and
609  /// offset pointer and addressing mode by reference if the node's address
610  /// can be legally represented as pre-indexed load / store address.
611  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
612  SDValue &Offset,
614  SelectionDAG &DAG) const override;
615 
616  /// SelectAddressRegReg - Given the specified addressed, check to see if it
617  /// can be represented as an indexed [r+r] operation. Returns false if it
618  /// can be more efficiently represented with [r+imm].
619  bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
620  SelectionDAG &DAG) const;
621 
622  /// SelectAddressRegImm - Returns true if the address N can be represented
623  /// by a base register plus a signed 16-bit displacement [r+imm], and if it
624  /// is not better represented as reg+reg. If Aligned is true, only accept
625  /// displacements suitable for STD and friends, i.e. multiples of 4.
626  bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
627  SelectionDAG &DAG, unsigned Alignment) const;
628 
629  /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
630  /// represented as an indexed [r+r] operation.
631  bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
632  SelectionDAG &DAG) const;
633 
634  Sched::Preference getSchedulingPreference(SDNode *N) const override;
635 
636  /// LowerOperation - Provide custom lowering hooks for some operations.
637  ///
638  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
639 
640  /// ReplaceNodeResults - Replace the results of node with an illegal result
641  /// type with new values built out of custom code.
642  ///
643  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
644  SelectionDAG &DAG) const override;
645 
646  SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
647  SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
648 
649  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
650 
651  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
652  std::vector<SDNode *> *Created) const override;
653 
654  unsigned getRegisterByName(const char* RegName, EVT VT,
655  SelectionDAG &DAG) const override;
656 
657  void computeKnownBitsForTargetNode(const SDValue Op,
658  KnownBits &Known,
659  const APInt &DemandedElts,
660  const SelectionDAG &DAG,
661  unsigned Depth = 0) const override;
662 
663  unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
664 
665  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
666  return true;
667  }
668 
669  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
670  AtomicOrdering Ord) const override;
671  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
672  AtomicOrdering Ord) const override;
673 
675  EmitInstrWithCustomInserter(MachineInstr &MI,
676  MachineBasicBlock *MBB) const override;
677  MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
678  MachineBasicBlock *MBB,
679  unsigned AtomicSize,
680  unsigned BinOpcode,
681  unsigned CmpOpcode = 0,
682  unsigned CmpPred = 0) const;
683  MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
684  MachineBasicBlock *MBB,
685  bool is8bit,
686  unsigned Opcode,
687  unsigned CmpOpcode = 0,
688  unsigned CmpPred = 0) const;
689 
690  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
691  MachineBasicBlock *MBB) const;
692 
693  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
694  MachineBasicBlock *MBB) const;
695 
696  ConstraintType getConstraintType(StringRef Constraint) const override;
697 
698  /// Examine constraint string and operand type and determine a weight value.
699  /// The operand object must already have been set up with the operand type.
700  ConstraintWeight getSingleConstraintMatchWeight(
701  AsmOperandInfo &info, const char *constraint) const override;
702 
703  std::pair<unsigned, const TargetRegisterClass *>
704  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
705  StringRef Constraint, MVT VT) const override;
706 
707  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
708  /// function arguments in the caller parameter area. This is the actual
709  /// alignment, not its logarithm.
710  unsigned getByValTypeAlignment(Type *Ty,
711  const DataLayout &DL) const override;
712 
713  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
714  /// vector. If it is invalid, don't add anything to Ops.
715  void LowerAsmOperandForConstraint(SDValue Op,
716  std::string &Constraint,
717  std::vector<SDValue> &Ops,
718  SelectionDAG &DAG) const override;
719 
720  unsigned
721  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
722  if (ConstraintCode == "es")
724  else if (ConstraintCode == "o")
726  else if (ConstraintCode == "Q")
728  else if (ConstraintCode == "Z")
730  else if (ConstraintCode == "Zy")
732  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
733  }
734 
735  /// isLegalAddressingMode - Return true if the addressing mode represented
736  /// by AM is legal for this target, for a load/store of the specified type.
737  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
738  Type *Ty, unsigned AS,
739  Instruction *I = nullptr) const override;
740 
741  /// isLegalICmpImmediate - Return true if the specified immediate is legal
742  /// icmp immediate, that is the target has icmp instructions which can
743  /// compare a register against the immediate without having to materialize
744  /// the immediate into a register.
745  bool isLegalICmpImmediate(int64_t Imm) const override;
746 
747  /// isLegalAddImmediate - Return true if the specified immediate is legal
748  /// add immediate, that is the target has add instructions which can
749  /// add a register and the immediate without having to materialize
750  /// the immediate into a register.
751  bool isLegalAddImmediate(int64_t Imm) const override;
752 
753  /// isTruncateFree - Return true if it's free to truncate a value of
754  /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
755  /// register X1 to i32 by referencing its sub-register R1.
756  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
757  bool isTruncateFree(EVT VT1, EVT VT2) const override;
758 
759  bool isZExtFree(SDValue Val, EVT VT2) const override;
760 
761  bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
762 
763  /// \brief Returns true if it is beneficial to convert a load of a constant
764  /// to just the constant itself.
765  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
766  Type *Ty) const override;
767 
768  bool convertSelectOfConstantsToMath(EVT VT) const override {
769  return true;
770  }
771 
772  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
773 
774  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
775  const CallInst &I,
776  unsigned Intrinsic) const override;
777 
778  /// getOptimalMemOpType - Returns the target specific optimal type for load
779  /// and store operations as a result of memset, memcpy, and memmove
780  /// lowering. If DstAlign is zero that means it's safe to destination
781  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
782  /// means there isn't a need to check it against alignment requirement,
783  /// probably because the source does not need to be loaded. If 'IsMemset' is
784  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
785  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
786  /// source is constant so it does not need to be loaded.
787  /// It returns EVT::Other if the type should be determined using generic
788  /// target-independent logic.
789  EVT
790  getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
791  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
792  MachineFunction &MF) const override;
793 
794  /// Is unaligned memory access allowed for the given type, and is it fast
795  /// relative to software emulation.
796  bool allowsMisalignedMemoryAccesses(EVT VT,
797  unsigned AddrSpace,
798  unsigned Align = 1,
799  bool *Fast = nullptr) const override;
800 
801  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
802  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
803  /// expanded to FMAs when this method returns true, otherwise fmuladd is
804  /// expanded to fmul + fadd.
805  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
806 
807  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
808 
809  // Should we expand the build vector with shuffles?
810  bool
811  shouldExpandBuildVectorWithShuffles(EVT VT,
812  unsigned DefinedValues) const override;
813 
814  /// createFastISel - This method returns a target-specific FastISel object,
815  /// or null if the target does not support "fast" instruction selection.
817  const TargetLibraryInfo *LibInfo) const override;
818 
819  /// \brief Returns true if an argument of type Ty needs to be passed in a
820  /// contiguous block of registers in calling convention CallConv.
822  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
823  // We support any array type as "consecutive" block in the parameter
824  // save area. The element type defines the alignment requirement and
825  // whether the argument should go in GPRs, FPRs, or VRs if available.
826  //
827  // Note that clang uses this capability both to implement the ELFv2
828  // homogeneous float/vector aggregate ABI, and to avoid having to use
829  // "byval" when passing aggregates that might fully fit in registers.
830  return Ty->isArrayTy();
831  }
832 
833  /// If a physical register, this returns the register that receives the
834  /// exception address on entry to an EH pad.
835  unsigned
836  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
837 
838  /// If a physical register, this returns the register that receives the
839  /// exception typeid on entry to a landing pad.
840  unsigned
841  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
842 
843  /// Override to support customized stack guard loading.
844  bool useLoadStackGuardNode() const override;
845  void insertSSPDeclarations(Module &M) const override;
846 
847  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
848 
849  unsigned getJumpTableEncoding() const override;
850  bool isJumpTableRelative() const override;
851  SDValue getPICJumpTableRelocBase(SDValue Table,
852  SelectionDAG &DAG) const override;
853  const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
854  unsigned JTI,
855  MCContext &Ctx) const override;
856 
857  private:
858  struct ReuseLoadInfo {
859  SDValue Ptr;
860  SDValue Chain;
861  SDValue ResChain;
862  MachinePointerInfo MPI;
863  bool IsDereferenceable = false;
864  bool IsInvariant = false;
865  unsigned Alignment = 0;
866  AAMDNodes AAInfo;
867  const MDNode *Ranges = nullptr;
868 
869  ReuseLoadInfo() = default;
870 
871  MachineMemOperand::Flags MMOFlags() const {
873  if (IsDereferenceable)
875  if (IsInvariant)
877  return F;
878  }
879  };
880 
881  bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
882  SelectionDAG &DAG,
884  void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
885  SelectionDAG &DAG) const;
886 
887  void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
888  SelectionDAG &DAG, const SDLoc &dl) const;
889  SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
890  const SDLoc &dl) const;
891 
892  bool directMoveIsProfitable(const SDValue &Op) const;
893  SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
894  const SDLoc &dl) const;
895 
896  SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
897  SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
898 
899  bool
900  IsEligibleForTailCallOptimization(SDValue Callee,
901  CallingConv::ID CalleeCC,
902  bool isVarArg,
904  SelectionDAG& DAG) const;
905 
906  bool
907  IsEligibleForTailCallOptimization_64SVR4(
908  SDValue Callee,
909  CallingConv::ID CalleeCC,
911  bool isVarArg,
914  SelectionDAG& DAG) const;
915 
916  SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
917  SDValue Chain, SDValue &LROpOut,
918  SDValue &FPOpOut,
919  const SDLoc &dl) const;
920 
922  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
923  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
924  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
925  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
926  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
927  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
928  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
929  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
931  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
932  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
933  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
934  SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
935  SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
937  SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
938  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
939  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
940  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
941  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
942  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
943  const SDLoc &dl) const;
944  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
945  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
946  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
947  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
948  SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
949  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
953  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
954  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
955  SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
956  SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
958  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
959  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
960 
961  SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
962  SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
963 
964  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
965  CallingConv::ID CallConv, bool isVarArg,
967  const SDLoc &dl, SelectionDAG &DAG,
968  SmallVectorImpl<SDValue> &InVals) const;
969  SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
970  bool isTailCall, bool isVarArg, bool isPatchPoint,
971  bool hasNest, SelectionDAG &DAG,
972  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
973  SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
974  SDValue &Callee, int SPDiff, unsigned NumBytes,
976  SmallVectorImpl<SDValue> &InVals,
977  ImmutableCallSite CS) const;
978 
979  SDValue
980  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
982  const SDLoc &dl, SelectionDAG &DAG,
983  SmallVectorImpl<SDValue> &InVals) const override;
984 
986  SmallVectorImpl<SDValue> &InVals) const override;
987 
988  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
989  bool isVarArg,
991  LLVMContext &Context) const override;
992 
993  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
995  const SmallVectorImpl<SDValue> &OutVals,
996  const SDLoc &dl, SelectionDAG &DAG) const override;
997 
998  SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
999  SelectionDAG &DAG, SDValue ArgVal,
1000  const SDLoc &dl) const;
1001 
1002  SDValue LowerFormalArguments_Darwin(
1003  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1004  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1005  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1006  SDValue LowerFormalArguments_64SVR4(
1007  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1008  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1009  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1010  SDValue LowerFormalArguments_32SVR4(
1011  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1012  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1013  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1014 
1015  SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1016  SDValue CallSeqStart,
1017  ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1018  const SDLoc &dl) const;
1019 
1020  SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1021  CallingConv::ID CallConv, bool isVarArg,
1022  bool isTailCall, bool isPatchPoint,
1023  const SmallVectorImpl<ISD::OutputArg> &Outs,
1024  const SmallVectorImpl<SDValue> &OutVals,
1025  const SmallVectorImpl<ISD::InputArg> &Ins,
1026  const SDLoc &dl, SelectionDAG &DAG,
1027  SmallVectorImpl<SDValue> &InVals,
1028  ImmutableCallSite CS) const;
1029  SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1030  CallingConv::ID CallConv, bool isVarArg,
1031  bool isTailCall, bool isPatchPoint,
1032  const SmallVectorImpl<ISD::OutputArg> &Outs,
1033  const SmallVectorImpl<SDValue> &OutVals,
1034  const SmallVectorImpl<ISD::InputArg> &Ins,
1035  const SDLoc &dl, SelectionDAG &DAG,
1036  SmallVectorImpl<SDValue> &InVals,
1037  ImmutableCallSite CS) const;
1038  SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1039  CallingConv::ID CallConv, bool isVarArg,
1040  bool isTailCall, bool isPatchPoint,
1041  const SmallVectorImpl<ISD::OutputArg> &Outs,
1042  const SmallVectorImpl<SDValue> &OutVals,
1043  const SmallVectorImpl<ISD::InputArg> &Ins,
1044  const SDLoc &dl, SelectionDAG &DAG,
1045  SmallVectorImpl<SDValue> &InVals,
1046  ImmutableCallSite CS) const;
1047 
1048  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1049  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1050 
1051  SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1052  SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1053  SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1054  SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1055  SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1056  SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1057  SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1058 
1059  /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1060  /// SETCC with integer subtraction when (1) there is a legal way of doing it
1061  /// (2) keeping the result of comparison in GPR has performance benefit.
1062  SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1063 
1064  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1065  int &RefinementSteps, bool &UseOneConstNR,
1066  bool Reciprocal) const override;
1067  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1068  int &RefinementSteps) const override;
1069  unsigned combineRepeatedFPDivisors() const override;
1070 
1071  CCAssignFn *useFastISelCCs(unsigned Flag) const;
1072 
1073  SDValue
1074  combineElementTruncationToVectorTruncation(SDNode *N,
1075  DAGCombinerInfo &DCI) const;
1076 
1077  /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1078  /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1079  /// essentially any shuffle of v8i16 vectors that just inserts one element
1080  /// from one vector into the other.
1081  SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1082 
1083  /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1084  /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1085  /// essentially v16i8 vector version of VINSERTH.
1086  SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1087 
1088  // Return whether the call instruction can potentially be optimized to a
1089  // tail call. This will cause the optimizers to attempt to move, or
1090  // duplicate return instructions to help enable tail call optimizations.
1091  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1092  }; // end class PPCTargetLowering
1093 
1094  namespace PPC {
1095 
1097  const TargetLibraryInfo *LibInfo);
1098 
1099  } // end namespace PPC
1100 
1101  bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1102  CCValAssign::LocInfo &LocInfo,
1103  ISD::ArgFlagsTy &ArgFlags,
1104  CCState &State);
1105 
1106  bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1107  MVT &LocVT,
1108  CCValAssign::LocInfo &LocInfo,
1109  ISD::ArgFlagsTy &ArgFlags,
1110  CCState &State);
1111 
1112  bool
1113  CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
1114  MVT &LocVT,
1115  CCValAssign::LocInfo &LocInfo,
1116  ISD::ArgFlagsTy &ArgFlags,
1117  CCState &State);
1118 
1119  bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1120  MVT &LocVT,
1121  CCValAssign::LocInfo &LocInfo,
1122  ISD::ArgFlagsTy &ArgFlags,
1123  CCState &State);
1124 
1125  bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1126  bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1127 
1128 } // end namespace llvm
1129 
1130 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Return with a flag operand, matched by &#39;blr&#39;.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
LLVMContext & Context
QVFPERM = This corresponds to the QPX qvfperm instruction.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
GPRC = address of GLOBAL_OFFSET_TABLE.
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:146
This class represents a function call, abstracting a target machine&#39;s calling convention.
This file contains the declarations for metadata subclasses.
QBRC, CHAIN = QVLFSb CHAIN, Ptr The 4xf32 load used for v4i1 constants.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction...
Function Alias Analysis Results
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
Metadata node.
Definition: Metadata.h:862
F(f)
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
CALL - A direct function call.
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The memory access is dereferenceable (i.e., doesn&#39;t trap).
static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)
Direct move from a GPR to a VSX register (algebraic)
X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
QVALIGNI = This corresponds to the QPX qvaligni instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
Context object for machine code objects.
Definition: MCContext.h:59
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
G8RC = ADDIS_TLSGD_HA X2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
This contains information for each constraint that we are lowering.
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
amdgpu Simplify well known AMD library false Value * Callee
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
FSEL - Traditional three-operand fsel node.
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
static Value * LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP)
LowerBSWAP - Emit the code to lower bswap of V before the specified instruction IP.
This is an important base class in LLVM.
Definition: Constant.h:42
G8RC = ADDIS_DTPREL_HA X3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
SExtVElems, takes an input vector of a smaller type and sign extends to an output vector of a larger ...
VECINSERT - The PPC vector insert instruction.
Direct move from a VSX register to a GPR.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:891
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask...
STFIWX - The STFIWX instruction.
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
G8RC = ADDIS_TLSLD_HA X2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
QVESPLATI = This corresponds to the QPX qvesplati instruction.
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Common code between 32-bit and 64-bit PowerPC targets.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
Extract a subvector from unsigned integer vector and convert to FP.
QBFLT = Access the underlying QPX floating-point boolean representation.
CCState - This class holds information needed while lowering arguments and return values...
X3 = GET_TLSLD_ADDR X3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
XXSPLT - The PPC VSX splat instructions.
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
VECSHL - The PPC vector shift left instruction.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Provides information about what library functions are available for the current target.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
CHAIN = SC CHAIN, Imm128 - System call.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
X3 = GET_TLS_ADDR X3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
VPERM - The PPC VPERM Instruction.
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction...
static bool Enabled
Definition: Statistic.cpp:49
STXSIX - The STXSI[bh]X instruction.
i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after execu...
G8RC = ADDIS_GOT_TPREL_HA X2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Class for arbitrary precision integers.
Definition: APInt.h:69
QVGPCI = This corresponds to the QPX qvgpci instruction.
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2...
Flags
Flags values. These may be or&#39;d together.
amdgpu Simplify well known AMD library false Value Value * Arg
GPRC = address of GLOBAL_OFFSET_TABLE.
Representation of each machine instruction.
Definition: MachineInstr.h:59
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Reciprocal estimate instructions (unary FP ops).
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Establish a view to a call site for examination.
Definition: CallSite.h:713
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Direct move from a GPR to a VSX register (zero)
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
The CMPB instruction (takes two operands of i32 or i64).
The memory access always returns the same value (or traps).
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction. ...
TC_RETURN - A tail call return.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
XXREVERSE - The PPC VSX reverse instruction.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
These nodes represent PPC shifts.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Extract a subvector from signed integer vector and convert to FP.
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain...
RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate...
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
XXPERMDI - The PPC XXPERMDI instruction.
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:218
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871
int isQVALIGNIShuffleMask(SDNode *N)
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. ...