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PPCInstPrinter.cpp
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1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstPrinter.h"
17 #include "PPCInstrInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSymbol.h"
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "asm-printer"
30 
31 // FIXME: Once the integrated assembler supports full register names, tie this
32 // to the verbose-asm setting.
33 static cl::opt<bool>
34 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
35  cl::desc("Use full register names when printing assembly"));
36 
37 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
38 static cl::opt<bool>
39 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
40  cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
41 
42 #define PRINT_ALIAS_INSTR
43 #include "PPCGenAsmWriter.inc"
44 
45 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
46  const char *RegName = getRegisterName(RegNo);
47  if (RegName[0] == 'q' /* QPX */) {
48  // The system toolchain on the BG/Q does not understand QPX register names
49  // in .cfi_* directives, so print the name of the floating-point
50  // subregister instead.
51  std::string RN(RegName);
52 
53  RN[0] = 'f';
54  OS << RN;
55 
56  return;
57  }
58 
59  OS << RegName;
60 }
61 
63  StringRef Annot, const MCSubtargetInfo &STI) {
64  // Check for slwi/srwi mnemonics.
65  if (MI->getOpcode() == PPC::RLWINM) {
66  unsigned char SH = MI->getOperand(2).getImm();
67  unsigned char MB = MI->getOperand(3).getImm();
68  unsigned char ME = MI->getOperand(4).getImm();
69  bool useSubstituteMnemonic = false;
70  if (SH <= 31 && MB == 0 && ME == (31-SH)) {
71  O << "\tslwi "; useSubstituteMnemonic = true;
72  }
73  if (SH <= 31 && MB == (32-SH) && ME == 31) {
74  O << "\tsrwi "; useSubstituteMnemonic = true;
75  SH = 32-SH;
76  }
77  if (useSubstituteMnemonic) {
78  printOperand(MI, 0, O);
79  O << ", ";
80  printOperand(MI, 1, O);
81  O << ", " << (unsigned int)SH;
82 
83  printAnnotation(O, Annot);
84  return;
85  }
86  }
87 
88  if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
89  MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
90  O << "\tmr ";
91  printOperand(MI, 0, O);
92  O << ", ";
93  printOperand(MI, 1, O);
94  printAnnotation(O, Annot);
95  return;
96  }
97 
98  if (MI->getOpcode() == PPC::RLDICR ||
99  MI->getOpcode() == PPC::RLDICR_32) {
100  unsigned char SH = MI->getOperand(2).getImm();
101  unsigned char ME = MI->getOperand(3).getImm();
102  // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
103  if (63-SH == ME) {
104  O << "\tsldi ";
105  printOperand(MI, 0, O);
106  O << ", ";
107  printOperand(MI, 1, O);
108  O << ", " << (unsigned int)SH;
109  printAnnotation(O, Annot);
110  return;
111  }
112  }
113 
114  // dcbt[st] is printed manually here because:
115  // 1. The assembly syntax is different between embedded and server targets
116  // 2. We must print the short mnemonics for TH == 0 because the
117  // embedded/server syntax default will not be stable across assemblers
118  // The syntax for dcbt is:
119  // dcbt ra, rb, th [server]
120  // dcbt th, ra, rb [embedded]
121  // where th can be omitted when it is 0. dcbtst is the same.
122  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
123  unsigned char TH = MI->getOperand(0).getImm();
124  O << "\tdcbt";
125  if (MI->getOpcode() == PPC::DCBTST)
126  O << "st";
127  if (TH == 16)
128  O << "t";
129  O << " ";
130 
131  bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
132  if (IsBookE && TH != 0 && TH != 16)
133  O << (unsigned int) TH << ", ";
134 
135  printOperand(MI, 1, O);
136  O << ", ";
137  printOperand(MI, 2, O);
138 
139  if (!IsBookE && TH != 0 && TH != 16)
140  O << ", " << (unsigned int) TH;
141 
142  printAnnotation(O, Annot);
143  return;
144  }
145 
146  if (MI->getOpcode() == PPC::DCBF) {
147  unsigned char L = MI->getOperand(0).getImm();
148  if (!L || L == 1 || L == 3) {
149  O << "\tdcbf";
150  if (L == 1 || L == 3)
151  O << "l";
152  if (L == 3)
153  O << "p";
154  O << " ";
155 
156  printOperand(MI, 1, O);
157  O << ", ";
158  printOperand(MI, 2, O);
159 
160  printAnnotation(O, Annot);
161  return;
162  }
163  }
164 
165  if (!printAliasInstr(MI, O))
166  printInstruction(MI, O);
167  printAnnotation(O, Annot);
168 }
169 
170 
172  raw_ostream &O,
173  const char *Modifier) {
174  unsigned Code = MI->getOperand(OpNo).getImm();
175 
176  if (StringRef(Modifier) == "cc") {
177  switch ((PPC::Predicate)Code) {
178  case PPC::PRED_LT_MINUS:
179  case PPC::PRED_LT_PLUS:
180  case PPC::PRED_LT:
181  O << "lt";
182  return;
183  case PPC::PRED_LE_MINUS:
184  case PPC::PRED_LE_PLUS:
185  case PPC::PRED_LE:
186  O << "le";
187  return;
188  case PPC::PRED_EQ_MINUS:
189  case PPC::PRED_EQ_PLUS:
190  case PPC::PRED_EQ:
191  O << "eq";
192  return;
193  case PPC::PRED_GE_MINUS:
194  case PPC::PRED_GE_PLUS:
195  case PPC::PRED_GE:
196  O << "ge";
197  return;
198  case PPC::PRED_GT_MINUS:
199  case PPC::PRED_GT_PLUS:
200  case PPC::PRED_GT:
201  O << "gt";
202  return;
203  case PPC::PRED_NE_MINUS:
204  case PPC::PRED_NE_PLUS:
205  case PPC::PRED_NE:
206  O << "ne";
207  return;
208  case PPC::PRED_UN_MINUS:
209  case PPC::PRED_UN_PLUS:
210  case PPC::PRED_UN:
211  O << "un";
212  return;
213  case PPC::PRED_NU_MINUS:
214  case PPC::PRED_NU_PLUS:
215  case PPC::PRED_NU:
216  O << "nu";
217  return;
218  case PPC::PRED_BIT_SET:
219  case PPC::PRED_BIT_UNSET:
220  llvm_unreachable("Invalid use of bit predicate code");
221  }
222  llvm_unreachable("Invalid predicate code");
223  }
224 
225  if (StringRef(Modifier) == "pm") {
226  switch ((PPC::Predicate)Code) {
227  case PPC::PRED_LT:
228  case PPC::PRED_LE:
229  case PPC::PRED_EQ:
230  case PPC::PRED_GE:
231  case PPC::PRED_GT:
232  case PPC::PRED_NE:
233  case PPC::PRED_UN:
234  case PPC::PRED_NU:
235  return;
236  case PPC::PRED_LT_MINUS:
237  case PPC::PRED_LE_MINUS:
238  case PPC::PRED_EQ_MINUS:
239  case PPC::PRED_GE_MINUS:
240  case PPC::PRED_GT_MINUS:
241  case PPC::PRED_NE_MINUS:
242  case PPC::PRED_UN_MINUS:
243  case PPC::PRED_NU_MINUS:
244  O << "-";
245  return;
246  case PPC::PRED_LT_PLUS:
247  case PPC::PRED_LE_PLUS:
248  case PPC::PRED_EQ_PLUS:
249  case PPC::PRED_GE_PLUS:
250  case PPC::PRED_GT_PLUS:
251  case PPC::PRED_NE_PLUS:
252  case PPC::PRED_UN_PLUS:
253  case PPC::PRED_NU_PLUS:
254  O << "+";
255  return;
256  case PPC::PRED_BIT_SET:
257  case PPC::PRED_BIT_UNSET:
258  llvm_unreachable("Invalid use of bit predicate code");
259  }
260  llvm_unreachable("Invalid predicate code");
261  }
262 
263  assert(StringRef(Modifier) == "reg" &&
264  "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
265  printOperand(MI, OpNo+1, O);
266 }
267 
268 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
269  raw_ostream &O) {
270  unsigned Code = MI->getOperand(OpNo).getImm();
271  if (Code == 2)
272  O << "-";
273  else if (Code == 3)
274  O << "+";
275 }
276 
277 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
278  raw_ostream &O) {
279  unsigned int Value = MI->getOperand(OpNo).getImm();
280  assert(Value <= 1 && "Invalid u1imm argument!");
281  O << (unsigned int)Value;
282 }
283 
284 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
285  raw_ostream &O) {
286  unsigned int Value = MI->getOperand(OpNo).getImm();
287  assert(Value <= 3 && "Invalid u2imm argument!");
288  O << (unsigned int)Value;
289 }
290 
291 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
292  raw_ostream &O) {
293  unsigned int Value = MI->getOperand(OpNo).getImm();
294  assert(Value <= 8 && "Invalid u3imm argument!");
295  O << (unsigned int)Value;
296 }
297 
298 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
299  raw_ostream &O) {
300  unsigned int Value = MI->getOperand(OpNo).getImm();
301  assert(Value <= 15 && "Invalid u4imm argument!");
302  O << (unsigned int)Value;
303 }
304 
305 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
306  raw_ostream &O) {
307  int Value = MI->getOperand(OpNo).getImm();
308  Value = SignExtend32<5>(Value);
309  O << (int)Value;
310 }
311 
312 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
313  raw_ostream &O) {
314  unsigned int Value = MI->getOperand(OpNo).getImm();
315  assert(Value <= 31 && "Invalid u5imm argument!");
316  O << (unsigned int)Value;
317 }
318 
319 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
320  raw_ostream &O) {
321  unsigned int Value = MI->getOperand(OpNo).getImm();
322  assert(Value <= 63 && "Invalid u6imm argument!");
323  O << (unsigned int)Value;
324 }
325 
326 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
327  raw_ostream &O) {
328  unsigned int Value = MI->getOperand(OpNo).getImm();
329  assert(Value <= 127 && "Invalid u7imm argument!");
330  O << (unsigned int)Value;
331 }
332 
333 // Operands of BUILD_VECTOR are signed and we use this to print operands
334 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
335 // print as unsigned.
336 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
337  raw_ostream &O) {
338  unsigned char Value = MI->getOperand(OpNo).getImm();
339  O << (unsigned int)Value;
340 }
341 
342 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
343  raw_ostream &O) {
344  unsigned short Value = MI->getOperand(OpNo).getImm();
345  assert(Value <= 1023 && "Invalid u10imm argument!");
346  O << (unsigned short)Value;
347 }
348 
349 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
350  raw_ostream &O) {
351  unsigned short Value = MI->getOperand(OpNo).getImm();
352  assert(Value <= 4095 && "Invalid u12imm argument!");
353  O << (unsigned short)Value;
354 }
355 
356 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
357  raw_ostream &O) {
358  if (MI->getOperand(OpNo).isImm())
359  O << (short)MI->getOperand(OpNo).getImm();
360  else
361  printOperand(MI, OpNo, O);
362 }
363 
364 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
365  raw_ostream &O) {
366  if (MI->getOperand(OpNo).isImm())
367  O << (unsigned short)MI->getOperand(OpNo).getImm();
368  else
369  printOperand(MI, OpNo, O);
370 }
371 
372 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
373  raw_ostream &O) {
374  if (!MI->getOperand(OpNo).isImm())
375  return printOperand(MI, OpNo, O);
376 
377  // Branches can take an immediate operand. This is used by the branch
378  // selection pass to print .+8, an eight byte displacement from the PC.
379  O << ".+";
380  printAbsBranchOperand(MI, OpNo, O);
381 }
382 
384  raw_ostream &O) {
385  if (!MI->getOperand(OpNo).isImm())
386  return printOperand(MI, OpNo, O);
387 
388  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
389 }
390 
391 
392 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
393  raw_ostream &O) {
394  unsigned CCReg = MI->getOperand(OpNo).getReg();
395  unsigned RegNo;
396  switch (CCReg) {
397  default: llvm_unreachable("Unknown CR register");
398  case PPC::CR0: RegNo = 0; break;
399  case PPC::CR1: RegNo = 1; break;
400  case PPC::CR2: RegNo = 2; break;
401  case PPC::CR3: RegNo = 3; break;
402  case PPC::CR4: RegNo = 4; break;
403  case PPC::CR5: RegNo = 5; break;
404  case PPC::CR6: RegNo = 6; break;
405  case PPC::CR7: RegNo = 7; break;
406  }
407  O << (0x80 >> RegNo);
408 }
409 
410 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
411  raw_ostream &O) {
412  printS16ImmOperand(MI, OpNo, O);
413  O << '(';
414  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
415  O << "0";
416  else
417  printOperand(MI, OpNo+1, O);
418  O << ')';
419 }
420 
421 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
422  raw_ostream &O) {
423  // When used as the base register, r0 reads constant zero rather than
424  // the value contained in the register. For this reason, the darwin
425  // assembler requires that we print r0 as 0 (no r) when used as the base.
426  if (MI->getOperand(OpNo).getReg() == PPC::R0)
427  O << "0";
428  else
429  printOperand(MI, OpNo, O);
430  O << ", ";
431  printOperand(MI, OpNo+1, O);
432 }
433 
434 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
435  raw_ostream &O) {
436  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
437  // come at the _end_ of the expression.
438  const MCOperand &Op = MI->getOperand(OpNo);
439  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
440  O << refExp.getSymbol().getName();
441  O << '(';
442  printOperand(MI, OpNo+1, O);
443  O << ')';
444  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
445  O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
446 }
447 
448 
449 /// stripRegisterPrefix - This method strips the character prefix from a
450 /// register name so that only the number is left. Used by for linux asm.
451 static const char *stripRegisterPrefix(const char *RegName) {
453  return RegName;
454 
455  switch (RegName[0]) {
456  case 'r':
457  case 'f':
458  case 'q': // for QPX
459  case 'v':
460  if (RegName[1] == 's')
461  return RegName + 2;
462  return RegName + 1;
463  case 'c': if (RegName[1] == 'r') return RegName + 2;
464  }
465 
466  return RegName;
467 }
468 
469 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
470  raw_ostream &O) {
471  const MCOperand &Op = MI->getOperand(OpNo);
472  if (Op.isReg()) {
473  unsigned Reg = Op.getReg();
474 
475  // There are VSX instructions that use VSX register numbering (vs0 - vs63)
476  // as well as those that use VMX register numbering (v0 - v31 which
477  // correspond to vs32 - vs63). If we have an instruction that uses VSX
478  // numbering, we need to convert the VMX registers to VSX registers.
479  // Namely, we print 32-63 when the instruction operates on one of the
480  // VMX registers.
481  // (Please synchronize with PPCAsmPrinter::printOperand)
482  if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
483  !ShowVSRNumsAsVR) {
485  Reg = PPC::VSX32 + (Reg - PPC::V0);
486  else if (PPCInstrInfo::isVFRegister(Reg))
487  Reg = PPC::VSX32 + (Reg - PPC::VF0);
488  }
489 
490  const char *RegName = getRegisterName(Reg);
491  // The linux and AIX assembler does not take register prefixes.
492  if (!isDarwinSyntax())
493  RegName = stripRegisterPrefix(RegName);
494 
495  O << RegName;
496  return;
497  }
498 
499  if (Op.isImm()) {
500  O << Op.getImm();
501  return;
502  }
503 
504  assert(Op.isExpr() && "unknown operand kind in printOperand");
505  Op.getExpr()->print(O, &MAI);
506 }
507 
bool isImm() const
Definition: MCInst.h:59
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
VariantKind getKind() const
Definition: MCExpr.h:320
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
bool isReg() const
Definition: MCInst.h:58
void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:291
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:96
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
int64_t getImm() const
Definition: MCInst.h:76
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:404
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
static const char * getRegisterName(unsigned RegNo)
bool isExpr() const
Definition: MCInst.h:61
void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier=nullptr)
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
const MCSymbol & getSymbol() const
Definition: MCExpr.h:318
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:173
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:288
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, raw_ostream &OS)
void printInstruction(const MCInst *MI, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
bool isDarwinSyntax() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
MCSubtargetInfo - Generic base class for all target subtargets.
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
LLVM Value Representation.
Definition: Value.h:73
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
Definition: PPCInstrInfo.h:71
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getOpcode() const
Definition: MCInst.h:168
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static StringRef getVariantKindName(VariantKind Kind)
Definition: MCExpr.cpp:185
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)