LLVM  8.0.0svn
PPCInstrInfo.h
Go to the documentation of this file.
1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
16 
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
29 namespace PPCII {
30 enum {
31  // PPC970 Instruction Flags. These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34 
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38 
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
42 
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
46 
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
51 };
53  /// These are the various PPC970 execution unit pipelines. Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
63 };
64 
65 enum {
66  /// Shift count to bypass PPC970 flags
68 
69  /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
70  /// register (v0-v31).
72  /// This instruction is an X-Form memory operation.
73  XFormMemOp = 0x1 << (NewDef_Shift+1)
74 };
75 } // end namespace PPCII
76 
77 // Instructions that have an immediate form might be convertible to that
78 // form if the correct input is a result of a load immediate. In order to
79 // know whether the transformation is special, we might need to know some
80 // of the details of the two forms.
81 struct ImmInstrInfo {
82  // Is the immediate field in the immediate form signed or unsigned?
83  uint64_t SignedImm : 1;
84  // Does the immediate need to be a multiple of some value?
85  uint64_t ImmMustBeMultipleOf : 5;
86  // Is R0/X0 treated specially by the original r+r instruction?
87  // If so, in which operand?
88  uint64_t ZeroIsSpecialOrig : 3;
89  // Is R0/X0 treated specially by the new r+i instruction?
90  // If so, in which operand?
91  uint64_t ZeroIsSpecialNew : 3;
92  // Is the operation commutative?
93  uint64_t IsCommutative : 1;
94  // The operand number to check for add-immediate def.
95  uint64_t OpNoForForwarding : 3;
96  // The operand number for the immediate.
97  uint64_t ImmOpNo : 3;
98  // The opcode of the new instruction.
99  uint64_t ImmOpcode : 16;
100  // The size of the immediate.
101  uint64_t ImmWidth : 5;
102  // The immediate should be truncated to N bits.
103  uint64_t TruncateImmTo : 5;
104  // Is the instruction summing the operand
105  uint64_t IsSummingOperands : 1;
106 };
107 
108 // Information required to convert an instruction to just a materialized
109 // immediate.
111  unsigned Imm : 16;
112  unsigned Is64Bit : 1;
113  unsigned SetCR : 1;
114 };
115 
116 class PPCSubtarget;
118  PPCSubtarget &Subtarget;
119  const PPCRegisterInfo RI;
120 
121  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
122  int FrameIdx, const TargetRegisterClass *RC,
123  SmallVectorImpl<MachineInstr *> &NewMIs) const;
124  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
125  unsigned DestReg, int FrameIdx,
126  const TargetRegisterClass *RC,
127  SmallVectorImpl<MachineInstr *> &NewMIs) const;
128 
129  // If the inst has imm-form and one of its operand is produced by a LI,
130  // put the imm into the inst directly and remove the LI if possible.
131  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
132  unsigned ConstantOpNo, int64_t Imm) const;
133  // If the inst has imm-form and one of its operand is produced by an
134  // add-immediate, try to transform it when possible.
135  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
136  unsigned ConstantOpNo,
138  bool KillDefMI) const;
139  // Try to find that, if the instruction 'MI' contains any operand that
140  // could be forwarded from some inst that feeds it. If yes, return the
141  // Def of that operand. And OpNoForForwarding is the operand index in
142  // the 'MI' for that 'Def'. If we see another use of this Def between
143  // the Def and the MI, SeenIntermediateUse becomes 'true'.
144  MachineInstr *getForwardingDefMI(MachineInstr &MI,
145  unsigned &OpNoForForwarding,
146  bool &SeenIntermediateUse) const;
147 
148  // Can the user MI have it's source at index \p OpNoForForwarding
149  // forwarded from an add-immediate that feeds it?
150  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
151  unsigned OpNoForForwarding) const;
152  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
153  const ImmInstrInfo &III,
154  MachineOperand *&ImmMO,
155  MachineOperand *&RegMO) const;
156  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
157  const MachineInstr &DefMI,
158  const ImmInstrInfo &III,
159  int64_t &Imm) const;
160  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
161  const MachineInstr &DefMI,
162  const MachineInstr &MI,
163  bool KillDefMI) const;
164  const unsigned *getStoreOpcodesForSpillArray() const;
165  const unsigned *getLoadOpcodesForSpillArray() const;
166  virtual void anchor();
167 
168 protected:
169  /// Commutes the operands in the given instruction.
170  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
171  ///
172  /// Do not call this method for a non-commutable instruction or for
173  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
174  /// Even though the instruction is commutable, the method may still
175  /// fail to commute the operands, null pointer is returned in such cases.
176  ///
177  /// For example, we can commute rlwimi instructions, but only if the
178  /// rotate amt is zero. We also have to munge the immediates a bit.
179  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
180  unsigned OpIdx1,
181  unsigned OpIdx2) const override;
182 
183 public:
184  explicit PPCInstrInfo(PPCSubtarget &STI);
185 
186  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
187  /// such, whenever a client has an instance of instruction info, it should
188  /// always be able to get register info as well (through this method).
189  ///
190  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
191 
192  bool isXFormMemOp(unsigned Opcode) const {
193  return get(Opcode).TSFlags & PPCII::XFormMemOp;
194  }
195  static bool isSameClassPhysRegCopy(unsigned Opcode) {
196  unsigned CopyOpcodes[] =
197  { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
198  PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
199  PPC::CROR, PPC::EVOR, -1U };
200  for (int i = 0; CopyOpcodes[i] != -1U; i++)
201  if (Opcode == CopyOpcodes[i])
202  return true;
203  return false;
204  }
205 
207  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
208  const ScheduleDAG *DAG) const override;
210  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
211  const ScheduleDAG *DAG) const override;
212 
213  unsigned getInstrLatency(const InstrItineraryData *ItinData,
214  const MachineInstr &MI,
215  unsigned *PredCost = nullptr) const override;
216 
217  int getOperandLatency(const InstrItineraryData *ItinData,
218  const MachineInstr &DefMI, unsigned DefIdx,
219  const MachineInstr &UseMI,
220  unsigned UseIdx) const override;
222  SDNode *DefNode, unsigned DefIdx,
223  SDNode *UseNode, unsigned UseIdx) const override {
224  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
225  UseNode, UseIdx);
226  }
227 
228  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
229  const MachineInstr &DefMI,
230  unsigned DefIdx) const override {
231  // Machine LICM should hoist all instructions in low-register-pressure
232  // situations; none are sufficiently free to justify leaving in a loop
233  // body.
234  return false;
235  }
236 
237  bool useMachineCombiner() const override {
238  return true;
239  }
240 
241  /// Return true when there is potentially a faster code sequence
242  /// for an instruction chain ending in <Root>. All potential patterns are
243  /// output in the <Pattern> array.
244  bool getMachineCombinerPatterns(
245  MachineInstr &Root,
247 
248  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
249 
250  bool isCoalescableExtInstr(const MachineInstr &MI,
251  unsigned &SrcReg, unsigned &DstReg,
252  unsigned &SubIdx) const override;
253  unsigned isLoadFromStackSlot(const MachineInstr &MI,
254  int &FrameIndex) const override;
255  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
256  AliasAnalysis *AA) const override;
257  unsigned isStoreToStackSlot(const MachineInstr &MI,
258  int &FrameIndex) const override;
259 
260  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
261  unsigned &SrcOpIdx2) const override;
262 
263  void insertNoop(MachineBasicBlock &MBB,
264  MachineBasicBlock::iterator MI) const override;
265 
266 
267  // Branch analysis.
268  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
269  MachineBasicBlock *&FBB,
271  bool AllowModify) const override;
272  unsigned removeBranch(MachineBasicBlock &MBB,
273  int *BytesRemoved = nullptr) const override;
274  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
276  const DebugLoc &DL,
277  int *BytesAdded = nullptr) const override;
278 
279  // Select analysis.
280  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
281  unsigned, unsigned, int &, int &, int &) const override;
282  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
283  const DebugLoc &DL, unsigned DstReg,
284  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
285  unsigned FalseReg) const override;
286 
287  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
288  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
289  bool KillSrc) const override;
290 
291  void storeRegToStackSlot(MachineBasicBlock &MBB,
293  unsigned SrcReg, bool isKill, int FrameIndex,
294  const TargetRegisterClass *RC,
295  const TargetRegisterInfo *TRI) const override;
296 
297  void loadRegFromStackSlot(MachineBasicBlock &MBB,
299  unsigned DestReg, int FrameIndex,
300  const TargetRegisterClass *RC,
301  const TargetRegisterInfo *TRI) const override;
302 
303  unsigned getStoreOpcodeForSpill(unsigned Reg,
304  const TargetRegisterClass *RC = nullptr) const;
305 
306  unsigned getLoadOpcodeForSpill(unsigned Reg,
307  const TargetRegisterClass *RC = nullptr) const;
308 
309  bool
310  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
311 
312  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
313  MachineRegisterInfo *MRI) const override;
314 
315  // If conversion by predication (only supported by some branch instructions).
316  // All of the profitability checks always return true; it is always
317  // profitable to use the predicated branches.
319  unsigned NumCycles, unsigned ExtraPredCycles,
320  BranchProbability Probability) const override {
321  return true;
322  }
323 
324  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
325  unsigned NumT, unsigned ExtraT,
326  MachineBasicBlock &FMBB,
327  unsigned NumF, unsigned ExtraF,
328  BranchProbability Probability) const override;
329 
330  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
331  BranchProbability Probability) const override {
332  return true;
333  }
334 
336  MachineBasicBlock &FMBB) const override {
337  return false;
338  }
339 
340  // Predication support.
341  bool isPredicated(const MachineInstr &MI) const override;
342 
343  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
344 
345  bool PredicateInstruction(MachineInstr &MI,
346  ArrayRef<MachineOperand> Pred) const override;
347 
348  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
349  ArrayRef<MachineOperand> Pred2) const override;
350 
351  bool DefinesPredicate(MachineInstr &MI,
352  std::vector<MachineOperand> &Pred) const override;
353 
354  bool isPredicable(const MachineInstr &MI) const override;
355 
356  // Comparison optimization.
357 
358  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
359  unsigned &SrcReg2, int &Mask, int &Value) const override;
360 
361  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
362  unsigned SrcReg2, int Mask, int Value,
363  const MachineRegisterInfo *MRI) const override;
364 
365  /// GetInstSize - Return the number of bytes of code the specified
366  /// instruction may be. This returns the maximum number of bytes.
367  ///
368  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
369 
370  void getNoop(MCInst &NopInst) const override;
371 
372  std::pair<unsigned, unsigned>
373  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
374 
376  getSerializableDirectMachineOperandTargetFlags() const override;
377 
379  getSerializableBitmaskMachineOperandTargetFlags() const override;
380 
381  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
382  bool expandVSXMemPseudo(MachineInstr &MI) const;
383 
384  // Lower pseudo instructions after register allocation.
385  bool expandPostRAPseudo(MachineInstr &MI) const override;
386 
387  static bool isVFRegister(unsigned Reg) {
388  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
389  }
390  static bool isVRRegister(unsigned Reg) {
391  return Reg >= PPC::V0 && Reg <= PPC::V31;
392  }
393  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
394  static int getRecordFormOpcode(unsigned Opcode);
395 
396  bool isTOCSaveMI(const MachineInstr &MI) const;
397 
398  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
399  const unsigned PhiDepth) const;
400 
401  /// Return true if the output of the instruction is always a sign-extended,
402  /// i.e. 0 to 31-th bits are same as 32-th bit.
403  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
404  return isSignOrZeroExtended(MI, true, depth);
405  }
406 
407  /// Return true if the output of the instruction is always zero-extended,
408  /// i.e. 0 to 31-th bits are all zeros
409  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
410  return isSignOrZeroExtended(MI, false, depth);
411  }
412 
413  bool convertToImmediateForm(MachineInstr &MI,
414  MachineInstr **KilledDef = nullptr) const;
415  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
416 
417  bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III) const;
418 
419  /// getRegNumForOperand - some operands use different numbering schemes
420  /// for the same registers. For example, a VSX instruction may have any of
421  /// vs0-vs63 allocated whereas an Altivec instruction could only have
422  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
423  /// register number needed for the opcode/operand number combination.
424  /// The operand number argument will be useful when we need to extend this
425  /// to instructions that use both Altivec and VSX numbering (for different
426  /// operands).
427  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
428  unsigned OpNo) {
429  if (Desc.TSFlags & PPCII::UseVSXReg) {
430  if (isVRRegister(Reg))
431  Reg = PPC::VSX32 + (Reg - PPC::V0);
432  else if (isVFRegister(Reg))
433  Reg = PPC::VSX32 + (Reg - PPC::VF0);
434  }
435  return Reg;
436  }
437 };
438 
439 }
440 
441 #endif
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:45
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:91
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:49
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:237
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
uint64_t IsCommutative
Definition: PPCInstrInfo.h:93
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:55
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:103
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:41
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:95
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:105
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:403
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:37
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:192
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:390
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:335
Provide an instruction scheduling machine model to CodeGen passes.
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:88
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
#define P(N)
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
Definition: PPCInstrInfo.h:71
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:73
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:195
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:330
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:427
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
Represents one node in the SelectionDAG.
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:387
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:228
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:64
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:221
#define I(x, y, z)
Definition: MD5.cpp:58
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:67
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:85
LLVM Value Representation.
Definition: Value.h:73
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:190
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:318
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:409