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PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPC.h"
17 #include "PPCRegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "PPCGenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 /// PPCII - This namespace holds all of the PowerPC target-specific
26 /// per-instruction flags. These must match the corresponding definitions in
27 /// PPC.td and PPCInstrFormats.td.
28 namespace PPCII {
29 enum {
30  // PPC970 Instruction Flags. These flags describe the characteristics of the
31  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
32  // raw machine instructions.
33 
34  /// PPC970_First - This instruction starts a new dispatch group, so it will
35  /// always be the first one in the group.
36  PPC970_First = 0x1,
37 
38  /// PPC970_Single - This instruction starts a new dispatch group and
39  /// terminates it, so it will be the sole instruction in the group.
41 
42  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
43  /// two dispatch pipes to be available to issue.
45 
46  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
47  /// an instruction is issued to.
50 };
52  /// These are the various PPC970 execution unit pipelines. Each instruction
53  /// is one of these.
54  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
55  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
56  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
57  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
58  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
59  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
60  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
61  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
62 };
63 
64 enum {
65  /// Shift count to bypass PPC970 flags
67 
68  /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
69  /// register (v0-v31).
71  /// This instruction is an X-Form memory operation.
72  XFormMemOp = 0x1 << (NewDef_Shift+1)
73 };
74 } // end namespace PPCII
75 
76 // Instructions that have an immediate form might be convertible to that
77 // form if the correct input is a result of a load immediate. In order to
78 // know whether the transformation is special, we might need to know some
79 // of the details of the two forms.
80 struct ImmInstrInfo {
81  // Is the immediate field in the immediate form signed or unsigned?
82  uint64_t SignedImm : 1;
83  // Does the immediate need to be a multiple of some value?
84  uint64_t ImmMustBeMultipleOf : 5;
85  // Is R0/X0 treated specially by the original r+r instruction?
86  // If so, in which operand?
87  uint64_t ZeroIsSpecialOrig : 3;
88  // Is R0/X0 treated specially by the new r+i instruction?
89  // If so, in which operand?
90  uint64_t ZeroIsSpecialNew : 3;
91  // Is the operation commutative?
92  uint64_t IsCommutative : 1;
93  // The operand number to check for add-immediate def.
94  uint64_t OpNoForForwarding : 3;
95  // The operand number for the immediate.
96  uint64_t ImmOpNo : 3;
97  // The opcode of the new instruction.
98  uint64_t ImmOpcode : 16;
99  // The size of the immediate.
100  uint64_t ImmWidth : 5;
101  // The immediate should be truncated to N bits.
102  uint64_t TruncateImmTo : 5;
103  // Is the instruction summing the operand
104  uint64_t IsSummingOperands : 1;
105 };
106 
107 // Information required to convert an instruction to just a materialized
108 // immediate.
110  unsigned Imm : 16;
111  unsigned Is64Bit : 1;
112  unsigned SetCR : 1;
113 };
114 
115 class PPCSubtarget;
117  PPCSubtarget &Subtarget;
118  const PPCRegisterInfo RI;
119 
120  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
121  int FrameIdx, const TargetRegisterClass *RC,
122  SmallVectorImpl<MachineInstr *> &NewMIs) const;
123  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
124  unsigned DestReg, int FrameIdx,
125  const TargetRegisterClass *RC,
126  SmallVectorImpl<MachineInstr *> &NewMIs) const;
127 
128  // If the inst has imm-form and one of its operand is produced by a LI,
129  // put the imm into the inst directly and remove the LI if possible.
130  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
131  unsigned ConstantOpNo, int64_t Imm) const;
132  // If the inst has imm-form and one of its operand is produced by an
133  // add-immediate, try to transform it when possible.
134  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
135  unsigned ConstantOpNo,
137  bool KillDefMI) const;
138  // Try to find that, if the instruction 'MI' contains any operand that
139  // could be forwarded from some inst that feeds it. If yes, return the
140  // Def of that operand. And OpNoForForwarding is the operand index in
141  // the 'MI' for that 'Def'. If we see another use of this Def between
142  // the Def and the MI, SeenIntermediateUse becomes 'true'.
143  MachineInstr *getForwardingDefMI(MachineInstr &MI,
144  unsigned &OpNoForForwarding,
145  bool &SeenIntermediateUse) const;
146 
147  // Can the user MI have it's source at index \p OpNoForForwarding
148  // forwarded from an add-immediate that feeds it?
149  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
150  unsigned OpNoForForwarding) const;
151  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
152  const ImmInstrInfo &III,
153  MachineOperand *&ImmMO,
154  MachineOperand *&RegMO) const;
155  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
156  const MachineInstr &DefMI,
157  const ImmInstrInfo &III,
158  int64_t &Imm) const;
159  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
160  const MachineInstr &DefMI,
161  const MachineInstr &MI,
162  bool KillDefMI) const;
163  const unsigned *getStoreOpcodesForSpillArray() const;
164  const unsigned *getLoadOpcodesForSpillArray() const;
165  virtual void anchor();
166 
167 protected:
168  /// Commutes the operands in the given instruction.
169  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
170  ///
171  /// Do not call this method for a non-commutable instruction or for
172  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
173  /// Even though the instruction is commutable, the method may still
174  /// fail to commute the operands, null pointer is returned in such cases.
175  ///
176  /// For example, we can commute rlwimi instructions, but only if the
177  /// rotate amt is zero. We also have to munge the immediates a bit.
178  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
179  unsigned OpIdx1,
180  unsigned OpIdx2) const override;
181 
182 public:
183  explicit PPCInstrInfo(PPCSubtarget &STI);
184 
185  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
186  /// such, whenever a client has an instance of instruction info, it should
187  /// always be able to get register info as well (through this method).
188  ///
189  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
190 
191  bool isXFormMemOp(unsigned Opcode) const {
192  return get(Opcode).TSFlags & PPCII::XFormMemOp;
193  }
194  static bool isSameClassPhysRegCopy(unsigned Opcode) {
195  unsigned CopyOpcodes[] =
196  { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
197  PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
198  PPC::CROR, PPC::EVOR, -1U };
199  for (int i = 0; CopyOpcodes[i] != -1U; i++)
200  if (Opcode == CopyOpcodes[i])
201  return true;
202  return false;
203  }
204 
206  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
207  const ScheduleDAG *DAG) const override;
209  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
210  const ScheduleDAG *DAG) const override;
211 
212  unsigned getInstrLatency(const InstrItineraryData *ItinData,
213  const MachineInstr &MI,
214  unsigned *PredCost = nullptr) const override;
215 
216  int getOperandLatency(const InstrItineraryData *ItinData,
217  const MachineInstr &DefMI, unsigned DefIdx,
218  const MachineInstr &UseMI,
219  unsigned UseIdx) const override;
221  SDNode *DefNode, unsigned DefIdx,
222  SDNode *UseNode, unsigned UseIdx) const override {
223  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
224  UseNode, UseIdx);
225  }
226 
227  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
228  const MachineInstr &DefMI,
229  unsigned DefIdx) const override {
230  // Machine LICM should hoist all instructions in low-register-pressure
231  // situations; none are sufficiently free to justify leaving in a loop
232  // body.
233  return false;
234  }
235 
236  bool useMachineCombiner() const override {
237  return true;
238  }
239 
240  /// Return true when there is potentially a faster code sequence
241  /// for an instruction chain ending in <Root>. All potential patterns are
242  /// output in the <Pattern> array.
243  bool getMachineCombinerPatterns(
244  MachineInstr &Root,
246 
247  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
248 
249  bool isCoalescableExtInstr(const MachineInstr &MI,
250  unsigned &SrcReg, unsigned &DstReg,
251  unsigned &SubIdx) const override;
252  unsigned isLoadFromStackSlot(const MachineInstr &MI,
253  int &FrameIndex) const override;
254  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
255  AliasAnalysis *AA) const override;
256  unsigned isStoreToStackSlot(const MachineInstr &MI,
257  int &FrameIndex) const override;
258 
259  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
260  unsigned &SrcOpIdx2) const override;
261 
262  void insertNoop(MachineBasicBlock &MBB,
263  MachineBasicBlock::iterator MI) const override;
264 
265 
266  // Branch analysis.
267  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
268  MachineBasicBlock *&FBB,
270  bool AllowModify) const override;
271  unsigned removeBranch(MachineBasicBlock &MBB,
272  int *BytesRemoved = nullptr) const override;
273  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
275  const DebugLoc &DL,
276  int *BytesAdded = nullptr) const override;
277 
278  // Select analysis.
279  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
280  unsigned, unsigned, int &, int &, int &) const override;
281  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
282  const DebugLoc &DL, unsigned DstReg,
283  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
284  unsigned FalseReg) const override;
285 
286  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
287  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
288  bool KillSrc) const override;
289 
290  void storeRegToStackSlot(MachineBasicBlock &MBB,
292  unsigned SrcReg, bool isKill, int FrameIndex,
293  const TargetRegisterClass *RC,
294  const TargetRegisterInfo *TRI) const override;
295 
296  void loadRegFromStackSlot(MachineBasicBlock &MBB,
298  unsigned DestReg, int FrameIndex,
299  const TargetRegisterClass *RC,
300  const TargetRegisterInfo *TRI) const override;
301 
302  unsigned getStoreOpcodeForSpill(unsigned Reg,
303  const TargetRegisterClass *RC = nullptr) const;
304 
305  unsigned getLoadOpcodeForSpill(unsigned Reg,
306  const TargetRegisterClass *RC = nullptr) const;
307 
308  bool
309  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
310 
311  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
312  MachineRegisterInfo *MRI) const override;
313 
314  // If conversion by predication (only supported by some branch instructions).
315  // All of the profitability checks always return true; it is always
316  // profitable to use the predicated branches.
318  unsigned NumCycles, unsigned ExtraPredCycles,
319  BranchProbability Probability) const override {
320  return true;
321  }
322 
323  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
324  unsigned NumT, unsigned ExtraT,
325  MachineBasicBlock &FMBB,
326  unsigned NumF, unsigned ExtraF,
327  BranchProbability Probability) const override;
328 
329  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
330  BranchProbability Probability) const override {
331  return true;
332  }
333 
335  MachineBasicBlock &FMBB) const override {
336  return false;
337  }
338 
339  // Predication support.
340  bool isPredicated(const MachineInstr &MI) const override;
341 
342  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
343 
344  bool PredicateInstruction(MachineInstr &MI,
345  ArrayRef<MachineOperand> Pred) const override;
346 
347  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
348  ArrayRef<MachineOperand> Pred2) const override;
349 
350  bool DefinesPredicate(MachineInstr &MI,
351  std::vector<MachineOperand> &Pred) const override;
352 
353  bool isPredicable(const MachineInstr &MI) const override;
354 
355  // Comparison optimization.
356 
357  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
358  unsigned &SrcReg2, int &Mask, int &Value) const override;
359 
360  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
361  unsigned SrcReg2, int Mask, int Value,
362  const MachineRegisterInfo *MRI) const override;
363 
364  /// GetInstSize - Return the number of bytes of code the specified
365  /// instruction may be. This returns the maximum number of bytes.
366  ///
367  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
368 
369  void getNoop(MCInst &NopInst) const override;
370 
371  std::pair<unsigned, unsigned>
372  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
373 
375  getSerializableDirectMachineOperandTargetFlags() const override;
376 
378  getSerializableBitmaskMachineOperandTargetFlags() const override;
379 
380  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
381  bool expandVSXMemPseudo(MachineInstr &MI) const;
382 
383  // Lower pseudo instructions after register allocation.
384  bool expandPostRAPseudo(MachineInstr &MI) const override;
385 
386  static bool isVFRegister(unsigned Reg) {
387  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
388  }
389  static bool isVRRegister(unsigned Reg) {
390  return Reg >= PPC::V0 && Reg <= PPC::V31;
391  }
392  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
393  static int getRecordFormOpcode(unsigned Opcode);
394 
395  bool isTOCSaveMI(const MachineInstr &MI) const;
396 
397  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
398  const unsigned PhiDepth) const;
399 
400  /// Return true if the output of the instruction is always a sign-extended,
401  /// i.e. 0 to 31-th bits are same as 32-th bit.
402  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
403  return isSignOrZeroExtended(MI, true, depth);
404  }
405 
406  /// Return true if the output of the instruction is always zero-extended,
407  /// i.e. 0 to 31-th bits are all zeros
408  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
409  return isSignOrZeroExtended(MI, false, depth);
410  }
411 
412  bool convertToImmediateForm(MachineInstr &MI,
413  MachineInstr **KilledDef = nullptr) const;
414  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
415  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
416  int64_t Imm) const;
417 
418  bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III,
419  bool PostRA) const;
420 
421  /// getRegNumForOperand - some operands use different numbering schemes
422  /// for the same registers. For example, a VSX instruction may have any of
423  /// vs0-vs63 allocated whereas an Altivec instruction could only have
424  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
425  /// register number needed for the opcode/operand number combination.
426  /// The operand number argument will be useful when we need to extend this
427  /// to instructions that use both Altivec and VSX numbering (for different
428  /// operands).
429  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
430  unsigned OpNo) {
431  if (Desc.TSFlags & PPCII::UseVSXReg) {
432  if (isVRRegister(Reg))
433  Reg = PPC::VSX32 + (Reg - PPC::V0);
434  else if (isVFRegister(Reg))
435  Reg = PPC::VSX32 + (Reg - PPC::VF0);
436  }
437  return Reg;
438  }
439 };
440 
441 }
442 
443 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:90
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
Definition: PPCInstrInfo.h:70
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:236
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
uint64_t IsCommutative
Definition: PPCInstrInfo.h:92
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:54
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:102
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:94
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:104
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:402
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:191
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:389
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:334
Provide an instruction scheduling machine model to CodeGen passes.
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:87
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
#define P(N)
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:66
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:194
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:329
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:36
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:40
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:429
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
Represents one node in the SelectionDAG.
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:386
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:227
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:63
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:220
#define I(x, y, z)
Definition: MD5.cpp:58
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:44
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:48
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:84
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:72
IRTranslator LLVM IR MI
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:189
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:317
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:408