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PPCMCCodeEmitter.cpp
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1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "PPCInstrInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/Support/Endian.h"
33 #include <cassert>
34 #include <cstdint>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mccodeemitter"
39 
40 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
41 
42 namespace {
43 
44 class PPCMCCodeEmitter : public MCCodeEmitter {
45  const MCInstrInfo &MCII;
46  const MCContext &CTX;
47  bool IsLittleEndian;
48 
49 public:
50  PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
51  : MCII(mcii), CTX(ctx),
52  IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
53  PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete;
54  void operator=(const PPCMCCodeEmitter &) = delete;
55  ~PPCMCCodeEmitter() override = default;
56 
57  unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
59  const MCSubtargetInfo &STI) const;
60  unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
62  const MCSubtargetInfo &STI) const;
63  unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
65  const MCSubtargetInfo &STI) const;
66  unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
68  const MCSubtargetInfo &STI) const;
69  unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
71  const MCSubtargetInfo &STI) const;
72  unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
74  const MCSubtargetInfo &STI) const;
75  unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
77  const MCSubtargetInfo &STI) const;
78  unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
80  const MCSubtargetInfo &STI) const;
81  unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
83  const MCSubtargetInfo &STI) const;
84  unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
86  const MCSubtargetInfo &STI) const;
87  unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
89  const MCSubtargetInfo &STI) const;
90  unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
92  const MCSubtargetInfo &STI) const;
93  unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
95  const MCSubtargetInfo &STI) const;
96  unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
98  const MCSubtargetInfo &STI) const;
99 
100  /// getMachineOpValue - Return binary encoding of operand. If the machine
101  /// operand requires relocation, record the relocation and return zero.
102  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
104  const MCSubtargetInfo &STI) const;
105 
106  // getBinaryCodeForInstr - TableGen'erated function for getting the
107  // binary encoding for an instruction.
108  uint64_t getBinaryCodeForInstr(const MCInst &MI,
110  const MCSubtargetInfo &STI) const;
111 
112  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
114  const MCSubtargetInfo &STI) const override {
115  verifyInstructionPredicates(MI,
116  computeAvailableFeatures(STI.getFeatureBits()));
117 
118  unsigned Opcode = MI.getOpcode();
119  const MCInstrDesc &Desc = MCII.get(Opcode);
120 
121  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
122 
123  // Output the constant in big/little endian byte order.
124  unsigned Size = Desc.getSize();
125  support::endianness E = IsLittleEndian ? support::little : support::big;
126  switch (Size) {
127  case 0:
128  break;
129  case 4:
130  support::endian::write<uint32_t>(OS, Bits, E);
131  break;
132  case 8:
133  // If we emit a pair of instructions, the first one is
134  // always in the top 32 bits, even on little-endian.
135  support::endian::write<uint32_t>(OS, Bits >> 32, E);
136  support::endian::write<uint32_t>(OS, Bits, E);
137  break;
138  default:
139  llvm_unreachable("Invalid instruction size");
140  }
141 
142  ++MCNumEmitted; // Keep track of the # of mi's emitted.
143  }
144 
145 private:
146  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
147  void verifyInstructionPredicates(const MCInst &MI,
148  uint64_t AvailableFeatures) const;
149 };
150 
151 } // end anonymous namespace
152 
154  const MCRegisterInfo &MRI,
155  MCContext &Ctx) {
156  return new PPCMCCodeEmitter(MCII, Ctx);
157 }
158 
159 unsigned PPCMCCodeEmitter::
160 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
161  SmallVectorImpl<MCFixup> &Fixups,
162  const MCSubtargetInfo &STI) const {
163  const MCOperand &MO = MI.getOperand(OpNo);
164  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
165 
166  // Add a fixup for the branch target.
167  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
169  return 0;
170 }
171 
172 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
173  SmallVectorImpl<MCFixup> &Fixups,
174  const MCSubtargetInfo &STI) const {
175  const MCOperand &MO = MI.getOperand(OpNo);
176  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
177 
178  // Add a fixup for the branch target.
179  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
181  return 0;
182 }
183 
184 unsigned PPCMCCodeEmitter::
185 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
186  SmallVectorImpl<MCFixup> &Fixups,
187  const MCSubtargetInfo &STI) const {
188  const MCOperand &MO = MI.getOperand(OpNo);
189  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
190 
191  // Add a fixup for the branch target.
192  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
194  return 0;
195 }
196 
197 unsigned PPCMCCodeEmitter::
198 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
199  SmallVectorImpl<MCFixup> &Fixups,
200  const MCSubtargetInfo &STI) const {
201  const MCOperand &MO = MI.getOperand(OpNo);
202  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
203 
204  // Add a fixup for the branch target.
205  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
207  return 0;
208 }
209 
210 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
211  SmallVectorImpl<MCFixup> &Fixups,
212  const MCSubtargetInfo &STI) const {
213  const MCOperand &MO = MI.getOperand(OpNo);
214  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
215 
216  // Add a fixup for the immediate field.
217  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
219  return 0;
220 }
221 
222 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
223  SmallVectorImpl<MCFixup> &Fixups,
224  const MCSubtargetInfo &STI) const {
225  // Encode (imm, reg) as a memri, which has the low 16-bits as the
226  // displacement and the next 5 bits as the register #.
227  assert(MI.getOperand(OpNo+1).isReg());
228  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
229 
230  const MCOperand &MO = MI.getOperand(OpNo);
231  if (MO.isImm())
232  return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
233 
234  // Add a fixup for the displacement field.
235  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
237  return RegBits;
238 }
239 
240 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
241  SmallVectorImpl<MCFixup> &Fixups,
242  const MCSubtargetInfo &STI) const {
243  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
244  // displacement and the next 5 bits as the register #.
245  assert(MI.getOperand(OpNo+1).isReg());
246  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
247 
248  const MCOperand &MO = MI.getOperand(OpNo);
249  if (MO.isImm())
250  return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
251 
252  // Add a fixup for the displacement field.
253  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
255  return RegBits;
256 }
257 
258 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
259  SmallVectorImpl<MCFixup> &Fixups,
260  const MCSubtargetInfo &STI) const {
261  // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
262  // displacement and the next 5 bits as the register #.
263  assert(MI.getOperand(OpNo+1).isReg());
264  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
265 
266  const MCOperand &MO = MI.getOperand(OpNo);
267  assert(MO.isImm() && !(MO.getImm() % 16) &&
268  "Expecting an immediate that is a multiple of 16");
269 
270  return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
271 }
272 
273 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
274  SmallVectorImpl<MCFixup> &Fixups,
275  const MCSubtargetInfo &STI)
276  const {
277  // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
278  // as the displacement and the next 5 bits as the register #.
279  assert(MI.getOperand(OpNo+1).isReg());
280  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
281 
282  const MCOperand &MO = MI.getOperand(OpNo);
283  assert(MO.isImm());
284  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
285  return reverseBits(Imm | RegBits) >> 22;
286 }
287 
288 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
289  SmallVectorImpl<MCFixup> &Fixups,
290  const MCSubtargetInfo &STI)
291  const {
292  // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
293  // as the displacement and the next 5 bits as the register #.
294  assert(MI.getOperand(OpNo+1).isReg());
295  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
296 
297  const MCOperand &MO = MI.getOperand(OpNo);
298  assert(MO.isImm());
299  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
300  return reverseBits(Imm | RegBits) >> 22;
301 }
302 
303 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
304  SmallVectorImpl<MCFixup> &Fixups,
305  const MCSubtargetInfo &STI)
306  const {
307  // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
308  // as the displacement and the next 5 bits as the register #.
309  assert(MI.getOperand(OpNo+1).isReg());
310  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
311 
312  const MCOperand &MO = MI.getOperand(OpNo);
313  assert(MO.isImm());
314  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
315  return reverseBits(Imm | RegBits) >> 22;
316 }
317 
318 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
319  SmallVectorImpl<MCFixup> &Fixups,
320  const MCSubtargetInfo &STI) const {
321  const MCOperand &MO = MI.getOperand(OpNo);
322  if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
323 
324  // Add a fixup for the TLS register, which simply provides a relocation
325  // hint to the linker that this statement is part of a relocation sequence.
326  // Return the thread-pointer register's encoding.
327  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
329  const Triple &TT = STI.getTargetTriple();
330  bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
331  return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
332 }
333 
334 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
335  SmallVectorImpl<MCFixup> &Fixups,
336  const MCSubtargetInfo &STI) const {
337  // For special TLS calls, we need two fixups; one for the branch target
338  // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
339  // and one for the TLSGD or TLSLD symbol, which is emitted here.
340  const MCOperand &MO = MI.getOperand(OpNo+1);
341  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
343  return getDirectBrEncoding(MI, OpNo, Fixups, STI);
344 }
345 
346 unsigned PPCMCCodeEmitter::
347 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
348  SmallVectorImpl<MCFixup> &Fixups,
349  const MCSubtargetInfo &STI) const {
350  const MCOperand &MO = MI.getOperand(OpNo);
351  assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
352  MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
353  (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
354  return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
355 }
356 
357 unsigned PPCMCCodeEmitter::
358 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
359  SmallVectorImpl<MCFixup> &Fixups,
360  const MCSubtargetInfo &STI) const {
361  if (MO.isReg()) {
362  // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
363  // The GPR operand should come through here though.
364  assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
365  MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
366  MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
367  unsigned Reg = MO.getReg();
368  unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg);
369 
370  if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg))
372  Encode += 32;
373 
374  return Encode;
375  }
376 
377  assert(MO.isImm() &&
378  "Relocation required in an instruction that we cannot encode!");
379  return MO.getImm();
380 }
381 
382 #define ENABLE_INSTR_PREDICATE_VERIFIER
383 #include "PPCGenMCCodeEmitter.inc"
bool isImm() const
Definition: MCInst.h:59
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned Reg
bool isReg() const
Definition: MCInst.h:58
STATISTIC(NumFunctions, "Total number of functions")
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:30
#define R2(n)
const Triple & getTargetTriple() const
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:346
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like &#39;li&#39; or &#39;addis&#39;.
Definition: PPCFixupKinds.h:34
24-bit absolute relocation for direct branches like &#39;ba&#39; and &#39;bla&#39;.
Definition: PPCFixupKinds.h:27
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:43
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:76
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
Definition: PPCInstrInfo.h:71
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like &#39;std&#39;...
Definition: PPCFixupKinds.h:38
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:295
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:24
unsigned getOpcode() const
Definition: MCInst.h:174
T reverseBits(T Val)
Reverse the bits in Val.
Definition: MathExtras.h:269
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:574