38 #define DEBUG_TYPE "mccodeemitter" 40 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
51 : MCII(mcii), CTX(ctx),
52 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
53 PPCMCCodeEmitter(
const PPCMCCodeEmitter &) =
delete;
54 void operator=(
const PPCMCCodeEmitter &) =
delete;
55 ~PPCMCCodeEmitter()
override =
default;
57 unsigned getDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
60 unsigned getCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
63 unsigned getAbsDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
66 unsigned getAbsCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
69 unsigned getImm16Encoding(
const MCInst &
MI,
unsigned OpNo,
72 unsigned getMemRIEncoding(
const MCInst &
MI,
unsigned OpNo,
75 unsigned getMemRIXEncoding(
const MCInst &
MI,
unsigned OpNo,
78 unsigned getMemRIX16Encoding(
const MCInst &
MI,
unsigned OpNo,
81 unsigned getSPE8DisEncoding(
const MCInst &
MI,
unsigned OpNo,
84 unsigned getSPE4DisEncoding(
const MCInst &
MI,
unsigned OpNo,
87 unsigned getSPE2DisEncoding(
const MCInst &
MI,
unsigned OpNo,
90 unsigned getTLSRegEncoding(
const MCInst &
MI,
unsigned OpNo,
93 unsigned getTLSCallEncoding(
const MCInst &
MI,
unsigned OpNo,
96 unsigned get_crbitm_encoding(
const MCInst &
MI,
unsigned OpNo,
108 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
115 verifyInstructionPredicates(MI,
121 uint64_t
Bits = getBinaryCodeForInstr(MI, Fixups, STI);
129 if (IsLittleEndian) {
138 if (IsLittleEndian) {
139 uint64_t Swapped = (Bits << 32) | (Bits >> 32);
153 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
154 void verifyInstructionPredicates(
const MCInst &MI,
155 uint64_t AvailableFeatures)
const;
163 return new PPCMCCodeEmitter(MCII, Ctx);
166 unsigned PPCMCCodeEmitter::
167 getDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
171 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
179 unsigned PPCMCCodeEmitter::getCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
183 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
191 unsigned PPCMCCodeEmitter::
192 getAbsDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
196 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
204 unsigned PPCMCCodeEmitter::
205 getAbsCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
209 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
217 unsigned PPCMCCodeEmitter::getImm16Encoding(
const MCInst &MI,
unsigned OpNo,
221 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
229 unsigned PPCMCCodeEmitter::getMemRIEncoding(
const MCInst &MI,
unsigned OpNo,
235 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 16;
239 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
247 unsigned PPCMCCodeEmitter::getMemRIXEncoding(
const MCInst &MI,
unsigned OpNo,
253 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 14;
257 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
265 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(
const MCInst &MI,
unsigned OpNo,
271 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 12;
274 assert(MO.isImm() && !(MO.getImm() % 16) &&
275 "Expecting an immediate that is a multiple of 16");
277 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
280 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(
const MCInst &MI,
unsigned OpNo,
291 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
295 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(
const MCInst &MI,
unsigned OpNo,
306 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
310 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(
const MCInst &MI,
unsigned OpNo,
321 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
325 unsigned PPCMCCodeEmitter::getTLSRegEncoding(
const MCInst &MI,
unsigned OpNo,
329 if (MO.
isReg())
return getMachineOpValue(MI, MO, Fixups, STI);
341 unsigned PPCMCCodeEmitter::getTLSCallEncoding(
const MCInst &MI,
unsigned OpNo,
350 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
353 unsigned PPCMCCodeEmitter::
354 get_crbitm_encoding(
const MCInst &MI,
unsigned OpNo,
364 unsigned PPCMCCodeEmitter::
385 "Relocation required in an instruction that we cannot encode!");
389 #define ENABLE_INSTR_PREDICATE_VERIFIER 390 #include "PPCGenMCCodeEmitter.inc" void push_back(const T &Elt)
Compute iterated dominance frontiers using a linear time algorithm.
Describe properties that are true of each instruction in the target description file.
STATISTIC(NumFunctions, "Total number of functions")
14-bit absolute relocation for conditional branches.
const Triple & getTargetTriple() const
static bool isVRRegister(unsigned Reg)
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
const MCExpr * getExpr() const
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
const MCOperand & getOperand(unsigned i) const
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'...
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This class implements an extremely fast bulk output stream that can only output to a stream...
14-bit PC relative relocation for conditional branches.
unsigned getOpcode() const
T reverseBits(T Val)
Reverse the bits in Val.
Instances of this class represent operands of the MCInst class.
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...