LLVM 19.0.0git
PPCMCTargetDesc.cpp
Go to the documentation of this file.
1//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides PowerPC specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
16#include "PPCELFStreamer.h"
17#include "PPCTargetStreamer.h"
18#include "PPCXCOFFStreamer.h"
21#include "llvm/ADT/StringRef.h"
24#include "llvm/MC/MCAssembler.h"
26#include "llvm/MC/MCContext.h"
27#include "llvm/MC/MCDwarf.h"
29#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInstrInfo.h"
35#include "llvm/MC/MCStreamer.h"
37#include "llvm/MC/MCSymbol.h"
38#include "llvm/MC/MCSymbolELF.h"
47
48using namespace llvm;
49
50#define GET_INSTRINFO_MC_DESC
51#define ENABLE_INSTR_PREDICATE_VERIFIER
52#include "PPCGenInstrInfo.inc"
53
54#define GET_SUBTARGETINFO_MC_DESC
55#include "PPCGenSubtargetInfo.inc"
56
57#define GET_REGINFO_MC_DESC
58#include "PPCGenRegisterInfo.inc"
59
60/// stripRegisterPrefix - This method strips the character prefix from a
61/// register name so that only the number is left. Used by for linux asm.
62const char *PPC::stripRegisterPrefix(const char *RegName) {
63 switch (RegName[0]) {
64 case 'a':
65 if (RegName[1] == 'c' && RegName[2] == 'c')
66 return RegName + 3;
67 break;
68 case 'f':
69 if (RegName[1] == 'p')
70 return RegName + 2;
71 [[fallthrough]];
72 case 'r':
73 case 'v':
74 if (RegName[1] == 's') {
75 if (RegName[2] == 'p')
76 return RegName + 3;
77 return RegName + 2;
78 }
79 return RegName + 1;
80 case 'c':
81 if (RegName[1] == 'r')
82 return RegName + 2;
83 break;
84 case 'w':
85 // For wacc and wacc_hi
86 if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
87 if (RegName[4] == '_')
88 return RegName + 7;
89 else
90 return RegName + 4;
91 }
92 break;
93 case 'd':
94 // For dmr, dmrp, dmrrow, dmrrowp
95 if (RegName[1] == 'm' && RegName[2] == 'r') {
96 if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
97 RegName[6] == 'p')
98 return RegName + 7;
99 else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
100 return RegName + 6;
101 else if (RegName[3] == 'p')
102 return RegName + 4;
103 else
104 return RegName + 3;
105 }
106 break;
107 }
108
109 return RegName;
110}
111
112/// getRegNumForOperand - some operands use different numbering schemes
113/// for the same registers. For example, a VSX instruction may have any of
114/// vs0-vs63 allocated whereas an Altivec instruction could only have
115/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
116/// register number needed for the opcode/operand number combination.
117/// The operand number argument will be useful when we need to extend this
118/// to instructions that use both Altivec and VSX numbering (for different
119/// operands).
120unsigned PPC::getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
121 unsigned OpNo) {
122 int16_t regClass = Desc.operands()[OpNo].RegClass;
123 switch (regClass) {
124 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
125 // VSX32-VSX63 during encoding/disassembling
126 case PPC::VSSRCRegClassID:
127 case PPC::VSFRCRegClassID:
128 if (PPC::isVFRegister(Reg))
129 return PPC::VSX32 + (Reg - PPC::VF0);
130 break;
131 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
132 // VSX32-VSX63 during encoding/disassembling
133 case PPC::VSRCRegClassID:
134 if (PPC::isVRRegister(Reg))
135 return PPC::VSX32 + (Reg - PPC::V0);
136 break;
137 // Other RegClass doesn't need mapping
138 default:
139 break;
140 }
141 return Reg;
142}
143
145
146// Pin the vtable to this file.
148
150 MCInstrInfo *X = new MCInstrInfo();
151 InitPPCMCInstrInfo(X);
152 return X;
153}
154
156 bool isPPC64 =
157 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
158 unsigned Flavour = isPPC64 ? 0 : 1;
159 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
160
162 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
163 return X;
164}
165
167 StringRef CPU, StringRef FS) {
168 // Set some default feature to MC layer.
169 std::string FullFS = std::string(FS);
170
171 if (TT.isOSAIX()) {
172 if (!FullFS.empty())
173 FullFS = "+aix," + FullFS;
174 else
175 FullFS = "+aix";
176 }
177
178 return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS);
179}
180
182 const Triple &TheTriple,
183 const MCTargetOptions &Options) {
184 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
185 TheTriple.getArch() == Triple::ppc64le);
186
187 MCAsmInfo *MAI;
188 if (TheTriple.isOSBinFormatXCOFF())
189 MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple);
190 else
191 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
192
193 // Initial state of the frame pointer is R1.
194 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
195 MCCFIInstruction Inst =
196 MCCFIInstruction::cfiDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
197 MAI->addInitialFrameState(Inst);
198
199 return MAI;
200}
201
202static MCStreamer *
204 std::unique_ptr<MCAsmBackend> &&MAB,
205 std::unique_ptr<MCObjectWriter> &&OW,
206 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
207 return createPPCELFStreamer(Context, std::move(MAB), std::move(OW),
208 std::move(Emitter));
209}
210
212 const Triple &T, MCContext &Context, std::unique_ptr<MCAsmBackend> &&MAB,
213 std::unique_ptr<MCObjectWriter> &&OW,
214 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
215 return createPPCXCOFFStreamer(Context, std::move(MAB), std::move(OW),
216 std::move(Emitter));
217}
218
219namespace {
220
221class PPCTargetAsmStreamer : public PPCTargetStreamer {
223
224public:
225 PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
226 : PPCTargetStreamer(S), OS(OS) {}
227
228 void emitTCEntry(const MCSymbol &S,
229 MCSymbolRefExpr::VariantKind Kind) override {
230 if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(&S)) {
231 MCSymbolXCOFF *TCSym =
232 cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
233 ->getQualNameSymbol();
234 // On AIX, we have TLS variable offsets (symbol@({gd|ie|le|ld}) depending
235 // on the TLS access method (or model). For the general-dynamic access
236 // method, we also have region handle (symbol@m) for each variable. For
237 // local-dynamic, there is a module handle (_$TLSML[TC]@ml) for all
238 // variables. Finally for local-exec and initial-exec, we have a thread
239 // pointer, in r13 for 64-bit mode and returned by .__get_tpointer for
240 // 32-bit mode.
241 if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
242 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM ||
243 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE ||
244 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE ||
245 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLD ||
246 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSML)
247 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
249 else
250 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
251
252 if (TCSym->hasRename())
253 Streamer.emitXCOFFRenameDirective(TCSym, TCSym->getSymbolTableName());
254 return;
255 }
256
257 OS << "\t.tc " << S.getName() << "[TC]," << S.getName() << '\n';
258 }
259
260 void emitMachine(StringRef CPU) override {
261 OS << "\t.machine " << CPU << '\n';
262 }
263
264 void emitAbiVersion(int AbiVersion) override {
265 OS << "\t.abiversion " << AbiVersion << '\n';
266 }
267
268 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
269 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
270
271 OS << "\t.localentry\t";
272 S->print(OS, MAI);
273 OS << ", ";
274 LocalOffset->print(OS, MAI);
275 OS << '\n';
276 }
277};
278
279class PPCTargetELFStreamer : public PPCTargetStreamer {
280public:
281 PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
282
283 MCELFStreamer &getStreamer() {
284 return static_cast<MCELFStreamer &>(Streamer);
285 }
286
287 void emitTCEntry(const MCSymbol &S,
288 MCSymbolRefExpr::VariantKind Kind) override {
289 // Creates a R_PPC64_TOC relocation
290 Streamer.emitValueToAlignment(Align(8));
291 Streamer.emitSymbolValue(&S, 8);
292 }
293
294 void emitMachine(StringRef CPU) override {
295 // FIXME: Is there anything to do in here or does this directive only
296 // limit the parser?
297 }
298
299 void emitAbiVersion(int AbiVersion) override {
300 MCAssembler &MCA = getStreamer().getAssembler();
301 unsigned Flags = MCA.getELFHeaderEFlags();
302 Flags &= ~ELF::EF_PPC64_ABI;
303 Flags |= (AbiVersion & ELF::EF_PPC64_ABI);
304 MCA.setELFHeaderEFlags(Flags);
305 }
306
307 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
308 MCAssembler &MCA = getStreamer().getAssembler();
309
310 // encodePPC64LocalEntryOffset will report an error if it cannot
311 // encode LocalOffset.
312 unsigned Encoded = encodePPC64LocalEntryOffset(LocalOffset);
313
314 unsigned Other = S->getOther();
315 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
316 Other |= Encoded;
317 S->setOther(Other);
318
319 // For GAS compatibility, unless we already saw a .abiversion directive,
320 // set e_flags to indicate ELFv2 ABI.
321 unsigned Flags = MCA.getELFHeaderEFlags();
322 if ((Flags & ELF::EF_PPC64_ABI) == 0)
323 MCA.setELFHeaderEFlags(Flags | 2);
324 }
325
326 void emitAssignment(MCSymbol *S, const MCExpr *Value) override {
327 auto *Symbol = cast<MCSymbolELF>(S);
328
329 // When encoding an assignment to set symbol A to symbol B, also copy
330 // the st_other bits encoding the local entry point offset.
331 if (copyLocalEntry(Symbol, Value))
332 UpdateOther.insert(Symbol);
333 else
334 UpdateOther.erase(Symbol);
335 }
336
337 void finish() override {
338 for (auto *Sym : UpdateOther)
339 if (Sym->isVariable())
340 copyLocalEntry(Sym, Sym->getVariableValue());
341
342 // Clear the set of symbols that needs to be updated so the streamer can
343 // be reused without issues.
344 UpdateOther.clear();
345 }
346
347private:
349
350 bool copyLocalEntry(MCSymbolELF *D, const MCExpr *S) {
351 auto *Ref = dyn_cast<const MCSymbolRefExpr>(S);
352 if (!Ref)
353 return false;
354 const auto &RhsSym = cast<MCSymbolELF>(Ref->getSymbol());
355 unsigned Other = D->getOther();
356 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
357 Other |= RhsSym.getOther() & ELF::STO_PPC64_LOCAL_MASK;
358 D->setOther(Other);
359 return true;
360 }
361
362 unsigned encodePPC64LocalEntryOffset(const MCExpr *LocalOffset) {
363 MCAssembler &MCA = getStreamer().getAssembler();
364 int64_t Offset;
365 if (!LocalOffset->evaluateAsAbsolute(Offset, MCA))
366 MCA.getContext().reportError(LocalOffset->getLoc(),
367 ".localentry expression must be absolute");
368
369 switch (Offset) {
370 default:
372 LocalOffset->getLoc(), ".localentry expression must be a power of 2");
373 return 0;
374 case 0:
375 return 0;
376 case 1:
377 return 1 << ELF::STO_PPC64_LOCAL_BIT;
378 case 4:
379 case 8:
380 case 16:
381 case 32:
382 case 64:
384 }
385 }
386};
387
388class PPCTargetMachOStreamer : public PPCTargetStreamer {
389public:
390 PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
391
392 void emitTCEntry(const MCSymbol &S,
393 MCSymbolRefExpr::VariantKind Kind) override {
394 llvm_unreachable("Unknown pseudo-op: .tc");
395 }
396
397 void emitMachine(StringRef CPU) override {
398 // FIXME: We should update the CPUType, CPUSubType in the Object file if
399 // the new values are different from the defaults.
400 }
401
402 void emitAbiVersion(int AbiVersion) override {
403 llvm_unreachable("Unknown pseudo-op: .abiversion");
404 }
405
406 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
407 llvm_unreachable("Unknown pseudo-op: .localentry");
408 }
409};
410
411class PPCTargetXCOFFStreamer : public PPCTargetStreamer {
412public:
413 PPCTargetXCOFFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
414
415 void emitTCEntry(const MCSymbol &S,
416 MCSymbolRefExpr::VariantKind Kind) override {
417 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
418 const unsigned PointerSize = MAI->getCodePointerSize();
419 Streamer.emitValueToAlignment(Align(PointerSize));
420 Streamer.emitValue(MCSymbolRefExpr::create(&S, Kind, Streamer.getContext()),
421 PointerSize);
422 }
423
424 void emitMachine(StringRef CPU) override {
425 llvm_unreachable("Machine pseudo-ops are invalid for XCOFF.");
426 }
427
428 void emitAbiVersion(int AbiVersion) override {
429 llvm_unreachable("ABI-version pseudo-ops are invalid for XCOFF.");
430 }
431
432 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
433 llvm_unreachable("Local-entry pseudo-ops are invalid for XCOFF.");
434 }
435};
436
437} // end anonymous namespace
438
441 MCInstPrinter *InstPrint,
442 bool isVerboseAsm) {
443 return new PPCTargetAsmStreamer(S, OS);
444}
445
447 return new PPCTargetStreamer(S);
448}
449
450static MCTargetStreamer *
452 const Triple &TT = STI.getTargetTriple();
453 if (TT.isOSBinFormatELF())
454 return new PPCTargetELFStreamer(S);
455 if (TT.isOSBinFormatXCOFF())
456 return new PPCTargetXCOFFStreamer(S);
457 return new PPCTargetMachOStreamer(S);
458}
459
461 unsigned SyntaxVariant,
462 const MCAsmInfo &MAI,
463 const MCInstrInfo &MII,
464 const MCRegisterInfo &MRI) {
465 return new PPCInstPrinter(MAI, MII, MRI, T);
466}
467
468namespace {
469
470class PPCMCInstrAnalysis : public MCInstrAnalysis {
471public:
472 explicit PPCMCInstrAnalysis(const MCInstrInfo *Info)
474
475 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
476 uint64_t &Target) const override {
477 unsigned NumOps = Inst.getNumOperands();
478 if (NumOps == 0 ||
479 Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType !=
481 return false;
482 Target = Addr + Inst.getOperand(NumOps - 1).getImm() * Size;
483 return true;
484 }
485};
486
487} // end anonymous namespace
488
490 return new PPCMCInstrAnalysis(Info);
491}
492
496 // Register the MC asm info.
498
499 // Register the MC instruction info.
501
502 // Register the MC register info.
504
505 // Register the MC subtarget info.
507
508 // Register the MC instruction analyzer.
510
511 // Register the MC Code Emitter
513
514 // Register the asm backend.
516
517 // Register the elf streamer.
519
520 // Register the XCOFF streamer.
522
523 // Register the object target streamer.
526
527 // Register the asm target streamer.
529
530 // Register the null target streamer.
532
533 // Register the MCInstPrinter.
535 }
536}
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
dxil DXContainer Global Emitter
uint64_t Addr
uint64_t Size
std::optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1290
Symbol * Sym
Definition: ELF_riscv.cpp:479
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
#define RegName(no)
static LVOptions Options
Definition: LVOptions.cpp:25
static MCTargetStreamer * createNullTargetStreamer(MCStreamer &S)
LLVMContext & Context
static MCTargetStreamer * createAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetMC()
static MCInstPrinter * createPPCMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCTargetStreamer * createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstrAnalysis * createPPCMCInstrAnalysis(const MCInstrInfo *Info)
static MCAsmInfo * createPPCMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
static MCSubtargetInfo * createPPCMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCRegisterInfo * createPPCMCRegisterInfo(const Triple &TT)
static MCInstrInfo * createPPCMCInstrInfo()
SI optimize exec mask operations pre RA
raw_pwrite_stream & OS
This file defines the SmallPtrSet class.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:75
unsigned getCodePointerSize() const
Get the code pointer size in bytes.
Definition: MCAsmInfo.h:546
MCContext & getContext() const
Definition: MCAssembler.h:326
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:281
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:282
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:541
Context object for machine code objects.
Definition: MCContext.h:76
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1064
void emitValueToAlignment(Align, int64_t, unsigned, unsigned) override
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
SMLoc getLoc() const
Definition: MCExpr.h:82
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
int64_t getImm() const
Definition: MCInst.h:80
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
unsigned getOther() const
void setOther(unsigned Other)
static StringRef getVariantKindName(VariantKind Kind)
Definition: MCExpr.cpp:221
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
StringRef getSymbolTableName() const
Definition: MCSymbolXCOFF.h:67
bool hasRename() const
Definition: MCSymbolXCOFF.h:60
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
Target specific streamer interface.
Definition: MCStreamer.h:93
~PPCTargetStreamer() override
PPCTargetStreamer(MCStreamer &S)
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:361
bool isOSBinFormatXCOFF() const
Tests whether the OS uses the XCOFF binary format.
Definition: Triple.h:726
LLVM Value Representation.
Definition: Value.h:74
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ STO_PPC64_LOCAL_MASK
Definition: ELF.h:412
@ STO_PPC64_LOCAL_BIT
Definition: ELF.h:411
@ EF_PPC64_ABI
Definition: ELF.h:406
const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
static bool isVRRegister(unsigned Reg)
static bool isVFRegister(unsigned Reg)
unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Target & getThePPC64LETarget()
Target & getThePPC32Target()
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:313
MCXCOFFStreamer * createPPCXCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter)
@ Ref
The access may reference the value stored in memory.
Target & getThePPC64Target()
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getThePPC32LETarget()
MCELFStreamer * createPPCELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Description of the encoding of one expression Op.
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterXCOFFStreamer(Target &T, Target::XCOFFStreamerCtorTy Fn)
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)